ESD protection circuit providing multiple detection signals

Abstract

The present disclosure relates to an ESD protection circuit that provides multiple detection signals. The ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors, each current mirror for providing two detection signals. The ESD protection circuit includes a drive circuit system, and the drive circuit system generates a trigger signal to a clamp circuit in response to an ESD event based on the detection signal from the current mirror, so that the clamp circuit is conductive.

Description

Technical Field

[0001] The present invention relates to electrostatic discharge (ESD) protection circuits for integrated circuits. Background Art

[0002] Some integrated circuits include electrostatic discharge (ESD) protection circuitry to protect the circuitry of the integrated circuit from ESD events. An example of an ESD event that may occur to an integrated circuit is one in which static charge accumulated on an external object (e.g., manufacturing equipment or a human body) is discharged to a conductive structure (e.g., a bonding pad) of the integrated circuit. Such a discharge may produce abnormally high voltages and / or currents in the integrated circuit, which may damage the circuitry of the integrated circuit. The ESD protection circuitry may include a detection circuit to detect the occurrence of an ESD event on a bonding pad, and to cause a clamping circuit to conduct to discharge the charge of the ESD event to a ground rail of the integrated circuit. Summary of the invention

[0003] According to one embodiment, a circuit includes:

[0004] a first current mirror coupled to a first power rail and comprising a master device and a mirror device, the first current mirror comprising: a first output from a current electrode of the master device of the first current mirror, the first output configured to provide a first detection signal indicative of an ESD event; and a second output from a current electrode of the mirror device of the first current mirror, the second output configured to provide a second detection signal indicative of the ESD event;

[0005] a second current mirror coupled to a second power rail and comprising a master device and a mirror device, the second current mirror comprising: a first output from a current electrode of the master device of the second current mirror, the first output configured to provide a third detection signal indicative of the ESD event; and a second output from a current electrode of the mirror device of the second current mirror, the second output configured to provide a fourth detection signal indicative of the ESD event;

[0006] a first trigger path comprising an input receiving at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and an output providing a first trigger signal to a first ESD clamp device, wherein the first trigger signal is configured to enable the first ESD clamp device in response to the ESD event, wherein the first trigger signal is provided based on the at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal; and

[0007] and a second trigger path comprising an input for receiving at least another one of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and an output for providing a second trigger signal to a second ESD clamping device, wherein the second trigger signal is configured to enable the second ESD clamping device in response to the ESD event, wherein the second trigger signal is provided based on at least the other one of the first signal, the second signal, the third signal, and the fourth signal.

[0008] In some embodiments, the first trigger path includes:

[0009] a series of buffers, wherein the series of buffers receive at least one detection signal of the at least two detection signals among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal, and outputs of the series of buffers are connected to an output node providing the first trigger signal; and

[0010] A node assertion path is parallel to at least a portion of the series of buffers and includes an input receiving another detection signal of the at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and includes an output coupled to a node of the series of buffers.

[0011] In some embodiments, the second trigger path includes:

[0012] A second series buffer includes an input receiving the other of the first detection signal, the second detection signal, the third detection signal and the fourth detection signal and an output connected to a second output node to provide the second trigger signal.

[0013] In some embodiments:

[0014] The series of buffers receive the second detection signal;

[0015] The input of the node assertion path of the first trigger path receives the first detection signal.

[0016] In some embodiments, the second series of buffers receives the fourth detection signal.

[0017] In some embodiments, the first power rail is characterized by a voltage higher than a voltage of the second power rail, and wherein:

[0018] The series of buffers receive the second detection signal;

[0019] The input of the node assertion path of the first trigger path receives the first detection signal.

[0020] In some embodiments, the first power rail is characterized by a voltage lower than a voltage of the second power rail, wherein:

[0021] The series of buffers receive the second detection signal;

[0022] The input of the node assertion path of the first trigger path receives the first detection signal.

[0023] In some embodiments, the node assertion path of the first trigger path includes a device coupled between the first power rail and the node and controlled by the other detection signal of the at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal, wherein the device is configured to pull the voltage of the node toward the voltage of the first power rail during the ESD event.

[0024] In some implementations, the node assertion path is characterized in that the assertion path pulls the voltage of the node to the assertion voltage faster than the series of buffers during an ESD event.

[0025] In some embodiments, the circuit further comprises:

[0026] a node assertion device comprising a first electrode coupled to a first circuit node of the first trigger path, a second current electrode coupled to the second power rail, and a control electrode coupled to receive the third detection signal or the fourth detection signal, wherein the first trigger path asserts the first trigger signal based on at least one of the first detection signal or the second detection signal.

[0027] In some embodiments, the circuit further comprises:

[0028] a second node assertion device comprising a first electrode coupled to the first circuit node of the first trigger path, a second current electrode coupled to the second power rail, and the control electrode coupled to receive an inverted signal of the other of the third detection signal or the fourth detection signal that is not received by the control electrode of the node assertion device.

[0029] According to another embodiment, a circuit includes:

[0030] a first current mirror coupled to a first power rail and comprising a master device and a mirror device, the first current mirror comprising: a first output from a current electrode of the master device of the first current mirror, the first output configured to provide a first detection signal indicative of an ESD event; and a second output from a current electrode of the mirror device of the first current mirror, the second output configured to provide a second detection signal indicative of the ESD event;

[0031] a second current mirror coupled to a second power rail and comprising a master device and a mirror device, the second current mirror comprising: a first output from a current electrode of the master device of the second current mirror, the first output configured to provide a third detection signal indicative of the ESD event; and a second output from a current electrode of the mirror device of the second current mirror, the second output configured to provide a fourth detection signal indicative of the ESD event;

[0032] A driver circuit system configured to: provide a first trigger signal to a first ESD clamp device, wherein the first trigger signal is asserted during an ESD event to enable the first ESD clamp device; and provide a second trigger signal to a second ESD clamp device, wherein the second trigger signal is asserted during an ESD event to enable the second ESD clamp device, wherein the driver circuit system comprises:

[0033] a first node assertion path configured to pull a voltage at a first circuit node in the driver circuitry to an asserted state of the first circuit node during an ESD event based on at least a first detection signal of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal;

[0034] a second node assertion path configured to pull a voltage at a second circuit node in the driver circuitry to an asserted state of the second circuit node during an ESD event based on at least a second detection signal of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal; and

[0035] and a third node assertion path configured to pull a voltage of a third circuit node in the driver circuit system to an asserted state of the third circuit node during an ESD event based on at least a third detection signal among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal.

[0036] In some embodiments:

[0037] the first circuit node being at a control electrode of the first ESD clamp device, and the first node assertion path pulling the voltage of the first circuit node to an asserted state of the first circuit node during the ESD event based on the first detection signal or the second detection signal;

[0038] the second circuit node and the first circuit node being the same circuit node, and the second assertion path pulling the voltage of the first circuit node to an asserted state of the first circuit node during the ESD event based on at least the other of the first detection signal or the second detection signal; and

[0039] The second trigger signal is responsive to the third circuit node assertion, and the third node assertion path pulls the voltage of the third circuit node to an asserted state of the third circuit node during the ESD event based on at least the third detection signal or a fourth detection signal.

[0040] In some embodiments:

[0041] the first node assertion path comprising a first device including a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to receive one of the third detection signal or the fourth detection signal;

[0042] the first circuit node and the second circuit node being the same circuit node, the second node asserting a path comprising a second device comprising a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to a node whose assertion state is dependent on the other of the third detection signal or the fourth detection signal; and

[0043] The third node assertion path is configured to pull the voltage of the third circuit node in the driver circuitry to an asserted state of the third circuit node during the ESD event based on the first detection signal or the second detection signal, wherein the first trigger signal is responsive to at least the third circuit node assertion.

[0044] In some implementations, the third node assertion path includes two transistors of opposite conductivity type coupled between the first power rail and the first circuit node, wherein a first current electrode of each of the two transistors is connected together at the third circuit node.

[0045] In some embodiments, the driving circuit system further comprises:

[0046] and a fourth node assertion path configured to pull a voltage of a fourth circuit node in the driver circuit system to an asserted state of the fourth circuit node during the ESD event based on at least a fourth detection signal among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal.

[0047] In some embodiments:

[0048] The first node assertion path is configured to pull the voltage of the first circuit node in the driver circuitry to an asserted state of the first circuit node during an ESD event based on the third detection signal or the fourth detection signal, wherein the second trigger signal is responsive to at least the first circuit node assertion.

[0049] In some embodiments:

[0050] the first node assertion path comprising at least one buffer coupled between the second current mirror and the first circuit node, the at least one buffer comprising an input for receiving one of the third detection signal or the fourth detection signal;

[0051] The second node assertion path includes a device including a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to receive the other of the third detection signal or the fourth detection signal, wherein the first circuit node and the second circuit node are the same circuit node.

[0052] In some embodiments:

[0053] the first node assertion path comprising a first device including a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to receive the third detection signal or the fourth detection signal, wherein the second trigger signal is responsive to at least the first circuit node assertion;

[0054] the second circuit node and the first circuit node being the same circuit node, and the second node assertion path pulls the voltage of the first circuit node to an asserted state of the first circuit node during the ESD event based on at least the other of the third detection signal or the fourth detection signal; and

[0055] The third node assertion path is configured to pull the voltage of the third circuit node in the driver circuitry to an asserted state of the third circuit node during the ESD event based on the first detection signal or the second detection signal, wherein the first trigger signal is responsive to the third circuit node assertion.

[0056] In some embodiments, the first detection signal and the second detection signal are characterized as being complementary to each other, and the third detection signal and the fourth detection signal are characterized as being complementary to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0058] Figure 1 FIG. 1 is a circuit diagram of a portion of an integrated circuit according to an embodiment of the present invention.

[0059] Figure 2 According to one embodiment of the present invention Figure 1 Circuit diagram of the ESD protection circuit.

[0060] Figure 3 According to another embodiment of the present invention Figure 1 Circuit diagram of the ESD protection circuit.

[0061] Figure 4 FIG. 4 is a circuit diagram of an ESD protection circuit according to another embodiment of the present invention.

[0062] Figure 5 FIG. 4 is a circuit diagram of an ESD protection circuit according to another embodiment of the present invention.

[0063] Unless otherwise indicated, the same reference numerals are used in different drawings to indicate the same items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0064] A detailed description of the mode for carrying out the invention is set forth below. The description is intended to illustrate the invention and should not be considered limiting.

[0065] In some embodiments disclosed herein, an ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors, each of which is used to provide two detection signals. The ESD protection circuit includes a drive circuit system that generates a trigger signal to a clamp circuit in response to an ESD event to make the clamp circuit conductive. The drive circuit system includes a node assertion path that pulls a circuit node of the drive circuit system to an asserted state of the circuit node during an ESD event in response to the detection signal. In some embodiments, the use of multiple detection signals and multiple assertion paths allows the trigger signal to be adjusted according to speed and drive strength.

[0066] Figure 1 A circuit diagram of a portion of an integrated circuit of an ESD protection circuit according to an embodiment of the present invention is shown. Integrated circuit 101 includes a plurality of external terminals (e.g., pads). In the illustrated embodiment, the integrated circuit includes a VDD pad 103 for receiving an external power supply voltage (e.g., 3.3 volts), a VSS pad 107 for receiving a second external power supply voltage (e.g., ground), and an I / O pad 105 for receiving and / or supplying an information signal (e.g., discrete or analog). The circuit system for performing the intended function of the circuit system (e.g., processing circuit system, analog circuit system, sensor, memory) of the integrated circuit is not shown. Such circuit systems will be connected to receive power supply voltage from pads 103 and pads 107 and connected to transfer information via pads 105. The integrated circuit may include more pads (not shown). In other embodiments, the integrated circuit may include other types of external terminals (e.g., pillars, bumps).

[0067] In the illustrated embodiment, circuit 101 includes diodes 113, 119, and 115 for shunting current from an ESD event from pad 105 or pad 107 to VDD power rail 106 and boost bus 108. The boost bus may be characterized as a power rail for ESD circuitry. During an ESD event, the current shunted to boost bus 108 and VDD power rail 106 raises the voltage of boost bus 108 so that trigger circuit 121 will assert trigger signal TRIG1 and trigger signal TRIG2 to cause conductive clamp 109 and conductive clamp 111 (implemented as NFETs in the illustrated embodiment) to clamp VDD rail 106 to VSS rail 110, so that the ESD event current is discharged to rail 110 and the large voltage difference on the circuitry of integrated circuit 101 caused by the ESD event is reduced. During an ESD event applied to pad 105 with pad 107 grounded, a high ESD current (typically on the order of several amperes) flows through diode 113 to VDD rail 106, and then to ground rail 110 via clamp 109 and clamp 111. A much smaller current is required to power trigger circuit 121 via diode 119 to boost bus 108. Due to these differences in current magnitudes, and the associated IR drops in the two current paths, the boost bus voltage seen by trigger circuit 121 typically far exceeds the VDD bus voltage seen by the drain terminal of clamp 109. The result is that the control electrodes of clamp 109 and clamp 111 are typically driven well above the VDD bus voltage. This can significantly increase the conductivity of clamp 109 and clamp 111, so that the desired clamp can be achieved in a compact area.

[0068] In the illustrated embodiment, integrated circuit 101 includes a boost circuit 117 to allow boost bus 108 to rise to a higher voltage than VDD rail 106 during assertion of the trigger signal so as to more strongly turn on clamp 109 and clamp 111, while maintaining boost bus 108 and VDD rail 106 at the same potential when the trigger signal is not asserted. In the illustrated embodiment, circuit 117 includes resistor 123 and PFET transistor 125, the control electrode of which is connected to receive the TRIG2 signal. Before assertion of the TRIG2 signal, transistor 125 is conductive so that rail 106 and boost bus 108 are at approximately the same potential. Once the trigger signal is asserted during an ESD event, transistor 125 becomes non-conductive so that boost bus 108 can still be maintained at a higher potential, even when VDD rail 106 is clamped at a low potential by clamp 109 and clamp 111. However, in other embodiments, boost circuit 117 may have other configurations. In one embodiment, diode 119 is sized so that it directs a limited amount of ESD energy to boost bus 108. Also in some embodiments, boost bus 108 may be made relatively resistive to limit the current on the bus during an ESD event.

[0069] Some integrated circuits of other embodiments may not include boost bus 108 and boost circuit 117. In some such embodiments, a trigger circuit is connected to VDD rail 106, wherein trigger circuit 121 detects an ESD event on VDD rail 106 and provides the voltage of rail 106 to driver circuitry of circuit 121 to generate a trigger signal to drive clamp 109 and clamp 111.

[0070] In other embodiments, the boost bus 108 will be coupled to a plurality of I / O pads (not shown) via diodes (not shown). In some embodiments, the boost bus runs along the perimeter of the integrated circuit and is coupled to the VDD rail 106 at a plurality of locations with a boost circuit (117). In some embodiments, the integrated circuit may include a plurality of boost buses for each power rail. In other embodiments, a plurality of trigger circuits (not shown) located throughout the perimeter of the integrated circuit will be connected to the boost bus 108. In some such embodiments, the trigger signals from the plurality of trigger circuits will be provided to the trigger circuit bus, wherein each trigger signal (TRIG1, TRIG2) will have its own trigger signal bus for that trigger signal. Each trigger signal bus will be connected to a plurality of clamps located through the perimeter of the integrated circuit. For example, a trigger signal bus (not shown) for signal TRIG1 may be driven by any of a number of trigger circuits (121) distributed around integrated circuit 101 and coupled to boost bus 108 to provide trigger signal TRIG1 to a number of clamps similar to clamp 111 to close the clamps in response to detecting an ESD event. However, in other embodiments, the ESD circuit may have other configurations.

[0071] Figure 2 for Figure 1 1. Circuit diagram of trigger circuit 121 and other circuit systems of an ESD protection circuit. Trigger circuit 121 includes detection circuit 201 for detecting an ESD event on boost bus 108 and driver circuit 203 for asserting trigger signals (TRIG1 and TRIG2) in response to the detected ESD event.

[0072] In the illustrated embodiment, the trigger circuit 121 includes a bias circuit 205 for generating a bias voltage (1 / 2 VBB) that is half the voltage (VBB) of the boost bus 108. The circuit 205 includes a stack of PFETs 207 and a stack of PFETs 209. The bias voltage is provided to nodes 228 and 232 of the detection circuit 201 and nodes 236, 241, and 263 of the drive circuit 203 via transistors 227, 234, 231, 240, and 269, respectively, to bias the nodes to 1 / 2 VBB (approximately 1 / 2 VDD when the transistor 125 is turned off) during normal operation. This is to ensure that no device is stressed during normal operation beyond the nominally allowed voltage range of the device in order to avoid potential drops. In the illustrated embodiment, the nominally allowed voltage range is between 0 and 1 / 2 VDD. When an ESD event is detected, transistor 227, transistor 234, transistor 231, transistor 240, and transistor 269 are rendered non-conductive to nodes where they are not biased at 1 / 2 VBB. However, during a short ESD event duration, the overstress is limited in time. Therefore, in some embodiments, it may be acceptable to allow the device to briefly operate outside the range allowed by the device in order to make the trigger circuit more effective.

[0073] The detection circuit 201 includes two current mirrors 211 and 221. The current mirror 211 includes a main device 213 and a mirror device 215. The main device 213 is implemented as a PFET in a diode configuration, and the mirror device 215 is implemented as a PFET. The current mirror 221 includes a main device 223 and a mirror device 225. The main device 223 is implemented as an NFET in a diode configuration, and the mirror device 225 is implemented as an NFET. The circuit 201 includes capacitors 217 and 219 (implemented as NFETs in a capacitor configuration) and resistors 214 and 216. The drain of the main device 213 (current electrode of the FET) provides an upper primary detection signal (UCM1), the drain of the mirror device 215 provides an upper secondary detection signal (UCM2), the drain of the main device 223 provides a lower primary detection signal (LCM1), and the drain of the mirror device 225 provides a lower secondary detection signal (LCM2).

[0074] In the illustrated embodiment, the detection circuit 201 detects whether an ESD event is occurring by monitoring the voltage slew rate (dV / dt) of the boost bus 108. The circuit 201 is designed to distinguish between the faster rise time of a typical ESD event of an integrated circuit and the slower rise time of a normal power-on event. In the illustrated embodiment, when there is a change in the voltage on the boost bus 108, the voltage slew rate between the bus 108 and the VSS rail 110 becomes non-zero. If the slew rate is small enough (for example, if the rise time is much longer than the RC time constant of the capacitor 217 and the master device 213 (configured as a diode) and the time constant of the capacitor 219 and the master device 223), then it is considered that no ESD event has occurred. In this case, the increase in the voltage difference between the bus 108 and the rail 110 is completely dropped on the capacitors 217 and 219, and the voltage drop on the master device 213 and the master device 223 does not increase. If the slew rate on the boost bus 108 exceeds the threshold set by the time constant, it is determined that an ESD event has occurred. Under such conditions, the increase in the voltage differential between bus 108 and rail 110 is partially dropped on master device 213 and master device 223, which causes the primary upper detection signal (UCM1) to become below VBB and the primary lower detection signal (LCM1) to rise above VSS, each signal indicating that an ESD event has been detected.

[0075] When UCM1 additionally drops below VBB to indicate an ESD event, then the mirror device 215 becomes more conductive to pull the voltage of UCM2 toward VBB to indicate an ESD event. In addition, when LCM1 additionally rises above VSS, the mirror device becomes more conductive, wherein LCM2 is pulled closer to VSS to indicate an ESD event. Therefore, UCM1 and LCM1 can be considered as complementary signals of UCM2 and LCM2, respectively. In other embodiments, the detection circuit can have other configurations and / or operate in different ways to detect ESD events. In addition, in other embodiments, the detection circuit can generate a different number of detection signals.

[0076] The driving circuit 203 includes two trigger paths. One path is used to generate the TRIG2 signal, and the other path is used to generate the TRIG1 signal. Each path includes a plurality of inverter buffer stages. In the illustrated embodiment, the paths share the buffer stage. The two paths include an input for receiving a plurality of detection signals (UCM1, UCM2, LCM1, and LCM2) to generate a trigger signal. The driving circuit 203 includes a transistor 229, a transistor 233, a transistor 235, a transistor 237, a transistor 239, a transistor 243, a transistor 245, a transistor 253, a transistor 251, a transistor 255, a transistor 257, and a transistor 262. The driving circuit also includes a resistor 249, a resistor 247, and a resistor 259.

[0077] During normal operation when no ESD event is detected, signals UCM1 and LCM2 are at relatively high voltage levels, and signals UCM2 and LCM1 are at relatively low voltage levels. Node 228, node 232, node 236, node 241, and node 263 are at 1 / 2 VBB (approximately 1 / 2 VDD). Node 267 is at a relatively low voltage level (VSS), and node 261 is at a relatively high voltage level (1 / 2 VBB). Node 265 is at a relatively high voltage level (VBB). TRIG1 is at a relatively low voltage level (VSS), and TRIG2 is at a relatively low voltage level (1 / 2 VBB), wherein both clamp 109 and clamp 111 are non-conductive.

[0078] When an ESD event is detected, UCM2 and LCM1 transition to a relatively high voltage level, and UCM1 and LCM2 transition to a relatively low voltage level. Therefore, node 267 transitions to a high voltage asserted state (1 / 2 VBB, then TRIG1 is asserted), and transistor 229 becomes conductive. Node 265 transitions to a low voltage asserted state (1 / 2 VBB, then TRIG1 is asserted), and node 261 transitions to a low voltage asserted state (VSS). Node 265 at a low voltage makes transistor 262 conductive to pull TRIG2 to the asserted VBB voltage, and node 261 enters a low voltage asserted state causing TRIG1 to be pulled high to make clamp 111 conductive.

[0079] During an ESD event, when TRIG1 becomes asserted, transistor 227, transistor 234, transistor 231, transistor 240, and transistor 269 become disabled, so nodes 228, node 232, node 236, node 241, and node 263 are no longer biased to 1 / 2 VBB. Therefore, node 236 is additionally pulled toward VBB because UCM1 is at a relatively low level. The voltage of node 236 is even further increased to make both transistor 243 and transistor 253 more conductive, which makes it more difficult to pull both node 241 and node 261 toward VSS. Node 261 is more difficult to pull toward VSS and node 263 is pulled higher due to no longer being biased to 1 / 2 VBB, making it more difficult to drive TRIG1. Because nodes 228 , 232 , 236 , 241 , and 263 are biased at ½ VBB before TRIG1 is asserted and are not biased at ½ VBB after TRIG1 is asserted, the voltage levels of the asserted states of the nodes may vary.

[0080] Using two current mirrors to generate additional detection signals allows the driver circuit to implement multiple node assertion paths to pull a node to an asserted state during an ESD event. A node assertion path is any path that pulls a circuit node to the asserted state of the circuit node during an ESD event. Figure 2 As shown in FIG, signal UCM1 and signal LCM2 are in a low asserted state to indicate an ESD event. This pulls node 267 higher to make transistor 253 conductive to pull node 261 toward VSS (which is the asserted state of node 261) during an ESD event. In addition, transistor 251 is made conductive using the asserted high LMC1 signal to additionally pull node 261 toward VSS (the asserted state of node 261).

[0081] Furthermore, the use of current mirrors to generate additional detection signals may allow the amount of driver circuitry to be reduced. Figure 2 As shown in , because mirror 211 generates UMC1 and UMC2 signals that are considered complementary, opposite values ​​of the upper detection signal can be implemented without having to use additional cascaded inverter circuitry. For example, an upper detection signal (UCM1) having an asserted low state indicating an ESD event is provided to an inverter buffer stage of transistor 229, transistor 233, and transistor 235. An upper detection signal (UCM2) having an asserted high state indicating an ESD event is provided to an inverter buffer stage of transistor 237, transistor 239, and transistor 243 and an inverter buffer stage of transistor 237, transistor 239, and transistor 245.

[0082] Pulling node 261 toward the asserted state of node 261 using two node assertion paths allows driver circuit 203 to have a more "adjusted" response to ESD events, because different paths may have different response characteristics to ESD events. For example, during an ESD event, using LMC2 (and UCM1) to drive the inverter buffer stage output of transistor 229, transistor 233, and transistor 235 to make transistor 253 conductive to pull node 261 to VSS may have a stronger signal strength (which provides a stronger clamping conductivity). While the path of signal LCM1 driving transistor 251 toward VSS to pull node 261 is faster (without an intermediate inverter buffer stage). Therefore, using two node assertion paths to pull node 261 toward VSS and thereby drive the TRIG 1 signal allows the TRIG1 signal to have a faster component when being driven to the asserted state (from transistor 251), and also have a stronger drive signal strength (from the inverter of transistor 253) at a later time during the ESD event. This may cause the clamping device to become conductive faster in response to an ESD event, which reduces VDD stress during an earlier portion of the ESD event.

[0083] In addition, driver circuit 203 includes two asserted node paths for pulling node 241 toward VSS during an ESD event after transistor 240 is rendered non-conductive. One node asserted path is the path where signals LMC2 and UCM1 drive transistor 229, transistor 233, and inverter buffer stage output node 267 of transistor 235 to render transistor 243 conductive, and the other path is the path where signal LCM1 drives transistor 245 more conductive. In this example, both paths are used to pull node 241 more quickly toward the asserted VSS state of node 241 after the TRIG1 signal has been asserted.

[0084] After the ESD event has dissipated, the signals of the detection circuit 201 transition to the non-asserted states of the signals (UMC1 high, UCM2 low, LCM1 low, and LCM2 high) to place the nodes of the circuit 203 in a non-asserted state. For example, UCM2 goes to a low state and LCM2 goes to a high state driving transistor 237, transistor 239, and the inverter stage of transistor 243 to pull node 265 high to make transistor 262 non-conductive. Signal UMC1 and signal LCM2 go high to pull node 267 toward VSS, which makes transistor 253 non-conductive, allowing resistor 247 to pull node 261 high to pull the TRIG1 signal low to turn off clamp 111 (signal LCM1 transitions to a low voltage to make transistor 251 non-conductive).

[0085] In other embodiments, the driver circuit may have other configurations, operate in other ways, and / or may have other circuit systems. For example, although the driver circuit 203 is implemented with multiple inverter buffer stages, other embodiments may include amplifier stages and non-inverting buffer stages. In addition, the circuit system that receives the primary detection signals (UCM1 and LCM1) may actually receive the secondary detection signals (UCM2 and LCM2), and vice versa, where the circuit system includes appropriate inverter stages or is configured accordingly.

[0086] Figure 33 is a circuit diagram of another embodiment of the trigger circuit 121 according to the present invention. The detection circuit 301 includes a current mirror 311 and a current mirror 321. The current mirror 311 includes a master device 313 and a mirror device 315. During an ESD event, the current mirror generates an upper detection signal UMC1 that is asserted to be low and an upper detection signal UMC2 that is asserted to be high. The current mirror 321 includes a master device 323 and a mirror device 325, and during an ESD event, generates a lower detection signal LCM1 that is asserted to be high and a lower detection signal LCM2 that is asserted to be low. The detection circuit 301 also includes capacitors 317 and 319 and resistors 314 and 316. In one embodiment, the capacitors 317 and 319 are implemented as transistors in a capacitor configuration. Detection circuit 301 operates similarly to detection circuit 201, except that when the TRIG1 signal is deasserted, the node between resistor 314 and resistor 316 and the node between capacitor 317 and capacitor 319 are not biased to 1 / 2 VBB. In other embodiments of detection circuit 301, bias circuitry similar to the bias circuitry in 201 may be added to provide a 1 / 2 VBB bias to the node between resistor 314 and resistor 316 and the node between capacitor 317 and capacitor 319.

[0087] Driver circuit 303 includes trigger path circuitry for generating a TRIG2 signal and a TRIG1 signal to drive clamp 109 and clamp 111, respectively, during an ESD event. TRIG1 is generated by controlling the LCM2 signal of a series of inverting buffers (inverter 343, inverter 345, and inverter 347) and the LCM1 signal of a driver transistor 351. The TRIG2 signal is generated using a signal UMC2 that controls a series of inverting buffers (inverter 333 and inverter 335) and the UMC1 signal that drives transistor 337. In the illustrated embodiment, inverter 333, inverter 335, inverter 343, inverter 345, and inverter 347 have power terminals that are connected from the LCM2 signal. Figure 3 The bias circuit not shown in the figure is biased to 1 / 2 VBB.

[0088] exist Figure 3In the embodiment of the present invention, the driver circuit 303 includes two node assertion paths for pulling the voltage of the TRIG2 signal toward the asserted state (VBB) of the TRIG2 signal during an ESD event. During an ESD event, the path 331 of the inverter 333 and the inverter 335 pulls TRIG2 toward VBB in response to the UMC2 detection signal transitioning to a high state, and during an ESD event, the transistor 337 is made conductive in response to the UCM1 detection signal transitioning to an asserted low state. The latter path 339 (transistor 337) pulls the TRIG2 signal to the asserted state faster than the path 331 of the inverter 333 and the inverter 335 because the path 339 has fewer stages in the path. However, the path of the inverter 333 and the inverter 335 is slower but stronger and provides greater clamping conductivity in the later stages of an ESD event.

[0089] Driver circuit 303 also includes two assertion node paths when generating the TRIG1 signal. Asserting a low LCM2 signal controls inverters 343 and 345 to pull node 355 toward VSS during an ESD event. Asserting a high LCM1 signal makes transistor 351 conductive to pull node 355 to VSS during an ESD event. The paths of inverters 343 and 345 are stronger but slower paths when pulling node 355 toward VSS, but the node assertion path of transistor 351 is faster because the node assertion path includes fewer stages. In other embodiments, when the circuit is appropriately configured, circuit 303 can be configured so that path 331 and path 341 receive UCM1 and LCM1 signals, respectively, and transistor 337 and transistor 351 are configured to receive UCM2 and LCM2 signals, respectively.

[0090] Figure 4 4 is a circuit diagram of an ESD protection circuit 401 according to another embodiment of the present invention. The circuit 401 includes a detection circuit 402. The circuit 402 includes current mirrors 411 and 421, main devices 413 and 423, mirror devices 415 and 425, capacitors 417 and 419, and resistors 414 and 416, which are similar to Figure 3The corresponding device of the detection circuit 301 of the embodiment. The circuit 402 generates asserted high UCM2 and LCM1 detection signals and asserted low UCM1 and LCM2 detection signals in response to the ESD event. The circuit 401 includes a multi-stage stacked drive circuit 431 for providing multiple trigger signals (TRIG1-TRIGN) to the stack clamps (433, 435, 437 and 439). The drive circuit 431 may include an inverting buffer, a resistor, an amplifier and / or a non-inverting buffer (none of which is shown) implemented in a stacked configuration for providing the stacked trigger signals (TRIG1-TRIGN). During the ESD event, the drive circuit 431 pulls all the trigger signals (TRIG1-TRIGN) to the corresponding asserted states of all the trigger signals in response to the detection signals (UCM1, LCM1, UMC2 and LCM2) being in the corresponding asserted states of the detection signals. In the illustrated embodiment, when the detection circuit detects an ESD event and asserts all detection signals (UCM1, LCM1, UMC2, and LCM2), the driver circuit 431 pulls all trigger signals (TRIG1-TRIGN) high, as close to VBB as possible, to make the stacked NFET clamps (433, 435, 437, and 439) as conductive as possible. In the illustrated embodiment, during an ESD event, at least some of the trigger signals shown are generated in response to the detection signals with multiple node assertion paths for pulling the nodes of the trigger paths toward asserted voltages.

[0091] Figure 5 is a circuit diagram of an ESD protection circuit 501 according to another embodiment. The circuit 501 includes a detection circuit 503, which includes two current mirrors (not shown) for generating four detection signals UCM1, UCM2, LCM1 and LCM2 generated in a manner similar to the detection signals of the detection circuit 201, the detection circuit 301 or the detection circuit 402.

[0092] In the illustrated embodiment, the driver circuit 505 includes a plurality of trigger path partial sets 513-518, each trigger path partial set for providing parallel summed outputs to form a plurality of stacked trigger signals (TRIG1-TRIGN) that are summed in parallel to drive the stacked clamp 507 (with Figure 5 In the illustrated embodiment, each set of path portions includes an input that receives at least one of the four detection signals (UCM1, UCM2, LCM1, and LCM2) generated by the detection circuit 503.

[0093] Each trigger path portion set (513-518) can be adjusted to provide a signal with specific speed and intensity characteristics, which are combined with other signals of other path portion sets to provide each stacked trigger signal with an overall desired speed and intensity distribution, and accordingly provide an overall desired ESD response through circuit 501. Although each path portion set is shown as receiving all four of the detection signals, in some embodiments, some of the path portion sets may utilize less than all four detection signals when providing the signal of the path portion set. In addition, in some embodiments, some of the path portion sets (513-518) may share circuit systems with other path portion sets. For example, referring to Figure 3 , one signal path 341 for generating the TRIG1 signal includes an inverter 343 , an inverter 345 , and an inverter 347 , and another signal path 349 includes a transistor 351 and an inverter 347 .

[0094] In some embodiments, providing a detection circuit including a current mirror for generating multiple detection signals can enable the driver circuit to implement multiple node assertion paths for pulling the node toward the asserted state during an ESD event. Using multiple node assertion paths can provide a trigger signal that can have assertion signal parameters adjusted to desired values ​​of drive strength and speed throughout the ESD event. Such adjustment of the drive signal can provide a desired clamping conductivity and a desired VDD stress profile throughout the ESD event.

[0095] In one embodiment, the circuit includes a first current mirror, which is coupled to a first power rail and includes a master device and a mirror device. The first current mirror includes a first output from a current electrode of the master device of the first current mirror, the first output is configured to provide a first detection signal indicating an ESD event, and a second output from a current electrode of the mirror device of the first current mirror, the second output is configured to provide a second detection signal indicating an ESD event. The circuit includes a second current mirror, which is coupled to a second power rail and includes a master device and a mirror device. The second current mirror includes a first output from a current electrode of the master device of the second current mirror, the first output is configured to provide a third detection signal indicating an ESD event, and a second output from a current electrode of the mirror device of the second current mirror, the second output is configured to provide a fourth detection signal indicating an ESD event. The circuit includes a first trigger path, the first trigger path includes an input for receiving at least two detection signals of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and an output for providing a first trigger signal to a first ESD clamping device, wherein the first trigger signal is configured to start the first ESD clamping device in response to an ESD event. The first trigger signal is provided based on at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal. The circuit includes a second trigger path, the second trigger path including an input receiving at least another of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and an output providing a second trigger signal to a second ESD clamping device, wherein the second trigger signal is configured to activate the second ESD clamping device in response to an ESD event, wherein the second trigger signal is provided based on at least another of the first signal, the second signal, the third signal, and the fourth signal.

[0096] In another embodiment, the circuit includes a first current mirror, which is coupled to a first power rail and includes a master device and a mirror device. The first current mirror includes a first output from a current electrode of the master device of the first current mirror, the first output is configured to provide a first detection signal indicating an ESD event, and a second output from a current electrode of the mirror device of the first current mirror, the second output is configured to provide a second detection signal indicating an ESD event. The circuit includes a second current mirror, which is coupled to a second power rail and includes a master device and a mirror device. The second current mirror includes a first output from a current electrode of the master device of the second current mirror, the first output is configured to provide a third detection signal indicating an ESD event, and a second output from a current electrode of the mirror device of the second current mirror, the second output is configured to provide a fourth detection signal indicating an ESD event. The circuit includes a driver circuit system configured to provide a first trigger signal to a first ESD clamp device, wherein the first trigger signal is asserted during an ESD event to activate the first ESD clamp device, and provide a second trigger signal to a second ESD clamp device, wherein the second trigger signal is asserted during an ESD event to activate the second ESD clamp device. The driver circuit system includes a first node assertion path, the first node assertion path is configured to pull a voltage at a first circuit node in the driver circuit system to an asserted state of the first circuit node during an ESD event based on at least a first detection signal, a second detection signal, a third detection signal, and a fourth detection signal. The driver circuit system includes a second node assertion path, the second node assertion path is configured to pull a voltage at a second circuit node in the driver circuit system to an asserted state of the second circuit node during an ESD event based on at least a second detection signal of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal. The driver circuit system includes a third node assertion path, which is configured to pull a voltage at a third circuit node in the driver circuit system to an asserted state of the third circuit node during an ESD event based on at least a third detection signal among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal.

[0097] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from the present invention and its broader aspects, and therefore, the appended claims are intended to cover within the scope of the appended claims all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. A circuit, characterized in that: include: a first current mirror coupled to a first power rail and comprising a master device and a mirror device, the first current mirror comprising: a first output from a current electrode of the master device of the first current mirror, the first output configured to provide a first detection signal indicative of an ESD event; and a second output from a current electrode of the mirror device of the first current mirror, the second output configured to provide a second detection signal indicative of the ESD event; a second current mirror coupled to a second power rail and comprising a master device and a mirror device, the second current mirror comprising: a first output from a current electrode of the master device of the second current mirror, the first output configured to provide a third detection signal indicative of the ESD event; and a second output from a current electrode of the mirror device of the second current mirror, the second output configured to provide a fourth detection signal indicative of the ESD event; wherein a first output of the first current mirror is connected to a first output of the second current mirror through a first capacitor and a second capacitor, and a second output of the first current mirror is connected to a second output of the second current mirror through a first resistor and a second resistor; a first trigger path comprising an input receiving at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and an output providing a first trigger signal to a first ESD clamp device, wherein the first trigger signal is configured to enable the first ESD clamp device in response to the ESD event, wherein the first trigger signal is provided based on the at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal; and and a second trigger path comprising an input for receiving at least one other detection signal among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and an output for providing a second trigger signal to a second ESD clamping device, wherein the second trigger signal is configured to enable the second ESD clamping device in response to the ESD event, wherein the second trigger signal is provided based on the at least one other detection signal among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal.

2. The circuit according to claim 1, characterized in that The first trigger path includes: a series of buffers, wherein the series of buffers receive at least one detection signal of the at least two detection signals among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal, and outputs of the series of buffers are connected to an output node providing the first trigger signal; and A node assertion path is parallel to at least a portion of the series of buffers and includes an input receiving another detection signal of the at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal and includes an output coupled to a node of the series of buffers.

3. The circuit according to claim 2, characterized in that The first power rail is characterized by a voltage higher than a voltage of the second power rail, and wherein: The series of buffers receive the second detection signal; The input of the node assertion path of the first trigger path receives the first detection signal.

4. The circuit according to claim 2, characterized in that The first power rail is characterized by a voltage lower than a voltage of the second power rail, wherein: The series of buffers receive the second detection signal; The input of the node assertion path of the first trigger path receives the first detection signal.

5. The circuit according to claim 2, characterized in that The node assertion path of the first trigger path includes a device coupled between the first power rail and the node and controlled by the other detection signal of the at least two of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal, wherein the device is configured to pull the voltage of the node toward the voltage of the first power rail during the ESD event.

6. The circuit according to claim 1, characterized in that Also includes: a node assertion device comprising a first electrode coupled to a first circuit node of the first trigger path, a second current electrode coupled to the second power rail, and a control electrode coupled to receive the third detection signal or the fourth detection signal, wherein the first trigger path asserts the first trigger signal based on at least one of the first detection signal or the second detection signal.

7. A circuit, characterized in that: include: a first current mirror coupled to a first power rail and comprising a master device and a mirror device, the first current mirror comprising: a first output from a current electrode of the master device of the first current mirror, the first output configured to provide a first detection signal indicative of an ESD event; and a second output from a current electrode of the mirror device of the first current mirror, the second output configured to provide a second detection signal indicative of the ESD event; a second current mirror coupled to a second power rail and comprising a master device and a mirror device, the second current mirror comprising: a first output from a current electrode of the master device of the second current mirror, the first output configured to provide a third detection signal indicative of the ESD event; and a second output from a current electrode of the mirror device of the second current mirror, the second output configured to provide a fourth detection signal indicative of the ESD event; wherein a first output of the first current mirror is connected to a first output of the second current mirror through a first capacitor and a second capacitor, and a second output of the first current mirror is connected to a second output of the second current mirror through a first resistor and a second resistor; A driver circuit system configured to: provide a first trigger signal to a first ESD clamp device, wherein the first trigger signal is asserted during an ESD event to enable the first ESD clamp device; and provide a second trigger signal to a second ESD clamp device, wherein the second trigger signal is asserted during an ESD event to enable the second ESD clamp device, wherein the driver circuit system comprises: a first node assertion path configured to pull a voltage at a first circuit node in the driver circuitry to an asserted state of the first circuit node during an ESD event based on at least a first detection signal of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal; a second node assertion path configured to pull a voltage at a second circuit node in the driver circuitry to an asserted state of the second circuit node during an ESD event based on at least a second detection signal of the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal; and and a third node assertion path configured to pull a voltage of a third circuit node in the driver circuit system to an asserted state of the third circuit node during an ESD event based on at least a third detection signal among the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal.

8. The circuit according to claim 7, characterized in that: the first circuit node being at a control electrode of the first ESD clamp device, and the first node assertion path pulling the voltage of the first circuit node to an asserted state of the first circuit node during the ESD event based on the first detection signal or the second detection signal; the second circuit node and the first circuit node being the same circuit node, and the second node assertion path pulling the voltage of the first circuit node to an asserted state of the first circuit node during the ESD event based on at least the other of the first detection signal or the second detection signal; and The second trigger signal is responsive to the third circuit node assertion, and the third node assertion path pulls the voltage of the third circuit node to an asserted state of the third circuit node during the ESD event based on at least the third detection signal or a fourth detection signal.

9. The circuit according to claim 7, characterized in that: the first node assertion path comprising a first device including a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to receive one of the third detection signal or the fourth detection signal; the first circuit node and the second circuit node being the same circuit node, the second node asserting a path comprising a second device comprising a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to a node whose assertion state is dependent on the other of the third detection signal or the fourth detection signal; and The third node assertion path is configured to pull the voltage of the third circuit node in the driver circuitry to an asserted state of the third circuit node during the ESD event based on the first detection signal or the second detection signal, wherein the first trigger signal is responsive to at least the third circuit node assertion.

10. The circuit according to claim 7, characterized in that: the first node assertion path comprising a first device including a first current electrode coupled to the first circuit node, a second current electrode coupled to the second power rail, and a control electrode coupled to receive the third detection signal or the fourth detection signal, wherein the second trigger signal is responsive to at least the first circuit node assertion; the second circuit node and the first circuit node being the same circuit node, and the second node assertion path pulling the voltage of the first circuit node to an asserted state of the first circuit node during the ESD event based on at least the other of the third detection signal or the fourth detection signal; and The third node assertion path is configured to pull the voltage of the third circuit node in the driver circuitry to an asserted state of the third circuit node during the ESD event based on the first detection signal or the second detection signal, wherein the first trigger signal is responsive to the third circuit node assertion.

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