Buffer circuit and its application in switching power supply

Abstract

This invention discloses a buffer circuit applied in a flyback converter. The buffer circuit is connected in parallel with the rectifier circuit on the secondary side of the flyback converter. The buffer circuit is characterized in that it includes a capacitor configured to charge the primary power transistor of the flyback converter when the primary power transistor is turned on, and to discharge through the secondary winding of the transformer when the primary power transistor is turned off to reduce the leakage inductance energy of the primary winding, thereby reducing the peak voltage on the secondary side and improving the efficiency of the flyback converter.

Description

Technical Field

[0001] This invention relates to power electronics technology, and more specifically, to a buffer circuit and a switching power supply using the same. Background Technology

[0002] To address the voltage spikes generated by the leakage inductance of the transformer secondary winding, there are two existing technical solutions: one is to use a secondary diode with a higher reverse withstand voltage instead of a snubber circuit; the other is to connect an RC snubber circuit in parallel with the secondary diode, see [link to technical solution]. Figure 1 R2 and C2 in the diagram. Lpk is the primary leakage inductance, Lsk is the secondary leakage inductance, and Ls is the secondary winding. Below are the working principles, advantages, and disadvantages of two existing technical solutions.

[0003] refer to Figure 1 When using a diode with a higher reverse withstand voltage, the secondary diode D2 has an internal junction capacitance Cd. When the primary power transistor M1 is turned on, the voltage at point LX decreases, and the voltage at the anode of the secondary diode D2 decreases. The junction capacitance Cd is charged by the output capacitor Cout, and the charging current loop is: Cout - Cd - Lsk - Ls - SGND - Cout, where SGND is the secondary ground. During the charging process of the junction capacitance Cd, the junction capacitance Cd and the secondary leakage inductance Lsk are connected in series. When the voltage at point LX drops to 0V, the voltage at the anode of the secondary diode D2 drops to (-Vbus*Ns / Np), where Vbus is the DC bus voltage and Ns / Np is the turns ratio of the primary and secondary sides of transformer T. Under the freewheeling effect of Lsk, the charging current continues to pull down the voltage at the anode of the secondary diode D2. After several cycles of oscillation, the voltage at the anode of the secondary diode D2 stabilizes at (-Vbus*Ns / Np). The presence of the transformer secondary leakage inductance Lsk causes the secondary diode D2 to withstand a higher reverse spike voltage, which will worsen the EMI performance of the switching power supply. Only diodes with higher withstand voltage can be selected for the secondary side, which will sacrifice efficiency and increase cost.

[0004] When the secondary diode D2 is connected in parallel with an RC snubber circuit, Figure 1 As shown, the capacitance of the parallel capacitor C2 is much larger than the junction capacitance Cd. When the primary power transistor M1 is turned on, C2 will also be charged, and the charging effect is much greater than that of Cd. The presence of the series resistor R2 dampens the series resonance behavior of the secondary leakage inductance Lsk, effectively reducing the voltage spikes caused by the leakage inductance. However, the series resistor will generate power consumption and reduce efficiency. Regarding the voltage spikes in the transformer secondary winding, the two existing technical solutions have obvious drawbacks: they increase the cost of the power supply, reduce its efficiency, and are not conducive to the miniaturization of power supply products. Summary of the Invention

[0005] In view of this, the present invention provides a buffer circuit to solve the problem of low efficiency of existing buffer circuits.

[0006] In a first aspect, a buffer circuit is provided for use in a flyback converter, wherein the buffer circuit is connected in parallel with the rectifier circuit on the secondary side of the flyback converter, characterized in that the buffer circuit comprises:

[0007] A capacitor is configured to charge the primary power transistor of the flyback converter when the primary power transistor is turned on, and to discharge through the secondary winding of the transformer when the primary power transistor is turned off, thereby reducing the leakage inductance energy of the primary winding and improving the efficiency of the flyback converter while reducing the peak voltage on the secondary side.

[0008] Preferably, the capacitor resonates with the leakage inductance of the transformer secondary winding, and its discharge circuit does not pass through a resistive element.

[0009] Preferably, the rectifier circuit is a secondary diode or a synchronous rectifier circuit.

[0010] Preferably, the buffer circuit is composed of the capacitor, which is connected in parallel with the rectifier circuit.

[0011] Preferably, the rectifier circuit is connected between one end of the secondary winding and the secondary ground.

[0012] Preferably, the buffer circuit includes the capacitor, the buffer resistor, and the buffer diode, wherein the buffer resistor and the buffer diode are connected in parallel and then connected in series with the capacitor.

[0013] Preferably, the charging current of the capacitor passes through the buffer resistor, and the discharging current of the capacitor does not pass through the buffer resistor.

[0014] Preferably, the connection direction of the buffer diode is the same as that of the secondary diode.

[0015] Preferably, the anode of the buffer diode is connected to the source of the synchronous rectifier in the synchronous rectifier circuit, or the cathode of the buffer diode is connected to the drain of the synchronous rectifier.

[0016] Preferably, the buffer diode is a fast recovery diode.

[0017] In a second aspect, a switching power supply is provided, characterized in that it comprises:

[0018] The power stage circuitry is configured as a flyback converter, and...

[0019] The aforementioned buffer circuit.

[0020] The secondary-side buffer circuit of this invention reduces losses by preventing the discharge current of the buffer capacitor from passing through the buffer resistor. Specifically, by directly connecting a buffer capacitor in parallel on the secondary side, or by connecting a buffer diode in parallel with the buffer resistor, not only can the series-connected buffer resistor dampen the resonant behavior of the leakage inductance and reduce voltage spikes, but also, due to the presence of the buffer diode, when the buffer capacitor is charging, the buffer diode does not conduct in reverse, and the buffer resistor can still play a role in damping resonance; when the buffer capacitor is discharging, the buffer diode conducts in forward, short-circuiting the buffer resistor, so that the discharge current of the buffer capacitor and the excitation current of the transformer no longer pass through the buffer resistor, thereby improving efficiency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a switching power supply using a buffer circuit in the prior art;

[0023] Figure 2 A schematic diagram of a switching power supply employing a buffer circuit according to the first embodiment of the present invention;

[0024] Figure 3 A schematic diagram of a switching power supply employing a buffer circuit according to a second embodiment of the present invention;

[0025] Figure 4 A schematic diagram of a switching power supply employing a buffer circuit according to a third embodiment of the present invention;

[0026] Figure 5 A schematic diagram of a switching power supply employing a buffer circuit according to the fourth embodiment of the present invention;

[0027] Figure 6 A schematic diagram of a switching power supply employing a buffer circuit according to the fifth embodiment of the present invention;

[0028] Figure 7 A schematic diagram of a switching power supply employing a buffer circuit according to the sixth embodiment of the present invention;

[0029] Figure 8 A schematic diagram of a switching power supply employing a buffer circuit according to the seventh embodiment of the present invention;

[0030] Figure 9 This is an efficiency comparison table. Detailed Implementation

[0031] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0032] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0033] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0034] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0035] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0036] Figure 2 A schematic diagram of a switching power supply employing a buffer circuit according to a first embodiment of the present invention is shown. The switching power supply includes a power stage circuit and a control circuit (not shown in the figure). The power stage circuit is a flyback topology, including a primary winding Lp and a primary power transistor M1 connected in series between the voltage input terminal Vbus and the ground terminal, a secondary winding Ls coupled to the primary winding Lp, and a rectifier circuit 20 connected to the secondary winding Ls. In this embodiment, the rectifier circuit 20 is a secondary diode or a synchronous rectifier circuit. Furthermore, the power stage circuit also includes a primary leakage inductance Lpk and a secondary leakage inductance Lsk. The power stage circuit can obtain the output voltage information, the zero-crossing time of the current in the secondary winding Ls, and the current valley time information through auxiliary windings or other means. Based on the above information, the primary power transistor M1 is controlled to obtain the required output voltage or output current.

[0037] According to Figure 1Analysis shows that the presence of the transformer secondary leakage inductance Lsk causes the secondary diode D2 or synchronous rectifier circuit to withstand higher reverse spike voltages, which degrades the EMI performance of the switching power supply. This necessitates the selection of higher voltage-rated diodes or transistors on the secondary side, sacrificing efficiency and increasing cost. In existing solutions, while the series resistor R2 in the RC snubber circuit dampens the series resonance behavior of the secondary leakage inductance Lsk and effectively reduces the spike voltage caused by the leakage inductance, the series resistor also generates power dissipation, reducing efficiency.

[0038] Based on this, the solution proposed in this invention is that the buffer circuit includes a capacitor. The capacitor is configured such that when the primary power transistor M1 of the flyback converter is turned on, the output capacitor Cout charges it. When the primary power transistor M1 is turned off, the capacitor discharges through the secondary winding Ls of the transformer to reduce the leakage inductance energy of the primary winding Lp, thereby reducing the peak voltage on the secondary side and improving the efficiency of the flyback converter. Specifically, a buffer circuit is connected in parallel across the secondary diode or synchronous rectifier circuit. The buffer circuit includes a capacitor that resonates with the leakage inductance Lsk of the secondary winding Ls of the transformer, and the discharge path of the capacitor does not pass through a resistive element.

[0039] Specifically, the first solution involves a buffer circuit consisting solely of a capacitor, specifically a buffer capacitor C2. This buffer capacitor C2 is directly connected in parallel with the secondary diode of the flyback converter or the synchronous rectifier diode of the synchronous rectifier circuit. Figure 2 As shown. The principle behind how the technology of this invention can reduce losses is analyzed below:

[0040] When the primary-side power transistor M1 is turned on, the voltage at point A on the left side of rectifier circuit 20 drops. At this time, rectifier circuit 20 is in the off state, and buffer capacitor C2 is charged by output capacitor Cout. The charging circuit is as follows: Figure 2 As indicated by the solid arrow in the middle.

[0041] When the primary-side power transistor M1 is turned off, the voltage at point A rises, and the buffer capacitor C2 discharges to the output capacitor Cout. The discharge circuit is as follows: Figure 2 As indicated by the dashed arrow. Specifically, the working states are as follows, in chronological order:

[0042] (1) The voltage at point LX on the primary side starts to rise from 0V, and the voltage at point A on the secondary side starts to rise from (-Vbus*Ns / Np), where Vbus is the DC bus voltage and Ns / Np is the turns ratio of the primary and secondary sides of transformer T. The primary current flows through the primary winding Lp, the primary leakage inductance Lpk, the LX node, and the parasitic capacitance to the primary ground; the secondary buffer capacitor C2 begins to discharge, and the discharge current path is as follows. Figure 2As shown by the dashed arrow, current flows through the secondary winding Ls. When the secondary winding Ls is reverse-biased, the magnetizing current of the transformer T is carried to the secondary winding Ls, generating the magnetizing current that first appears on the secondary winding Ls. During this process, the discharge path of the buffer capacitor C2 does not pass through a resistive load. Therefore, the magnetizing current carried to the secondary winding Ls by the discharge current of the buffer capacitor C2 is larger, resulting in lower primary leakage inductance loss. Furthermore, compared to existing technologies, there is no heat loss from the buffer resistor itself, thus improving efficiency.

[0043] (2) When the voltage at point LX rises to Vbus+Vor, where the reflected voltage Vor=(Vo+Vf)*Np / Ns, and Vf is the forward conduction voltage drop of the secondary diode; when the voltage at point A rises to Vo+Vf, the voltage of the secondary winding Ls has been established. On the primary side of transformer T, the DC bus voltage Vbus no longer generates excitation current, and the magnetic field energy (excitation current) of transformer T continues to charge the parasitic capacitance of node LX, and the voltage at point LX continues to rise; on the secondary side of transformer T, the secondary current charges the output capacitor Cout through rectifier circuit 20.

[0044] (3) When the voltage at point LX rises to Vclamp, where Vclamp is the clamping voltage (i.e., the voltage between the negative terminal of diode D1 and the primary side ground), on the primary side of transformer T, diode D1, the first capacitor C1, and the first resistor constitute the buffer circuit of the primary side. Diode D1 is forward-biased, and the primary side current flows through the primary winding Lp, the primary leakage inductance Lpk, the LX node, and diode D1 and the first capacitor C1 to the DC bus voltage Vbus. At this time, the secondary winding Ls is already conducting, and the voltage of the primary winding Lp is clamped at the reflected voltage Vor. The voltage applied to the primary leakage inductance Lpk is Vclamp - Vbus - Vor, and the energy of the primary leakage inductance Lpk begins to be stored in the first capacitor C1. The secondary current of transformer T is shown in ② / ③. The secondary current charges the output capacitor Cout through the rectifier circuit 20.

[0045] (4) When the current of the primary leakage inductance Lpk drops to 0, the excitation current of the primary side of transformer T drops to 0. Diode D1 has a reverse recovery time Trr. During Trr, diode D1 remains in the conducting state. At this time, Vclamp>Vbus+Vor, and the first capacitor C1 begins to discharge to the primary leakage inductance Lpk and the primary winding Lp. When this current passes through the primary winding Lp, transformer T is in forward mode, and energy is sent to the secondary winding Ls, which charges the output capacitor Cout through the rectifier circuit 20.

[0046] (5) After the reverse recovery time Trr of diode D1 ends, the current in the primary winding Lp returns to zero, the transformer T completes the transition state, and the excitation current is transmitted to the secondary winding Ls.

[0047] In summary, the buffer capacitor C2 is charged by the output capacitor Cout when the primary power transistor M1 is turned on, and discharges to the output capacitor Cout when the primary power transistor M1 is turned off. In step (1), when the buffer capacitor C2 discharges, the current flows through the secondary winding Ls. Since the discharge current does not pass through the resistive element, a larger portion of the excitation current is carried to the secondary winding Ls, reducing the energy stored in the primary leakage inductance Lpk, thus improving efficiency. Furthermore, efficiency is further improved in subsequent steps.

[0048] Figure 3 The schematic diagram of the switching power supply with a buffer circuit according to the second embodiment of the present invention differs from that of the first embodiment only in that the rectifier circuit is connected between one end of the secondary winding Ls and the secondary ground, that is, the rectifier circuit is connected to the low potential side of the secondary side, which helps to simplify the driving circuit of the synchronous rectifier tube in the rectifier circuit.

[0049] The second solution provided by this invention, such as a buffer circuit, is as follows: Figure 5 The schematic diagram shown is of a switching power supply employing a buffer circuit according to a fourth embodiment of the present invention. The buffer circuit includes a capacitor, a buffer resistor R2, and a buffer diode D3, where the capacitor is a buffer capacitor C2. The buffer resistor R2 and the buffer diode D3 are connected in parallel, and then connected in series with the buffer capacitor C1. Preferably, the buffer diode D3 is configured as a fast recovery diode. Specifically, when the rectifier circuit is a synchronous rectifier circuit, the source of the synchronous rectifier diode in the synchronous rectifier circuit is connected to the secondary winding Ls, and the drain is connected to the high-voltage terminal of the output voltage Vout. More specifically, the anodes of the buffer resistor R2 and the buffer diode D3 are connected together to the source of the synchronous rectifier diode, and the cathodes of the buffer resistor R2 and the buffer diode D3 are connected together to one end of the buffer capacitor C2. The other end of the buffer capacitor C2 is connected to the drain of the synchronous rectifier diode. This arrangement ensures that the charging current of the buffer capacitor C2 passes through the buffer resistor R2, and the discharging current of the buffer capacitor C2 does not pass through the buffer resistor R2, but instead short-circuits the buffer resistor R2 through the buffer diode D3.

[0050] To address the leakage inductance spike voltage on the secondary side of a transformer, a second existing technical solution employs an RC snubber circuit. This involves using a snubber resistor R2 and a snubber capacitor C2 to buffer and dampen the series resonance, thus achieving the effect of buffering the spike voltage. However, this solution sacrifices efficiency by connecting the snubber resistor R2 in series in the charging and discharging circuit of C2. The second technical solution of this invention connects a snubber diode D3 in parallel with the snubber resistor R2 to form a snubber circuit on the secondary side, as described in [link to invention]. Figure 5This circuit maintains the damping effect for series resonance while optimizing efficiency. Specifically, when the buffer capacitor C2 is charging, the buffer diode D3 is reverse-biased and does not conduct, thus not affecting the damping effect. When the buffer capacitor C2 is discharging, the buffer diode D3 conducts forward, and the buffer resistor R2 is short-circuited. This results in a larger excitation current carried to the secondary winding Ls by the discharge current of the buffer capacitor C2, and a smaller primary leakage inductance loss. At the same time, the short-circuiting of the buffer resistor R2 by the buffer diode D3 itself reduces heat loss, thereby improving efficiency.

[0051] Figure 6 The schematic diagram of the switching power supply with a buffer circuit according to the fifth embodiment of the present invention differs from that of the fourth embodiment only in that the rectifier circuit is connected between one end of the secondary winding Ls and the secondary ground, that is, the rectifier circuit is connected to the low potential side of the secondary winding. All other parts are the same and will not be described again here.

[0052] Figure 7 The schematic diagram of the switching power supply with a buffer circuit according to the sixth embodiment of the present invention differs from that of the fifth embodiment only in that the synchronous rectification circuit is replaced by a secondary diode D2, and the secondary diode D2 is also connected between one end of the secondary winding Ls and the secondary ground. All other parts are the same and will not be described again here. (See reference...) Figure 7 It can be seen that the connection direction of the buffer diode D3 is the same as that of the secondary diode D2. Specifically, the anode of the buffer diode D3 is directly connected to the anode of the secondary diode D2, or the cathode of the buffer diode D3 is directly connected to the cathode of the secondary diode D2. In this embodiment of the invention, the buffer resistor R2 and the cathode of the buffer diode D3 are both connected to the cathode of the secondary diode D2, the buffer resistor R2 and the anode of the buffer diode D3 are both connected to one end of the buffer capacitor C2, and the other end of the buffer capacitor C2 is connected to the anode of the secondary diode D2.

[0053] Figure 8 The schematic diagram of the switching power supply employing a buffer circuit according to the seventh embodiment of the present invention differs from that of the sixth embodiment only in the change of the positional relationship of the components in the buffer circuit. All other parts are the same and will not be described again here. Specifically, in the buffer circuit, the buffer capacitor C2 is placed to the left of the buffer resistor R2 and the buffer diode D3. It is understood that this change does not affect the operation of the buffer circuit; it only changes the order in which the charging and discharging current of the buffer capacitor flows through the circuit components.

[0054] Figure 9This table compares the efficiency of the technical solutions of this invention with those of existing technologies. Existing technology solution 1 uses a diode or synchronous rectifier with higher reverse withstand voltage, or existing technology solution 2 connects an RC resistor in parallel on the secondary side to buffer leakage inductance spike voltage. It is evident that the parallel buffering solutions in the prior art can improve efficiency to some extent, but the series buffer resistor generates power consumption, resulting in a limited improvement in efficiency. The two technical solutions provided by this invention address this problem: first, by directly connecting a buffer capacitor in parallel on the secondary side, the discharge current of the capacitor carries a portion of the excitation current to the secondary side, reducing the energy stored in the primary leakage inductance and thus improving efficiency; second, by connecting a buffer diode in parallel with the buffer resistor, upgrading the RC buffer circuit on the secondary side to an RCD buffer, which can both buffer leakage inductance spike voltage and reduce the loss of the series resistor, thereby improving the power supply conversion efficiency.

[0055] As can be seen, the secondary-side buffer circuit of this invention reduces losses by preventing the discharge current of the buffer capacitor from passing through the buffer resistor. Specifically, by directly connecting a buffer capacitor in parallel on the secondary side, or by connecting a buffer diode in parallel with the buffer resistor, not only can the series-connected buffer resistor dampen the resonant behavior of the leakage inductance and reduce voltage spikes, but also, due to the presence of the buffer diode, when the buffer capacitor is charging, the buffer diode does not conduct in reverse, and the buffer resistor can still play a role in damping resonance; when the buffer capacitor is discharging, the buffer diode conducts in forward, short-circuiting the buffer resistor, so that the discharge current of the buffer capacitor and the excitation current of the transformer no longer pass through the buffer resistor, thereby improving efficiency.

[0056] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A snubber circuit applied in a flyback converter, the snubber circuit being connected in parallel with a rectifier circuit of a secondary side of the flyback converter, characterized in that, The buffer circuit comprises: The capacitor device is configured to output a capacitance for charging when a primary power tube of the flyback converter is turned on, and discharge through a secondary winding of a transformer to reduce leakage energy of the primary winding when the primary power tube is turned off, thereby reducing the peak voltage of the secondary winding while improving the efficiency of the flyback converter; The buffer circuit further comprises a buffer resistor and a buffer diode, wherein the buffer resistor and the buffer diode are connected in parallel, and then connected in series with the capacitor device; The charging circuit of the capacitor device passes through a resistive element, and the discharging circuit of the capacitor device does not pass through a resistive element.

2. The snubber circuit of claim 1, wherein, The capacitor device resonates with the leakage inductance of the secondary winding of the transformer.

3. The snubber circuit of claim 1, wherein, The rectifier circuit is a secondary diode or a synchronous rectifier circuit.

4. The snubber circuit of claim 2, wherein, The buffer circuit is composed of the capacitor device, and the capacitor device is connected in parallel with the rectifier circuit.

5. The snubber circuit of claim 3, wherein, The rectifier circuit is connected between one end of the secondary winding and the secondary ground.

6. The snubber circuit of claim 1, wherein, The charging current of the capacitor device passes through the buffer resistor, and the discharging current of the capacitor device does not pass through the buffer resistor.

7. The snubber circuit of claim 3, wherein, Wherein, The connection direction of the buffer diode is the same as that of the secondary diode.

8. The snubber circuit of claim 3, wherein, The anode of the buffer diode is connected to the source of the synchronous rectifier tube in the synchronous rectifier circuit, or the cathode of the buffer diode is connected to the drain of the synchronous rectifier tube.

9. The snubber circuit of claim 1, wherein, The buffer diode is a fast recovery diode.

10. A switching power supply, characterized by Comprise: A power stage circuit configured as a flyback converter, and the buffer circuit of claim 1.

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