Leakage compensation circuit and corresponding method, integrated circuit having a leakage compensation circuit

Abstract

The invention relates to a leakage compensation circuit and a method for leakage compensation, and an integrated circuit having the leakage compensation circuit. In one form, the leakage compensation circuit comprises a buffer amplifier, a link coupling element and a leakage compensation element. The buffer amplifier has an output and an input coupled to a sense node. The link coupling element has an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to its output. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to integrated circuits, and more particularly to a leakage compensation circuit for use in an integrated circuit, and a method for leakage compensation. BACKGROUND

[0002] Certain environmental sensors, such as rain and light sensors, ambient light sensors, laser ranging and distance (LiDAR) sensors, and the like, require very high dynamic range at their inputs. For example, they can produce sensing currents on the order of 50 pico-ampere (pA) or less. While integrated circuit and radio frequency (RF) noise can be reduced by choosing an appropriate circuit topology or by increasing the current consumption of the sensor, direct current (DC) offsets caused by leakage currents generated on the integrated circuit are still very difficult to compensate. For example, integrated circuit input terminals are typically protected by diodes that inject leakage currents onto various circuit nodes. These DC offset currents significantly limit the achievable gain, limiting the input range, and can actually completely block some small signals from being detectable.

[0003] While DC offset voltages can be removed by chopping mechanisms with differential circuit structures, DC leakage currents are typically single-ended. In addition, while DC offset voltages can be removed by storing the offset voltage using a switched capacitor mechanism, currents cannot be stored. Furthermore, leakage currents are typically very small and it is practically impossible to compensate for them by any known current digital-to-analog converter (DAC) because the currents are too low to be handled using current mirrors. Bi-directional current DACs based on a reference leakage current and single-ended current DACs with optional current mirrors have proven insufficient to compensate for these small leakage currents. Thus, leakage currents, which are an inherent feature of integrated circuit design, limit the dynamic range of the sensors. SUMMARY

[0004] In one aspect, the present invention provides a leakage compensation circuit, comprising: a buffer amplifier having an output and an input coupled to a sense node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

[0005] In another aspect, the invention provides an integrated circuit having a leakage compensation circuit, the leakage compensation circuit comprising: a buffer amplifier having an output and an input coupled to a sense node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

[0006] In another aspect, the invention provides a method of performing leakage compensation for a leakage current into or out of a sense node, comprising: buffering a voltage on the sense node, and providing a buffer voltage to an intermediate node in response to the buffering; unidirectionally coupling the buffer voltage to a control node; and biasing a leakage compensation element having a first current terminal coupled to the sense node and a second current terminal coupled to a reference voltage terminal by coupling a control terminal of the leakage compensation element to the control node. BRIEF DESCRIPTION OF DRAWINGS

[0007] The disclosure can be better understood, and its numerous features and advantages can become apparent to those skilled in the art by reference to the following drawings, in which:

[0008] Figure 1 A sensor circuit susceptible to leakage is shown in block diagram form;

[0009] Figure 2 Leakage compensation circuits according to various embodiments are shown in partial block and partial schematic form;

[0010] Figure 3 A buffer amplifier according to another embodiment of the buffer amplifier of Figure 2 is shown in partial block and partial schematic form;

[0011] Figure 4 A buffer amplifier according to yet another embodiment of the buffer amplifier of Figure 2 is shown in partial block and partial schematic form;

[0012] Figure 5 A buffer amplifier according to yet another embodiment of the buffer amplifier of Figure 2 is shown in partial block and partial schematic form;

[0013] Figure 6 A link coupling element according to another embodiment of the link coupling element of Figure 2 is shown in schematic form;

[0014] Figure 7Another embodiment of a link coupling element is shown in schematic form, according to Figure 2 Another embodiment of a link coupling element is shown in schematic form, according to

[0015] Figure 8 Portions of a leakage compensation circuit according to other embodiments are shown in partial block and partial schematic form;

[0016] Figure 9 A set of related graphs showing relationships of signals related to operation of a leakage compensation circuit according to Figure 2

[0017] Figure 10 A cross-section of an integrated circuit that can be used to implement a portion of a leakage compensation circuit according to Figure 2

[0018] Figure 11 A cross-section of another integrated circuit that can be used to implement a portion of a leakage compensation circuit according to Figure 2

[0019] Figure 12 A cross-section of yet another integrated circuit that can be used to implement a portion of a leakage compensation circuit according to Figure 2

[0020] Figure 13 A cross-section of yet another integrated circuit that can be used to implement a portion of a leakage compensation circuit according to Figure 2

[0021] Figure 14 A cross-section of yet another integrated circuit that can be used to implement a portion of a leakage compensation circuit according to Figure 2

[0022] The same reference symbols are used in different drawings to indicate the same or similar elements. Unless otherwise noted, the word coupled and its associated verb forms mean both direct connection and indirect electrical connection through known means; and unless otherwise noted, any reference to direct connection implies the alternative embodiment using indirect electrical connection through suitable forms. DETAILED DESCRIPTION

[0023] Figure 1 ​​​​​​A sensor circuit 100 that is susceptible to leakage is shown in block diagram form. The sensor circuit 100 includes a sensor 110, a sense node 120 labeled "SENSE," a transimpedance amplifier 130, and an integrated circuit terminal 140. The sensor 110 has an output for providing a current to the sense node 120 in response to sensing one of a variety of environmental conditions, such as rain, light, ambient light, etc. The transimpedance amplifier 120 has an input connected to the sense node 120, and an output connected to the integrated circuit terminal 140 for providing a voltage labeled "V OUT " and an associated transimpedance labeled "1 / gm" thereto.

[0024] Certain non-ideal factors distort the operation of the sensor 110 and reduce its dynamic range. For example, a direct current (DC) offset caused by a relatively small leakage current of unknown sign is still very difficult to compensate. Figure 1 Two possible leakage currents that can affect the operation of the sensor 110 are shown. One possible leakage current, labeled "ILEAK_PUSH," represents a positive current that is injected (or "pushed") onto the sense node 120. The other possible leakage current, labeled "ILEAK_PULL," represents a positive current that is drawn (or "pulled") from the sense node 120. In many integrated circuits, these small currents cannot be easily estimated or measured in advance, and even the direction of the leakage current is not easily predictable, making them very difficult to compensate.

[0025] A DC offset voltage can be removed by a chopping mechanism. However, a chopping mechanism cannot be used to compensate for a DC leakage current because it typically involves a differential structure, while a DC leakage current is single-ended. In addition, while a DC offset voltage can be removed by storing the offset voltage using a switched capacitor circuit, a leakage current cannot be stored. Furthermore, since leakage currents are typically very small, they are practically impossible to be compensated by any other known circuit, such as a current digital-to-analog converter (DAC).

[0026] Figure 2 A leakage compensation circuit 200 according to various embodiments is shown in partial block and partial schematic form. The leakage compensation circuit 200 generally includes a buffer amplifier 210, a link coupling element 220, and a leakage compensation element 230. The buffer amplifier 210 has an input connected to the SENSE node and an output connected to a node labeled "CTRL." The link coupling element 220 has an input connected to the output of the buffer amplifier 210 and an output connected to a node labeled "MID." The leakage compensation element 230 has a first current terminal connected to the SENSE node, a control terminal connected to the MID node, and a second current terminal connected to a reference voltage terminal labeled "REF."

[0027] InFigure 2 In the illustrated embodiment, buffer amplifier 210 includes a differential amplifier 212, a variable offset generator 214, and an offset circuit 216. Differential amplifier 212 has a positive input labeled "+", a negative input labeled "-", and an output connected to its negative input for providing an output voltage to the CTRL node. Variable offset generator 214 has a negative terminal connected to the SENSE node, a digital control input, and a positive terminal connected to the positive input of differential amplifier 212. Offset circuit 216 has an output connected to the digital control input of variable offset generator 214 for providing a multi-bit digital signal labeled "TRIM". Link coupling element 220 includes a PN junction diode 222 having an anode forming the input of link coupling element 220 and a cathode forming the output of link coupling element 220. Leakage compensation element 230 includes an anti-series diode having a PN junction diode 232 and a PN junction diode 234. PN junction diode 232 is a "top" diode having an anode connected to the SENSE node and a cathode connected to the MID node. The PN junction diode 232 is a "bottom" diode with a cathode connected to the MID node and an anode connected to the REF terminal.

[0028] In operation, the leakage compensation circuit 200 subtracts (pulls) or adds (pulls) the name of the SENSE node flowing out or into it, which is "I". COMP The controlled compensation leakage current is used to compensate for the leakage current at the SENSE node. This will be explained further below, due to I... COMP The property is also the node leakage current, therefore I is expected to be... COMP The general behavior above temperature is similar to that of existing leakage currents. Furthermore, the leakage compensation circuit 200 controls the exact amount of compensation current and its indication by applying a voltage to the leakage compensation element 230.

[0029] In the leakage compensation circuit 200, a buffer amplifier 210 is connected in a voltage follower configuration, wherein the output provided to the CTRL node is equal to the voltage at the SENSE node plus the offset voltage V. OS Offset voltage V OSThe digital trim signal TRIM provided by the offset circuit 216 is then set by the digital correction signal TRIM. The link coupling element 220 is a diode that conducts current in the direction from input to output when the voltage across the PN junction is forward biased. Because the magnitude of the forward current is substantially larger than the magnitude of the reverse saturation current around the turn-on voltage, e.g., by more than three orders of magnitude, the link coupling element 220 is considered a unidirectional element. Thus, the PN junction diode 222 is a link coupling element that can conduct more current in one direction (forward) than in the other direction (reverse) and sets the voltage on the MID node. Through the feedback control loop formed by the buffer amplifier 210, the link coupling element 220, and the leakage compensation element 230, the leakage compensation circuit 200 provides a compensation current I COMP that precisely matches the leakage current.

[0030] More details of various implementations of the components of the leakage compensation circuit 200 will now be presented.

[0031] Implementation of buffer amplifier 210

[0032] Figure 3 A further implementation of the buffer amplifier 210 according to Figure 2 is shown in the form of a partial block diagram and a partial schematic diagram of a buffer amplifier 300. The buffer amplifier 300 includes a differential amplifier 212 and an offset circuit 216 as previously described with respect to Figure 2 However, unlike the buffer amplifier 210, the buffer amplifier 300 includes a variable offset generator 314 configured differently than the variable offset generator 214 of Figure 2 The variable offset generator 314 has a positive terminal connected to the output of the differential amplifier 212, a digital control input connected to the output of the offset circuit 216 for receiving the TRIM signal therefrom, and a negative terminal connected to the negative input of the differential amplifier 212. Thus, the variable offset generator, Figure 2 of 214 or Figure 3 of 314 can achieve the same result by being connected to the positive input of the differential amplifier 212 or the negative input of the differential amplifier 212.

[0033] Figure 4 Yet another implementation of the buffer amplifier 210 according to Figure 2 is shown in the form of a partial block diagram and a partial schematic diagram of a buffer amplifier 400. The buffer amplifier 400 includes a differential amplifier 212 and an offset circuit 216 as previously described with respect to Figure 2 However, unlike the buffer amplifier 210, the buffer amplifier 400 includes a variable offset generator 414 configured differently than the variable offset generator 214 of Figure 2The variable offset generator 214 is configured differently from the variable offset generator 414. The variable offset generator 414 has a negative terminal connected to the output of the differential amplifier 212, a control input connected to the output of the offset circuit 216 for receiving a TRIM signal from it, and a positive terminal connected to the CTRL node. The buffer amplifier 400 demonstrates that the same result can be achieved by connecting the variable offset generator 414 to the output of the differential amplifier 212.

[0034] Figure 5 The diagram is shown in the form of a partial block diagram and a partial schematic diagram. Figure 2 Another embodiment of the buffer amplifier 210 is a buffer amplifier 500. The buffer amplifier 500 includes, as described above, a buffer amplifier relative to... Figure 2 The differential amplifier 212 and offset circuit 216 are described above. However, unlike the buffer amplifier 210, the buffer amplifier 500 includes... Figure 2 The variable offset generator 214 is configured differently from the variable offset generator 514. The variable offset generator 514 includes a resistor 510, and current DACs 520 and 530, each labeled "IDAC". Resistor 510 has a first terminal connected to the output of differential amplifier 212 and a second terminal connected to the CTRL node. Current DAC 520 has a first current terminal connected to the power supply voltage terminal, a control input connected to the output of offset circuit 216 for receiving the TRIM signal, and a second current terminal connected to the CTRL node to supply current to the CTRL node. Current DAC 530 has a first terminal connected to the CTRL node for drawing current from the CTRL node, a control input connected to the output of offset circuit 216 for receiving the TRIM signal, and a second current terminal connected to ground. Because the control terminal of leakage compensation element 230 is a high-impedance node, the current flowing through resistor 510 supplied by current DACs 520 and 530 produces the desired voltage offset, the magnitude of which is determined by the TRIM signal.

[0035] from Figures 2-5 As will be apparent from the various examples shown, the offset voltage can be generated in various ways and various circuits can be used. The offset circuit 216 can also determine the value of the TRIM signal in various ways. For example, the value of the TRIM signal can be calibrated for each chip during manufacturing testing, and the offset circuit 216 may include non-volatile memory to store the calibration value for use during operation. In another example, the offset circuit 216 may determine the TRIM bit in part by using manufacturing process measurements from on-chip process control equipment or measurements of process control parameters in a wafer on which the chip is contained.

[0036] Implementation of link coupling element 220

[0037] Figure 6 Link coupling element 600 is shown in schematic form according to another implementation of link coupling element 220. Figure 2 Link coupling element 600 includes a transistor 610, which in the illustrated implementation is an N-channel MOS transistor having a drain connected to a positive supply terminal labeled "V DD DD is a higher supply voltage terminal with respect to the ground of the integrated circuit, which voltage is higher than the highest expected voltage of the MID node, so that transistor 610 operates as a source follower, and the voltage of the MID node follows the voltage of the CTRL node minus the threshold voltage drop. Like PN junction diode 222, Figure 2 Transistor 610 is biased unidirectional and allows current to flow into the MID node, but not any substantial DC current to flow out of the MID node, similar to PN junction diode 222.

[0038] Figure 7 Link coupling element 700 is shown in schematic form according to another implementation of link coupling element 220. Figure 2 Link coupling element 700 includes a transistor 710, which in the illustrated implementation is an NPN bipolar transistor having a collector connected to a positive supply terminal labeled "V CC CC is a higher supply voltage terminal with respect to the ground of the integrated circuit, which voltage is higher than the highest expected voltage of the MID node, so that transistor 710 operates as an emitter follower, and the voltage of the MID node follows the voltage of the CTRL node minus the diode turn-on voltage of the base-emitter diode. Like PN junction diode 222, Figure 2 Transistor 710 is biased unidirectional and allows current to flow into the MID node, but not any substantial DC current to flow out of the MID node, similar to PN junction diode 222.

[0039] Operation of control loop

[0040] Figure 8 Portion 800 is shown in partial block and partial schematic form according to other implementations of leakage compensation circuits 810 and 820. Leakage compensation circuit 810 includes buffer amplifier 210 and low pass filter 812 as shown previously with respect to Figure 2 Leakage compensation circuit 820 includes buffer amplifier 220 and low pass filter 822 as shown previously with respect to Figure 8 ​​additional elements of the leakage compensation circuit 200 not shown in FIG. 8. The low pass filter 812 includes a resistor 814 and a capacitor 816. The resistor 814 has a first terminal connected to the output of the buffer amplifier 210, and a second terminal connected to the CTRL node. The capacitor 816 has a first terminal connected to the second terminal of the resistor 814, and a second terminal connected to ground.

[0041] The leakage compensation circuit 820 includes a buffer amplifier 210 and a low pass filter 822 as previously described with respect to Figure 2 and Figure 8 additional elements of the leakage compensation circuit 200 not shown in FIG. 8. The low pass filter 822 includes a resistor 824 and a capacitor 826. The resistor 824 has a first terminal connected to the SENSE node, and a second terminal connected to the input of the buffer amplifier 210. The capacitor 826 has a first terminal connected to the second terminal of the resistor 824, and a second terminal connected to ground potential.

[0042] The leakage compensation circuit 200 is a feedback control loop formed by the buffer amplifier 210 having an input connected to the SENSE node, the link coupling element 220, and the leakage compensation element 230 having an output connected to the SENSE node. In various embodiments, the SENSE node can carry a useful signal, or it can receive electromagnetic interference (EMI) noise. The leakage compensation circuits 810 and 820 compensate for signal variations by providing low pass filtering to prevent the leakage compensation loop from following these signals. It is believed Figure 8 that the simple RC low pass filter shown is sufficient for this purpose. However, other suitable filters can be used where appropriate, such as higher order low pass filters, band pass filters, etc.

[0043] Figure 9 FIG. 8 shows a diagram showing a comparison of the leakage compensation circuit 200 of FIG. 1 with Figure 2A set of correlation graphs 900 showing the relationship between the operation of the leakage compensation circuit 200 and related signals. Graph 900 includes graphs 910 and 920 related via mirror line 930. Graph 910 shows the relationship between the voltage at the CTRL node, labeled "V(CTRL)" on the horizontal axis in volts, and the voltage at the MID node, labeled "V(MID)" on the vertical axis in volts. Waveform 912 displays the value of V(MID) as a function of V(CTRL). Generally, waveform 912 shows that V(MID) follows V(CTRL) and is substantially parallel to but offset downwards due to the turn-on voltage of the PN junction silicon diode. For forward bias conditions, it also generally follows a 45-degree line through the origin, as expected from the piecewise linear model of the voltage-current characteristics of the PN junction diode. For all V(MID) voltages above 0 volts, V(CTRL) is chosen to vary substantially linearly to provide a large tuning range. Below V(MID)≈0 volts, V(MID) is saturated.

[0044] Figure 920 shows V(MID) along the horizontal axis in volts and the compensation current I pushed into or pulled from the SENSE node along the vertical axis in picoamperes (pA). COMP The relationship between them. Mirror line 930 shows the correspondence between V(MID) along the vertical axis in curve 910 and V(MID) along the horizontal axis in curve 920. Waveform 922 will I COMP The function is displayed as V(MID).

[0045] exist Figure 9 In the example shown, the specific leakage current to be compensated is pushed into the SENSE node (I LEAK In _PUSH), as shown along the vertical axis in graph 920. Waveform 922 shows V(MID) and I that will balance ILEAK_PUSH. COMP The relationship between ILEAK_PUSH and waveform 922 indicates the ideal value of V(MID), which will generate an I that is equal to and opposite to ILEAK_PUSH. COMP Then, the V(MID) value is projected onto waveform 912 using mirror line 930. The V(CTRL) value at the point where the projected V(MID) line intersects with waveform 912 determines the ideal value of V(CTRL). The difference between the ideal V(CTRL) and V(SENSE) is equal to the ideal offset voltage V. OS .

[0046] When V(CTRL) >> V(SENSE), such as when V(SENSE) + V OS>>When V(SENSE), the link coupling element 220 pulls up the MID node to (V(SENSE) + V OS -VFW_LINK), where VFW_LINK is the forward voltage of the PN junction diode 222, thus reversing the potential across the PN junction diode 232. In this case, the SENSE node will receive a compensation current I COMP equivalent to the reverse saturation current of the PN junction diode 232. For this example, an additional current is pushed into the SENSE node, thus tending to pull up the SENSE node. The leakage current of the PN junction diode 234 does not flow to the SENSE node but passes through the PN junction diode 222 and is delivered by the differential amplifier 212.

[0047] When V(CTRL) << V(SENSE), such as when V(SENSE) + V OS << V(SENSE), the unidirectional characteristic of the PN junction diode 222 prevents the PN junction diode 222 from determining V(MID). Instead, V(MID) will stabilize at its minimum value, equal to V(SENSE - VFW_DTOP), where VFW_DTOP is the forward bias turn-on voltage of the PN junction diode 232. This can occur regardless of how low V(CTRL) is relative to V(SENSE). In this case, the SENSE node will receive a compensation current I COMP equivalent to the reverse saturation current of the PN junction diode 232 with a reverse voltage equal to V(MID) – REF and the reverse saturation current of the PN junction diode 222 with a reverse voltage equal to V(MID) – V(CTRL). Therefore, in this case, I COMP will be pulled out from the SENSE node, thus tending to pull down the SENSE node.

[0048] Therefore, by adjusting the voltage on the CTRL node relative to the SENSE node by setting V OS , the leakage compensation circuit 200 operates bidirectionally and is capable of compensating for small leakage currents regardless of their sign.

[0049] <​​​​​​​​

[0051] Figure 10 It shows what can be used to implement Figure 2 A cross-section of an integrated circuit 1000 is shown as a portion of the leakage compensation element 230. The portion of the integrated circuit 1000 illustrates a device structure that can be used to implement the leakage compensation element 230. The integrated circuit 1000 includes a semiconductor body 1010 having an epitaxially grown P-type region, labeled “Pepi,” which forms the anode of a bottom diode (PN junction diode 234). An N-type region 1020 covers the Pepi region and forms the common cathode region of an anti-series diode. In various embodiments, the N-type region 1020 may be a deep N-well region or an N-type reduced surface field region (NRESURF). The integrated circuit 1000 includes N-type semiconductor well regions 1030 and 1040 extending from the N-type region 1020 to the surface of a semiconductor substrate 1110. Both N-type well regions 1030 and 1040 isolate the P-type well region 1050 from surrounding circuitry. The P-type well region 1050 forms the anode of the PN junction diode 232 of the leakage compensation element and also forms a SENSE node. The P-type well region 1050 may contain all or part of the sensor 110, part of the buffer amplifier 210, or other components and circuits of the integrated circuit 1000, or other circuits 1060.

[0052] Figure 11 The following are examples of implementations available according to various schemes. Figure 2 The image shows a cross-section of another integrated circuit 1100, which is part of the leakage compensation circuit 200. The inventors of this patent application have implemented the leakage compensation circuit 200 using a structure known as dielectric trench isolation (MTI). Details of the structure of integrated circuit 1100 are described in U.S. Patent No. 10,026,728, the entire contents of which are incorporated herein by reference.

[0053] The integrated circuit 1100 includes a semiconductor substrate 1110 in which the link coupling element 220 and the leakage compensation element 230 are formed. The semiconductor substrate 1110 includes a P-type region 1112, a buried N-type region 1114, an N-type region 1116, a P-type region 1118, a deep trench structure 1120, a metal trench isolation (MTI) structure 1130, a circuit region 1140, a circuit region 1150, a conductive contact 1160, and an electrode 1170. The P-type region 1112 serves as the REF node, and the buried N-type region 1114 forms the bottom diode (PN junction diode 234). The N-type region 1116 and the overlying P-type region 1118 together form the top diode (PN junction diode 232), with the P-type region 1118 forming the SENSE node. The portion of the N-type region 1116 and the P-type region 1118 between the deep trench structure 1120 and the MTI structure 1130 forms the PN junction diode 222. The deep trench structure 1120 includes a dielectric layer 1122 lining the deep trench structure and a polysilicon layer 1124 filling the deep trench structure 1120. Likewise, the MTI structure 1130 includes a dielectric layer 1132 lining the MTI structure and a polysilicon layer 1134 filling the MTI structure 1130.

[0054] Because the N-type region 1114 is not interrupted by the MTI structure 1130, the cathode of the PN junction diode 222 is electrically connected to the cathodes of the PN junction diodes 232 and 234, conveniently forming the MID node. Thus, Figure 11 The device structures shown in cross-section with the MTI structure 1130 can be used to form the link coupling element 220 and the leakage compensation element 230.

[0055] Figure 11 The device structures shown in can be implemented using known integrated circuit fabrication techniques, including those described in U.S. Patent No. 10,026,728 and other known techniques. In Figure 11 In the embodiments shown, the device structures use batch processes, but in other embodiments they can be formed with corresponding epitaxial structures.

[0056] Figure 12 A cross-section of yet another integrated circuit 1200 that can be used to implement a portion of the leakage compensation circuit 200 of Figure 2 Figure 12 ​The portion of the integrated circuit 1200 shown implements the link coupling element 220 and the leakage compensation element 230. The integrated circuit 1200 includes a semiconductor body 1210 having a Pepi region that forms the anode of a bottom diode (PN junction diode 234). An N-type region 1220 overlies the Pepi region and forms the common cathode region of the anti- series diode and the cathode region of the PN junction diode 222 in the link coupling element 220. In various embodiments, the N-type region 1020 can be a deep N-well region, an N-type reduced surface field region (NRESURF), or an N-type well region. The integrated circuit 1200 includes N-type semiconductor well regions 1230, 1240, and 1250 that form the MID node, which extends from the deep N-well region 1220 to the surface of the semiconductor body 1210. The N-type well region 1230 and the N-type well region 1250 isolate the P-type well region 1260 from surrounding circuitry. The P-well region 1260 forms the anode of the PN junction diode 232 of the leakage compensation element 230 and also forms the SENSE node. The N-type well region 1250 and the N-type well region 1240 isolate the P-type well region 1270 from surrounding circuitry. The P-type well region 1270 forms the anode of the PN junction diode 222 of the link coupling element 220 and also forms the CTRL node.

[0057] Figure 13 An implementation of the link coupling element 220 and the leakage compensation element 230 is shown in FIG. 12. The portion of the integrated circuit 1200 shown implements the link coupling element 220 and the leakage compensation element 230. The integrated circuit 1200 includes a semiconductor body 1210 having a Pepi region that forms the anode of a bottom diode (PN junction diode 234). An N-type region 1220 overlies the Pepi region and forms the common cathode region of the anti- series diode and the cathode region of the PN junction diode 222 in the link coupling element 220. In various embodiments, the N-type region 1020 can be a deep N-well region, an N-type reduced surface field region (NRESURF), or an N-type well region. The integrated circuit 1200 includes N-type semiconductor well regions 1230, 1240, and 1250 that form the MID node, which extends from the deep N-well region 1220 to the surface of the semiconductor body 1210. The N-type well region 1230 and the N-type well region 1250 isolate the P-type well region 1260 from surrounding circuitry. The P-well region 1260 forms the anode of the PN junction diode 232 of the leakage compensation element 230 and also forms the SENSE node. The N-type well region 1250 and the N-type well region 1240 isolate the P-type well region 1270 from surrounding circuitry. The P-type well region 1270 forms the anode of the PN junction diode 222 of the link coupling element 220 and also forms the CTRL node. Figure 2a cross-section of yet another integrated circuit 1300 that is part of the leakage compensation circuit 200 of FIG. 1. The integrated circuit 1300 includes a semiconductor body 1310 having a Pepi region that forms the anode of a bottom diode (PN junction diode 234). A first N-type region 1320 overlies the Pepi region and forms a common cathode region of an anti-series diode. The integrated circuit 1300 includes N-type semiconductor well regions 1330 and 1340 that form the MID node that extends from the first N-type region 1320 to the surface of the semiconductor body 1310. The N-well regions 1330 and 1340 surround and isolate a P-well region 1350. The P-well region 1350 forms the anode of the PN junction diode 232 of the leakage compensation element 230 and also forms the SENSE node. A second N-type region 1360 overlies the Pepi region and forms a common cathode region of a second anti-series diode. The integrated circuit 1300 includes N-well regions 1370 and 1380 that form the MID node that extends from the second N-type region 1360 to the surface of the semiconductor body 1310. The N-well regions 1370 and 1380 surround and isolate a P-well region 1390. The P-well region 1390 forms the anode of the PN junction diode 222 of the link coupling element 220 and also forms the CTRL node. In various embodiments, the N regions 1320 and 1360 can be deep N-well regions, N RESURF regions, or N-type well regions. This portion of the integrated circuit 1300 shows that a device structure can be used to implement both the link coupling element 220 and the leakage compensation element 230 using only one type of device structure, in this case there is a PN junction diode 224 but it is not used.

[0058] Figure 14 shows that a device structure can be used to implement both the link coupling element 220 and the leakage compensation element 230 using only one type of device structure, in this case there is a PN junction diode 224 but it is not used. Figure 2A cross-section of yet another integrated circuit 1400 that is part of the leakage compensation circuit 200 of FIG. 1. The integrated circuit 1400 includes a semiconductor body 1410 having a Pepi region that forms the anode of a bottom diode (PN junction diode 234). A first N-type region 1430 overlies the Pepi region and forms a common cathode region of an anti-series diode. The integrated circuit 1400 includes N-type well regions 1440 and 1450 that form the MID node that extends from the first N-type region 1430 to the surface of the semiconductor body 1410. The N-type well regions 1430 and 1450 surround and isolate a P-type well region 1460. The P-type well region 1460 forms the anode of the PN junction diode 232 of the leakage compensation element 230, and also forms the SENSE node. A second N-type region 1470 overlies the Pepi region and forms a common cathode region of a second anti-series diode. The integrated circuit 1300 includes N-type well regions 1480 and 1490 that also form the MID node that extends from the second N-type region 1470 to the surface of the semiconductor body 1310 and is connected to the N-type well region 1450 by a metal conductor. The N-type well regions 1480 and 1490 surround and isolate a P-type well region 1492. The P-type well region 1492 forms the anode of the PN junction diode 222 of the link coupling element 220, and also forms the CTRL node. This portion of the integrated circuit 1400 shows a device structure that can be used to implement both the link coupling element 220 and the leakage compensation element 230 using only one type of device structure, in this case there is a PN junction diode 224 but it is not used.

[0059] In addition, the integrated circuit 1400 includes an N-type well region 1420 that forms the cathode of a PN junction diode 236. The anode of the PN junction diode 236 is formed in the semiconductor body 1410. The N-type well 1420 is connected to the MID node by a metal connection, for example at the N-type well region 1440. The diode 236 operates in parallel with the diode 234 to increase the reverse saturation current. Figure 14 The portion of the integrated circuit 1400 shown implements a modification of the link coupling element 230 that has an increased junction area of the bottom diode, allowing an increased reverse saturation current when the MID node is biased to a relatively high voltage.

[0060] Thus, the leakage compensation circuit and method as disclosed herein accurately compensates for small leakage currents that are not easily compensated for by conventional techniques. The leakage compensation circuit exhibits a temperature dependence that will track the temperature dependence of various leakage sources, such as ESD protection diodes. In one form, the leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an output and an input coupled to a sense node. The link coupling element has an output and an input coupled to the output of the buffer amplifier, where the link coupling element is unidirectional in a direction from the input to its output. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

[0061] The leakage compensation circuit includes a leakage compensation element capable of injecting a compensation current I COMP with a variable magnitude and a variable sign. It acts as a voltage-controlled bidirectional current source and can perform in-situ leakage compensation. Thus, a sensor circuit incorporating the leakage compensation circuit can achieve a higher dynamic input range.

[0062] The subject matter disclosed above is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other implementations falling within the true scope of the claims. For example, various implementations of each of the buffer amplifier, the link coupling element, and the leakage compensation element are possible. For example, the buffer amplifier can generate the desired offset for the SENSE node in a variety of ways. The link coupling element can be implemented with a unidirectional circuit element such as a diode, a MOS transistor source follower, or a bipolar transistor emitter follower. The leakage compensation element can also be implemented in a variety of ways. If an anti- series diode is used for the link coupling element, the anti-series diode can have back-to-back cathodes or back-to-back anodes. The anti-series diode can also be implemented with a variety of integrated circuit device structures, including structures in which the link coupling element and the leakage compensation element share a common buried diffusion region using an MTI structure.

[0063] In one form, the leakage compensation circuit includes a buffer amplifier having an output and an input coupled to a sense node, a link coupling element having an output and an input coupled to the output of the buffer amplifier, where the link coupling element is unidirectional in a direction from the input to its output, and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

[0064] According to one aspect, the buffer amplifier includes a single-ended non-inverting amplifier having a positive input coupled to the sense node and an output coupled to the output of the buffer amplifier. According to this aspect, the buffer amplifier can further include a variable offset generator coupled between the sense node and one of the positive input of the differential amplifier and the negative input of the differential amplifier and having a control input for receiving a digital correction signal, and an offset circuit having an output coupled to the control input of the variable offset generator to provide the digital correction signal.

[0065] According to another aspect, the link coupling element includes a metal oxide semiconductor (MOS) transistor having a drain coupled to the second reference voltage terminal, a gate coupled to the output of the buffer amplifier, and a source coupled to the control terminal of the leakage compensation element.

[0066] According to yet another aspect, the link coupling element includes a bipolar transistor having a collector coupled to the second reference voltage terminal, a base coupled to the output of the buffer amplifier, and an emitter coupled to the control terminal of the leakage compensation element.

[0067] According to yet another aspect, the leakage compensation element includes an anti- series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal acting as a control terminal of the leakage compensation element coupled to the output of the link coupling element. According to this aspect, the anti-series diode can include a first PN diode having an anode coupled to the sense node and a cathode forming the intermediate terminal of the anti-series diode, and a second PN diode having an anode coupled to the reference voltage terminal and a cathode coupled to the cathode of the first PN diode.

[0068] According to another aspect, the leakage compensation circuit further includes a filter for compensating a loop between the sense node and the first current terminal of the leakage compensation element.

[0069] In another form, an integrated circuit has a leakage compensation circuit including a buffer amplifier having an output and an input coupled to a sense node, a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input to the output thereof, and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

[0070] According to one aspect, the first current terminal of the leakage compensation element is formed in a first region of the integrated circuit, and the first region includes at least one semiconductor device formed in the first region.

[0071] According to another aspect, the leakage compensation element includes an anti-series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal forming a control terminal of the leakage compensation element, the intermediate terminal coupled to the output of the link coupling element. According to this aspect, the anti-series diode can include a first PN diode having an anode coupled to the sense node and a cathode forming the intermediate terminal of the anti-series diode, and a second PN diode having an anode coupled to the reference voltage terminal and a cathode coupled to the cathode of the first PN diode. In this case, the integrated circuit can further include a semiconductor region of the first conductivity type, wherein the semiconductor region forms terminal regions of both the first and second PN diodes. According to this aspect, the integrated circuit can further include a semiconductor region of the first conductivity type, wherein the semiconductor region forms terminal regions of the anti-series diode and terminals of other semiconductor devices.

[0072] According to yet another aspect, the output of the link coupling element and the control terminal of the leakage compensation element are coupled together using a metal connection.

[0073] In another form, a method of performing leakage compensation for a leakage current flowing into or out of a sense node includes buffering a voltage on the sense node, and providing the buffered voltage to an intermediate node in response to the buffering; unidirectionally coupling the buffered voltage to a control node; and biasing a leakage compensation element having a first current terminal coupled to the sense node and a second current terminal coupled to a reference voltage terminal by coupling a control terminal of the leakage compensation element to the control node.

[0074] According to one aspect, the buffering includes buffering the voltage on the sense node using a differential amplifier, and applying an offset to the differential amplifier.

[0075] According to another aspect, unidirectionally coupling the buffered voltage to the control node includes coupling the buffered voltage to the control node using a PN diode.

[0076] According to yet another aspect, unidirectionally coupling the buffered voltage to the control node includes coupling the buffered voltage to the control node using a metal oxide semiconductor (MOS) transistor having a drain coupled to a second reference voltage terminal, a gate for receiving the buffered voltage, and a source coupled to the intermediate node.

[0077] According to yet another aspect, coupling the buffer voltage unidirectionally to the control node comprises coupling a bipolar transistor having a collector coupled to the second reference voltage terminal, a base for receiving the buffer voltage, and an emitter coupled to the control node.

[0078] According to yet another aspect, the bias leakage compensation element comprises a biasing anti-series diode having a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal coupled to the control node.

[0079] Accordingly, to the maximum extent allowable by law, the scope of the present application should be determined by the broadest interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A leakage compensation circuit, characterized by, The leakage compensation circuit comprises: a buffer amplifier having an output and an input coupled to a sense node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input thereof to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal, wherein the leakage compensation element comprises an anti-series diode; wherein the anti-series diode has a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal acting as the control terminal of the leakage compensation element, the intermediate terminal being coupled to the output of the link coupling element.

2. The leakage compensation circuit of claim 1, wherein, The buffer amplifier comprises: a differential amplifier having a positive input coupled to the sense node, a negative input, and an output coupled to the negative input, the output forming the output of the buffer amplifier.

3. The leakage compensation circuit of claim 1, wherein, The buffer amplifier comprises: a single-ended non-inverting amplifier having a positive input coupled to the sense node, and an output coupled to the output of the buffer amplifier.

4. The leakage compensation circuit of claim 1, wherein, The link coupling element comprises: a diode having an anode coupled to the output of the buffer amplifier and a cathode coupled to the control terminal of the leakage compensation element.

5. An integrated circuit having a leakage compensation circuit, characterized by The leakage compensation circuit comprises: a buffer amplifier having an output and an input coupled to a sense node; a link coupling element having an output and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input thereof to the output thereof; and a leakage compensation element having a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal, wherein the leakage compensation element comprises an anti-series diode; wherein the anti-series diode has a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal acting as the control terminal of the leakage compensation element, the intermediate terminal being coupled to the output of the link coupling element.

6. The integrated circuit of claim 5, wherein: the intermediate terminal of the anti-series diode and the output of the link coupling element are formed in a common semiconductor region.

7. The integrated circuit of claim 6, wherein: the common semiconductor region is a common floating buried layer, and the input of the link coupling element is isolated from the first current terminal of the anti-series diode by a trench partially penetrating the common semiconductor region.

8. A method of performing leakage compensation on a leakage current flowing into or out of a sense node, the method comprising: The method comprises: buffering a voltage on the sense node through a buffer amplifier having an output and an input coupled to the sense node, and providing a buffer voltage to an intermediate node in response to the buffer; unidirectionally coupling the buffer voltage to a control node through a link coupling element having an output coupled to the control node and an input coupled to the output of the buffer amplifier, wherein the link coupling element is unidirectional in a direction from the input thereof to the output thereof; and biasing a leakage compensation element having a first current terminal coupled to the sense node and a second current terminal coupled to a reference voltage terminal by coupling a control terminal of the leakage compensation element to the control node, wherein biasing the leakage compensation element comprises biasing a reverse series diode, wherein the reverse series diode has a first current terminal coupled to the sense node, a second current terminal coupled to the reference voltage terminal, and an intermediate terminal acting as the control terminal of the leakage compensation element coupled to the output of the link coupling element.

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