Circuit device and search method for quickly searching for the most significant bit of data

Abstract

A circuit device for searching the most significant bit of data includes N-level data selectors for determining whether the low-order part of the data bit width is transmitted to the subsequent circuit according to a selection signal; and N-level OR gates for performing bitwise OR operations on the high-order part of each part of the data bit width. The present invention also discloses a method for searching the most significant bit of data. When the present invention is applied to the detection of the most significant bit of data, the circuit structure is simple, the complexity is low, and the logic gate circuits used are relatively few, which can effectively reduce the area occupied by the circuit when it is implemented on the chip and reduce the production cost. The present invention can greatly reduce the delay of signal transmission, speed up the clock frequency of the circuit, and improve the working efficiency of the system.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a circuit device and a search method for quickly searching for the most significant bit of data. Background Art

[0002] When normalizing fixed-point data, it is necessary to enlarge or reduce it by a certain ratio, which is achieved by shifting. Since the position of the most significant bit is not fixed in different data, it is not easy to determine its specific position. For example, the 16-bit fixed-point data with a decimal width and an integer width of 8 bits is defined as xxxx_xxxx_xxxx_xxxx, such as the following three data (the bits shifted out of the low bit are ignored):

[0003] 0001_0011_0100_0011=0000_0001_0011_0100 2 4 -----Formula 1

[0004] 0000_0111_0101_0010=0000_0001_1101_0100 2 2 -----Formula 2

[0005] 0000_0000_0001_0010=0000_0001_0010_0000 2 -4 ------Formula 3

[0006] The most significant bits are Data

[12] , Data

[10] , and Data[4], and the number of bits that need to be right-shifted for normalization is 4, 2, and -4, respectively. The logic "1" after the most significant bit, that is, the logic "1" of the lower bit, does not affect the number of bits of data shift and is not processed or calculated.

[0007] Using sequential circuits to achieve Figure 1 As shown, taking 32-bit binary data as an example, the MSB (Most Significant Bit) (i.e. b31) is first input into the detection circuit, and the LSB (Least Significant Bit) (i.e. b0) is input last. Each clock moves one bit, and there is a corresponding cyclic adder cnt for counting. The b31 input into the circuit and the cnt value of 0 are in the same clock cycle. When the first logic "1" (i.e. the most significant bit) is encountered, the corresponding count value is locked. The count value appears in the next cycle when the lock signal is valid. This value is recorded as P, and the P value is the position of the most significant bit in the binary data.

[0008] When P[4:0]=5'b00000, the value of S is needed to determine whether there is a "1" in M. That is, when S=1'b1, it means that the highest bit 1 is M[0]. If S=1'b0, it means that M=32'h00000000, that is, all bits of M are not "1".

[0009] In the sequential circuit, the fastest P[4:0] cycle is 1, and the slowest is 31. Therefore, the working efficiency of the whole circuit is 31 clock cycles to process a 32-bit data. By analogy, if 64-bit data is to be processed, 63 cycles are required, and 128-bit data is required 127 cycles, which is very inefficient. If WIDTH(M) is the bit width of data M, T clk is the clock cycle, and the number of output cycles of the value at the position of the most significant bit of the data is N cycle , then the time required to output the result is

[0010] D0 = T clk N cycle = T clk (WIDTH( M)-1) -----------------Equation 4

[0011] The number of cycles required to output the result is linearly related to the bit width, which is very inefficient.

[0012] The circuit structure using combinational logic for valid bit position detection is as follows Figure 2 As shown, M

[31] has the highest priority. When M

[31] =“1”, output P=5'd31. When M

[31] =“0” and M

[30] =“1”, output P=5'd30. And so on to M[1]. When P=5'b0, the value of S is needed to determine whether there is a "1" in M. That is, when S=1'b1, it means that the highest bit 1 is M[0]. If S=1'b0, it means that M=32'h00000000, that is, all bits are not "1".

[0013] The output of the P value requires data to be transmitted stage by stage. There are 31 levels of data selectors. Assuming that the delay of a single level is d1, the delay of the longest path is

[0014] D1 = d1 31 -----------------Formula 5

[0015] Therefore, when the data width is WIDTH(M) bits, the maximum delay is

[0016] D1 = d1 ( WIDTH(M) - 1 ) ----------------- Formula 6

[0017] The delay of this combinational logic circuit is linearly related to the bit width of the data. When the data bit width is doubled, the operating frequency of the circuit will be halved, seriously affecting the working efficiency of the circuit.

[0018] exist Figure 1 In the equation 4 corresponding to the circuit shown, it can be seen that the delay D0 = T clk WIDTH(M), the processing of the circuit requires several clock cycles, and the number of cycles required to output the result is linearly related to the bit width. Therefore, the circuit delay is very serious, and it is impossible to obtain the data result in a single cycle.

[0019] exist Figure 2 In the combinational logic circuit, the delay D1 = d1 ( WIDTH(M) - 1 ), the delay of the critical path is also linearly related to the bit width. For 16-bit data, 15 selectors are required for cascade transmission, while 32-bit data requires up to 31 selectors. Without the use of pipeline technology, the long delay path of the combinational logic will lead to a significant reduction in the operating frequency of the entire circuit.

[0020] For the adoption Figure 1 and Figure 2 Circuits that process in this way all face the problem of long delay, resulting in low circuit efficiency, especially the circuit implemented in the second combinational logic method. Although the output is shortened to one clock cycle, the critical path is long and there is a long transmission delay, which will greatly affect the clock frequency and the working efficiency of the entire circuit. Summary of the invention

[0021] In view of this, the main purpose of the present invention is to provide a circuit device and a search method for quickly searching for the most significant bit of data, so as to at least partially solve at least one of the above technical problems.

[0022] In order to achieve the above object, as one aspect of the present invention, a circuit device for quickly searching for the most significant bit of data is provided, comprising:

[0023] N-stage data selectors, used to determine whether the low-order part of the data bit width is transmitted to the subsequent circuit according to the selection signal;

[0024] N levels of OR gates are used to perform bitwise OR operations on the high-order parts of each data bit width.

[0025] Among them, the delay of the critical path of the circuit is:

[0026] D2 = (d1+d2) N;

[0027] Among them, d1 is the delay of the data selector, d2 is the delay of the OR gate, and N is the number of selector levels.

[0028] As another aspect of the present invention, a method for quickly searching for the most significant bit of data is also provided, comprising the following steps:

[0029] The data M is divided into two parts. If the bit width of M is not a power of 2, the high bits are padded to expand its bit width to a power of 2. For example, if the bit width of M is 32 bits, the high-order part is M[31:16] and the low-order part is M[15:0]. The high-order part is bitwise ORed to generate signal P[4], which is used as the selection signal of M[31:16] and M[15:0].

[0030] When M[31:16] contains "1", the value of P[4] is "1", then the value of M1 is M[31:16], and the most significant bit is between M[31:16]. At this time, the value of M[15:0] will no longer be transmitted to the subsequent circuit for processing; when M[31:16] does not contain "1", the value of P[4] is "0", then the value of M1 is M[15:0];

[0031] When M1[15:8] contains "1", the value of P[3] is "1", then the value of M2 is M1[15:8], and the most significant bit is between M1[15:8]. At this time, the value of M1[7:0] will no longer be transmitted to the subsequent circuit for processing; when M1[15:8] does not contain "1", the value of P[3] is "0", then the value of M2 is M1[7:0];

[0032] When M2[7:4] contains "1", the value of P[2] is "1", then the value of M3 is M2[7:4], and the most significant bit is between M2[7:4]. At this time, the value of M2[3:0] will no longer be transmitted to the subsequent circuit for processing; when M2[7:4] does not contain "1", the value of P[2] is "0", then the value of M3 is M2[3:0];

[0033] When M3[3:2] contains "1", the value of P[1] is "1", then the value of M4 is M3[3:2], and the most significant bit is between M3[3:2]. At this time, the value of M3[1:0] will no longer be transmitted to the subsequent circuit for processing; when M3[3:2] does not contain "1", the value of P[1] is "0", then the value of M4 is M3[1:0];

[0034] The value of P[0] is M4[1], and the value of S is M4[0];

[0035] In the above process, the value of P[4:0] is the position where the highest bit 1 appears, that is, the value of P[4:0] is W, which means that the most significant bit is M[W].

[0036] Among them, when the data bit width is not equal to the power of 2, the search method is applicable only by padding its high bits to the nearest power of 2 value.

[0037] Among them, when P[4:0] = 5'b00000, the value of S is needed to determine whether there is a 1 in M, that is, when S=1'b1, it means that the highest bit 1 is M[0]. If S=1'b0, it means that M=32'h00000000, and all bits are 0.

[0038] Based on the above technical solution, it can be known that the circuit device and search method for quickly searching the most significant bit of data of the present invention have at least some of the following beneficial effects compared with the prior art:

[0039] When the present invention is applied to the detection of the most significant bit of data, the circuit structure is simple, the complexity is low, and the logic gate circuits used are relatively few, which can effectively reduce the area occupied by the circuit when it is implemented on the chip and reduce the production cost; the present invention can greatly reduce the delay of signal transmission, speed up the clock frequency of the circuit, and improve the working efficiency of the system. The data is divided from the middle for detection. This binary detection idea can exponentially improve the detection efficiency and is applied to similar detection circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a circuit for searching the most significant bit of data using a sequential logic circuit in the prior art;

[0041] Figure 2 It is a schematic diagram of the circuit structure of performing effective bit position detection using combinational logic in the prior art;

[0042] Figure 3 FIG. 4 is a schematic diagram of the structure of a circuit device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The circuit device of the present invention uses combinational logic to shorten the length of the critical path from input data to output data, thereby reducing the transmission delay of the circuit and improving the operating frequency of the system circuit.

[0044] Specifically, the present invention discloses a circuit device for quickly searching for the most significant bit of data, comprising:

[0045] N-stage data selectors, used to determine whether the low-order part of the data bit width is transmitted to the subsequent circuit according to the selection signal;

[0046] N levels of OR gates are used to perform bitwise OR operations on the high-order parts of each data bit width.

[0047] Among them, the delay of the critical path of the circuit is:

[0048] D2 = (d1+d2) N;

[0049] Among them, d1 is the delay of the data selector, d2 is the delay of the OR gate, and N is the number of selector levels.

[0050] The present invention also discloses a method for quickly searching for the most significant bit of data, comprising the following steps:

[0051] The data M is divided into two parts. If the bit width of M is not a power of 2, the high bits are padded to expand its bit width to a power of 2. For example, if the bit width of M is 32 bits, the high-order part is M[31:16] and the low-order part is M[15:0]. The high-order part is bitwise ORed to generate signal P[4], which is used as the selection signal of M[31:16] and M[15:0].

[0052] When M[31:16] contains "1", the value of P[4] is "1", then the value of M1 is M[31:16], and the most significant bit is between M[31:16]. At this time, the value of M[15:0] will no longer be transmitted to the subsequent circuit for processing; when M[31:16] does not contain "1", the value of P[4] is "0", then the value of M1 is M[15:0];

[0053] When M1[15:8] contains "1", the value of P[3] is "1", then the value of M2 is M1[15:8], and the most significant bit is between M1[15:8]. At this time, the value of M1[7:0] will no longer be transmitted to the subsequent circuit for processing; when M1[15:8] does not contain "1", the value of P[3] is "0", then the value of M2 is M1[7:0];

[0054] When M2[7:4] contains "1", the value of P[2] is "1", then the value of M3 is M2[7:4], and the most significant bit is between M2[7:4]. At this time, the value of M2[3:0] will no longer be transmitted to the subsequent circuit for processing; when M2[7:4] does not contain "1", the value of P[2] is "0", then the value of M3 is M2[3:0];

[0055] When M3[3:2] contains "1", the value of P[1] is "1", then the value of M4 is M3[3:2], and the most significant bit is between M3[3:2]. At this time, the value of M3[1:0] will no longer be transmitted to the subsequent circuit for processing; when M3[3:2] does not contain "1", the value of P[1] is "0", then the value of M4 is M3[1:0];

[0056] The value of P[0] is M4[1], and the value of S is M4[0];

[0057] In the above process, the value of P[4:0] is the position where the highest bit 1 appears, that is, the value of P[4:0] is W, which means that the most significant bit is M[W].

[0058] Among them, when the data bit width is not equal to the power of 2, the search method is applicable only by padding its high bits to the nearest power of 2 value.

[0059] Among them, when P[4:0] = 5'b00000, the value of S is needed to determine whether there is a 1 in M, that is, when S=1'b1, it means that the highest bit 1 is M[0]. If S=1'b0, it means that M=32'h00000000, and all bits are 0.

[0060] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0061] like Figure 3 In the circuit device shown, M is 32-bit wide data. M is divided into two parts, the high-order part is M[31:16], and the low-order part is M[15:0]. The high-order part is subjected to a bitwise OR operation to generate a signal P[4], which is used as a selection signal of M[31:16] and M[15:0].

[0062] The bit width of M1 is 16 bits (i.e., M1[15:0]), and its value is M[31:16] or M[15:0]. When M[31:16] contains "1", the value of P[4] is "1", and the value of M1 is M[31:16]. At this time, the most significant bit is between M[31:16], so the value of M[15:0] will no longer be transmitted to the subsequent circuit for processing. Otherwise, the value of M1 is M[15:0]. The relationship between M2 and M1 is similar to that between M1 and M0. When M1[15:8] contains "1", P[3] is "1", and the value of M2 is M1[15:8]. Otherwise, the value of M2 is M1[7:0], and so on, until M4 with a bit width of 2 bits.

[0063] The value of P[4:0] is the position where the most significant bit 1 appears. For example, if the value of P[4:0] is 12, then the most significant bit is M

[12] . It should be noted that when P[4:0] = 5'b00000, the value of S is needed to determine whether there is a 1 in M. That is, when S=1'b1, it means that the most significant bit 1 is M[0]. If S=1'b0, it means that M=32'h00000000, and all bits are 0.

[0064] from Figure 3 It can be seen from the circuit device shown that the longest delay path of the entire circuit is a 4-stage data selector and a 4-stage OR gate. The delay of the data selector is d1, and the delay of the OR gate is d2. Then the delay of the critical path of the circuit is

[0065] D2 = (d1+d2) 4 ---------------------------Formula 7

[0066] Extended to the general case, let WIDTH(M) be the bit width of data M, and satisfy

[0067] 2 K-1 <WIDTH(M)≤ 2 K , where K is a positive integer,

[0068] At this time, if there is

[0069] WIDTH(M) ≠2 K ---------------------------Formula 8

[0070] Then fill its high bit with "0", so that

[0071] WIDTH(M)=2 K ---------------------------Formula 9

[0072] Then there is

[0073] D2 = (d1+d2) N ---------------------------Formula 10

[0074] in

[0075] N= K-1 ---------------------------Formula 11

[0076] There is a logarithmic relationship between the delay and the data bit width, that is, when the data bit width doubles, the total delay only increases by the delay of one selector and OR gate. Figure 1 and Figure 2 The circuit structure, the delay change is very small.

Claims

1. A circuit device for finding the most significant bit of data, characterized in that: include N-stage data selectors, used to determine whether the low-order part of the data bit width is transmitted to the subsequent circuit according to the selection signal; N-level OR gates are used to perform bitwise OR operations on the high-order parts of each portion of the data bit width; wherein the circuit device uses the N-level data selectors and the N-level OR gates to find the most significant bit of the data through the following steps: The data M is divided into two parts. If the bit width of M is not a power of 2, the high bits are padded to expand its bit width to a power of 2. If the bit width of M is set to 32 bits, the high-order part is M[31:16] and the low-order part is M[15:0]. The high-order part is bitwise ORed to generate signal P[4], which is used as the selection signal of M[31:16] and M[15:0]. When M[31:16] contains "1", the value of P[4] is "1", then the value of M1 is M[31:16], and the most significant bit is between M[31:16]. At this time, the value of M[15:0] will no longer be transmitted to the subsequent circuit for processing; when M[31:16] does not contain "1", the value of P[4] is "0", then the value of M1 is M[15:0]; When M1[15:8] contains "1", the value of P[3] is "1", then the value of M2 is M1[15:8], and the most significant bit is between M1[15:8]. At this time, the value of M1[7:0] will no longer be transmitted to the subsequent circuit for processing; when M1[15:8] does not contain "1", the value of P[3] is "0", then the value of M2 is M1[7:0]; When M2[7:4] contains "1", the value of P[2] is "1", then the value of M3 is M2[7:4], and the most significant bit is between M2[7:4]. At this time, the value of M2[3:0] will no longer be transmitted to the subsequent circuit for processing; when M2[7:4] does not contain "1", the value of P[2] is "0", then the value of M3 is M2[3:0]; When M3[3:2] contains "1", the value of P[1] is "1", then the value of M4 is M3[3:2], and the most significant bit is between M3[3:2]. At this time, the value of M3[1:0] will no longer be transmitted to the subsequent circuit for processing; when M3[3:2] does not contain "1", the value of P[1] is "0", then the value of M4 is M3[1:0]; The value of P[0] is M4[1], and the value of S is M4[0]; In the above process, the value of P[4:0] is the position where the highest bit 1 appears, that is, the value of P[4:0] is W, which means that the most significant bit is M[W]; In the circuit device, the delay of the critical path of the circuit is: D2 = (d1+d2) N; Where d1 is the delay of the data selector, d2 is the delay of the OR gate, and N is the number of selector levels; The critical path is the longest path formed by the N-stage data selectors and the N-stage OR gates.

2. A method for searching the most significant bit of data, using the circuit device as claimed in claim 1, characterized in that: The following steps are involved: The data M is divided into two parts. If the bit width of M is not a power of 2, the high bits are padded to expand its bit width to a power of 2. If the bit width of M is set to 32 bits, the high-order part is M[31:16] and the low-order part is M[15:0]. The high-order part is bitwise ORed to generate signal P[4], which is used as the selection signal of M[31:16] and M[15:0]. When M[31:16] contains "1", the value of P[4] is "1", then the value of M1 is M[31:16], and the most significant bit is between M[31:16]. At this time, the value of M[15:0] will no longer be transmitted to the subsequent circuit for processing; when M[31:16] does not contain "1", the value of P[4] is "0", then the value of M1 is M[15:0]; When M1[15:8] contains "1", the value of P[3] is "1", then the value of M2 is M1[15:8], and the most significant bit is between M1[15:8]. At this time, the value of M1[7:0] will no longer be transmitted to the subsequent circuit for processing; when M1[15:8] does not contain "1", the value of P[3] is "0", then the value of M2 is M1[7:0]; When M2[7:4] contains "1", the value of P[2] is "1", then the value of M3 is M2[7:4], and the most significant bit is between M2[7:4]. At this time, the value of M2[3:0] will no longer be transmitted to the subsequent circuit for processing; when M2[7:4] does not contain "1", the value of P[2] is "0", then the value of M3 is M2[3:0]; When M3[3:2] contains "1", the value of P[1] is "1", then the value of M4 is M3[3:2], and the most significant bit is between M3[3:2]. At this time, the value of M3[1:0] will no longer be transmitted to the subsequent circuit for processing; when M3[3:2] does not contain "1", the value of P[1] is "0", then the value of M4 is M3[1:0]; The value of P[0] is M4[1], and the value of S is M4[0]; In the above process, the value of P[4:0] is the position where the highest bit 1 appears, that is, the value of P[4:0] is W, which means that the most significant bit is M[W].

3. The search method according to claim 2, characterized in that: When the data bit width is not equal to a power of 2, the search method pads the high bits to the nearest power of 2 value.

4. The search method according to claim 2, characterized in that: When P[4:0] = 5'b00000, the value of S is needed to determine whether there is a 1 in M. That is, when S=1'b1, it means that the highest bit 1 is M[0]. If S=1'b0, it means that M=32'h00000000, and all bits are 0.

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