A capacitor constant power aging circuit and aging method

Abstract

The present invention provides a capacitor constant power aging circuit and an aging method thereof, which are used in a constant power aging device for aluminum electrolytic capacitors, including a charging power supply output terminal, a capacitor Cx to be aged, a transistor Q1, and an operational amplifier U1, and a reference voltage REF is also connected to the positive input terminal of the operational amplifier; the charging power supply output terminal forms a charging loop with the capacitor Cx, the transistor Q1 and the resistor R1, and the resistor R1 is grounded; at the same time, a feedback circuit and a reverse adder are connected to the input terminal of the operational amplifier U1 to form a constant current source. The charging current of the capacitor to be aged is dynamically adjusted according to the voltage loaded on the capacitor, so that a larger charging current is given when the voltage is low, and the charging current is automatically reduced as the voltage rises, so as to control the heat generation of the capacitor during aging and prevent the electrolyte from evaporating due to excessive temperature. The present invention can greatly improve the quality of the capacitor and extend the service life of the capacitor.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitor manufacturing, and in particular to a capacitor constant power aging circuit and an aging method thereof. Background Art

[0002] Because the capacitor's formed foil needs to be cut during production, the cutting process will damage the formed aluminum oxide on the surface and lose its original voltage resistance. Therefore, the capacitor needs to be charged after assembly to repair the aluminum oxide on the foil surface. This process is commonly known as aging.

[0003] In the traditional capacitor aging process, only a current-limiting resistor is connected in series to charge the capacitor. The capacitor aging process usually takes several hours to dozens of hours. Unaged capacitors cannot be charged. The charging process requires an electrochemical reaction to generate insulating aluminum oxide on the surface of the capacitor's positive foil. As aluminum oxide is generated, the surface of the positive foil begins to insulate, and the capacitor's withstand voltage gradually increases. Since the voltage applied to the capacitor and the resistor during the aging process is higher than the withstand voltage of the capacitor's aluminum foil, even if a current-limiting resistor is connected in series, as the voltage slowly increases, the current flowing through the capacitor can generate very high heat, causing the electrolyte inside the capacitor to evaporate, and it can also cause carbonization of the electrolytic paper, seriously affecting the service life of the capacitor. Summary of the invention

[0004] The present invention provides a new aging method for the capacitor aging process. In order to solve the above-mentioned shortcomings, the market is also in urgent need of an aging device that can effectively control the internal heat of the capacitor during aging. The present invention is a constant power aging device that dynamically adjusts the charging current of the capacitor to be aged according to the voltage loaded on the capacitor, so that a larger charging current is given when the voltage is low, and the charging current is automatically reduced as the voltage rises, so as to control the heat generation of the capacitor during aging and prevent the electrolyte from evaporating due to excessive temperature.

[0005] The present invention can greatly improve the quality of capacitors and extend the service life of capacitors.

[0006] The present invention provides a capacitor constant power aging circuit for an aluminum electrolytic capacitor constant power aging device, a capacitor constant power aging circuit for an aluminum electrolytic capacitor constant power aging device, comprising a charging power supply, a capacitor to be aged Cx, a semiconductor switch device, and a feedback circuit electrically connected in sequence, wherein:

[0007] The output end of the semiconductor switch device is electrically connected to a resistor R1 and is grounded;

[0008] The feedback circuit includes an operational amplifier, and a reference voltage is connected to the positive input terminal of the operational amplifier; the output terminal of the charging power supply forms a charging loop with the capacitor to be aged, the semiconductor switch device and the resistor R1. At the same time, the feedback circuit feeds back the voltage and current, and automatically adjusts the constant current value as the voltage changes to form a constant current source.

[0009] The semiconductor switch device options include transistors and field effect transistors, the transistors include triodes or insulated gate bipolar transistors, bipolar junction transistors, metal oxide semiconductor field effect transistors; and also include current-type fully controlled devices and voltage-type fully controlled devices.

[0010] The semiconductor switch device is a transistor Q1, the output end of the operational amplifier is connected to the base of the transistor Q1, the feedback circuit is a resistor R2 connected between the reverse input end of the operational amplifier and the positive end of the capacitor Cx, and the emitter of the transistor Q1 and the reverse input end of the operational amplifier are further connected to a resistor R4; wherein the operational amplifier and the resistors R2 and R4 form an inverse adder.

[0011] The reverse input terminal of the operational amplifier is connected to the emitter of the transistor Q1, and resistors R2 and R3 are connected in series between the positive input terminal of the operational amplifier U1 and the output terminal of the positive charging power supply. The positive input terminal of the operational amplifier U1 is connected to the output terminal of another operational amplifier U2, and the reference voltage REF is connected to the positive input terminal of the operational amplifier U2; the reverse input terminal of the operational amplifier U2 is connected to the node between the resistor R3 and the resistor R2.

[0012] A rectifier bridge D1 is connected between the transistor Q1 and the capacitor Cx to be aged. The capacitor Cx, the rectifier bridge D1, the transistor Q1, and the resistor R1 form a charging and discharging circuit. The transistor Q1, the operational amplifier U1, and the resistor R1 form a constant current source; the resistor R2, the resistor R3, and the operational amplifier U2 form an inverting amplifier.

[0013] A rectifier bridge D1 is connected between the transistor Q1 and the capacitor to be aged Cx, a DC voltage positive output terminal of the rectifier bridge D1 is connected to the collector of the transistor, and a DC voltage negative output terminal of the rectifier bridge D1 is grounded.

[0014] The semiconductor switch device is a transistor Q1, and the feedback circuit includes an operational amplifier U1. A voltage divider circuit and a digital-to-analog conversion circuit are connected between the positive input terminal of the operational amplifier U1 and the positive charging power supply output terminal.

[0015] The reverse input terminal of the operational amplifier U1 is connected to the emitter of the transistor Q1; a rectifier bridge D1 is connected between the transistor Q1 and the capacitor to be aged Cx, the DC voltage positive output terminal of the rectifier bridge D1 is connected to the collector of the transistor, and the DC voltage negative output terminal of the rectifier bridge D1 is grounded.

[0016] The digital-to-analog conversion circuit includes an MCU and a resistor R5 connected to the PWM output end of the MCU, and the resistor R5 is connected to the positive input end of the operational amplifier U1; the voltage divider circuit is connected to the analog-to-digital conversion input end of the MCU; the voltage divider circuit includes a resistor R2 and a resistor R3, and the resistor R3 is grounded.

[0017] The positive input terminal of the operational amplifier U1 is also connected to a filter circuit, and the filter circuit includes a resistor R6 and a capacitor C1 connected in parallel. The resistor R6 and the capacitor C1 are connected in parallel and grounded.

[0018] A aging method for a capacitor constant power aging device, the process is as follows: A. First, after the charging power supply is turned on, a power size instruction is issued through the host computer; B. After the single-chip microcomputer receives the instruction, the MCU receives the instruction and outputs a PWM value after parsing; C. The PWM is converted into an analog quantity through an integration circuit and used as a reference voltage REF of a feedback circuit; D. A sampling current is obtained by connecting a resistor and transmitted to the reverse input terminal of an amplifier of the feedback circuit; F. The sampling current and the reference voltage signal are compared by an operational amplifier to control the conduction or closing of a switch device, and the purpose of forming a constant current is achieved through repeated cycles.

[0019] The feedback circuit includes two operational amplifiers. After the charging power supply HV+ terminal passes through a resistor and reaches the operational amplifier U2, it operates with the reference voltage REF. The higher the voltage at the charging power supply HV+ terminal, the lower the output voltage of the operational amplifier U2, thereby achieving the purpose of constant power.

[0020] The charging power source HV+ reaches the single-chip microcomputer through the voltage feedback circuit for analog-to-digital conversion, and the PWM duty cycle is dynamically changed after software calculation. The voltage feedback circuit is connected to the inverting input terminal of the operational amplifier U1, and forms an adder with the current sampling signal. The higher the voltage of the charging power source HV+, the higher the voltage of the inverting input terminal of the operational amplifier U1, and the current flowing through the current sampling resistor also becomes lower accordingly to reach the reference voltage REF, thereby achieving the purpose of constant power.

[0021] The present invention is a constant power aging device, which dynamically adjusts the charging current of the capacitor to be aged according to the voltage loaded on the capacitor, so that a larger charging current is given when the voltage is low, and the charging current is automatically reduced as the voltage rises, so as to control the heat generated during the aging of the capacitor and prevent the electrolyte from evaporating due to excessive temperature. The present invention can greatly improve the quality of the capacitor and extend the service life of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The circuit structure schematic diagram of the specific implementation example 1 of the present invention is shown in FIG0

[0023] Figure 2 It is a circuit structure principle diagram of a specific implementation example 2 of the present invention;

[0024] Figure 3 It is a circuit structure principle diagram of a specific implementation example 3 of the present invention;

[0025] Figure 4 It is a circuit structure principle diagram of a specific implementation example 4 of the present invention;

[0026] Figure 5 This is a circuit structure schematic diagram of specific implementation example 5 of the present invention.

[0027] Figure 6 This is a schematic diagram of the circuit structure of multiple aging units connected in parallel according to the solution of the present invention.

[0028] Figure 7 It is a flowchart of the aging method scheme of the device of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with examples and drawings. It should be noted that the following description is only to help readers better understand this patent, and therefore only describes one or several specific implementations. The scope of protection of this patent is not limited to the specific implementations described below, but should include various changes made by those skilled in the art using conventional technical means.

[0030] The present invention provides a capacitor constant power aging circuit, which is used for an aluminum electrolytic capacitor constant power aging device, and includes a charging power supply output end, a capacitor Cx to be aged, a transistor Q1, and an operational amplifier U1. In addition, a reference voltage REF is connected to the positive input end of the operational amplifier; the charging power supply output end forms a charging loop with the capacitor Cx, the transistor Q1 and a resistor R1, and the resistor R1 is grounded; at the same time, a feedback circuit and a reverse adder are connected to the input end of the operational amplifier U1 to form a constant current source.

[0031] See attached for details Figure 1 ,like Figure 1The circuit structure schematic diagram of the present invention is shown (the monitoring control management unit is not shown). In this embodiment, the charging power supply output terminal includes: a positive output terminal HV+ and a negative output terminal HV-, which are connected in sequence to the capacitor Cx to be aged and the transistor Q1 of the positive output terminal HV+, and the resistor R1 connected to the emitter of the transistor Q1, and then connected to the negative output terminal HV- of the charging power supply; the base terminal of the transistor Q1 is connected to the output terminal of the operational amplifier U1; the charging power supply output terminal and the capacitor Cx, the transistor Q1 and the resistor R1 form a charging loop, and the resistor R1 is grounded; at the same time, a resistor R2 is connected between the reverse input terminal of the operational amplifier U1 and the positive output terminal HV+ of the charging power supply, and a resistor R4 is connected between the reverse input terminal of the operational amplifier U1 and the emitter of the transistor Q1; the transistor Q1, the operational amplifier U1, the resistor R1 and the resistor R4 form a constant current source. The operational amplifier U1 and the resistor R2 form a voltage feedback circuit. The operational amplifier U1, the resistor R4 and the transistor Q1 form an inverse adder. The higher the charging voltage, the smaller the current flowing through the constant current source. In addition, a reference voltage REF is connected to the positive input terminal of the operational amplifier to adjust the power of the entire device. The circuit device has a simple structure, the aged circuit is stable, and the constant current source is stable.

[0032] Figure 2 The circuit structure principle diagram of the specific implementation case 2 of the present invention is shown; as shown in the figure, the reverse input terminal 2 of the operational amplifier U1 and the emitter of the transistor Q1 are directly connected, the resistor R2 and the resistor R3 are connected between the positive input terminal 3 of the operational amplifier U1 and the positive charging power supply output terminal, and the output terminal 6 of the operational amplifier U2 is connected to the positive input terminal 3 of the operational amplifier U1, and the reverse input terminal 2 of the operational amplifier U2 is connected to the node between the resistor R3 and the resistor R2; the reference voltage REF is connected to the positive input terminal 3 of the operational amplifier U2. In this embodiment, the resistor R2, the resistor R3, and the operational amplifier U2 form an inverting amplifier circuit, providing a voltage feedback network for the constant current source. When the charging voltage is higher, the output voltage of the operational amplifier U2 is lower, and the reference voltage provided to the constant current source is also smaller, so as to achieve the purpose of constant power.

[0033] Figure 3 It is a circuit structure schematic diagram of a specific implementation case 3 of the present invention; in this embodiment, a rectifier bridge D1 is connected between the transistor Q1 and the capacitor Cx to be aged, the capacitor Cx and the rectifier bridge D1, the transistor Q1, and the resistor R1 form a charging and discharging circuit, the transistor Q1 and the operational amplifier U1 and the resistor R1 form a constant current source; the resistor R2 and the resistor R3, the operational amplifier U2 form an inverting amplifier; by adding the rectifier bridge D1, the reverse or forward power supply voltage can reach a stable constant current source, eliminate voltage or current waves, and convert alternating current into direct current.

[0034] Figure 4 It is a circuit structure principle diagram of a specific implementation case 4 of the present invention; in this embodiment, a rectifier bridge D1 is connected between the transistor Q1 and the capacitor Cx to be aged, the negative terminal of the capacitor Cx is connected to the AC input terminal 2 of the rectifier bridge, and the AC input terminal 1 of the rectifier bridge is connected to the negative terminal HV- of the charging power supply output terminal; the collector of the transistor Q1 is connected to the DC voltage output positive terminal 3 of the rectifier bridge D1, and the DC voltage output negative terminal 4 of the rectifier bridge D1 is grounded; at the same time, a resistor R2 is connected between the reverse input terminal of the operational amplifier U1 and the positive output terminal HV+ of the charging power supply, and a resistor R4 is connected between the reverse input terminal of the operational amplifier U1 and the emitter of the transistor Q1; and then the resistor R1 is connected and then grounded.

[0035] The capacitor Cx to be aged forms a charging and discharging circuit with the rectifier bridge D1, transistor Q1, and resistor R1. At the same time, resistor R1 is also a current sampling resistor. Transistor Q1, operational amplifier U1, resistor R1, and resistor R4 form a constant current source. Operational amplifier U1 and resistor R2 form a voltage feedback network. Operational amplifier U1, resistor R4, and transistor Q1 form a reverse adder. The higher the charging voltage, the smaller the current flowing through the constant current source. In addition, a reference voltage REF is connected to the positive input terminal of the operational amplifier to adjust the power of the entire device.

[0036] Figure 5 The circuit structure schematic diagram of the specific implementation case 5 of the present invention, a rectifier bridge D1 is connected between the transistor Q1 and the capacitor Cx to be aged, the negative terminal of the capacitor Cx is connected to the AC input terminal 2 of the rectifier bridge D1, and the AC input terminal 1 of the rectifier bridge is connected to the negative terminal HV- of the charging power supply output terminal; the collector of the transistor Q1 is connected to the DC voltage output positive terminal 3 of the rectifier bridge D1, and the DC voltage output negative terminal 4 of the rectifier bridge D1 is grounded; the emitter of the transistor Q1 is grounded through the resistor R1, and R1 is also a current sampling resistor;

[0037] The reverse input terminal of the operational amplifier U1 and the emitter of the transistor Q1 are short-circuited, but in this embodiment, a voltage divider circuit and a digital-to-analog conversion circuit are connected between the forward input terminal of the operational amplifier U1 and the positive charging power supply output terminal.

[0038] The digital-to-analog conversion circuit includes a single-chip microcomputer MCU (STM8S103F single-chip microcomputer is used in this embodiment) and a resistor R5, a resistor R6 and a capacitor C1 connected to the PWM (i.e., Pulse Width Modulation) output end of the MCU, and the resistor R6 and the capacitor C1 are connected in parallel and grounded; the voltage divider circuit is connected to the analog-to-digital conversion input end of the MCU; the voltage divider circuit includes a resistor R2 and a resistor R3, and the resistor R3 is grounded.

[0039] Figure 6 The charging power supply, the capacitor to be aged Cx and the rectifier bridge D1, the transistor Q1 and the resistor R1 form a charging and discharging circuit. The transistor Q1 and the operational amplifier U1 and the resistor R1 and the resistor R8 form a constant current source. The above constitutes an aging unit.

[0040] The aging unit is connected to a voltage divider circuit and a digital-to-analog conversion circuit and receives commands from the host computer through the serial port, forming a whole aging device. Multiple aging units can be connected in parallel to unify the external voltage divider circuit and digital-to-analog conversion circuit. Such aging units can be connected in parallel to form multiple aging units, and the aged capacitors Cx can be processed in batches.

[0041] See Figure 6 The schematic diagram of the circuit structure of multiple aging units in parallel in the scheme of the present invention, in which N aging units are connected in parallel, see unit 1. When the charging power supply is turned on, the HV+ terminal is connected to the positive terminal of the capacitor Cx, and the negative terminal of the aged capacitor Cx is connected to the transistor Q1 through the rectifier bridge D1. The negative terminal of the capacitor Cx is connected to the AC input terminal 2 of the rectifier bridge D1, and the AC input terminal 1 of the rectifier bridge is connected to the negative terminal HV- of the charging power supply output terminal and grounded; the collector of the transistor Q1 is connected to the DC voltage output positive terminal 3 of the rectifier bridge D1, and the DC voltage output negative terminal 4 of the rectifier bridge D1 is grounded; the emitter of the transistor Q1 is grounded through the resistor R1, and R1 is also a current sampling resistor; the reverse input terminal of the operational amplifier U1 is connected to the emitter of the transistor Q1, and in this embodiment, a resistor R7 is connected, and the operational amplifier U1 The negative input terminal is connected to the emitter of transistor Q1, and in this embodiment is connected to the emitter of transistor Q1 through resistor R8; in this embodiment, a voltage divider circuit and a digital-to-analog conversion circuit are externally connected to the positive input terminal of operational amplifier U1.

[0042] The digital-to-analog conversion circuit includes a single-chip microcomputer MCU (in this embodiment, a

[0043] The invention relates to a STM8S103F single chip microcomputer) and a resistor R5, a resistor R6 and a capacitor C1 connected to the PWM (i.e., Pulse Width Modulation) output terminal of the MCU, wherein the resistor R6 and the capacitor C1 are connected in parallel and grounded; the voltage divider circuit is connected to the analog-to-digital conversion input terminal of the MCU; the voltage divider circuit comprises a resistor R2 and a resistor R3, and the resistor R3 is grounded.

[0044] See Figure 7The flowchart of the aging method of the device of the present invention is as follows: A. First, after the charging power is turned on, a power size instruction is issued by the host computer; B. After the single-chip microcomputer receives the instruction, the MCU receives the instruction and outputs the PWM value after parsing; C. The PWM is converted into an analog quantity through an integration circuit as the reference voltage REF of the feedback circuit; D. The sampling current is obtained by connecting a resistor and transmitted to the reverse input terminal of the amplifier of the feedback circuit; F. The sampling current and the reference voltage signal are compared by the operational amplifier to control the conduction or closing of the switch device, and the purpose of repeated circulation is to form a constant current.

[0045] Specifically, the host computer sends a power command through the serial port, and the microcontroller interprets the received command into a PWM value of the corresponding duty cycle (ie, Pulse Width Modulation). The integrator circuits R5 and C1 convert the PWM into a corresponding analog REF signal to adjust the power.

[0046] In the charging circuit of the capacitor to be aged, R1 is a current sampling resistor. The sampled current signal is sent to the reverse input terminal of the operational amplifier U1 and compared with the reference voltage REF. When the current signal is less than the reference voltage REF, the operational amplifier U1 outputs a high level and the transistor Q1 is turned on; when the current signal is greater than the reference voltage REF, the operational amplifier U1 outputs a low level and the transistor Q1 is turned off. Repeated cycles achieve the purpose of constant current.

[0047] After the charging power supply HV+ reaches the operational amplifier U2 through the voltage feedback network (feedback circuit) resistor R2, it is calculated with the reference voltage REF. The higher the HV+ voltage, the lower the output voltage of the operational amplifier U2, achieving the purpose of constant power. Similarly, the charging power supply HV+ can also reach the microcontroller U3 through the voltage feedback network resistor R2 for analog-to-digital conversion, and dynamically change the PWM duty cycle after software calculation, which also achieves the purpose of constant power. In applications without operational amplifier U2, the voltage feedback resistor is connected to the inverting input terminal of the operational amplifier U1, forming an adder with the current sampling signal. The higher the HV+ voltage, the higher the voltage at the inverting input terminal of the operational amplifier U1, and the current flowing through the current sampling resistor R1 also becomes lower accordingly to reach the reference voltage REF, which also achieves the purpose of constant power.

[0048] The present invention is a constant power aging device, which dynamically adjusts the charging current of the capacitor to be aged according to the voltage loaded on the capacitor, so that a larger charging current is given when the voltage is low, and the charging current is automatically reduced as the voltage rises, so as to control the heat generated by the capacitor during aging and prevent the electrolyte from evaporating due to excessive temperature. The present invention can greatly improve the quality of the capacitor and extend the service life of the capacitor.

Claims

1. A capacitor constant power aging circuit, used for an aluminum electrolytic capacitor constant power aging device, characterized in that: It includes a charging power source, a capacitor Cx to be aged, a semiconductor switch device, and a feedback circuit which are electrically connected in sequence, wherein: The output end of the semiconductor switch device is electrically connected to a resistor R1 and is grounded; The feedback circuit comprises an operational amplifier, and a reference voltage is connected to the positive input terminal of the operational amplifier; The charging power supply output terminal forms a charging loop with the capacitor to be aged, the semiconductor switch device and the resistor R1. At the same time, the feedback circuit feeds back the voltage and current and automatically adjusts the constant current value as the voltage changes to form a constant current source.

2. A capacitor constant power aging circuit according to claim 1, characterized in that: The semiconductor switch device is a transistor Q1, the output end of the operational amplifier is connected to the base of the transistor Q1, the feedback circuit is a resistor R2 connected between the reverse input end of the operational amplifier and the positive end of the capacitor Cx, and the emitter of the transistor Q1 and the reverse input end of the operational amplifier are further connected to a resistor R4; wherein the operational amplifier The operational amplifier forms an inverting adder with resistors R2 and R4.

3. A capacitor constant power aging circuit according to claim 2, characterized in that: The reverse input terminal of the operational amplifier is connected to the emitter of the transistor Q1, and resistors R2 and R3 are connected in series between the positive input terminal of the operational amplifier U1 and the output terminal of the positive charging power supply. The positive input terminal of the operational amplifier U1 is connected to the output terminal of another operational amplifier U2, and the reference voltage REF is connected to the positive input terminal of the operational amplifier U2; the reverse input terminal of the operational amplifier U2 is connected to the node between the resistor R3 and the resistor R2.

4. A capacitor constant power aging circuit according to claim 3, characterized in that: A rectifier bridge D1 is connected between the transistor Q1 and the capacitor Cx to be aged. The capacitor Cx, the rectifier bridge D1, the transistor Q1 and the resistor R1 form a charging and discharging circuit. The transistor Q1, the operational amplifier U1 and the resistor R1 form a constant current source. The resistor R2, the resistor R3 and the operational amplifier U2 form an inverting amplifier.

5. A capacitor constant power aging circuit according to claim 2, characterized in that: A rectifier bridge D1 is connected between the transistor Q1 and the capacitor to be aged Cx, a DC voltage positive output terminal of the rectifier bridge D1 is connected to the collector of the transistor, and a DC voltage negative output terminal of the rectifier bridge D1 is grounded.

6. A capacitor constant power aging circuit according to claim 1, characterized in that: The semiconductor switch device is a transistor Q1, and the feedback circuit includes an operational amplifier U1, a voltage divider circuit and a digital-to-analog conversion circuit are connected between the positive input terminal of the operational amplifier U1 and the positive charging power supply output terminal; the reverse input terminal of the operational amplifier U1 is connected to the emitter of the transistor Q1; a rectifier bridge D1 is connected between the transistor Q1 and the capacitor to be aged Cx, the DC voltage positive output terminal of the rectifier bridge D1 is connected to the collector of the transistor, and the DC voltage negative output terminal of the rectifier bridge D1 is grounded.

7. A capacitor constant power aging circuit according to claim 6, characterized in that: The digital-to-analog conversion circuit includes an MCU and a resistor R5 connected to the PWM output end of the MCU, and the resistor R5 is connected to the positive input end of the operational amplifier U1; the voltage divider circuit is connected to the analog-to-digital conversion input end of the MCU; the voltage divider circuit includes a resistor R2 and a resistor R3, and the resistor R3 is grounded.

8. A capacitor constant power aging circuit according to claim 7, characterized in that: The positive input terminal of the operational amplifier U1 is also connected to a filter circuit, and the filter circuit is grounded via a capacitor C1.

9. A aging method using the capacitor constant power aging circuit according to claim 7 or 8, characterized in that: A. First, after the charging power is turned on, the power size instruction is issued through the host computer; B. After the microcontroller receives the instruction, the MCU receives the instruction and parses it and then outputs the PWM value: C. The PWM is converted into an analog quantity through an integration circuit and used as a reference voltage REF of a feedback circuit; D. Obtain the sampling current by connecting a resistor and transmit it to the inverting input terminal of the amplifier of the feedback circuit; F. The sampling current and the reference voltage signals are compared through the operational amplifier to control the on or off of the switching device, and the cycle is repeated to form a constant current.

10. The aging method according to claim 9, characterized in that: The feedback circuit includes two operational amplifiers. After the charging power reaches the operational amplifier U2 through a resistor, it performs an operation with the reference voltage REF. The higher the charging power voltage is, the lower the output voltage of the operational amplifier U2 is, thereby achieving the purpose of constant power.

11. The aging method according to claim 9, characterized in that: The charging power source reaches the single-chip microcomputer through the voltage feedback circuit for analog-to-digital conversion, and the PWM duty cycle is dynamically changed after software calculation. The voltage feedback circuit is connected to the inverting input terminal of the operational amplifier U1, and forms an adder with the current sampling signal. The higher the charging power source voltage is, the higher the voltage at the inverting input terminal of the operational amplifier U1 is, and the current flowing through the current sampling resistor is correspondingly lowered to reach the reference voltage REF, thereby also achieving the purpose of constant power.

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