Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device comprises a lower semiconductor chip, an upper semiconductor chip arranged above an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and an adhesive material fixing the upper semiconductor chip to the lower semiconductor chip, wherein the metallization layer has a structure having an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along the contour of the upper semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The semiconductor device can be, for example, a semiconductor package including more than one semiconductor chip (for example, two semiconductor chips arranged stacked on each other). The stacked semiconductor chips can, for example, be a power semiconductor chip and an associated control chip. Here, the upper semiconductor chip can be fixed to the upper main side of the lower semiconductor chip by means of an adhesive material such as an adhesive. Depending on parameters such as the viscosity of the corresponding adhesive material, the amount of adhesive material deposited, etc., the upper semiconductor chip will "float (aufschwimmen)" on the adhesive material and thus leave its set position. This may lead to the following situation: the upper semiconductor chip causes a short circuit in the semiconductor device or cannot be properly electrically connected (this is, for example, because if the upper semiconductor chip is not correctly positioned, the wire automatic bonding device cannot reach the connection portion of the upper semiconductor chip). An improved semiconductor device or an improved method for manufacturing a semiconductor device can help to overcome these and other problems.

[0003] The object on which the invention is based is achieved by the features of the independent claims.

[0004] Advantageous embodiments and developments of the invention are described in the dependent claims. Summary of the invention

[0005] A specific example relates to a semiconductor device comprising: a lower semiconductor chip; an upper semiconductor chip arranged above an upper main side of the lower semiconductor chip; a metallization layer arranged on the upper main side of the lower semiconductor chip; and an adhesive material that fixes the upper semiconductor chip to the lower semiconductor chip, wherein the metallization layer has a structure having an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along a contour of the upper semiconductor chip.

[0006] A specific example relates to a semiconductor device, which includes: a lower semiconductor chip; an upper semiconductor chip, which is arranged above the upper main side of the lower semiconductor chip; a metallization layer, which is arranged on the upper main side of the lower semiconductor chip; and an adhesive material, which fixes the upper semiconductor chip on the lower semiconductor chip, wherein the metallization layer has a surface structuring portion, which has a plurality of recesses, wherein the surface structuring portion is arranged along the contour of the upper semiconductor chip.

[0007] A specific example relates to a method for manufacturing a semiconductor device, the method comprising: providing a lower semiconductor chip; applying a metallization layer on an upper main side of the lower semiconductor chip; structuring the metallization layer; fixing an upper semiconductor chip on the upper main side of the lower semiconductor chip by means of an adhesive material, wherein the metallization layer is structured in such a way that the metallization layer has an increased roughness along the contour of the upper semiconductor chip compared to the rest of the metallization layer, wherein this structure limits the wetting (Benetzung) of the upper main side of the lower semiconductor chip by the adhesive material to a region below the upper semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings illustrate examples and are used to explain the principles of the present invention in conjunction with the specification. The elements of the accompanying drawings are not necessarily drawn to scale with each other. The same reference numerals may represent corresponding, similar or identical parts to each other.

[0009] Figure 1A and 1B A top view of a semiconductor device is shown ( Figure 1A ) and cross-sectional view ( Figure 1B ), the semiconductor device having two semiconductor chips stacked one above the other and a structured metallization layer;

[0010] Figure 2 shows a top view of another semiconductor device in which the structure includes a dedicated current carrying path;

[0011] FIG. 3A to FIG. 3C 3D views of semiconductor devices at different manufacturing stages are shown. Figure 3A In the deposition of bonding material, Figure 3B In the process, an upper semiconductor chip is placed on the adhesive material. Figure 3C It shows the situation that the adhesive material that flows on the metallization layer due to its low viscosity is constrained by the structure;

[0012] FIG. 4A to FIG. 4D showing different possible shapes of the recesses of the structure;

[0013] Figure 5 A flow chart showing a method for manufacturing a semiconductor device. DETAILED DESCRIPTION

[0014] In this specification, the terms “coupled” and / or “electrically coupled” do not mean that the elements must be directly coupled; intermediate elements may be provided between the “coupled” or “electrically coupled” elements.

[0015] A semiconductor device including a plurality of semiconductor chips is described below. The semiconductor chips may be of different types, manufactured by different technologies and, for example, include integrated circuits, electro-optical circuits or electromechanical circuits and / or passive components. The semiconductor chip may, for example, be designed as a power semiconductor chip, such as a power MOSFET (metal oxide semiconductor field effect transistor), an IGBT (bipolar transistor with an insulated gate), a JFET (junction field effect transistor), a power bipolar transistor or a power diode. In addition, the semiconductor chip may include a control circuit, a microprocessor or a micro-electromechanical component. In one example, a semiconductor chip with a vertical structure may appear, that is, the semiconductor chip may be manufactured so that an electric current may flow in a direction perpendicular to the main surface of the semiconductor chip. In one example, a semiconductor chip with a vertical structure may have a turn-on element on its two main surfaces, that is, on its upper side and lower side. The semiconductor chip may be made of a specific semiconductor material such as Si, SiC, SiGe, GaAs or GaN.

[0016] The semiconductor chip may have an electrode (or a connection portion or a connection surface) that allows electrical connection to be established with an integrated circuit included in the semiconductor chip. One or more metal layers may be applied to the electrodes of the semiconductor chip. The metal layer may be manufactured in any desired geometry and any desired material composition. The metal layer may exist, for example, in the form of a layer covering an area. Any desired metal or metal alloy (e.g., aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium) may be used as the material. The metal layer does not have to be homogeneous or made of only one material, that is, the material contained in the metal layer may have different compositions and different concentrations. The electrode may be located on the active main surface of the semiconductor chip.

[0017] The lower semiconductor chip described below can be placed on a system carrier (lead frame). The system carrier can have any shape, size and any material. The system carrier can include a carrier (die pad) and connecting wires (leads). During the manufacture of the semiconductor device, the carrier and the connecting wires can be connected to each other. The carrier and the connecting wires can also be made of one piece.

[0018] Figure 1AA top view of a schematic example of a semiconductor device 100 is shown. The semiconductor device 100 has a lower semiconductor chip 101 and an upper semiconductor chip 102. The upper semiconductor chip 102 is arranged above the upper main side 101_1 of the lower semiconductor chip 101. A metallization layer 103 is arranged on the upper main side 101_1 of the lower semiconductor chip 101, for example, between the lower semiconductor chip 101 and the upper semiconductor chip 102. The upper semiconductor chip 102 is fixed to the lower semiconductor chip 101 by means of an adhesive material 104. The metallization layer 103 has a structure 105 with increased roughness (in other words, a surface structure with a plurality of recesses), which is arranged along the contour 102_1 of the upper semiconductor chip 102.

[0019] Here, the term "roughness" refers in particular to a structured surface with a predefined pattern in the metallization layer 103. This roughness or surface structuring influences the wetting properties of a liquid, such as the adhesive material 104, deposited onto the metallization layer (for example, by increasing the contact angle). In particular, this can prevent the liquid from spreading on areas with increased roughness.

[0020] The lower semiconductor chip 101 may be, for example, a power semiconductor chip designed to operate at high voltage and / or high current. The lower semiconductor chip 101 may be, for example, a FET or an IGBT. The lower semiconductor chip 101 may have a vertical transistor structure having a first power electrode on the upper main side 101_1 and a second power electrode on the opposite lower main side. The first power electrode may be, for example, a source or an emitter. The second power electrode may be, for example, a drain or a collector. However, according to one example, the electrodes mentioned may also be arranged on the opposite main sides of the lower semiconductor chip 101, respectively. The lower semiconductor chip 101 may have other electrodes, for example, a gate or a measuring electrode. The gate or the measuring electrode may be arranged, for example, on the upper main side 101_1.

[0021] The upper semiconductor chip 102 may be, for example, a driver chip designed to control the lower semiconductor chip 101. The upper semiconductor chip 102 may be connected to the lower semiconductor chip 101 by, for example, a conductive connection such as a bonding wire. Figure 1A The upper semiconductor chip 102 may have a lateral dimension that is significantly smaller than the lateral dimension of the lower semiconductor chip 101 (e.g., about half the size or even smaller). According to one example, the upper semiconductor chip 102 has electrical connection terminals only on the upper main side facing away from the lower semiconductor chip 101. The lower main side of the upper semiconductor chip 102 facing the lower semiconductor chip 101 may have no electrical connection terminals.

[0022] The adhesive material 104 may be an adhesive, for example a non-conductive adhesive. The adhesive material 104 may completely or at least partially cover the lower main side of the upper semiconductor chip 102, and the adhesive material may electrically isolate the two semiconductor chips 101, 102 from each other. Figure 1A As shown, the adhesive material 104 may protrude beyond the outline 102_1 of the upper semiconductor chip 102. The adhesive material 104 may be deposited on the upper main side 101_1 of the lower semiconductor chip 101 by means of a suitable deposition method. For example, one or more droplets of the adhesive material 104 may be deposited on the upper main side 101_1 by a dispenser.

[0023] The adhesive material 104 may have a high viscosity or may also have a low viscosity. Here, "high viscosity" may mean that the droplets of adhesive material 104 deposited on the upper main side 101_1 do not or only slightly disperse after deposition (i.e., the shape of the adhesive material is substantially maintained). Here, "low viscosity" may mean that the droplets of adhesive material 104 deposited on the upper main side 101_1 tend to disperse after deposition (i.e., the shape of the adhesive material is substantially not maintained).

[0024] After the deposition of the adhesive material 104, the upper semiconductor chip 102 is placed on the adhesive material. Next, the adhesive material 104 can be hardened, for example, by heating in an oven. Before hardening, the upper semiconductor chip 102 is held in place only by viscosity or surface tension exerted by the adhesive material 104. In the case of using an adhesive material 104 with low viscosity in the semiconductor device 100, if the low-viscosity adhesive material 104 has spread on the upper main side 101_1, the upper semiconductor chip 102 may "float" from the desired position.

[0025] After the hardening of the adhesive material 104, if the actual position of the upper semiconductor chip 102 is seriously deviated from its expected position, the connection terminals on the upper semiconductor chip 102 may not be reached by the wire bonding device. In addition, electrical short circuits may be caused by the upper semiconductor chip 102 that is moved in position. As described in more detail below, the structure 105 can help avoid these problems.

[0026] The metallization layer 103 can be a metallization portion of an electrode (especially a power electrode) of the lower semiconductor chip 101. The metallization layer 103 can have one or more arbitrary suitable metals or metal alloys, or the metallization layer can be composed of Al, Ag, Cu or Ti, for example. The metallization layer 103 can be manufactured using a sputtering process. The metallization layer 103 can also be arranged below the lower main side of the upper semiconductor chip 102. The adhesive material 104 can electrically isolate the upper semiconductor chip 102 from the metallization layer 103. The metallization layer 103 can also have one or more additional connection areas 103_1, which are designed, for example, to provide a gate connection terminal or a measurement connection terminal of the lower semiconductor chip 101.

[0027] The structure 105 in the metallization layer 103 may completely surround the upper semiconductor chip 102 (eg, Figure 1A The structure 105 may be arranged along only one side, only two sides (e.g., L-shaped), or three sides (e.g., U-shaped) of the upper semiconductor chip 102. The structure 105 may extend into a region inside the outline 102_1 of the upper semiconductor chip 102, or the structure may be completely arranged outside the outline 102_1.

[0028] The structure 105 may have a plurality of recesses 106 which are formed in the metallization layer 103. The recesses 106 may be arranged in the substrate. For example, the recesses 106 may be produced in the metallization layer 103 by an etching process. The recesses 106 may be holes which extend completely through the metallization layer 103.

[0029] According to one example, the metallization layer may have a thickness in the range of 1 μm to 100 μm, in particular 2 μm to 30 μm or 5 μm to 20 μm. The metallization layer may in particular have a thickness of about 10 μm. All recesses 106 may have the same size. However, the recesses 106 may also have different sizes, for example, the recess 106 arranged closer to the upper semiconductor chip 102 may have different sizes from other recesses 106 arranged further away from the upper semiconductor chip 102. The recess 106 may have an edge length or diameter in the range of 0.05 mm to 0.5 mm (for example, about 0.1 mm).

[0030] like Figure 1A As shown, the structure 105 may have a substantially checkerboard pattern (in other words, the recesses 106 may be arranged in a checkerboard pattern). However, the structure 105 may also have another suitable pattern - for example, a pattern with circular recesses, triangular recesses, etc.

[0031] Figure 1B Shown along Figure 1A The line AA in FIG. 1 passes through the cross section of the semiconductor device 100. Figure 1BAs shown, the metallization layer 103 may extend below the area below the upper semiconductor chip 102. The adhesive material 104 may completely fill the area below the upper semiconductor chip 102, and the adhesive material may laterally protrude beyond the outline of the upper semiconductor chip 102. Figure 1A and 1B As can be seen in FIG, structures 105 represent areas that have increased roughness compared to the rest of the metallization layer 103. This increased roughness prevents the adhesive material 104 from flowing out of the area within the structures 105 after being applied (eg, by increasing the contact angle).

[0032] The semiconductor device 100 may include a carrier, such as a lead frame (English "leadframe"), on which the lower semiconductor chip 101 is arranged and may also be electrically connected to the carrier. The power connection terminal of the semiconductor device 100 may be arranged next to the upper semiconductor chip 102 on the metallization layer 103 and may be electrically connected to the upper semiconductor chip. The semiconductor device 100 may also have a molded body (English "molded body"), which encapsulates the lower semiconductor chip 101 and the upper semiconductor chip 102.

[0033] Figure 2 Another semiconductor device 200 is shown, which may be identical to the semiconductor device 100 except for the differences noted below.

[0034] With Figure 1A The structure 105 of the checkerboard pattern shown in FIG. 1 may result in that the area of ​​the metallization layer 103 directly below the upper semiconductor chip 102 (i.e., within the structure 105) and the area outside the structure 105 are not electrically connected to each other or are only poorly electrically connected to each other. However, it may be desirable that the areas of the metallization layer 103 inside and outside the structure 105 are electrically connected to each other. Therefore, the structure 105 may be configured such that a current path is guided through the structure 105 and connects these areas to each other.

[0035] exist Figure 2 In the example of FIG. 1 , the structure 105 has a dedicated current path 201. The current path 201 may have any suitable shape and arrangement. However, the current path 201 should be constructed so that the current passing through the current path does not counteract the intended effect of the structure 105 (i.e., preventing the upper semiconductor chip 102 from floating out of its intended position).

[0036] Figure 3A and 3B A semiconductor device 100 or 200 is shown at different production stages according to one example of a method for manufacturing a semiconductor device.

[0037] Figure 3AThe stage is shown at which the adhesive material 104 has been deposited on the lower semiconductor chip 101, in particular the metallization layer 103. Individual droplets 301 of the adhesive material 104 may in particular be deposited adjacent to one another. Figure 3B The stage is shown after the upper semiconductor chip 102 has been placed on the adhesive material 104. The adhesive material 104 may be pressed out laterally under the upper semiconductor chip 102 by the weight of the upper semiconductor chip 102 or by the pressure applied by the placement device. However, as already explained above, the structure 105 prevents the adhesive material 104 from being distributed over a larger area. This can be achieved, for example, by increasing the contact angle between the adhesive material 104 and the metallization layer 103 by the structure 105, which reduces the wettability of the metallization layer 103 in the region of the structure 105.

[0038] exist Figure 3A In the example of FIG, the bonding material 104 is shown in the form of a single droplet 301 after deposition. However, depending on the viscosity or hydrophilicity of the bonding material 104 used in each case, it may also be the case that the droplet 301 spreads after deposition and wets the entire area of ​​the metallization layer 103 within the structure 105, for example. Figure 3C An example of this is shown. However, even in this case, the adhesive material 104 cannot go over the area with the structure 105.

[0039] FIG. 4A to FIG. 4D Shown in top view Figure 3A , which may be used in place of a checkerboard pattern in structure 105. Figure 4A or Figure 4B As shown in , the structure 105 may, for example, have a pattern of circular recesses or holes 106. Figure 4A As shown in , the recesses 106 can be arranged spaced apart from each other. In this way, a current path can be constructed between an area inside the structure 105 and an area outside the structure 105. However, the recesses 106 can also be arranged so that adjacent recesses 106 touch each other (see Figure 4B ).

[0040] Other possible shapes of the recess are, for example, Figure 4C The triangular recess 106 shown in FIG. Figure 4D The diamond-shaped recess 106 is shown in FIG. The tip of the triangular recess 106 may point away from the upper semiconductor chip 102, or the tip may also point toward the upper semiconductor chip.

[0041] Figure 5 The flowchart of the method for manufacturing a semiconductor device is shown. The method 500 can be used to manufacture the semiconductor device 100 or 200, for example.

[0042] Method 500 includes: in 501, providing a lower semiconductor chip; in 502, applying a metallization layer on the upper main side of the lower semiconductor chip; in 503, structuring the metallization layer; in 504, fixing the upper semiconductor chip on the upper main side of the lower semiconductor chip by means of an adhesive material, wherein the metallization layer is structured in such a way that it has an increased roughness along the contour of the upper semiconductor chip compared to the rest of the metallization layer, wherein this structure limits the wetting of the upper main side of the lower semiconductor chip by the adhesive material to the area below the upper semiconductor chip.

[0043] The method 500 may further include sputtering to apply the metallization layer 103. After applying the metallization layer 103, a photoresist may be applied to photolithographically structure the metallization layer 103. Here, the metallization layer 103 covered by the structured photoresist may be etched (especially wet etched). Thus, the structure 105 and any other structures may be produced together in the metallization layer 103.

[0044] According to method 500, the fixing of the upper semiconductor chip 102 may include applying the adhesive material 104 on the upper main side 101_1 by drop dispensing. One or more drops of the adhesive material 104 may be applied in such a way that, as already explained above, the spreading of the one or more drops of adhesive material 104 is limited by the structure 105 in the metallization layer 103.

[0045] According to method 500 , adhesive material 104 may be hardened, for example by heating in an oven, after fixing upper semiconductor chip 102 . During hardening, upper semiconductor chip 102 may be fixed in place by surface tension exerted by structure 105 on adhesive material 104 .

[0046] Example

[0047] The semiconductor device and the method for manufacturing the semiconductor device are further described below based on specific examples.

[0048] Example 1 is a semiconductor device, comprising: a lower semiconductor chip; an upper semiconductor chip arranged above an upper main side of the lower semiconductor chip; a metallization layer arranged on the upper main side of the lower semiconductor chip; and an adhesive material that fixes the upper semiconductor chip to the lower semiconductor chip, wherein the metallization layer has a structure having an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along a contour of the upper semiconductor chip.

[0049] Example 2 is a semiconductor device according to Example 1, wherein the structure has a plurality of recesses.

[0050] Example 3 is the semiconductor device of Example 2, wherein the recess is a hole extending completely through the metallization layer.

[0051] Example 4 is the semiconductor device according to Example 2 or 3, wherein the recess has an edge length or a diameter in the range of 0.05 mm to 0.5 mm.

[0052] Example 5 is a semiconductor device according to any one of the above examples, wherein the structure completely surrounds the upper semiconductor chip.

[0053] Example 6 is a semiconductor device according to any of the above examples, wherein the wetting of the upper main side of the lower semiconductor chip by the adhesive material is restricted by the structure to a region below the upper semiconductor chip.

[0054] Example 7 is a semiconductor device according to any one of the above examples, wherein the bonding material is an adhesive.

[0055] Example 8 is a semiconductor device according to any of the above examples, wherein the metallization layer is a metallization portion of an electrode of a lower semiconductor chip.

[0056] Example 9 is a semiconductor device according to any one of the above examples, wherein the metallization layer includes Cu or Al or consists of Cu or Al.

[0057] Example 10 is a semiconductor device according to any of the above examples, wherein the structure is configured so that there is a current path through the structure in the metallization layer, and the current path is between the area of ​​the metallization layer below the upper semiconductor chip and the area of ​​the metallization layer outside the outline of the upper semiconductor chip.

[0058] Example 11 is a semiconductor device, which includes: a lower semiconductor chip; an upper semiconductor chip arranged above the upper main side of the lower semiconductor chip; a metallization layer arranged on the upper main side of the lower semiconductor chip; and an adhesive material that fixes the upper semiconductor chip to the lower semiconductor chip, wherein the metallization layer has a surface structuring portion, the surface structuring portion has a plurality of recesses, wherein the surface structuring portion is arranged along the contour of the upper semiconductor chip.

[0059] Example 12 is the semiconductor device of Example 11, wherein the recesses are arranged relative to each other such that the distance therebetween is no greater than twice the diameter or edge length of the recesses.

[0060] Example 13 is a semiconductor device according to example 11 or 12, wherein the recess is a hole extending completely through the metallization layer.

[0061] Example 14 is a method for manufacturing a semiconductor device, the method comprising: providing a lower semiconductor chip; applying a metallization layer to the upper main side of the lower semiconductor chip; structuring the metallization layer; fixing the upper semiconductor chip to the upper main side of the lower semiconductor chip by means of an adhesive material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along the contour of the upper semiconductor chip compared to the rest of the metallization layer, wherein such a structure limits the wetting of the upper main side of the lower semiconductor chip by the adhesive material to the area below the upper semiconductor chip.

[0062] Example 15 is the method of Example 14, wherein applying the metallization layer comprises sputtering.

[0063] Example 16 is the method of Example 14 or 15, wherein structuring the metallization layer comprises applying a photomask and etching the metallization layer.

[0064] Example 17 is a method according to any one of Examples 14 to 16, wherein fixing the upper semiconductor chip includes applying the adhesive material on the upper main side by droplet dispensing in such a way that the spreading of one or more droplets of the adhesive material is limited by structures in the metallization layer.

[0065] Example 18 is the method according to any one of Examples 14 to 17, wherein the fixing of the upper semiconductor chip includes arranging the upper semiconductor chip on the adhesive material such that the upper semiconductor chip floats on the adhesive material.

[0066] Example 19 is a method according to any one of Examples 14 to 18, wherein fixing the upper semiconductor chip includes hardening the adhesive material, wherein during hardening, the upper semiconductor chip is fixed by surface tension applied to the adhesive material by structures in the metallization layer.

[0067] Example 20 is an apparatus having means for performing the method according to any one of Examples 14 to 19.

[0068] Although specific examples have been shown and described herein, it will be apparent to those skilled in the art that multiple alternative and / or equivalent configurations of the specific examples shown and described may be considered without departing from the scope of the invention. This application is intended to cover all matches or variations of the specific examples discussed herein. It is therefore intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: Lower semiconductor chip; an upper semiconductor chip arranged above the upper main side of the lower semiconductor chip; a metallization layer arranged on the upper main side of the lower semiconductor chip; an adhesive material that fixes the upper semiconductor chip to the lower semiconductor chip; Therein, the metallization layer has a structure having an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along a contour of the upper semiconductor chip.

2. The semiconductor device according to claim 1, wherein The structure has a plurality of recesses.

3. The semiconductor device according to claim 2, wherein: The recess is a hole that extends completely through the metallization layer.

4. The semiconductor device according to claim 2 or 3, wherein: The recess has an edge length or a diameter in the range of 0.05 mm to 0.5 mm.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The structure completely surrounds the upper semiconductor chip.

6. The semiconductor device according to any one of claims 1 to 3, wherein: The structure limits the wetting of the upper main side of the lower semiconductor chip by the adhesive material to a region below the upper semiconductor chip.

7. The semiconductor device according to any one of claims 1 to 3, wherein: The bonding material is an adhesive.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The metallization layer is the metallization of the electrodes of the lower semiconductor chip.

9. The semiconductor device according to any one of claims 1 to 3, wherein: The metallization layer includes Cu or Al.

10. The semiconductor device according to any one of claims 1 to 3, wherein: The structure is designed such that a current path is present in the metallization layer through the structure, the current path being located between a region of the metallization layer below the upper semiconductor chip and a region of the metallization layer outside the contour of the upper semiconductor chip.

11. A semiconductor device comprising: Lower semiconductor chip; an upper semiconductor chip arranged above the upper main side of the lower semiconductor chip; a metallization layer arranged on the upper main side of the lower semiconductor chip; an adhesive material that fixes the upper semiconductor chip to the lower semiconductor chip; Therein, the metallization layer has a surface structuring, which has a plurality of recesses, wherein the surface structuring is arranged along a contour of the upper semiconductor chip.

12. The semiconductor device according to claim 11, wherein The recesses are arranged relative to one another in such a way that the distance between them is no greater than twice the diameter or edge length of the recesses.

13. The semiconductor device according to claim 11 or 12, wherein: The recess is a hole that extends completely through the metallization layer.

14. A method for manufacturing a semiconductor device, the method comprising: Providing a semiconductor chip; applying a metallization layer on the upper main side of the lower semiconductor chip; structuring the metallization layer; fixing an upper semiconductor chip on an upper main side of the lower semiconductor chip by means of an adhesive material; wherein the metallization layer is structured in such a way that it has an increased roughness along the contour of the upper semiconductor chip compared to the rest of the metallization layer, In this case, the structure limits the wetting of the upper main side of the lower semiconductor chip by the adhesive material to a region below the upper semiconductor chip.

15. The method according to claim 14, wherein: Applying of the metallization layer comprises sputtering.

16. The method according to claim 14 or 15, wherein: Structuring the metallization layer comprises applying a photomask and etching the metallization layer.

17. The method according to claim 14 or 15, wherein: The fixing of the upper semiconductor chip comprises applying the adhesive material on the upper main side by droplet dispensing in such a way that the spreading of one or more drops of the adhesive material is limited by the structure in the metallization layer.

18. The method according to claim 14 or 15, wherein: The fixing of the upper semiconductor chip includes arranging the upper semiconductor chip on the adhesive material such that the upper semiconductor chip floats on the adhesive material.

19. The method according to claim 14 or 15, wherein: The fixing of the upper semiconductor chip includes hardening the adhesive material, wherein during the hardening, the upper semiconductor chip is fixed by surface tension applied to the adhesive material by the structure in the metallization layer.

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