Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, the method comprising the following steps: forming a first organic insulating layer on a semiconductor region; forming a bump base film, the bump base film including an edge portion in contact with the first organic insulating layer; heat treating the bump base film; and forming a second organic insulating layer, the second organic insulating layer covering the edge portion of the bump base film and the first organic insulating layer around the bump base film and contacting the first organic insulating layer, the second organic insulating layer being provided with a first opening exposing the surface of the bump base film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2019-035719, filed on February 28, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0004] JP2005-150578A and JP2017-228583A disclose technologies related to methods for manufacturing semiconductor devices. In the method disclosed in JP2005-150578A, a rewiring is formed by a conductive film (Ti film and Pd film from the bottom layer) used as a base film (under bump metal (UBM) film) of an Au bump. A sputtering method is used to form the Ti film and the Pd film. When the resistance in the rewiring becomes a problem, an Au film is formed on the Pd film, thereby realizing a rewiring structure having a Ti film, a Pd film and an Au film from the bottom layer.

[0005] The method disclosed in JP2017-228583A includes the steps of forming a first metal layer, forming a covering film, and forming a second metal layer. In the step of forming the covering film, a covering film formed of any one of Cu, Ti, Al, Mg, and Cr is formed in the peripheral region of the first metal layer. In the step of forming the second metal layer with the first metal layer as a seed metal, a metal different from the material constituting the covering film and selected from Ni, Pd, and Al is subjected to chemical plating. The second metal layer is located on the upper surface of the first metal layer and does not extend to the outside of the covering film. Summary of the invention

[0006] The present disclosure provides a method for manufacturing a semiconductor device. The method includes the following steps: forming a first organic insulating layer on a semiconductor region; forming a bump base film, the bump base film including an edge portion in contact with the first organic insulating layer; performing a heat treatment on the bump base film; and forming a second organic insulating layer, the second organic insulating layer covering the edge portion of the bump base film and the first organic insulating layer around the bump base film while being in contact with the first organic insulating layer, the second organic insulating layer being provided with a first opening exposing a surface of the bump base film.

[0007] The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor region, a first organic insulating layer, a bump base film, a second organic insulating layer and a solder bump. The first organic insulating layer is disposed on the semiconductor region. The bump base film includes an edge portion located on the first organic insulating layer. The second organic insulating layer is disposed to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film, while being in contact with the first organic insulating layer. The second organic insulating layer is provided with a first opening exposing the surface of the bump base film. The solder bump covers the first opening and is in contact with the bump base film. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan view illustrating a semiconductor device according to an embodiment.

[0009] Figure 2 It is shown along Figure 1 FIG. 1 is an enlarged view of a cross section of a basic structure of a solder bump taken along line II-II shown in FIG.

[0010] Figure 3A , Figure 3B and Figure 3C is shown for manufacturing Figure 1 1 is a cross-sectional view of each step in the method of the semiconductor device shown in FIG.

[0011] Figure 4A , Figure 4B and Figure 4C are cross-sectional views showing each step in a method for manufacturing a semiconductor device.

[0012] Figure 5A and Figure 5B are cross-sectional views showing each step in a method for manufacturing a semiconductor device.

[0013] Figure 6 are views for describing effects achieved by the semiconductor device and the method for manufacturing the semiconductor device according to the embodiment.

[0014] Figure 7 is a cross-sectional view illustrating steps according to a modification example.

[0015] Figure 8 is a cross-sectional view showing a state in which an organic insulating layer is formed in a modification.

[0016] Fig.9A and Fig. 9B It is a view for describing the effects achieved by the manufacturing method according to the modification example.

[0017] Fig. 10Ais an enlarged cross-sectional view showing a portion of the structure of a comparative example of the semiconductor device disclosed in JP2017-228583A. Fig. 10B It is shown Fig. 10A An enlarged cross-sectional view of a portion of the. DETAILED DESCRIPTION

[0018] [Problems to be solved by the present disclosure]

[0019] Ball grid array (BGA) package can be used to perform flip chip installation of semiconductor devices on substrates, etc. Solder bumps are formed on the wiring layer of such semiconductor devices (for example, refer to JP2005-150578A, JP2017-228583A). In order to suppress the mutual diffusion of metal materials between the solder layer and the wiring layer, a bump base film (UBM film) is provided between the wiring layer and the solder bumps. For example, an organic insulating layer such as a polyimide film is provided on the semiconductor region as an interlayer film of the wiring layer.

[0020] Due to the difference between the thermal expansion coefficient of organic insulating materials such as polyimide and the thermal expansion coefficient of metal materials, the bump base film may be easily peeled off from the organic insulating layer due to thermal stress generated when the solder ball is installed. When a gap is generated between the bump base film and the organic insulating layer, solder may penetrate into the gap. If the solder penetrates, cracks are likely to occur on the boundary surface between the bump base film and the wiring layer, so that the reliability of the semiconductor device is deteriorated.

[0021] [Effects of the present disclosure]

[0022] The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device in which reliability can be improved by reducing the penetration of solder into a gap between a bump base film and an organic insulating layer.

[0023] [Description of Embodiments of the Present Disclosure]

[0024] The method for manufacturing a semiconductor device and a specific example of the semiconductor device disclosed in the present invention will be described below with reference to the accompanying drawings. The present invention is not limited to these examples. The present invention is indicated by the claims, and the present invention is intended to include all changes within the meaning and scope equivalent to the claims. In the following description, the same reference numerals are applied to the same elements in the description of the drawings, and repeated descriptions will be omitted.

[0025] Figure 1 1 is a plan view showing a semiconductor device 1A according to an embodiment. Figure 1As shown in FIG. 1 , a semiconductor device 1A as a BGA semiconductor device includes a semiconductor region 10 and a plurality of solder bumps 17 provided on the surface of the semiconductor region 10. The plurality of solder bumps 17 are provided in a planar dispersed manner on the surface of the semiconductor region 10. For example, the solder bumps 17 are substantially spherical structures made of a metal such as an alloy of tin and silver (Sn—Ag).

[0026] For example, when the semiconductor device 1A is a high electron mobility transistor (HEMT) composed of a semiconductor based on gallium nitride (GaN), the semiconductor region 10 includes a GaN channel layer and an AlGaN barrier layer (or an InAlN barrier layer). The semiconductor region 10 may include a field effect transistor (FET) other than the HEMT or a semiconductor layer for a semiconductor functional device other than this.

[0027] A ground wiring region 11 and a signal wiring region 12 are provided on the surface of the semiconductor region 10. The ground wiring region 11 is provided substantially on the entire surface of the semiconductor region 10. In the example, the planar shape of the ground wiring region 11 is substantially similar to the planar shape of the semiconductor device 1A and is substantially rectangular. N (in the direction of the ground wiring region 11) is formed in a pair of side surfaces 11a and 11b facing each other. Figure 1 In the example shown in , there are five) semicircular cutouts 11c, and each of the signal wiring areas 12 is arranged on the inner side of each of the cutouts 11c. For example, the planar shape of each of the signal wiring areas 12 is a circular shape. The ground wiring area 11 and each of the signal wiring areas 12 are isolated from each other, and a semi-annular gap area 13 is arranged between the ground wiring area 11 and the signal wiring area 12. Figure 1 In the example shown in , two signal wiring areas 12 are arranged side by side along one side 11 a of the ground wiring area 11 , and three signal wiring areas 12 are arranged side by side along the other side 11 b of the ground wiring area 11 .

[0028] The plurality of solder bumps 17 include M (in Figure 1 In the example shown in FIG. 1 , there are 12 ground solder bumps 17a and N signal solder bumps 17b. The M ground solder bumps 17a are arranged in a two-dimensional shape along the row direction and the column direction orthogonal to each other in the ground wiring area 11. The N signal solder bumps 17b are respectively provided on the signal wiring area 12. Some of the N signal solder bumps 17b (in Figure 1 ) are arranged along the side surface 11a of the ground wiring area 11, and the other (two in the example shown in Figure 1The ground wiring area 11 is arranged along the side surface 11 b of the ground wiring area 11 .

[0029] Figure 2 It is shown along Figure 1 FIG. 1 is an enlarged view of a cross section of the basic structure of the solder bump 17 taken along the line II-II shown in FIG. Figure 2 As shown in FIG. 1 , the semiconductor device 1A includes a metal wiring 21 provided on the surface of the semiconductor region 10 and an organic insulating layer 31 provided on the surface of the semiconductor region 10. In addition, the semiconductor device 1A includes metal films 22 and 23, a bump base film 26, and an organic insulating layer 32. Figure 2 middle, Figure 1 Illustration of the semiconductor region 10 and the solder bumps 17 shown in FIG. 1 is omitted.

[0030] The metal wiring 21 is a signal wiring provided on an inorganic insulating layer (e.g., a SiN layer or a SiO2 layer) on the semiconductor region 10. The metal wiring 21 is connected to an electrode (e.g., a source electrode and a drain electrode) in ohmic contact with the semiconductor region 10 or an electrode (e.g., a gate electrode) in Schottky contact with the semiconductor region 10. For example, the metal wiring 21 is composed of a metal such as gold (Au). The thickness of each of the metal wirings 21 may be in the range of 0.5 μm to 3.0 μm, and is 1 μm in the example.

[0031] The organic insulating layer 31 is an interlayer film of a dielectric provided between wiring layers. In the example, the organic insulating layer 31 is mainly formed of a resin and is formed of polyimide. The organic insulating layer 31 is provided on the entire surface of the semiconductor region 10 and covers the inorganic insulating layer and the metal wiring 21. The organic insulating layer 31 has an opening 31a on the metal wiring 21 for exposing a portion of the metal wiring 21. When viewed in the thickness direction of the semiconductor region 10, the opening 31a overlaps with the signal solder bump 17b (refer to Figure 1 ). The thickness of the organic insulating layer 31 may be in the range of 1 μm to 6 μm.

[0032] The metal film 22 is used as a ground wiring. The metal film 23 is used as a signal wiring. For example, the metal films 22 and 23 are provided on the organic insulating layer 31 and are formed of a metal such as gold (Au). The metal film 22 is provided on Figure 1 , and the planar shape of the metal film 22 is consistent with the planar shape of the ground wiring region 11. Specifically, the metal film 22 is provided substantially on the entire surface of the semiconductor region 10. In the example, the planar shape of the metal film 22 is substantially similar to the planar shape of the semiconductor device 1A, and is substantially rectangular. In a pair of side surfaces of the metal film 22 facing each other in a certain direction, a planar shape corresponding to the planar shape of the ground wiring region 11 is formed. Figure 1The semicircular cutouts corresponding to the cutouts 11c shown in FIG. 1 and each of the metal films 23 is disposed on the inner side of each of the cutouts. Figure 1 , and the planar shape of each of the metal films 23 is consistent with the planar shape of each of the signal wiring areas 12. For example, the metal film 22 and the metal film 23 are separated from each other, and the distance d1 between the metal film 22 and the metal film 23 is in the range of 50μm to 300μm. The metal film 23 fills the opening 31a formed in the organic insulating layer 31, completely covers the opening 31a, and is connected to the metal wiring 21 through the opening 31a. The thickness of each of the metal films 22 and 23 can be in the range of 0.5μm to 5.0μm and is 2μm in the example.

[0033] The bump base film 26 is configured to include a portion 26a disposed on and covering the metal film 22 and a portion 26b disposed on and covering the metal film 23. In the present embodiment, the portion 26a covers the upper surface and the side surface of the metal film 22, and the edge portion 26c of the portion 26a is located on the organic insulating layer 31 around the metal film 22 and in contact with the organic insulating layer 31. Each of the portions 26b covers the upper surface and the side surface of each of the metal films 23, and the edge portion 26d of each of the portions 26b is located on the organic insulating layer 31 around the metal film 23 and in contact with the organic insulating layer 31. The portion 26a and the corresponding portion 26b are separated from each other, wherein the gap region 13 (refer to Figure 1 ) is sandwiched between portion 26a and a corresponding portion 26b.

[0034] The bump base film 26 is mainly composed of a seed metal film 24 and a main film 25 arranged on the seed metal film 24. For example, the seed metal film 24 mainly includes metals such as titanium (Ti) and palladium (Pd). In the example, the seed metal film 24 includes a Ti layer arranged on the metal films 22 and 23, respectively, and a Pd layer arranged on the Ti layer. In this case, the thickness of the Ti layer can be in the range of 5nm to 100nm, and is 5nm in the example. The thickness of the Pd layer can be in the range of 10nm to 500nm, and is 10nm in the example. When the main film 25 is formed by chemical plating, the seed metal film 24 is used as a seed metal. When the main film 25 includes Ni (or NiCr) and the metal wiring 21 includes Au, the seed metal film 24 prevents Ni (or NiCr) and Au from forming an alloy.

[0035] The main film 25 is a metal film disposed on the seed metal film 24 and in contact with the seed metal film 24. For example, the main film 25 mainly includes a metal such as nickel (Ni) or nickel-chromium alloy (NiCr). The main film 25 is provided to prevent mutual diffusion of solder constituting the solder bump 17 and gold (Au) constituting the metal wiring 21. When the main film 25 is a Ni layer, for example, the thickness of the Ni layer is in the range of 3μm to 6μm. An edge portion 25c of the main film 25 protrudes from the seed metal film 24. The edge portion 25c may be provided with a gap in the thickness direction relative to the organic insulating layer 31 or may be in contact with the organic insulating layer 31.

[0036] For example, the organic insulating layer 32 mainly includes a photosensitive resin. For example, the photosensitive resin is a photosensitive polyimide. In the example, the organic insulating layer 32 is formed of the same material as the organic insulating layer 31. The organic insulating layer 32 is provided at least from above the edge portions 26c and 26d of the bump base film 26 to above the organic insulating layer 31 around the bump base film 26, and is in contact with the organic insulating layer 31. In the present embodiment, the organic insulating layer 32 is provided on the entire surface of the semiconductor region 10, and covers the organic insulating layer 31 exposed from the bump base film 26. The organic insulating layer 32 has an opening 32a for exposing a portion 26a of the bump base film 26 and an opening 32b for exposing a portion 26b of the bump base film 26. When viewed in the thickness direction of the semiconductor region 10, the opening 32a overlaps with the ground solder bump 17a (refer to Figure 1 ), and the opening 32b overlaps the signal solder bump 17b (refer to Figure 1 ). The ground solder bump 17a covers the opening 32a and contacts the main film 25 of the portion 26a of the bump base film 26 through the opening 32a. The signal solder bump 17b covers the opening 32b and contacts the main film 25 of the portion 26b of the bump base film 26 through the opening 32b. For example, the thickness of the organic insulating layer 32 is in the range of 1.0 μm to 10.0 μm.

[0037] Subsequently, a method for manufacturing the above-mentioned semiconductor device 1A will be described. First, a semiconductor region 10 is epitaxially grown on a substrate. For example, this is grown by using a metal organic chemical vapor deposition (MOCVD) method. Next, electrodes (for example, a gate electrode, a source electrode, and a drain electrode) are formed on the semiconductor region 10. For example, the electrode is formed in the following manner, namely: a resist mask having an opening is formed on the semiconductor region 10, and a vapor deposition of a metal that becomes an electrode material is performed inside the opening of the resist mask and on the resist mask (that is, stripping is performed). Subsequently, an inorganic insulating layer (for example, a SiN layer) is formed on the semiconductor region 10. For example, the inorganic insulating layer can be formed by a plasma CVD method.

[0038] FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C and Figure 5A and Figure 5B 1A is a cross-sectional view showing each step after performing the step of forming an inorganic insulating layer in the method for manufacturing the semiconductor device 1A. Figure 3A As shown in , metal wirings 21 each having a predetermined planar pattern are formed on the inorganic insulating layer by an electroplating method. At this time, the metal wirings 21 and the electrodes are connected to each other via an opening formed in the inorganic insulating layer interposed therebetween.

[0039] Subsequently, an organic insulating layer 31 is formed on the surface of the semiconductor region 10 on which the metal wiring 21 is provided. For example, the organic insulating layer 31 is formed by performing spin coating of a material (e.g., polyimide) of the organic insulating layer 31 on the semiconductor region 10. In addition, the opening 31a exposing the metal wiring 21 is formed by forming a mask having an opening pattern corresponding to the opening 31a on the organic insulating layer 31 and etching the organic insulating layer 31 using this mask interposed between the organic insulating layers 31. For example, the material of the mask is SiN or SiO2. For example, the opening of the mask is formed using photolithography or electron beam lithography. The opening 31a can be formed by dry etching using plasma.

[0040] Then, if Figure 3B As shown in FIG. 1 , metal films 22 and 23 each having a predetermined planar pattern are formed on the organic insulating layer 31 by, for example, an electroplating method. Figure 1 The metal film 22 is formed in the ground wiring region 11 shown in FIG. 1 , and each of the metal films 23 is formed in each of the signal wiring regions 12. At this time, the metal film 23 is connected to the metal wiring 21 using the opening 31a of the organic insulating layer 31 interposed between the metal film 23 and the metal wiring 21.

[0041] Then, if Figure 3C As shown in , a seed metal film 24 is formed on the entire surface of the semiconductor region 10, and the upper surface and side surface of the metal film 22, the upper surface and side surface of each metal film 23, and the surface of the organic insulating layer 31 exposed from the metal films 22 and 23 are covered by the seed metal film 24. For example, the seed metal film 24 is formed by a sputtering method. In the example, a Ti layer with a thickness of 5nm is formed by a sputtering method. Thereafter, a Pd layer with a thickness of 10nm is formed on the Ti layer by a sputtering method. The seed metal film 24 formed in this manner includes a portion 24a covering the metal film 22, a portion 24b covering the metal film 23, and a portion 24c located on the organic insulating layer 31.

[0042] Then, if Figure 4AAs shown in , a photoresist R is formed on the seed metal film 24. The photoresist R has an opening Ra on the portion 24c, and only the portion 24c is exposed through the opening Ra. For example, the photoresist R is a negative resist. In this case, a negative resist is applied to the seed metal film 24, and other regions except the region corresponding to the opening Ra are subjected to exposure and development, so that only the region corresponding to the opening Ra that has not been subjected to exposure can be removed. The photoresist R covers the portions 24a and 24b of the seed metal film 24, and covers the portion of the portion 24c adjacent to the circumferential edge portion of each of the portions 24a and 24b. In addition, the portion 24c of the seed metal film 24 exposed from the opening Ra of the photoresist R is removed by etching. The etching is, for example, wet etching using an iodine etchant (a trade name "AURUM" series manufactured by Kanto Chemical Co., Ltd.) or dry etching such as reactive ion etching (RIE). Therefore, the portions 24a and 24b of the seed metal film 24 are separated from each other. An edge portion of the seed metal film 24 located on and in contact with the organic insulating layer 31 remains around the portions 24a and 24b. Thereafter, the photoresist R is removed.

[0043] Then, if Figure 4B As shown in , parts 26a and 26b of the bump base film 26 are formed by forming a main film 25 on a seed metal film 24. In this step, the main film 25 is formed by a chemical plating method for making the seed metal film 24 a seed metal. For example, the main film 25 is formed by a chemical plating process (for example, a self-catalytic chemical plating process) using hypophosphite for self-catalytic plating as a catalyst. The reason for using chemical plating is that it has better reliability than electroplating. Since the seed metal film 24 is arranged in parts 24a and 24b in a restrictive manner, this chemical plating becomes selective electroplating, so that the main film 25 grows in a restrictive manner on part 24a and part 24b. Since the main film 25 also grows in the lateral direction, an edge portion 25c protruding from the seed metal film 24 is formed in the main film 25.

[0044] Chemical plating is a method for performing electroplating without using an external power source, and there are displacement plating using an ionization tendency, autocatalytic chemical plating (reduction plating) using a reducing agent, displacement reduction plating combining these, etc. Here, autocatalytic chemical plating is used, but other types of chemical plating can be used. On the other hand, electroplating is a method for performing electroplating by applying electrons from a cathode by causing an electric current to flow between electrodes using an external power source.

[0045] Subsequently, an Au film is formed on the main film 25. For example, the Au film is formed using chemical plating, electroplating, vapor deposition lift-off, or sputtering. For example, the thickness of the Au film is 10 μm.

[0046] Then, if Figure 4C As shown in , the product including the bump base film 26 is installed inside the heat treatment furnace Q, and a step of heat treating the bump base film 26 is performed. For example, the heat treatment temperature is a temperature higher than the reflow temperature of the solder bump 17 formed in the subsequent structure, and the heat treatment temperature is in the range of 260°C to 350°C. The heat treatment time lasts for 5 minutes to 60 minutes and is 30 minutes in the example. For example, the atmosphere for heat treatment is an atmosphere (a mixed atmosphere of nitrogen (N2) and oxygen (O2)), a vacuum atmosphere, or an inert gas atmosphere of argon (Ar) or helium (He).

[0047] Then, if Figure 5A As shown in FIG. 1 , an organic insulating layer 32 is formed on the surface of the semiconductor region 10 on which the bump base film 26 is formed. As described above, the organic insulating layer 32 is provided at least from above the edge portions 26c and 26d of the bump base film 26 to above the organic insulating layer 31 around the bump base film 26 and in contact with the organic insulating layer 31. Similar to the organic insulating layer 31, for example, the organic insulating layer 32 is formed by performing spin coating of a material of the organic insulating layer 32 (for example, photosensitive polyimide) on the bump base film 26 and the organic insulating layer 31 exposed from the bump base film 26. In addition, the organic insulating layer 32 is subjected to exposure and development using a photomask having an opening pattern corresponding to the openings 32a and 32b, so that the openings 32a and 32b are formed and the surfaces of the portions 26a and 26b of the bump base film 26 are exposed.

[0048] Then, if Figure 5B As shown in , a solder bump 17 is formed. That is, a grounding solder bump 17a covering the opening 32a and in contact with the portion 26a of the bump base film 26 and a signal solder bump 17b covering the opening 32b and in contact with the portion 26b of the bump base film 26 are formed. In this step, after applying the flux, for example, a solder bump 17 having a size such as 160 μm in diameter is formed by reflow (i.e., heat treatment) at a temperature of 250°C. In this step, the Au film formed on the seed metal film 24 is diffused roughly inside the solder bump 17. Thereafter, the flux is cleaned. Through the above steps, a Figure 1 and Figure 2 The semiconductor device 1A of this embodiment is shown in FIG.

[0049] Effects achieved by the above-described method for manufacturing the semiconductor device 1A according to the present embodiment will be described together with problems of the manufacturing method in the related art. Fig. 10AJP2017-228583A is an enlarged cross-sectional view showing a portion of the structure of a comparative example of a semiconductor device disclosed in JP2017-228583A. A metal wiring 120 composed of, for example, Au is provided on a semiconductor region 110 mainly including a nitride semiconductor, and the metal wiring 120 is covered by an inorganic insulating layer 141 that protects the semiconductor region 110. For example, the inorganic insulating layer 141 is a silicon compound film such as SiN. An organic insulating layer 133 formed of, for example, a resin such as polyimide is provided on the inorganic insulating layer 141. Openings 141a and 133a that penetrate the inorganic insulating layer 141 and the organic insulating layer 133 in the thickness direction are formed in the inorganic insulating layer 141 and the organic insulating layer 133, and these openings 141a and 133a are filled with, for example, metal wiring 121 composed of Au. The metal wiring 121 is connected to the metal wiring 120 through the openings 141a and 133a. The inorganic insulating layer 142 and the organic insulating layer 131 are laminated on the organic insulating layer 133. For example, the inorganic insulating layer 142 is a silicon compound film composed of SiN or the like. The organic insulating layer 131 is formed of a resin such as polyimide. The openings 142a and 131a of the inorganic insulating layer 142 and the organic insulating layer 131 are formed on the metal wiring 121, and the seed metal film 124 is provided on the side surface of each of the openings 142a and 131a and on the surface of the metal wiring 121 exposed from the openings 142a and 131a. For example, the seed metal film 124 is composed of Ti and Pd. A main film 125 is provided on the seed metal film 124, in which the seed metal film 124 is electroplated to form a seed metal. The seed metal film 124 and the main film 125 constitute a bump base film 126. The circumferential edge portion of the bump base film 126 contacts the surface of the organic insulating layer 131. Solder bumps are formed on the bump base film 126 .

[0050] When the solder bump is formed by reflow in the above structure, or when the above semiconductor device after the solder bump is formed is mounted on a wiring substrate by reflow, there is a case where the peripheral edge portion of the bump base film 126 is peeled off from the organic insulating layer 131 due to the difference between the thermal expansion coefficient of the organic insulating material such as polyimide and the thermal expansion coefficient of the metal material, such as Fig. 10B When the gap G is generated between the bump base film 126 and the organic insulating layer 131 , solder may penetrate into the gap G, and such solder may break the boundary surface between the bump base film 126 and the metal wiring 121 .

[0051] Regarding this matter, the method for manufacturing the semiconductor device 1A of the present embodiment includes the steps of: forming an organic insulating layer 31 on the semiconductor region 10; forming a bump base film 26; performing heat treatment on the bump base film 26; and forming an organic insulating layer 32. In the step of forming the bump base film 26, the bump base film 26 including the edge portions 26c and 26d located on the organic insulating layer 31 is formed. In the step of forming the organic insulating layer 32, the organic insulating layer 32 is formed, which is provided from at least above the edge portions 26c and 26d of the bump base film 26 to above the organic insulating layer 31 around the bump base film 26 and is in contact with the organic insulating layer 31, and has openings 32a and 32b for exposing the surface of the bump base film 26.

[0052] The semiconductor device 1A of the present embodiment includes a semiconductor region 10, an organic insulating layer 31 provided on the semiconductor region 10, a bump base film 26 including edge portions 26c and 26d located on the organic insulating layer 31, an organic insulating layer 32, and a solder bump 17 in contact with the bump base film 26. The organic insulating layer 32 is provided at least from above the edge portions 26c and 26d of the bump base film 26 to above the organic insulating layer 31 around the bump base film 26 and in contact with the organic insulating layer 31. The organic insulating layer 32 has openings 32a and 32b for exposing the surface of the bump base film 26. The ground solder bump 17a covers the opening 32a and is in contact with the bump base film 26, and the signal solder bump 17b covers the opening 32b and is in contact with the bump base film 26.

[0053] Figure 6 1A is a view for describing the effects achieved by the semiconductor device 1A according to the present embodiment and the method for manufacturing the semiconductor device. In the present embodiment, after the step of forming the bump base film 26 is performed, the step of heat treating the bump base film 26 is performed. At this time, due to the stress caused by the difference between the thermal expansion coefficients, the bump base film 26 is peeled off from the organic insulating layer 31 in the portion where the bonding strength between the bump base film 26 and the organic insulating layer 31 is low ( Figure 6 When the bump base film 26 and the exposed organic insulating layer 31 are covered with the organic insulating layer 32 in a subsequent step, the material of the organic insulating layer 32 enters the gap between the bump base film 26 and the organic insulating layer 31.

[0054] In this way, the present embodiment peels off the portion where the bonding strength between the bump base film 26 and the organic insulating layer 31 is low in advance before the reflow of the solder bump 17. The gap generated as a result is filled with the material of the organic insulating layer 32 in advance. Therefore, the internal stress of the bump base film 26 is released, and the generation of the gap between the bump base film 26 and the organic insulating layer 31 due to the heat during the reflow of the solder bump 17 can be reduced. Therefore, the penetration of solder into the gap between the bump base film 26 and the organic insulating layer 31 is reduced, so that the reliability of the semiconductor device 1A can be improved.

[0055] In the present embodiment, the organic insulating layer 32 may mainly include a photosensitive resin, and the step of forming the organic insulating layer 32 may include a step of forming the openings 32a and 32b by performing exposure and development on the organic insulating layer. With respect to the organic insulating layer 32, the openings 32a and 32b are generally formed by etching. However, when a photosensitive resin is used, the openings 32a and 32b are formed in the steps of exposure and development, so that the etching step can be omitted.

[0056] In the present embodiment, the method for manufacturing the semiconductor device 1A may include the following steps: forming the solder bump 17 by a reflow process to cover the openings 32a and 32b and to contact the bump base film 26. As described above, according to the manufacturing method of the present embodiment, it is possible to reduce the generation of a gap between the bump base film 26 and the organic insulating layer 31 due to heat during the reflow process of the solder bump 17. Therefore, it is possible to improve the reliability of the semiconductor device 1A when the solder bump 17 is formed by the reflow process.

[0057] In the present embodiment, in the step of heat treating the bump base film 26, the heat treatment can be performed at a temperature higher than the reflow temperature of the solder bump 17. Therefore, the bump base film 26 and the organic insulating layer 31 where peeling may occur at the reflow temperature of the solder bump 17 can be peeled off in a reliable manner before reflow. Therefore, the reliability of the semiconductor device 1A can be further improved.

[0058] In the present embodiment, the entire metal films 22 and 23 may be covered by the bump base film 26. Therefore, the area of ​​the bump base film 26 increases, and the contact between the solder and the metal films 22 and 23 can be further reduced.

[0059] (Revision)

[0060] Figure 7 is a cross-sectional view showing steps according to a modification example of the above-described embodiment. Figure 4C After the step of heat treating the bump base film 26 as shown in FIG. Figure 5AThis step is performed before the step of forming the organic insulating layer 32 shown in FIG. In this step, a portion of the organic insulating layer 31 exposed from the bump base film 26 is etched ( Figure 7 The organic insulating layer 31 is formed by etching the organic insulating layer 31 in the portion (arrow E in FIG. 1 ) to form a recessed portion 31 b recessed from the surface of the organic insulating layer 31. For example, the etching is reactive ion etching (RIE) using O2 plasma. The depth of the recessed portion 31 b from the surface of the organic insulating layer 31 may be less than half the thickness of the organic insulating layer 31. For example, when the thickness of the organic insulating layer 31 is 2 μm, the depth of the recessed portion 31 b is less than 1 μm. Figure 8 2 is a cross-sectional view illustrating a state where the organic insulating layer 32 is formed after the above-mentioned steps. Figure 8 As shown in FIG. 1 , the organic insulating layer 32 fills the recess 31 b .

[0061] When the step of heat-treating the bump base film 26 is performed and a minute gap is generated between the bump base film 26 and the organic insulating layer 31, depending on the size of the gap, there is a concern that the constituent material of the organic insulating layer 32 does not enter the gap due to the viscosity of the constituent material. In this case, if the organic insulating layer 31 is etched as in the present modification, it is possible to Fig.9A As shown in part B of FIG. 2 , the gap between the bump base film 26 and the organic insulating layer 31 is enlarged. Fig. 9B As shown in part C of , when the organic insulating layer 32 is formed, the constituent material of the organic insulating layer 32 easily enters the gap. Therefore, the gap can be easily filled with the constituent material of the organic insulating layer 32, so that the infiltration of solder into the gap can be more effectively reduced, and the reliability of the semiconductor device 1A can be further improved.

[0062] The method for manufacturing a semiconductor device and the semiconductor device disclosed in the present invention are not limited to the above-mentioned embodiments, and various other modifications can be performed. For example, in the above-mentioned embodiments, HEMT has been described as an example of a semiconductor region. However, the present disclosure is not limited to HEMT, and can be applied to various semiconductor devices including metal wiring and solder bumps.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first organic insulating layer on the semiconductor region; forming a bump base film, the bump base film including an edge portion in contact with the first organic insulating layer; thermally treating the bump base film; as well as After performing the heat treatment on the bump base film, forming a second organic insulating layer, the second organic insulating layer covers the edge portion of the bump base film and the first organic insulating layer around the bump base film and is in contact with the first organic insulating layer, and the second organic insulating layer is provided with a first opening exposing the surface of the bump base film; as well as A solder bump is formed by a reflow process to cover the first opening and to contact the bump base film.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising the following steps: After performing the step of heat-treating the bump base film and before performing the step of forming the second organic insulating layer, the first organic insulating layer is etched.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The first organic insulating layer is etched to form a recessed portion recessed from a surface of the first organic insulating layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: A depth of the recess from the surface of the first organic insulating layer is less than or equal to half of a thickness of the first organic insulating layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the second organic insulating layer includes forming the first opening by exposing and developing the second organic insulating layer mainly including a photosensitive resin.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of heat-treating the bump base film is performed at a temperature higher than a temperature of a reflow process of the solder bump.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of heat-treating the bump base film is performed at a temperature ranging from 260°C to 350°C.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of heat treating the bump base film lasts for 5 minutes to 60 minutes.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of heat treating the bump base film is performed in air, vacuum atmosphere, or inert gas atmosphere.

10. The method for manufacturing a semiconductor device according to claim 1, further comprising the following steps: forming a metal wiring serving as a signal wiring on the semiconductor region, Here, in the step of forming the first organic insulating layer, the first organic insulating layer is formed to have a second opening exposing a surface of the metal wiring.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising the following steps: forming a first metal film serving as a ground wiring in a ground wiring region on the first organic insulating layer; as well as In a signal wiring region isolated from the ground wiring region, a second metal film serving as the signal wiring is formed so as to be connected to the metal wiring through the second opening.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: In the step of forming the bump base film, a first portion of the bump base film covering the first metal film and a second portion of the bump base film covering the second metal film are formed separately.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: In the step of forming a bump base film, the first metal film and the second metal film are entirely covered by the bump base film.

14. A semiconductor device, comprising: Semiconductor region; a first organic insulating layer, the first organic insulating layer being disposed on the semiconductor region; a bump base film, the bump base film including an edge portion located on the first organic insulating layer; a second organic insulating layer, the second organic insulating layer being arranged to cover an edge portion of the bump base film and the first organic insulating layer around the bump base film and being in contact with the first organic insulating layer, the second organic insulating layer being provided with a first opening exposing a surface of the bump base film; as well as a solder bump covering the first opening and contacting the bump base film, The material constituting the second organic insulating layer enters into the gap between the first organic insulating layer and the bump base film.

15. The semiconductor device according to claim 14, further comprising: A metal wiring serving as a signal wiring is provided on the semiconductor region, wherein the first organic insulating layer has a second opening from which the metal wiring is exposed.

16. The semiconductor device according to claim 15, further comprising: a first metal film serving as a ground wiring, the first metal film being provided in a ground wiring region on the first organic insulating layer; and A second metal film serving as a signal wiring is provided in a signal wiring region isolated from the ground wiring region and is connected to the metal wiring through the second opening.

17. The semiconductor device according to claim 16, wherein: The bump base film includes a first portion covering the first metal film and a second portion separated from the first portion and covering the second metal film.

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