Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a first substrate, a second substrate, an electrical contact, and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contact is disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The support element includes a thermoset material.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package comprising two substrates to define a cavity and a method of manufacturing the same. Background Technology

[0002] The development of mobile communications has created a demand for high data rates and stable communication quality, making high-frequency wireless transmission (such as 28 GHz or 60 GHz) a top priority in the mobile communications industry. To achieve this high-frequency wireless transmission, signals can be transmitted in frequency bands with wavelengths ranging from approximately ten millimeters to approximately one millimeter ("millimeter wave"). However, signal attenuation is a problem in millimeter wave transmission. Summary of the Invention

[0003] In one or more embodiments, according to one aspect, a semiconductor device package includes a first substrate, second substrate electrical contacts, and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contacts are disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The support element comprises a thermosetting material.

[0004] In one or more embodiments, according to another aspect, a semiconductor device package includes a first substrate, a second substrate, electrical contacts, and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contacts are disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The curing temperature of the support element is higher than the melting point of the electrical contacts.

[0005] In one or more embodiments, according to another aspect, a method of manufacturing a semiconductor device package includes (a) providing a first substrate having a first surface; (b) disposing one or more support elements on the first surface of the first substrate; (c) disposing a second substrate on the support elements, the second substrate having one or more electrical contacts on the first surface of the second substrate facing the first substrate; (d) providing a first temperature to melt the electrical contacts; and (e) providing a second temperature to solidify the support elements. The second temperature is higher than the first temperature. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that various features may not be drawn to scale, and the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1AA cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 1B Description of some embodiments according to this disclosure Figure 1A The image shows a top view of the substrate.

[0009] Figure 1C Description of some embodiments according to this disclosure Figure 1A The image shows a top view of the substrate.

[0010] Figure 1D Description of some embodiments according to this disclosure Figure 1A The image shows a top view of the substrate.

[0011] Figure 1E Description of some embodiments according to this disclosure Figure 1A The image shows a top view of the substrate.

[0012] Figure 1F Description of some embodiments according to this disclosure Figure 1A An enlarged view of a portion of the support element shown in the image.

[0013] Figure 2A , Figure 2B and Figure 2C This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0014] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0015] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0016] Figure 1A The illustration shows a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, a substrate 11, one or more electrical contacts 12, one or more support elements 13, an antenna pattern 14, an antenna pattern 15, and an electronic component 16.

[0017] The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber copper foil laminate. The substrate 10 may include interconnect structures 10r, such as a redistribution layer (RDL) or a grounding element. In some embodiments, the substrate 10 may be a single-layer or multi-layer substrate, comprising a core layer and conductive material and / or structures disposed on a surface 101 (also referred to as the top surface or first surface) and a surface 102 (also referred to as the bottom surface or second surface) of the substrate 10. The conductive material and / or structure may comprise multiple traces. The substrate 10 may include one or more conductive pads 10c adjacent to, adjacent to, or embedded in the surface of the substrate and exposed at the surface of the substrate. The substrate 10 may include solder resist 10r (or solder mask) on the surface 101 of the substrate 10 to fully expose or expose at least a portion of the conductive pads 10c for electrical connection. For example, solder resist 10r may cover a portion of conductive pad 10c.

[0018] Antenna pattern 14 is disposed on surface 101 of substrate 10. In some embodiments, antenna pattern 14 includes a plurality of antenna elements. For example, antenna pattern 14 may include an array of antenna elements. In some embodiments, antenna pattern 14 may include an M×N array of antenna elements, where M and N are integers greater than 0.

[0019] Electronic component 16 is disposed on surface 102 of substrate 10. In some embodiments, electronic component 16 is electrically connected to antenna pattern 14 via interconnect structure 10r within substrate 10. Electronic component 16 may be a chip or die containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. Integrated circuit devices may include active devices such as transistors and / or inactive devices such as resistors, capacitors, inductors, or combinations thereof. Electronic component 16 may be electrically connected to substrate 10 (e.g., electrically connected to conductive pads), and the electrical connection may be achieved by means of flip-chip or wire bonding techniques.

[0020] Substrate 11 is disposed on and spaced apart from substrate 10. In some embodiments, substrate 11 may be the same as or different from substrate 10 depending on design specifications. Substrate 11 has a surface 111 and a surface 112 opposite to surface 111. Surface 112 of substrate 11 faces surface 101 of substrate 10. In some embodiments, surface 111 of substrate 11 is referred to as the top surface or second surface, and surface 112 of substrate 11 is referred to as the bottom surface or first surface. In some embodiments, surface 101 of substrate 10 is parallel to surface 112 of substrate 11. Substrate 11 may include one or more conductive pads 11c adjacent to, adjacent to, or embedded in, and exposed on the surface of substrate 11. Substrate 11 may include solder resist 11r (or solder mask) on surface 112 of substrate 11 to expose at least a portion of the conductive pads 11c for power connection.

[0021] Antenna pattern 15 is disposed on surface 112 of substrate 11. Antenna pattern 15 is disposed on surface 112 of substrate 11 corresponding to antenna pattern 14 disposed on surface 101 of substrate 10 (e.g., disposed above said antenna pattern). For example, antenna pattern 15 faces antenna pattern 14. For example, antenna pattern 15 may be aligned with antenna pattern 14. In some embodiments, antenna pattern 15 includes a plurality of antenna elements. For example, antenna pattern 15 may include an array of antenna elements. In some embodiments, antenna pattern 15 may include an M×N array of antenna elements, where M and N are integers greater than 0. In some embodiments, the antenna pattern may also be disposed on surface 111 of substrate depending on design specifications.

[0022] Electrical contact 12 is disposed between substrate 10 and substrate 11. Electrical contact 12 is disposed between surface 101 of substrate 10 and surface 112 of substrate 11. Electrical contact 12 is disposed on conductive pad 10c of substrate 10 and conductive pad 11c of substrate 11. Electrical contact 12 is in contact with conductive pad 10c of substrate 10 and conductive pad 11c of substrate 11. In some embodiments, the melting point of the electrical contact is in the range of about 217°C to about 225°C. In some embodiments, electrical contact 12 may be or comprise solder balls.

[0023] A support element 13 is disposed between substrates 10. The support element 13 is disposed between surface 101 of substrate 10 and surface 112 of substrate 11. The support element 13 is disposed on the solder resist 10r of substrate 10 and the solder resist 11r of substrate 11. The support element 13 is in contact with the solder resist 10r of substrate 10 and the solder resist 11r of substrate 11. The support element 13 is adhered to substrates 10 and 11. In some embodiments, the support element 13 has relatively strong adhesion or is bonded to the solder resist 10r and 11r of substrates 10 and 11 to prevent substrate 11 from peeling or detaching from substrate 10 in subsequent processes.

[0024] In some embodiments, the curing temperature of the support element 13 is higher than the melting point of the electrical contact 12. In some embodiments, the curing temperature of the support element 13 is about 225°C or higher. In some embodiments, the glass transition temperature (Tg) is about 115°C. In some embodiments, the support element 13 may comprise a thermosetting material, such as epoxy resin. In some embodiments, the support element 13 may comprise a Class B adhesive or cured Class B adhesive. In some embodiments, the support element 13 may comprise a material that is Class A at room temperature or below its Tg (e.g., 115°C), then becomes Class B at temperatures ranging from its Tg (e.g., 115°C) to its curing temperature (e.g., 225°C), and becomes Class C at temperatures above its curing temperature (225°C). In some embodiments, the time required for the manufacturing process to heat the support element 13 from its glass transition temperature to its curing temperature is about 200 seconds. In some embodiments, the viscosity of the support element is about 360 Pa·s.

[0025] like Figure 1A As shown, since the electrical contact 12 and the support element 13 are disposed between the substrates 10 and 11 to define the height, distance, and one or more cavities (e.g., air cavities) between them, the gain, bandwidth, and radiation efficiency of the antenna patterns 14 and 15 can be improved by promoting resonance between the antenna patterns 14 and 15. To achieve the desired level of resonance, the height H11 of the air cavity (e.g., the distance between the antenna patterns 14 and 15) and the tolerance of the height H11 can be controlled within a certain range. For example, the height H11 of the air cavity can be between about 230 micrometers (μm) and about 280 μm with a tolerance of less than ±28 μm. In some embodiments, the height H11 of the air cavity is determined based on the design (e.g., bandwidth or performance) of the antenna patterns 14 and 15.

[0026] In some embodiments, the electrical contact 12 or support element 13 may not horizontally overlap with the antenna pattern 14 or 15, which avoids interference with electromagnetic wave transmission between the antenna patterns 14 and 15. For example, the electrical contact 12 or support element 13 may have a horizontal displacement relative to the antenna pattern 14 or 15. For example, the electrical contact 12 or support element 13 may be horizontally spaced from the antenna pattern 14 or 15. For example, the projection of the electrical contact 12 or support element 13 onto the surface 101 of the substrate 10 may not overlap with the projection of the antenna pattern 14 or 15 onto the surface 101 of the substrate 10.

[0027] In some comparative embodiments, the support element 13 may be omitted, and only electrical contacts (e.g., solder balls) are used to support the substrate 11. However, the size (e.g., height) of the solder balls can be reduced after each reflow process. Therefore, it may be difficult to control the size of each solder ball after the reflow process, and difficult to control the uniformity of all solder balls (which may be desirable). Therefore, large tolerances may exist for the solder balls. For example, solder ball heights corresponding to the stated heights may be required, and the problems described above can cause variations larger than the desired range (e.g., ± about 50 μm or more), which can reduce the resonant efficiency of the antenna pattern. Therefore, solder balls can be applied to stacked structures where height accuracy is relatively low.

[0028] In some comparative embodiments, the support element 13 can be implemented using a solid spacer. For example, the spacer is disposed between substrates 10 and 11. However, the spacer will remain in a solid state during the manufacturing process, and therefore the shape or height of the spacer is substantially fixed. Therefore, it is difficult to control the amount of solder balls and the height, distance, or cavity between substrates 10 and 11 during the manufacturing process, which can hinder the connection or adhesion between substrates 10 and 11.

[0029] According to some embodiments of this disclosure, the support element 13 is implemented using a thermosetting material. During the manufacturing process of the semiconductor device package 1, the process temperature is gradually increased, and when the temperature reaches its melting point (e.g., about 217°C to about 225°C), the electrical contact 12 begins to melt, and then the support element 13 solidifies as the temperature continues to rise until its curing temperature (e.g., about 225°C) is reached. During the melting process of the electrical contact 12, the molten electrical contact can be firmly bonded to the conductive pads 10c and 11c of the substrates 10 and 11 and bring the substrates 10 and 11 closer together, thereby providing self-alignment functionality for the conductive pads 10c and 11c of the substrates 10 and 11. In addition, when the process temperature reaches the curing temperature of the support element 13, the support element 13 solidifies or becomes solidified, and remains in a solidified or solidified state even if the process temperature is reduced in subsequent manufacturing steps. This allows the air cavity defined by the electrical contact 12 and the support element 13 to have a relatively stable and precisely controlled height compared to an air cavity defined only by solder balls. Furthermore, the height and shape of the support element 13 can be adjusted before the curing temperature of the support element 13 is reached, which allows for flexible and precise control of the height of the air cavity defined by the electrical contact 12 and the support element 13 to the desired value.

[0030] Figure 1B Description of some embodiments according to this disclosure Figure 1A A top view of the substrate 10 of the semiconductor device package 1. (See figure) Figure 1B As shown, the support element 13 is arranged adjacent to the edge of the substrate 10. The support elements 13 are spaced apart from each other. For example, there is a gap between each of two adjacent support elements 13. In some embodiments, the support element 13 is separated from the electrical contact 12.

[0031] Figure 1C Description of some embodiments according to this disclosure Figure 1A A top view of the substrate 10 of the semiconductor device package 1. (Except in...) Figure 1C In this configuration, the support element 13 is further arranged adjacent to the center of the substrate 10 (which provides better or more stable support capability). Figure 1C The arrangement of the support element 13 and the electrical contact 12 in the middle Figure 1B Similarly. In some embodiments, the support element 13 is arranged adjacent to the edge of the substrate 10, and the center of the substrate 10 is formed of the same material. Alternatively, the support element 13 is arranged adjacent to the edge of the substrate 10, and the center of the substrate 10 is formed of a different material, which prevents bending problems.

[0032] Figure 1D Description of some embodiments according to this disclosure Figure 1A A top view of the substrate 10 of the semiconductor device package 1. (Except in...) Figure 1DIn addition, the support element 13 is arranged to form a wall structure around the edge of the substrate 10 (which prevents bending problems), Figure 1D The arrangement of the support element 13 and the electrical contact 12 in the middle Figure 1B similar.

[0033] Figure 1E Description of some embodiments according to this disclosure Figure 1A A top view of the substrate 10 of the semiconductor device package 1. (Except in...) Figure 1E In addition, the support element 13 is arranged to form a wall structure around the edge of the substrate 10 (which can provide better or more stable support capabilities), Figure 1E The arrangement of the support element 13 and the electrical contact 12 in the middle Figure 1C similar.

[0034] Figure 1F Description of some embodiments according to this disclosure Figure 1A An enlarged view of a portion of the semiconductor device package 1 enclosed by the dotted rectangle A. (See image.) Figure 1F As shown, the support element 13 has a concave sidewall 13a. For example, the sidewall 13a of the support element 13 is recessed inward. For example, the support element 13 has a neck-shaped sidewall. For example, the thickness of the support element 13 in contact with the solder resist 10r or 11r is greater than the thickness of the middle portion of the support element 13.

[0035] Figure 2A , Figure 2B and Figure 2C These are cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure. The figures have been simplified to provide a better understanding of various aspects of the present disclosure. In some embodiments, Figure 2A , Figure 2B and Figure 2C The method described herein is used to form Figure 1A The substrate 11 and electrical contact 12 are in the middle.

[0036] refer to Figure 2A A substrate comprising a substrate 11 is provided. The substrate 11 is provided having conductive pads 11c, solder resist 11r, and antenna pattern 15. Electrical contacts 12 (e.g., solder balls) are disposed or mounted on the conductive pads 11c of the substrate 11.

[0037] refer to Figure 2B Monomerization process to separate such Figure 2C The individual substrates shown herein. That is, monomerization is performed on the substrate strip containing substrate 11. Monomerization can be performed, for example, by using a dicing machine, laser or other suitable cutting techniques.

[0038] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F These are cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure. The figures have been simplified to provide a better understanding of various aspects of the present disclosure. In some embodiments, Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F The method described herein is used to form Figure 1A Semiconductor device packaging 1.

[0039] refer to Figure 3A A substrate comprising a substrate 10 is provided. The substrate 10 is provided having conductive pads 10c, solder resist 10r, and an antenna pattern 14. Electronic components 16 and solder balls are disposed or mounted on the surface 102 of the substrate 10. Subsequently... Figure 3A The structure in Figure 3B The image shown is flipped.

[0040] refer to Figure 3C Thermosetting material 13' (Class A or Class B adhesive) is applied to the solder resist 10c of substrate 10. In some embodiments, thermosetting material 13' is in gel or glue form at room temperature or below its Tg (e.g., 115°C). For example, thermosetting material 13' is Class A. Figure 2C The structure is disposed on the surface 101 of the substrate 10. For example, the electrical contact 12 is disposed or placed on the conductive pad 10c of the substrate 10.

[0041] refer to Figure 3D ,right Figure 3C The structure within is subjected to thermal processing. For example, heating... Figure 3CThe structure is as follows. In some embodiments, when the process temperature reaches the melting point of the electrical contact 12 (e.g., 217°C), the electrical contact 12 begins to melt to firmly bond to the conductive pads 10c and 11c of the substrates 10 and 11 and bring the substrates 10 and 11 closer together, thereby providing self-alignment functionality for the conductive pads 10c and 11c of the substrates 10 and 11. When the process temperature is maintained at an increased level to reach the curing temperature of the thermosetting material 13' (e.g., about 225°C), the thermosetting material 13' is cured or solidified to form the support element 13. For example, the thermosetting material 13' is in grade C. Even when the process temperature decreases in subsequent manufacturing steps, the support element 13 remains in a cured or solidified state, thereby allowing the air cavity defined by the electrical contact 12 and the support element 13 to have a relatively stable height. Furthermore, the height or shape of the support element 13 can be adjusted before the curing temperature of the support element 13 is reached, which allows for flexible and precise control of the height of the air cavity defined by the electrical contact 12 and the support element 13 to a desired value. In some embodiments, the time required for the manufacturing process to heat the support element 13 from its glass transition temperature (e.g., 115°C) to its curing temperature is approximately 200 seconds.

[0042] refer to Figure 3E Monomerization can be performed to separate items such as Figure 3F The individual semiconductor packaging equipment shown herein. That is, monomerization is performed on a substrate strip containing substrate 10. Monomerization can be performed, for example, by using a dicing machine, laser or other suitable cutting techniques.

[0043] As used herein, the terms “approximately,” “generally,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or where it occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values ​​can be considered “generally” the same. For example, "generally parallel" can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "generally perpendicular" can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0044] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0045] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to transfer electric current. Conductive materials typically indicate those that exhibit minimal or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material may vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0046] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, a component disposed “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0047] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist and are not precisely described. This specification and drawings are to be considered illustrative rather than restrictive. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: A first substrate having a first pad, a first solder resist, and a first antenna pattern; The second substrate has a second pad, a second solder resist and a second antenna pattern; An electrical contact element that is connected to the first gasket and the second gasket; and A support element configured to align and connect the first solder resist and the second solder resist, and to define the distance between the first substrate and the second substrate, to adjust the resonance of the first antenna pattern and the second antenna pattern, wherein the support element comprises a thermosetting material, and the support element has three stages of change between the glass transition temperature and the curing temperature; the support element is in a gel form in stage A; the support element is in an adjustable form in stage B; and the support element is in a solid form in stage C; the solid form of the support element is a persistent solid form. The electrical contact is configured to align the first antenna pattern with the second antenna pattern, and the support element remains solidified while the electrical contact melts.

2. The semiconductor device package of claim 1, wherein the support element comprises a cured Class B adhesive, wherein the electrical contacts begin to melt in the Class B state, and the support element transitions to a cured state as it moves from the Class B state to the Class C state and the electrical contacts continue to melt, wherein the first solder resist and the first antenna pattern are on the bottom surface of the first substrate, and the top surface of the support element is connected to the first substrate via the first solder resist.

3. The semiconductor device package of claim 1, wherein the curing temperature of the support element is higher than the melting point of the electrical contact, and wherein the second solder resist and the second antenna pattern are on the top surface of the second substrate, and the support element is separated from the electrical contact, wherein, in a top view, the volume of the support element is larger than the volume of the electrical contact.

4. The semiconductor device package according to claim 1, wherein The support element is situated entirely between the first substrate and the second substrate, and From the top view, the support element is sandwiched between two electrical contacts on the left and right.

5. The semiconductor device package of claim 1, wherein the support element is in contact with the first solder resist of the first substrate and the second solder resist of the second substrate, the support element being situated entirely between the first solder resist and the second solder resist, and the maximum width of the support element being less than the width of the first solder resist.

6. The semiconductor device package according to claim 1, wherein: The first antenna pattern or the second antenna pattern has a horizontal displacement relative to either the electrical contact or the support element; The first substrate, the second substrate, the electrical contact, and the support element define an air cavity. The electrical contacts are configured to provide self-alignment for the first and second gaskets when they melt upon reaching their melting point, which is in the range of 217°C to 225°C. Within the range of the melting point, the support element remains in a solidified state, such that the distance between the first substrate and the second substrate is the stable height of the air cavity.

7. The semiconductor device package of claim 1, further comprising a plurality of support elements and a plurality of electrical contacts, wherein the support elements are disposed along the edge of a first surface of the first substrate, and, in a top view, a single row of an Nx1 array comprising the plurality of support elements and the plurality of electrical contacts is adjacent to each other and does not extend beyond the first edge of the first substrate.

8. The semiconductor device package of claim 7, wherein at least four of the plurality of support elements are arranged symmetrically adjacent to the center of the first surface of the first substrate.

9. The semiconductor device package of claim 1, wherein the support element has a concave sidewall.

10. The semiconductor device package of claim 1, wherein the support element is adhered to the first substrate and the second substrate via the first solder resist and the second solder resist.

11. A semiconductor device package comprising: A first substrate having a first pad, a first solder resist, and a first antenna pattern; The second substrate has a second pad, a second solder resist and a second antenna pattern; An electrical contact element that is connected to the first gasket and the second gasket; and A support element configured to align and connect the first and second solder resists and define the distance between the first and second substrates to adjust the resonance of the first and second antenna patterns. The support element has a curing temperature higher than the melting point of the electrical contact. The support element has three states between the glass transition temperature and the curing temperature: in state A, it is in a gel form; in state B, it is in an adjustable form; and in state C, it is in a solid form. The solid form of the support element is a persistent solid form. The electrical contact is configured to align the first antenna pattern with the second antenna pattern, and the support element remains solidified while the electrical contact melts.

12. The semiconductor device package of claim 11, wherein the support element comprises a cured Class B adhesive, wherein the first solder resist and the first antenna pattern are on the bottom surface of the first substrate, and the top surface of the support element is connected to the first substrate via the first solder resist.

13. The semiconductor device package of claim 11, wherein the support element comprises epoxy resin, and wherein the second solder resist and the second antenna pattern are on the top surface of the second substrate, and the support element is separated from the electrical contact.

14. The semiconductor device package of claim 11, wherein... The support element is situated between the first substrate and the second substrate.

15. The semiconductor device package of claim 11, wherein the support element is in contact with the first solder resist of the first substrate and the second solder resist of the second substrate, the support element being integrally located between the first solder resist and the second solder resist, and the maximum width of the support element being less than the width of the first solder resist.

16. The semiconductor device package of claim 11, wherein: The first antenna pattern or the second antenna pattern has a horizontal displacement relative to either the electrical contact or the support element; The first substrate, the second substrate, the electrical contact, and the support element define an air cavity. The electrical contacts are configured to provide self-alignment for the first and second gaskets when they melt upon reaching their melting point, which is in the range of 217°C to 225°C. Within the range of the melting point, the support element remains in a solidified state, such that the distance between the first substrate and the second substrate is the stable height of the air cavity.

17. The semiconductor device package of claim 11, further comprising a plurality of support elements and a plurality of electrical contacts, wherein the support elements are disposed along the edge of a first surface of the first substrate, and, in a top view, a single row of an Nx1 array comprising the plurality of support elements and the plurality of electrical contacts is adjacent to each other and does not extend beyond the first edge of the first substrate.

18. The semiconductor device package of claim 17, wherein at least four of the plurality of support elements are arranged symmetrically adjacent to the center of the first surface of the first substrate.

19. The semiconductor device package of claim 11, wherein the support element has a concave sidewall.

20. The semiconductor device package of claim 11, wherein the support element is adhered to the first substrate and the second substrate via the first solder resist and the second solder resist.

21. A method for manufacturing a semiconductor device package, comprising: (a) A first substrate having a first surface is provided, wherein a first pad, a first solder resist and a first antenna pattern are disposed on the first surface; (b) One or more support elements are disposed on the first solder resist of the first substrate, wherein the support element comprises a thermosetting material, the support element has three-stage change states between the glass transition temperature and the curing temperature, the support element is in gel form in stage A, the support element is in shape-adjustable form in stage B, and the support element is in solid form in stage C, wherein the solid form of the support element is a persistent solid form; (c) When the support element is in the Class A state, a second substrate is placed on the support element, the second substrate having one or more electrical contacts on a first surface of the second substrate facing the first surface of the first substrate, wherein a second pad, a second solder resist and a second antenna pattern of the second substrate are disposed on the first surface of the second substrate, wherein the one or more electrical contacts are disposed on the second pad, and the support element is aligned and connected to the first solder resist and the second solder resist. (d) A first temperature is provided to melt the electrical contact, and the support element enters the Class B state, allowing for flexible adjustment of its height and shape; and (e) Providing a second temperature to bring the support element into the C-level state to solidify the support element to define the distance between the first substrate and the second substrate, so as to adjust the resonance of the first antenna pattern and the second antenna pattern; The second temperature is higher than the first temperature. The electrical contact is configured to align the first antenna pattern with the second antenna pattern, and the support element remains solidified while the electrical contact melts.

22. The method of claim 21, wherein in operation (d), the electrical contact is configured such that a conductive pad on the first surface of the first substrate is aligned with a corresponding conductive pad on the first surface of the second substrate, and the support element is integrally located between the first substrate and the second substrate and separated from the electrical contact, wherein the support element adjusts its shape to form a concave sidewall when entering the B-level state.

23. The method of claim 21, wherein In operation (d), the electrical contact is melted at the first temperature to bring the first substrate closer to the second substrate; In operation (e), the support element is cured at the second temperature to maintain the distance between the first substrate and the second substrate, and the time required for the support element to transition from the Class A state to the Class C state is 200 seconds; The first substrate, the second substrate, the electrical contact, and the support element define an air cavity. The electrical contacts are configured to provide self-alignment for the first and second gaskets when they melt at their melting points, the first temperature being 217°C and the second temperature being 225°C. At the second temperature, the support element remains in a solidified state, such that the distance between the first substrate and the second substrate is the stable height of the air cavity.

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