A circuit for adjusting chip fuses through headphone jack

Abstract

The present invention discloses a circuit for trimming a chip fuse through an earphone jack, the circuit is provided with an IIC data communication terminal, the circuit includes an OTP unit, an AND gate NAND1, an AND gate NAND2, an AND gate NAND3, an address encoder, a fuse detection circuit, a selector MUX1, a selector MUX2 and a latch LATCH, the OTP unit is connected to the AND gates NAND1, NAND2, NAND3 and the selector MUX1, the address encoder is connected to the AND gates NAND1, NAND2 and NAND3, the OTP unit is also connected to the latch LATCH and the fuse detection circuit, the latch LATCH is respectively connected to the selector MUX1 and the selector MUX2, the selector MUX1 is connected to the selector MUX2, and the fuse detection circuit is also connected to the selector MUX1 and the selector MUX2. The present invention can trim the chip inside the earphone through the 3.5mm earphone jack reserved by the earphone, the trimming operation is more convenient, which is conducive to reducing the production cost of the earphone and improving the production efficiency of the earphone.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit chip interior, and in particular relates to a circuit for adjusting chip fuses through an earphone jack. Background Art

[0002] In active noise canceling (ANC) headphones, in addition to mechanical components such as pads and speaker acoustic cavities, each noise canceling headphone also requires electroacoustic components such as speakers and active noise canceling microphones. These components combined together determine the frequency and phase characteristics of the headphones. Even the same headphone will have large differences in frequency and phase characteristics due to slight differences in different components.

[0003] By adjusting the gain of the operational amplifier inside the noise reduction chip, the amplitude-frequency and phase-frequency characteristics of the filter circuit outside the noise reduction chip are adjusted. This ensures that every noise reduction headset of the same product has the same noise reduction characteristics, thus ensuring product consistency.

[0004] When the noise reduction chip needs to be adjusted, usually in a finished headset, the commonly used fuse adjustment method requires the chip to be equipped with a dedicated test pin and connection line, so that the test line needs to be connected to the noise reduction chip inside the headset during headset production. This fuse adjustment method will affect the processing cost and efficiency of the headset manufacturer, and it is also difficult to carry out large-scale production and testing.

[0005] Noise-cancelling headphones will be equipped with a 3.5mm headphone jack. When the noise-cancelling headphones are out of power, you can plug the 3.5mm headphone jack into the playback device and continue to use them. The reserved 3.5mm headphone jack reserves the possibility for an external test microcontroller to communicate with the noise-cancelling chip.

[0006] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0007] The object of the present invention is to provide a circuit for trimming chip fuses through an earphone jack, thereby overcoming the above-mentioned defects in the prior art.

[0008] To achieve the above object, the present invention provides a circuit for trimming chip fuses through an earphone jack, the circuit being provided with an IIC data communication terminal, the circuit comprising an OTP unit, an AND gate NAND1, an AND gate NAND2, an AND gate NAND3, an address encoder, a fuse detection circuit, a selector MUX1, a selector MUX2 and a latch LATCH, the OTP unit being connected to the AND gates NAND1, NAND2, NAND3 and the selector MUX1, the address encoder being connected to the AND gates NAND1, NAND2 and NAND3, the OTP unit being connected to the fuse detection circuit, the II The C data communication terminal is connected to the input terminal of the selector MUX1, the OTP unit and the output terminal of the selector MUX1 are connected to the input terminal of the latch LATCH, the output terminal of the latch LATCH is connected to the input terminal of the selector MUX2, and the fuse detection circuit is respectively connected to the input terminal of the selector MUX1 and the input terminal of the selector MUX2; the OTP unit is composed of a storage unit SRAM_UNIT, a NAND gate NAND1, a NAND gate NAND1, an NMOS tube N1, and a PMOS tube P1 connected in sequence, the NMOS tube N1 is grounded, and the NMOS tube N1 is also connected to a fuse, and the fuse is connected to the VDD power supply interface.

[0009] There are 8 OTP units, and the 8 OTP units form an 8-bit register 8bit_REG.

[0010] Each OTP unit is connected to a data read / write control terminal, a data write input terminal, a data output terminal and a fuse state detection terminal.

[0011] The address encoder is connected by three identical inverters INV and eight identical NAND gates NAND, and the eight identical NAND gates NAND are respectively connected to the three identical inverters INV.

[0012] The fuse detection circuit includes a voltage comparator CMP1, a voltage comparator CMP2, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a resistor R5, and the voltage comparator CMP1 is connected to two ends of the fuse respectively.

[0013] The technical solution of the present invention has the following beneficial effects:

[0014] The present invention sets an IIC data communication terminal on the circuit, realizes data communication between the outside and the earphone chip through the IIC data communication terminal, thereby performing data reading and writing operations on the earphone chip, and completing the adjustment process of the internal chip of the earphone; wherein the OTP unit is provided with a fuse, and the data writing operation is realized by opening and closing the fuse, and the circuit is provided with a fuse detection circuit, which can read the state of each fuse, thereby more conveniently completing the data reading and writing operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is an overall schematic diagram of the present invention when the chip fuse is adjusted through the headphone jack;

[0016] Figure 2 A schematic diagram of a circuit for trimming a chip fuse through an earphone jack according to the present invention;

[0017] Figure 3 A schematic diagram of an OTP unit in a circuit for trimming a chip fuse through an earphone jack according to the present invention;

[0018] Figure 4 A schematic diagram of an 8-bit register 8bit_REG in a circuit for trimming a chip fuse through an earphone jack of the present invention;

[0019] Figure 5 A schematic diagram of an address encoder in a circuit for adjusting a chip fuse through an earphone jack of the present invention;

[0020] Figure 6 It is a schematic diagram of a fuse detection circuit in a circuit for trimming a chip fuse through an earphone jack of the present invention;

[0021] Figure numerals: 101 - IIC data communication terminal, 102 - address encoder, 103 - fuse detection circuit, 104 - latch LATCH, 105 - OTP unit read and write control terminal, 106 - OTP unit data write input terminal, 107 - OTP unit data output terminal, 108 - OTP unit fuse status detection terminal, 109 - fuse. DETAILED DESCRIPTION

[0022] The specific implementation modes of the present invention are described in detail below, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0023] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0024] like Figure 1-6As shown, a circuit for trimming a chip fuse through an earphone jack is provided with an IIC data communication terminal 101, and the circuit includes an OTP unit, an AND gate NAND1, an AND gate NAND2, an AND gate NAND3, an address encoder 102, a fuse detection circuit 103, a selector MUX1, a selector MUX2 and a latch LATCH104, the OTP unit is connected to the AND gates NAND1, NAND2, NAND3 and the selector MUX1, the address encoder 102 is connected to the AND gates NAND1, NAND2, and NAND3, the OTP unit is connected to the fuse detection circuit 103, and the IIC data communication terminal 101 is connected to the input end of the selector MUX1, the OTP unit and the output end of the selector MUX1 are connected to the input end of the latch LATCH104, the output end of the latch LATCH104 is connected to the input end of the selector MUX2, and the fuse detection circuit 103 is respectively connected to the input end of the selector MUX1 and the input end of the selector MUX2; the OTP unit is composed of a storage unit SRAM_UNIT, a NAND gate NAND1, a NAND gate NAND1, an NMOS tube N1, and a PMOS tube P1 connected in sequence, the NMOS tube N1 is grounded, and the NMOS tube N1 is also connected to a fuse 109, and the fuse 109 is connected to the VDD power supply interface.

[0025] There are 8 OTP units, and the 8 OTP units form an 8-bit register 8bit_REG.

[0026] Each of the OTP units is connected to a data read / write control terminal 105 , a data write input terminal 106 , a data output terminal 107 and a fuse status detection terminal 108 .

[0027] The address encoder 102 is connected by three identical inverters INV and eight identical NAND gates NAND, and the eight identical NAND gates NAND are respectively connected to the three identical inverters INV.

[0028] The fuse detection circuit 103 includes a voltage comparator CMP1 , a voltage comparator CMP2 , a resistor R1 , a resistor R2 , a resistor R3 , a resistor R4 , and a resistor R5 . The voltage comparator CMP1 is connected to two ends of the fuse 109 , respectively.

[0029] During implementation, the reserved 3.5mm headphone jack of the headphone is connected to the external fuse adjustment box (mainly composed of a 32-bit microcontroller and a 3.5mm headphone jack) through a 3.5mm dual male headphone cable to achieve communication; when the headphone chip is subjected to fuse adjustment operation, the debugging data is first written from DIN<0:7> to the 8-bit register 8bit_REG through the IIC data communication terminal 101, where the data is temporarily stored in the storage unit SRAM_UNIT of the OTP unit, and the data is output from DOUT<0:7> to a specific circuit to complete the verification. Then the burning operation is performed through DIN<0:7> to burn the data that meets the requirements into the 8-bit register 8bit_REG to complete the adjustment process.

[0030] Among them, the OTP unit is a one-time programmable memory inside the chip, which realizes the storage of "0" and "1" in digital logic by closing and opening a fuse 109, thereby realizing programmable operation; specifically, by default, the fuse 109 inside the chip is closed, and the "0" state is stored. During the write operation, after the NMOS tube N1 is turned on, the large current melts the fuse 109, and the "1" state is stored;

[0031] There are 8 OTP units, which can be used to store data of different functions to implement functions such as operational amplifier gain adjustment;

[0032] The function of the address encoder 102 is mainly to encode the serial address data input by the IIC data communication terminal 101, so as to open or close the 8-bit register 8bit_REG, and cooperate with the read enable signal RE_EN and the write enable signal WR_EN to perform read and write operations on the 8-bit register 8bit_REG; when the WR_CLK clock signal of the read / write control terminal of the specific OTP unit has a rising edge and WR_EN is "1", the data of the address encoder 102 passes through the AND gate NAND2 and then through WR_OTP to perform a write operation on a specific bit in the 8-bit register 8bit_REG;

[0033] When the fuse detection circuit 103 is working, the voltage across the fuse 109 is compared by the voltage comparator CMP1 to determine whether the fuse 109 inside the chip is in an open or closed state;

[0034] The latch LATCH104 mainly reads the written data from the register 8bit_REG, so that the chip can adjust the internal transport amplifier gain through the IIC terminal.

[0035] The present invention sets an IIC data communication terminal on the circuit, realizes data communication between the outside and the earphone chip through the IIC data communication terminal, thereby performing data reading and writing operations on the earphone chip, and completing the adjustment process of the internal chip of the earphone; wherein the OTP unit is provided with a fuse, and the data writing operation is realized by opening and closing the fuse, and the circuit is provided with a fuse detection circuit, which can read the state of each fuse, thereby more conveniently completing the data reading and writing operations.

[0036] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A circuit for trimming chip fuses through an earphone jack, characterized in that: The circuit is provided with an IIC data communication terminal, and the circuit includes an OTP unit, an AND gate NAND1, an AND gate NAND2, an AND gate NAND3, an address encoder, a fuse detection circuit, a selector MUX1, a selector MUX2 and a latch LATCH, the OTP unit is connected to the AND gates NAND1, NAND2, NAND3 and the selector MUX1, the address encoder is connected to the AND gates NAND1, NAND2, and NAND3, the OTP unit is connected to the fuse detection circuit, and the IIC data communication terminal is connected to the selector MUX1 input The input end, the OTP unit and the output end of the selector MUX1 are connected to the input end of the latch LATCH, the output end of the latch LATCH is connected to the input end of the selector MUX2, and the fuse detection circuit is respectively connected to the input end of the selector MUX1 and the input end of the selector MUX2; the OTP unit is composed of a storage unit SRAM_UNIT, a NAND gate NAND1, a NAND gate NAND1, an NMOS tube N1, and a PMOS tube P1 connected in sequence, the NMOS tube N1 is grounded, and the NMOS tube N1 is also connected to a fuse, and the fuse is connected to the VDD power supply interface.

2. The circuit for trimming chip fuses through the headphone jack according to claim 1, characterized in that: There are 8 OTP units, and the 8 OTP units form an 8-bit register 8bit_REG.

3. The circuit for trimming chip fuses through the headphone jack according to claim 2, characterized in that: Each OTP unit is connected to a data read / write control terminal, a data write input terminal, a data output terminal and a fuse state detection terminal.

4. The circuit for trimming chip fuses through the headphone jack according to claim 1, characterized in that: The address encoder is connected by three identical inverters INV and eight identical NAND gates NAND, and the eight identical NAND gates NAND are respectively connected to the three identical inverters INV.

5. The circuit for trimming chip fuses through the headphone jack according to claim 1, characterized in that: The fuse detection circuit includes a voltage comparator CMP1, a voltage comparator CMP2, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a resistor R5, and the voltage comparator CMP1 is connected to two ends of the fuse respectively.

Images