Analog-to-digital converters using memory in neural networks

Abstract

An analog-to-digital conversion device includes an input terminal for receiving an analog input signal; multiple output terminals for outputting multiple parallel bits of a digital signal representing the analog input signal; a training neural network layer, including multiple connections between each of the multiple output terminals, each connection has a weight, and the weight is adjustable. The synapses of the neural network are memristors, and the training uses online gradient descent.

Description

Technical Field

[0001] In certain embodiments, the present invention relates to analog-to-digital converters (ADCs) using memristors in neural networks. Background Art

[0002] The rapid evolution of data-driven systems into the Internet of Things era has paved the way for urgent communication and changing applications where data converters are ubiquitous. The need for accurate, fast, and power-efficient data converters continues to grow with the advent of high-speed, high-precision, and low-power mixed-signal systems. These systems operate on a variety of real-world continuous-time signals; examples include medical imaging, biosensors, wearables, consumer electronics, automotive, instrumentation, and radio communications. Unfortunately, the inherent speed-power-accuracy tradeoff in analog-to-digital converters (ADCs) has kept them out of the application range of interest. Furthermore, as Moore's Law continues to drive technology scaling, worrisome deep sub-micron effects have become a long-standing bottleneck in modern system design. These effects are not well handled using special design techniques that overload the data converter and incur significant overhead, exacerbating the tradeoffs and severely degrading its performance. Today, data converters lack design standards and are complex, specific design flows and architectures tailored to special-purpose applications. Summary of the invention

[0003] This embodiment includes constructing an analog-to-digital converter that samples the input and uses a neural network based on a memristor component to train a specific signal. The output bit and the current input are used as input to the neural network to generate a new output bit.

[0004] According to an aspect of some embodiments of the present invention, there is provided an analog-to-digital conversion device, comprising:

[0005] An input terminal, used to receive an analog input signal;

[0006] a plurality of output terminals for outputting a plurality of parallel bits of a digital signal representing the analog input signal; and

[0007] A trainable neural network layer comprises a plurality of connections between each of the plurality of output terminals, wherein each connection has a weight, and the weight is adjustable for training.

[0008] In one embodiment, the connection comprises a plurality of adaptable synapses to provide the weight to be adjustable.

[0009] In one embodiment, each adaptive synapse is configured with its own weight, and each output bit is a comparison result of a weighted sum of multiple output bits.

[0010] In one embodiment, each of the plurality of adaptive synapses comprises a memristor, and the memristor is configured with a respective weight.

[0011] Embodiments may further include a training unit having a training data set input, connected to the plurality of output bits, and configured to adjust each of the plurality of adaptive synapses until the plurality of outputs for a given input corresponds to a training data set.

[0012] In one embodiment, the training data set is used in conjunction with a predetermined maximum voltage and a predetermined number of the plurality of output bits.

[0013] Embodiments may be configured to perform the adjustment by using online gradient descent. The online gradient descent comprises the equation for a number of iterations k:

[0014]

[0015] Where η is the learning rate, Vi (k) is in k th A single empirical sample is provided to the input at the iteration, and the equation:

[0016]

[0017] In one embodiment, the adjusting includes minimizing a training error function and an energy cost function.

[0018] In one embodiment, the adjusting includes minimizing a quality factor, wherein:

[0019]

[0020] Where P is the power consumption during conversion, fs is the sampling frequency, and;

[0021]

[0022] Where SNDR is the signal-to-noise ratio.

[0023] According to a second aspect of the present invention, there is provided an analog-to-digital conversion method, comprising the steps of:

[0024] receiving an analog input signal;

[0025] outputting a plurality of parallel bits of a digital signal representing the analog input signal at a plurality of output terminals; providing a plurality of connections between each of the plurality of output terminals; and

[0026] Adjustable weights are provided to each connection, thereby providing a trainable neural network connecting the plurality of output terminals.

[0027] Unless otherwise defined, all technical and / or scientific terms used herein have the same meanings as those of ordinary skill in the art to which the invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the invention, exemplary methods and / or materials are described below. In the event of a conflict, the patent specification and its definition shall prevail. In addition, materials, methods and embodiments are illustrative only and are not intended to be necessarily restrictive. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Some embodiments of the present invention are described herein with reference to the accompanying drawings by way of example only. With specific reference now to the drawings, it is emphasized that the details shown are by way of example and for the purpose of illustrative discussion of embodiments of the present invention. In this regard, it will be apparent to those skilled in the art from the description in conjunction with the drawings how embodiments of the present invention may be practiced.

[0029] In the attached picture:

[0030] Figure 1 Shown is a simplified block diagram of a trainable ADC in accordance with an embodiment of the present invention.

[0031] Figure 2 A simplified flow chart showing how input and training signals are used to perform neural network training according to the present embodiment.

[0032] Figures 3a) to 3d) Four graphs showing the tradeoffs involved in prior art optimization.

[0033] Figure 4 A comparison diagram showing the training efficiency in the prior art and this embodiment.

[0034] Figure 5a) and 5b) It is a flowchart and a generalized circuit of a successive approximation of an embodiment of the present invention.

[0035] Figure 6a ) to 6c) are Figure 5b )'s three components of the circuit.

[0036] Figure 7a) to Figure 7d) are four diagrams showing aspects of the training process according to the present embodiment.

[0037] Figure 8a) to Figure 8d) Yes Display Figures 7a) to 7d) Four plots of the efficiency of the training process.

[0038] Figure 9a) to Figure 9d) are four graphs showing the speed-power-accuracy tradeoff according to the present embodiment. DETAILED DESCRIPTION

[0039] In certain embodiments, the present invention relates to analog to digital converters (ADCs) using memristors in neural networks.

[0040] Analog-to-digital converters (ADCs) are a staple in every data acquisition system. Unfortunately, modern ADCs require a trade-off between speed, power, and accuracy. In this embodiment, a novel neural-inspired approach is used to design an intelligent ADC that can be trained in real time for general-purpose applications and overcome the limitations of previous ADCs. Driven by artificial intelligence learning algorithms and neural network architectures, the proposed ADC integrates emerging memristor technology with CMOS. We design a trainable four-bit ADC with a memristor neural network that implements an online gradient descent algorithm. This supervised machine learning algorithm is suitable for a variety of application specifications, such as full-scale voltage range and sampling frequency. Theoretical analysis and simulation results show powerful collective properties, including reconfiguration, mismatch selfcalibration, adaptation to dynamic voltage and frequency scaling, noise tolerance, and power consumption optimization. The proposed ADC can achieve up to 8.25 fj / conv figure of merit (FOM), 3.7 effective number of resolution bits (ENOB), 0.4 LSB integral nonlinearity (INL), and 0.5 LSB differential nonlinearity (DNL). These features make it a leading contender for general and emerging data-driven applications.

[0041] That is, the present embodiment adopts a different approach to designing a general-purpose ADC. In the present embodiment, the converted data is used to train the converter to autonomously adapt to the exact specifications of the application being run and to adapt to environmental changes. This approach can shorten the time to market of the converter, effectively expand with new technologies, significantly reduce its cost, standardize the design process, and provide a general-purpose architecture for general-purpose applications. The proposed trainable ADC uses machine learning (ML) algorithms to train an artificial neural network (ANN) architecture based on the promising memristor technology. Memristors are widely used in the design of synapses in artificial neural systems due to their small footprint, analog storage characteristics, energy efficiency and non-volatility. These features allow synapse-like behavior, where the conductance of the memristor is considered as the weight of the synapse. We use memristors as synapses to achieve a high-precision, high-speed, low-power, simple, cost-effective and reconfigurable single-channel ADC architecture, thereby breaking the trade-off between speed and power accuracy. Please refer to the applicant's previous patent applications for online training on memristor synapses and digital-to-analog converters (DACs).

[0042] We will explain the motivation behind our approach and then introduce the ADC architecture, theory, and training algorithm. As an exemplary embodiment, the circuit design and mechanism of a four-bit ADC are detailed. The circuit operation and learning capabilities of the embodiment are evaluated. The design trade-offs and large-scale issues are discussed before we draw conclusions.

[0043] Before explaining at least one embodiment of the present invention in detail, it should be understood that the application of the present invention is not necessarily limited to the construction and arrangement details of the components and / or methods described in the following description and / or shown in the drawings and / or embodiments. The present invention can have other embodiments or can be practiced or implemented in various ways.

[0044] Reference now Figure 1, showing a simplified block diagram of an analog-to-digital converter 10 according to an embodiment of the present invention. The analog-to-digital converter has an input terminal 12 for receiving an analog input signal. An output terminal 14, exemplarily shown here as four outputs D0 to D3, outputs parallel bits of a digital signal representing the analog input signal. It should be noted that other numbers of output bits can be appropriately provided for specific purposes. The converter 10 is trainable, and as will be described in more detail below, one or more neural network layers provide connections between each output. Each connection has an adjustable weight, which is set by a training process. More specifically, the connection includes adaptive synapses, so that the weights can be adjusted by a training process. In operation, each adaptive synapse is set with a specific weight so that each output bit is the sum of different weights of all previous or current output bits. In an embodiment, a comparator is used to obtain a comparison result based on the sum of weights.

[0045] In an embodiment, a memristor with adjustable resistance is used to provide adjustable weights to the connection terminals. Through a training procedure, each memristor has a specific weight. The training can be performed in advance and / or during use.

[0046] To pre-train, a training unit 16 is connected to the output digital 14, which is compared with the training bits T0..T3 from the training data set input 18. The training unit adjusts each adaptive synapse until the output for a given input corresponds to the training data set. Although the frequency can be varied, the training data set can be chosen for a given maximum voltage and a given number of input bits. The training can then ensure that power consumption is minimized and the effective number of bits of resolution (ENOB), which is equivalent to minimizing the figure of merit (FOM).

[0047] The adjustment can be done using online gradient descent. Online gradient descent consists of the following iterations k:

[0048]

[0049] Where η is the learning rate, Vi (k) At iteration k th A single experience sample is provided to the input at the time, and:

[0050]

[0051] Adjustment may include minimizing a quality factor, as will be discussed in more detail below. Minimization may involve minimizing a training error function and an energy cost function, and a resulting quality factor, which may be an equation combining these functions. The quality factor may be given, for example, by the following equation:

[0052]

[0053] Where P is the power consumption during conversion, fs is the sampling frequency, and;

[0054]

[0055] SNDR is the signal to noise distortion ratio (SNR). More specifically, Figure 1 A trainable 4-bit ADC 10 is shown which receives a signal fs,VFS,N and is trained in real time by providing a specific teaching data set Ti. The training continues until the ADC reaches an optimal FOM.

[0056] Reference now Figure 2 , showing the use Figure 1 Simplified diagram of the analog to digital conversion method of the device shown. The network of connections between the outputs is initially trained – 20. Prior to training, the sampling frequency can be selected. Training involves providing weights for the memristor-based connections that form the neural network layer between the output bits – 22. The weights are provided using online gradient descent 24 as defined above, and minimizing the quality factor 26. The result is then set into the memristor 28.

[0057] During both training and use, an analog input signal is received and sampled 30. The samples are fed 32 through the trained neural network and output bits 34 are obtained to provide a digital representation of the input analog signal. During training, the output bits are compared to the training bits representing the correct answer the converter should achieve, and the weights are adjusted as described above until the difference between the output bits and the training bits is minimized.

[0058] The various embodiments are now considered in more detail.

[0059] A. Speed-Power-Accuracy Tradeoffs in ADC Architectures

[0060] While the main characteristic of the analog domain is energy efficiency in data processing, its digital counterpart excels in reliable computation. ADCs are mixed-signal systems that inherently combine hybrid analog-digital principles with the advantages and disadvantages of each domain.

[0061] Therefore, these systems are optimally tailored to fit a specific subset of a broad range of functions. Design tradeoffs are an extreme case when pushing a system to its performance limits. The ADC includes: a signal sampler that discretely samples a continuous-time signal at a constant rate; and a quantizer that converts the sampled values ​​into a corresponding discrete-time A-bil resolution binary encoded form. The quality of the system is considered ideal when the system achieves high speed and high accuracy. This paper presents a proof-of-concept of a real-time trainable ADC architecture for general-purpose applications that breaks the speed-power-accuracy trade-off. Inspired by the analogy between mixed-signal circuits and the neuromorphic paradigm, we exploit the intelligent properties of artificial neural networks and propose a pipelined SAR-style neural network architecture ADC trained online by a supervised ML algorithm.

[0062] The neural network of this embodiment can share the Hopfield energy model, and after the training is completed, we show the equivalent relationship between the energy function to the conversion cost function and the training error function.

[0063] The neural network can be implemented through a hybrid CMOS-memristor circuit design. The trainable mechanism can show the collective properties of the network when reconfigured to multiple full-scale voltages and frequencies, mismatch self-calibration, noise tolerance, stochastic resonance, power optimization, and dynamic scaling of FOM. We believe that the ADC according to the present embodiment can constitute a milestone for large-scale architectures of data converters and emerging real-time adaptive applications with changing conditions, such as wearable devices and automotive applications.

[0064] While the main characteristic of the analog domain is the energy efficiency of data processing, its digital counterpart excels in reliable computing. ADCs are mixed-signal systems that inherently combine hybrid analog-digital principles with the advantages and disadvantages of each domain. Therefore, these systems are optimally tailored to fit a specific subset of a wide range of functions. Design compromises are an extreme case when pushing the system to its performance limits. The ADC consists of: a signal sampler that discretely samples the continuous-time signal at a constant rate; and a quantizer that converts the sampled values ​​into a corresponding discrete-time N-bit resolution binary coded form. The quality of the system is considered ideal when high speed and high accuracy are achieved with low power consumption. However, in reality, the resolution decreases as the conversion rate increases, and greater power consumption is required to achieve the same resolution.

[0065] Device mismatch is the main factor affecting system accuracy. Larger devices must be used to improve system accuracy, but the result is increased capacitive loading of circuit nodes and more power is required to achieve a certain speed. The maximum speed of the system is a function of gain bandwidth, but is limited by the input pole.

[0066] In addition to device mismatch, there are four loss mechanisms that affect ADC resolution and limit the signal-to-noise ratio (SNDR): quantization noise, jitter, comparator ambiguity, and thermal noise. Quantization noise is the only error in an ideal ADC. Jitter is the variation between samples at the instant when sampling occurs. In addition, the conversion speed is limited by the ability of the comparator to make a deterministic decision about the relative magnitude of the input voltages. This limitation is called comparator ambiguity and is related to the speed of the device that manufactures the ADC. Device speed is measured as the frequency, fT, at which the unit current gain increases. Due to these limitations, approximately one bit of resolution is lost each time the sampling rate is doubled. Nonlinear distortion, memory effects, and device mismatch can be compensated to a certain extent, while thermal noise cannot be compensated. Therefore, it is one of the main limiting factors in ADC performance. Modeled by KT / C noise, where K represents Boltzmann's constant, T represents temperature, and C represents sampler capacitance. Reducing the noise floor by a factor of two in a purely thermal noise limited circuit will increase power consumption by a factor of four. The limit on power consumption imposed by device mismatch is about two orders of magnitude higher than the limit imposed by thermal noise.

[0067] Reference now Figure 3a) to Figure 3d) Figure 1. Showing the tradeoffs between (a) speed and accuracy, (b) speed and power, and (c) accuracy and energy for traditional ADC architectures. Since the power-accuracy tradeoff depends on the limitations of the underlying architecture, the energy-accuracy tradeoff is architecture-independent and the tradeoff is shown accordingly. Figure 3d ) is a spider diagram of ADC architectures (different lines), design tradeoffs, and related applications (blue). Figure 3a) to Figure 3c) It illustrates the speed-power-accuracy tradeoff and is based on data we obtained from Stanford's ADC survey, which includes papers published over the past two decades.

[0068] The need to digitize such a wide variety of signal types has resulted in a wide range of data converters with varying resolutions, sampling rates, and power budgets. These considerations profoundly impact system architecture and its performance.

[0069] The speed-power-accuracy tradeoff has led to a variety of ADC architectures optimized for special purposes such as high-speed, high-resolution, and low-power applications. Figure 3d ) gives the widely used ADC architectures, each corresponding to its market application.

[0070] B. ADC Figure of Merit (FOM)

[0071] When comparing ADCs with different specifications, a numerical value called a figure of merit (FOM) is used to characterize the performance of each ADC relative to its alternatives. Two or more metrics can be combined into a single FOM that accurately reflects the merits of an ADC in a particular situation and for a particular purpose. One of the most widely used FOMs is defined as:

[0072]

[0073] And the ADC power consumption P during conversion is related to performance based on the sampling frequency fs and the effective number of resolution bits (ENOB). Lower FOM values ​​will result in better ADC performance. ENOB is calculated from SNDR as:

[0074]

[0075] The aforementioned FOM best reflects the basic speed-power-accuracy tradeoff. To date, the trend in CMOS technology development has been toward smaller transistor sizes, leading to the development of ultra-deep submicron transistors.

[0076] The evolution of FOM is also best described by Moore's Law (ADC). Technology scaling improves sampling frequency because fT allows faster operation. However, the speed of the sampling frequency is limited by the ambiguity of the comparator. In the same case, the impact of technology scaling on power optimization is also limited by the supply voltages and leakage currents, which inevitably lead to an increase in the power consumption required to maintain SNDR. These limitations, as well as manufacturing process variations and device mismatches in ultra-deep submicron technologies, are the biggest obstacles to achieving high linearity, wide dynamic range, and high-resolution converters. Therefore, as technology shrinks, the speed-power-accuracy trade-off is becoming more and more severe, making future data converters beyond the scope of the application of interest.

[0077] Reference now Figure 4 ,illustrate Figure 1The average FOM evolution of different ADC architectures and specifications as technology nodes are scaled down is shown in . In general, FOM improves as technology scales down. However, the trend line shows an asymptotic slowdown over the past decade. Green star 40 shows the FOM based on the implementation of this embodiment and shows the overall improvement of FOM with respect to technology node. Except for considering star 40, the overall improvement may be attributed to lower resolution converters that benefit from technology scaling. However, this improvement has slowed down significantly and ADC performance has saturated recently. The noise floor has saturated over the past decade, indicating that future ADCs will most likely not even be able to maintain the current state-of-the-art noise performance.

[0078] C. Trainable ADC for General Applications

[0079] Techniques to avoid tradeoffs have been studied recently, with the goal of achieving ultra-low power converters with high resolution through a combination of system, architectural, and technical approaches. Examples of such approaches are digitally assisted background calibration, time-interleaving, pipelining, subranging, folding, interpolating, and oversampling. These techniques have successfully postponed FOM saturation.

[0080] Modem ADC architectures are custom designed circuits that can be fine-tuned to optimize specific functions and design parameters to meet the application specifications. Widely used approaches are complex, specific, and technology-dependent, lacking a standard design flow. These approaches require detailed characterization, extensive validation, and a relatively long time to market. In addition, a rapid growth in multi-channel ADCs has been observed recently. Multiple channels are monolithically integrated for diversity-based applications, increasing the overall area, cost, design complexity, and power consumption.

[0081] In the same context, reconfigurable architectures that dynamically select between a narrow range of different predefined design specifications have been developed. Conversely, minimalist design approaches have been proposed to improve power efficiency and potentially increase speed by utilizing simplified analog subcircuits. It is very likely that future collective improvements in ADC FOM will come from a combination of factors, including novel architectures, emerging technology devices beyond CMOS, and systems approaches beyond Moore's Law.

[0082] The field of machine learning (ML) is dedicated to the study and implementation of systems that can learn from data using their evolving perception capabilities to make critical decisions, predictions, and classifications based on past experiences. Data transformation can be viewed as a special case of classification optimization and signal recovery problems, which can be easily solved using ML to learn from data.

[0083] like Figure 1 The present embodiment can provide a trainable ADC architecture for general applications. In this embodiment, a set of parameters is determined to meet the requirements of the application being run. First, the sampling frequency fs is determined, then the number of bits of resolution N is determined, and then the full-scale voltage VFS is determined, which specifies the ADC input dynamic range. The ADC is then trained in real time by an ML algorithm to optimize ENOB and power consumption. This process is equivalent to dynamic FOM optimization, which will be demonstrated in the work and can potentially achieve much lower FOM than the trend line. Figure 4 FOM 40 in.

[0084] The technology is not limited to reconfiguration, but can be applied to device mismatch self-calibration, adaptation and noise tolerance using common standard methods. In addition, the trainability of the architecture increases flexibility, making it cost-effective and versatile, and its minimalist design uses one channel and smart ML algorithms.

[0085] III. Neural Network ADC

[0086] Neuromorphic computing is a mixed-signal design that inherently combines analog and digital domains at the molecular, biophysical, behavioral, and functional levels of abstraction. From electronics to neurobiology, it can be concluded that the brain effectively computes in a hybrid manner. Similarly, the present embodiment can interpolate perceptual capabilities from neurobiology to mixed-signal electronics to break through the derived design tradeoffs and leverage the advantages of both fields.

[0087] Artificial neural networks have received widespread attention as potential new architectures and models to solve a wide range of problems, such as pattern classification, object recognition, and signal processing. In addition, artificial neural networks are considered to be an efficient abstract platform for ML algorithms and big data interpretation. The massively parallel processing capabilities of neural networks lie in the collaboration between highly interconnected computing elements (neurons) connected by long-term storage elements (synapses). In addition, the trainable and adaptive capabilities of machine learning algorithms are considered novel intelligent features that can provide power in specific areas where traditional computers have poor performance compared to our brains.

[0088] Here, this embodiment can provide a neural network ADC example. We will show its architecture, basic principles, theory, and ML algorithm used to train the network.

[0089] A. Architecture

[0090] ANN architectures are distributed networks that jointly make decisions based on the adjustment of successive approximation weights. Remarkably, this mechanism accurately describes ADCs such as SAR ADCs in a bit-by-bit binary-weighted approximation manner on a temporal scale. While bit comparisons are equivalent to neural activations, in a successive binary search algorithm, each reference scale is equivalent to a binary-weighted synapse. In a first step, we first convert the temporal binary search algorithm for 4-bit SAR conversion into a spatial neural network with binary-weighted synapses and pipelined forward propagation neurons (MSB to LSB);

[0091]

[0092] Where Vin is the analog input, D3D2D1D0 is the corresponding digital form (i=3 is the MSB), and each bit (neuron product) has either zero voltage or full-scale voltage. u(·) is represented as the signal neural activation function, and Vref is the reference voltage equal to the smallest discrete voltage quantum (LSB). Each neuron is a collective integrator of its input. The analog input is sampled and approximated sequentially (through a pipeline) by a combination of binary-weighted inhibitory synaptic connections.

[0093] The process of approximating each bit in the ADC is modular. First, the MSB voltage D3 is determined independently of the other bits by comparing it to the middle of the full-scale voltage. When D3 is known, the second MSB is bypassed and it is found regardless of D1D0. If D3 is a '1', then D2 is compared to three-quarters of full scale; otherwise, it is compared to one-quarter of full scale. Similarly, the LSB is approximated based on driving the MSB. Figure 5a ), the successive approximation flow in the SAR-type neural network is described by a binary search tree 50 with all possible combinations. In the read cycle after the propagation time tp, each neuron makes a decision, decides to spend time td, and drives other neurons forward in an asynchronous pipeline manner, and the strength (synaptic weight) is proportional to its importance. The total propagation time shown by the arrow 52 is less than the duration of the read cycle.

[0094] In real-time operation where non-ideal, nonlinear, random and changing conditions affect the conversion accuracy, the correct weights cannot be deterministically distributed in a binary weighted manner. In this case, the weights should be updated in real time in situ through training feedback. Four different binary weighted weights are required to implement a 4-bit ADC, and 24 different accurate weights are required around each binary weighted weight to fine-tune the LSB neuron. The interconnected synaptic weights of the network are described by the matrix W, and each element Wij represents the connection weight from the presynaptic neuron j to the postsynaptic neuron i. Figure 5b ) is illustrated in Figure 5 , including its building blocks (neurons, synapses, and feedback). More specifically, a neural network 4-bit ADC architecture 60 may include synapses Wi,j 62 and feedback FBi 66 leading to neuron Ni 64. The waveform diagram of the neural activity during forward propagation between bits 68 shows how the signal increases for subsequent bits. The propagation time of the neural decision 52 should be less than the read cycle. The digital output Di 70 is sampled at the end of the read cycle and then latched during the write cycle to be compared with a taught data set Ti corresponding to the analog input ramp. The read and write related signals are marked blue and red, respectively.

[0095] theory

[0096] Surprisingly, the architecture used in this embodiment contains equivalents to well-studied architectures with emergent collective computing properties. A simple single-layer neural network was developed from the complex Hopfield neural network. The originally proposed Hopfield network was considered to be a subtype of recurrent neural network with a parallel single layer containing fully connected neurons with inhibitory feedback, bidirectional data traversal, and no automatic feedback. From a design point of view, the Hopfield network with symmetric connections is particularly convenient for ADC tasks.

[0097] Interestingly, ADC is based on an energy function that describes the macroscopic dynamics of the network. The energy function characterizes the energy minimization process and the recursive convergence of the network from the initial state to the minimum energy of the steady state. The energy function is used as a cost function of the network tailored to solve a specific optimization problem. The energy function is used as a cost function of the network tailored to solve a specific optimization problem.

[0098] However, Hopfield networks have some disadvantages that limit their use in practical applications. Due to the complex nature of the energy function, the solution of the symmetric network is highly dependent on its initial state. The energy function may decrease and then stabilize to one of the equilibrium points, called a "spurious state" or "local minimum", which does not correspond to the correct digital representation of the input signal and causes the ADC characteristics to be far from ideal. Fortunately, these nonlinearities can be eliminated using a modified Hopfield network with an additional self-correcting logic network and an extended resistor network. Another elimination technique is to use separate electronics to force the neurons to reset, which in turn limits the operating frequency and the ADC speed. In addition, Hopfield networks have structural drawbacks, especially at large scale: a large number of synapses, a high weight ratio, and quantization errors. Recently, a 2-bit Hopfield-based ADC quantizer based on level shifting was proposed to overcome the shortcomings of the original Hopfield network scaling and eliminate the digital errors that increase with the number of bits.

[0099] The ADC architecture of the present embodiment is equivalent to a specific class of asymmetric Hopfield type networks and has been designed to overcome the shortcomings and stability issues of Hopfield networks. The equilibrium point is globally attractive, globally asymptotically stable and guaranteed; that is, for each choice of initial conditions and each choice of nonlinearity, the system will converge towards this point. In addition, neural networks with lower block triangular interconnect structures for ADC applications have been extensively explored in the literature, including their mathematical basis, formalization, qualitative analysis, quantitative asymptotic constrained stability, encoding techniques and synthesis methods.

[0100] Similar to the Hopfield energy function, we describe the energy function of the proposed asymmetric architecture as:

[0101]

[0102] where Wij is the synapse (conductance) between the presynaptic neuron with index j and digital voltage Dj and the postsynaptic neuron with index i and digital voltage Di, as Figure 5b ) as shown.

[0103] The derivative of E with respect to Di is negative and equal to the inverse sum of the input currents of neuron i. Therefore, E is a monotonically decreasing function and reaches its minimum value when Di changes to ensure that the total current on the entire ramp input is zero. The first component refers to the power dissipation of the interconnected synapses, taking into account the asymmetry of the network (j counts from i). The second part refers to the external dissipated power consisting of the analog input voltage source and the reference voltage source.

[0104] The strategy used in creating equation (4) is to view the ADC as an optimization problem implemented by the following error function EQ, which is formalized similarly to the following:

[0105]

[0106] Where the first component is the power of the quantization error. The minimum value is obtained when the digital code corresponds to the correct analog input. The second component is added to eliminate the diagonal elements (self-feedback), and its value is always zero. By reordering equation (5) as an energy-like function, similar to equation (4), we obtain:

[0107]

[0108] 2 of them N is a constant and does not affect the optimal weights of the ADC network. The weights are extracted by comparing equation (6) with equation (4): ij(j>i) =-2 j ,W ij(j≤i) =0,W ii n =1,W ir =-2 i-1 , these values ​​are typical values ​​of a deterministic ADC similar to the ADC calculated in (3).

[0109] Unlike in the Hopfield network, the convergence of the energy function according to the present embodiment toward its minimum in the network is globally attractive and is not affected by the transient behavior of the circuit elements. In addition, the network according to the embodiment of the present invention is superior to the Hopfield network in terms of scalability: the number of synapses is halved, and each weight value is reduced by 2i.

[0110] In the following, it is shown that after training the network converges to the lowest energy level.

[0111] C. Training Algorithm

[0112] The learning capabilities of asymmetric Hopfield networks are thoroughly investigated. A learning algorithm based on the least mean square (LMS) algorithm is introduced, and several specific examples are considered to illustrate the learning capabilities, network flexibility, linear separability of transformations, and the effectiveness of LMS in training asymmetric networks compared to Hopfield and multilayer neural networks. The recursion of the Hopfield network complicates its feasibility in field training and adaptability. Alternatively, the Hopfield network can be cascaded by deep neural networks and trained using a back-propagation algorithm to adaptively calibrate quantization errors and keep the amplitude of the digital output code within a manageable operating voltage range. Compared to the network according to the present embodiment, the extension is split between the training (encoding) path and the transformation (inference) path, which may complicate the feasibility of a scalable level-shifting architecture and consume a lot of resources.

[0113] Consider the following supervised learning task. Suppose a learning system is run on K discrete trials, indexed as k = 1, 2, ..., K. In each trial k, the system obtains {V in ,T i}, i = 0, ..., N-1 empirical data set, where: V in (k) ∈R is a sampled simulation mode; Ti∈R N is corresponding to V in (k) , and D i (k) is the actual i-th digital output, all pairs share the same desired relationship, T i (k) =f(V in (k) ,D1,...,Di-1). Note that two different patterns can have the same label (in the case of an ADC, the same digital level depending on the quantization resolution). The goal of the system is to estimate (learn) the function f(·) using empirical data.

[0114] Assume W is the asymmetric matrix in question and consider each neuron estimator as:

[0115]

[0116] Where u(·) represents the signal neural activation function, c refers to a constant of the reference voltage, and each Di acts as a linear classifier with one output and propagates forward to approximate other outputs. Therefore, no hidden layer is required, and the signal activation function is sufficient to estimate the function f(·). The network according to this embodiment can be regarded as a concurrent single-layer or pipelined feedforward multi-layer neural network, where each layer determines the output bit. Each estimator Di (k)should aim to predict the correct taught label T for new unseen patterns Vin i (k) To solve the problem, W is adjusted to minimize a certain degree of error between the estimated labels and the expected labels on a K0-long subset (for k=1,...,K0) of the empirical data or training set. Then, the common metric error metric is the minimum mean square error function, defined as:

[0117]

[0118] The 1 / 2 coefficient is for mathematical convenience. Different error metrics can also be used. The performance of the resulting estimator is then tested on different subsets called test sets (k=K0+1,...,K). The following is an example of online stochastic gradient descent, which minimizes the error (i.e., updates W when the initial choice of W is arbitrary);

[0119]

[0120] where η is the learning rate, a (usually small) positive constant, and at each iteration k, a random sample of experience V is selected in (k) and is shown in the system input. Chain rules (7) and (8) are used to obtain the outer product:

[0121]

[0122] The update rule is called the least mean square (LMS) algorithm and is used in adaptive filters for signal processing and control. Note that the update rule (10) is local, i.e., the change in the synaptic weight Wij (j>i) depends only on the relevant component D i (k) ,T i (k) ,T j (k) .

[0123] Local updates are widely used in ANN training and ML algorithms to achieve massive parallel speedups. The training phase continues until the error falls below a threshold Ethreshold, which is a small predefined constant threshold that quantifies the learning accuracy. We show for the first time below that after training, the error function in (8) is proportional to the cost function in (5) and the network energy function in (4). The training algorithm can be given by Figure 5b ) is achieved by the feedback 66 shown in FIG.

[0124] Circuit Design

[0125] In the following, we present the circuit design building blocks of the ADC architecture of this embodiment, including its different components: neurons, synapses, and feedback circuits. L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky further discuss the design approach, operating mechanisms, and constraints of the building blocks, "DIDACTIC: Data-Intelligent Digital-to-Analog Converters with Trainable Integrated Circuits Using Memristors," IEEE J. Emerg. Sel. Topics in Circuit Systems, Vol. 8, No. 1, pp. 146-158, March 2018, the contents of which are incorporated herein by reference. For simplicity, we provide the circuit design of the quantization stage and assume that the analog inputs are sampled separately through external sample-and-hold circuits.

[0126] Artificial synapses

[0127] We adopt the synaptic circuit design from the earlier work mentioned above to provide a voltage-controlled memristor M80 connected to the shared terminal 82 of two MOSFET transistors (p-type 84 and n-type 86), as shown in Figure 6(a). The circuit exploits the intrinsic dynamics of the memristive crossbar switch (2T1R), whose impedance inherently implements Ohm's and Kirchhoff's laws, for implementing ANN hardware. The output of the synapse is the current flowing through the memristor. The synapse receives three voltage input signals: u is connected to the source of one transistor, is connected to the source of the other transistor and the enable signal e is connected to the gates of both transistors. The enable signal e can have a value of zero, which means that both transistors are not conducting, VDD, which means that only NMOS is conducting, or -VDD, which means that only PMOS is conducting.

[0128] The synaptic weight is modified according to the value of e, which selects the input u or u. Therefore, the write voltage Vw (or -Vw) is applied via the source terminals of the two transistors. Note that the right end of the memristor is connected to the virtual of the operational amplifier (OpAmp), while the left end is connected to the transistor and the damping capacitor operating in the ohmic state. The memristor value Mi,j varies between the low resistance state and the high resistance state, Ron and Roff, respectively.

[0129] As in our previous work, L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky, “DIDACTIC: Data-intelligent digital-to-analog converters with trainable integrated circuits using memristors,” IEEE J. Emerg. Sel. Topics in Circuits Systems, Vol. 8, No. 1, pp. 146-158, March 2018, the contents of which are incorporated herein by reference.

[0130] For the design of the ADC according to this embodiment, we can use a 0.18 / μm CMOS process and use the VTEAM model to assemble the memristor onto a Pt / HfO2 buffer layer. x / Hf / TiN RRAM device. The device has a high to low resistance state (HRS / LRS) ratio of ∼50 and formation, set and reset voltages. The circuit parameters are listed in Table 1.

[0131] Artificial Neurons

[0132] Neural activation is the de facto activity in neuromorphic computing, which jointly integrates analog inputs and triggers outputs through nonlinear activation functions. Neural activity is a mathematical abstraction that only aims to capture certain features of real biological neurons. Several implementations of artificial neuronal circuits have been proposed in the literature. The neural activation functions in the originally proposed Hopfield neural networks have some restrictions in terms of linearity and monotonicity, and can be implemented using complex designs to ensure interference-free and leakage-free transient neural activity. Fortunately, in asymmetric Hopfield networks, such strict constraints are not required and simple digital comparators can be used, while the device mismatch, parasitic effects and instability issues of neuronal circuits are adaptively compensated by the synapses.

[0133] Therefore, as shown in FIG6(b), a neuron circuit can be realized by a transimpedance amplifier 90 implemented as an inverting operational amplifier (OpAmp) 92, which is cascaded to a comparator 94 with a zero voltage reference 96, a zero voltage maximum 98, and -Vdd 100 as Vmin to generate a negative signal for LSB inhibition of the synapse. The comparators are latched using a time-staggered phase clock, and the decision result (0 V or -Vdd) is sampled at the output 102 at the end of the read cycle Tr after mitigating transient effects and synchronizing the neurons, and their output is forward propagated in the pipeline. It is latched during the entire write cycle Tw and processed by the feedback circuit 66, see Figure 5b ). Note that the effective weight is normalized by the operational amplifier 92 and is equal to Wij,j>i=Rf / Sij,j>i, where Rf is the negative feedback resistor and Sij is the effective resistance of Mij and the series transistor.

[0134] Feedback Circuit

[0135] The online gradient descent algorithm is executed by a feedback circuit 66, which precisely regulates the synaptic adaptation process. The goal is to design and implement basic subtraction and multiplication operations in hardware. The ADC system is more complex than the equivalent learning-based DAC system and has a stronger application impact; however, its training circuit design is much simpler because D i (k) ,Ti (k) ,T j (k) It is a digital value that does not require modulation technology. i (k) -D i (k) ) is implemented by a digital subtractor, and the implementation of the feedback circuit 110 including the digital subtractor 112 is shown in FIG6(c). The subtraction result of each neuron (except the MSB) is simultaneously back-propagated to all its synapses ( Figure 6a ). The multiplication is called through the synaptic transistor as an AND logic gate and is controlled by e, while the desired digital output after attenuation is T i (k) The feedback is disconnected from the conversion path after training is completed, i.e., the error is reduced to below a predetermined threshold (E ≤ Ethreshold).

[0136] evaluate

[0137] In the following, an implementation of a four-bit ADC is discussed and evaluated in SPICE simulation (Cadence Virtuoso) using a 0.18 / μm CMOS process and a VTEAM memristor model. First, the learning algorithm is evaluated in terms of minimum mean square error and training time. Next, the circuit is evaluated statically and dynamically, and finally the power consumption is analyzed.

[0138] The functionality and robustness of this embodiment are fully tested under extreme conditions using MATLAB. The design parameters and constraints are listed in Table 1. In addition, the circuit variations and noise sources are also quantified and verified as shown in Table 2.

[0139] Table 1

[0140] Circuit parameters

[0141]

[0142] Table 2

[0143] Circuit Variation and Noise

[0144]

[0145] Reconfiguration

[0146] The online gradient descent algorithm demonstrates the basic deterministic functionality of the four-bit ADC during training. The learning rate is critical to the adaptive performance: it depends on the circuit parameters, write voltage, pulse time width, feedback resistor, current state, and the physical properties of the memristor device. The learning rate is:

[0147]

[0148] Where Δs is the change in the internal state of the memristor;

[0149]

[0150] Among them, K on / off Follow α on / off are constants describing the state evolution rate and its nonlinearity, V on / off is the voltage threshold, and f(s) is the window function that adds nonlinearity and state correlation during the state evolution. These parameters are suitable for Pt / HfO x / Hf / TiN RRAM device. The fitted learning rate can converge to the global minimum with high accuracy. The learning rate depends on the state and time.

[0151] refer to Figures 7a) to 7d) , are four graphs showing the training evaluation according to the present embodiment. Figure 7a ) shows the reconfiguration of synaptic weights during the training phase when VFS = 1.8V and fs = 100KSPS. Synapses are immediately trained for VFS = 0.9V and fs = 10MSPS and displayed in real time. Figure 7b ) shows the optimization of the LMS error function during training until a threshold is reached. Figure 7c ) shows the actual digital output Di (logic value) at three different time scales during the training process. After the training is completed, a periodic digital output will be obtained, corresponding to the analog input ramp. Finally, Figure 7d ) shows the results at three different time stamps during the training process by connecting the corresponding discrete analog values ​​of the teaching data set to the ideal DAC and comparing it with the actual output, obtaining the same steps after training is completed.

[0152] More specifically, Figure 7a ) shows that two voltages with different full-scale ranges (VDD and VDD / 2) and different sampling frequencies (fs and 100f s ) in real-time synaptic resistance values ​​for the sawtooth training dataset. After about 4000 training samples, the error may be below the threshold E at a 0.1MSPS conversion rate equal to 40ms training time. threshold , and the network converges from a random initial state to a stable state. The threshold E threshold 50% of the digital output codes (8 codes for 4 bits) that are determined to be valid classification errors in the total number of training samples are shown in Table 1. In addition, when the full-scale voltage becomes V DD / 2 and the sampling frequency becomes 100f s, the system converges to a new steady-state mode that quantizes 0.9V full scale at a 10MSPS sampling rate. In each case, the network was reconfigured to operate correctly under different specifications, such as Figure 7a ) with different synaptic weights. During training, the minimum mean square error (5) optimization is performed toward its gradient descent as shown in Figure 7b ). In the same context, Figure 7c ) shows the adaptation of the neural activity representing the digital output bits at three different timestamps for the initial state before training (samples 0-15), coarse-grained training (i.e., the error is slightly higher than E threshold The digital output can be connected back-to-back with an ideal 4-bit DAC and converted into a discrete analog signal, accurately reproducing the current state of the ADC, such as Figure 7d ), three timestamps are displayed simultaneously.

[0153] Self-calibration

[0154] As mentioned above, the accuracy of the ADC depends on many key factors, including process variations, frequency-related variations, device mismatch, device wear, parasitic effects, deviations, poles, gain, and offset errors. Table 2 lists the degree of variation of these effects. The process variation parameters of the memristor are selected, randomly generated with a normal distribution, and incorporated into the VTEAM model with a variance of approximately 10% to cover a large reliability range. The transistor parameters, such as VW, W / L and VT Vi in Table 1, are selected to ensure a globally optimal solution even under such extreme conditions. Figure 7a) to Figure 7d) In , it is shown that the training algorithm of the present embodiment can tolerate such changes over time and compensate by using different synaptic weights.

[0155] Reference now Figure 8a) to Figure 8d) , shows a static conversion evaluation showing the efficiency of the training algorithm in calibrating the mismatch (a) differential and (b) integral nonlinearity of the ADC at three different time stamps in response to a DC input voltage ramp. Figure 8c ) is a dynamic conversion evaluation showing the efficiency of the training algorithm in terms of noise tolerance and distortion mitigation at three different times through the coherent Fast Fourier Transform of the ADC output in response to a sinusoidal input signal with a frequency of 44kHz, stamped during the training process using the ENOB calculation, and Figure 8d ) Power evaluation of the network, showing power optimization during training.

[0156] More specifically, if Figure 8a )and Figure 8b) is shown in FIG. 1 , which statically evaluates how the ADC of this embodiment responds to a DC ramp signal at three given time stamps. Figure 7d ) is a subset of the DC ramp input that can be statically evaluated at the above timestamps. Therefore, the difference between two adjacent digital output decimal codes in the actual ADC output is the differential nonlinearity (DNL). Similarly, the difference between the actual ADC output and the ideal step for each digital input code is the integral nonlinearity (INL). The DNL of the last code is undefined. The results for maximum DNL and INL are shown in Figure 8a )and Figure 8b ). Before training, the ADC is completely nonlinear and non-monotonic, with some codes missing. Therefore, INL = 8LSB, and DNL = 5LSB. An improvement in performance can be seen at the second timestamp (2ms ~ 200 samples), where the ADC behaves monotonic. However, it is still inaccurate (INL = 2LSB, DNL = 2LSB). After training is complete (40ms), the ADC is almost fully calibrated, monotonic, and accurate: INL = 0.4LSB, and DNL = 0.5LSB.

[0157] In addition, as shown in Table II, parasitic effects such as capacitance and inductance, which are the main factors in high-frequency ADC accuracy, have been adaptively captured by 10MSPS over a longer training time.

[0158] Noise resistance

[0159] In existing ADCs, calibration mechanisms can be used to compensate for device mismatches and process imperfections, but noise inevitably degrades performance. It is also not easy to capture noise during design. However, we believe that inherent noise has a relatively small impact on analog circuit performance: adaptive intelligent systems using machine learning techniques are inherently resistant to noise because noise is a key factor in designing to address it.

[0160] Noise sources include intrinsic thermal noise from feedback resistors, memristors, and transistors, in addition to quantization noise, jitter, comparator ambiguity, input reference noise, random offset, nonlinear distortion, training label sampling noise, memristor switching randomness, and frequency-dependent noise. These noise sources are listed in Table II.

[0161] ADC nonlinear function V responding to voltage input vi = Acos(ωt) out =f(vi), where A is the amplitude and ω is the frequency, which can be qualitatively described as:

[0162]

[0163] where ao is a DC constant, a1 is a small signal gain constant, and a2 is a distortion constant. Hence, due to nonlinear effects, we get harmonic distortion, which appears as spectral spurs at multiples of the sampling frequency and degrades the SNDR and ADC accuracy. We show that the algorithm is able to adaptively mitigate nonlinear distortion and tolerate noise by estimating the f(·) function.

[0164] The ADC is dynamically evaluated and analyzed at three given time stamps in response to a 44kHz sinusoidal input signal that meets the Nyquist condition. input ≤fs / 2, and a coherent Fast Fourier Transform (FFT) using a Hamming window and a prime number of periods distributed over 5000 samples is sufficient to perform a reliable FFT without collisions and data loss. Figure 7c ) shows the FFT of the signal and distortion power as a function of frequency, with each timestamp displayed in a different color.

[0165]

[0166] The ADC cut-off frequency fT,max is limited by the high to low memristor impedance ratio. Figure 7c ) shows that with the progress of training, the harmonic distortion is alleviated, the fundamental power is increased, and the SNDR and ENOB are improved.

[0167] Synaptic fluctuations due to noise and sources of variation are mitigated by the switching nonlinearities and thresholds of the memristors. However, the gradient descent algorithm continues to capture and average the random dynamics and timing uncertainty (jitter) of the sampled inputs. Comparison with noisy labels can enhance the network's resistance to overfitting and achieve reliable generalization performance. In the same case, the stochasticity of memristor switching is characterized by a Poisson process, listed in Table II, and incorporated into the VTEAM model as a probabilistic transition in the threshold. Together with quantization noise or jitter, this helps the network converge to the global minimum and improve ENOB, in some cases breaking through the thermal noise limit. This well-known phenomenon is called stochastic resonance. It has been reported in the past in artificial neural networks and memristors. Note that smaller learning rates will better overcome real-time variations; however, this will come at the cost of training time. In previous work referenced above, Monte-Carlo simulations were used to perform a large-scale analysis of the effective number of stable resistance levels resulting from statistically correlated changes in resistance values ​​as a function of noise margin (NM). Additionally, the impact on ENOB was determined, with typical results (in 38% of the cases) being 64 resistance levels, ~3% NM, and ~3.7 ENOB.

[0168] Power Optimization

[0169] As described above, an equivalence is found between the Hopfield-like energy function of the network given by equation (4) and the cost function for solving the conversion optimization given by equation (6). When the synaptic weights are configured to ensure that each analog input is correctly mapped to its corresponding digital output, the cost function will reach its minimum, the lower bound of the quantization error. In Figure 6(b), we show that when the network is successfully trained to configure the ADC, the error function given by equation (8) reaches a global minimum. Therefore, power consumption is optimized during the training process until it reaches a minimum at the end of training. When the network is configured in an ADC manner, the optimal energy state of the network according to the present embodiment is achieved. Therefore, the power consumption of the entire network will be analyzed and attributed to three sources:

[0170] 1. Neural integration power: The power dissipated in the operational amplifier feedback resistor is:

[0171]

[0172] As described in equation (3), this function solves the ADC quantization problem after training each neuron. The total neural integration capability of all neurons is

[0173]

[0174] 2. Neural activation power: Power consumed in comparators and operational amplifiers at the sampling frequency. The power supply is constant and negligible: Pacti = 3 μW in 0.18 / μm CMOS process in fT. The total activation power of all neurons is:

[0175]

[0176] 3. Synaptic power: The power consumption of synapses, including both reconfigurable and fixed synapses per neuron, is:

[0177]

[0178] The total power consumption of the synapse is Note that the effective transistor resistance in series with the memristor is also taken into account. Therefore, the total power consumption is the sum of the three supplies averaged over a full-scale ramp with 2N samples (epochs) during training, as Figure 7d ). Each point on the horizontal axis represents a full-scale ramp, and each corresponding value on the vertical axis represents the average of the total dissipated power. After training is complete and the network is configured as an ADC, the average synaptic power on the full-scale ramp is half of the maximum power consumption, while the neural integrated power is minimized. This balance achieves optimal power consumption.

[0179] Note that the dynamic power consumption due to updating the memristor during the training phase has not yet been determined and is not considered as switching power according to the FOM definition in equation (1). We ignore the power consumption of the feedback because after training, the feedback is disconnected and the network maintains a minimum power consumption level during switching. This power is assumed to be relatively low because the area of ​​the training feedback is small, the training time is short, and the ratio between training and switching cycles is small over the lifetime of the converter even at high application configuration rates.

[0180] generally

[0181] In the broader context of the results presented in this paper, we discuss the potential for breaking the speed-power-accuracy tradeoff. Additionally, we discuss the scaling issues of the architecture of this embodiment.

[0182] Breaking the speed-power-accuracy tradeoff.

[0183] Reference now Figure 9a) to Figure 9d) , showing a breakthrough in the speed-power-accuracy tradeoff. Figure 9a ) shows the speed-accuracy tradeoff achieved by obtaining the maximum ENOB regardless of fs after training is completed. Figure 9b ) shows the speed-power tradeoff after training is complete by obtaining the minimum P, regardless of fs. The power consumption that varies with frequency is negligible. Fig.9c ) shows the accuracy-power tradeoff after training is complete by achieving maximum ENOB and minimum P. Finally, Figure 9d ) shows the trained FOM dynamic optimization. More specifically, after demonstrating the dynamic mechanism of the trainable ADC, we study the real-time training of a general-purpose application ADC. For each selected fs within the bandwidth fT, the ADC is trained by a training dataset with the same specifications and achieves the best ENOB, such as Figure 9a ). The maximum ENOB (~3.7) is asymptotically limited by the inherent quantization noise. Similarly, the power consumption is dynamically optimized for each fs to achieve the minimum power consumption of the network, as shown in Figure 9b ). The power dissipation in resistors has a greater impact on the overall power consumption than the power dissipation that depends on frequency (e.g., capacitors). At the same time, and as we have shown, the equivalence between the quantization cost function (6) and the energy function (4) after optimizing the error function (8) leads to the joint optimization of the ENOB and power consumption of the training samples, as Fig.9c ) as shown.

[0184] Interestingly, the collective optimization of the proposed architecture breaks through the speed-power-accuracy tradeoff and dynamically expands the FOM to achieve a cutting-edge value of 8.25fJ / conv, as Figure 9d )and Figure 4 The versatility of the proposed architecture in terms of reconfiguration, mismatch self-calibration, noise tolerance, and power optimization can be achieved using a simple and minimalistic design with a reconfigurable single channel. Furthermore, the proposed architecture exploits the resistive parallel computing of memristors to achieve high speed, in addition to analog non-volatility, enabling standard digital ML algorithms to intelligently and precisely adjust their conductivity in situ, achieving high accuracy.

[0185] The simple design reduces power consumption, thus achieving a cost-effective ADC. All these features, when combined with the SAR architecture, pipeline architecture, and online trainable mechanism, enable a universal application architecture.

[0186] However, scaling the proposed architecture is challenging. When increasing the network size, the number of neurons, synapses, and feedback will increase quadratically. Therefore, this will significantly increase the area and power consumption as shown in Table III. Due to the continuous nature of the proposed ADC architecture, the number of neurons requires longer conversion times due to the propagation time, settling time, and decision time of each neuron. Therefore, to eliminate signal aliasing, the maximum Nyquist sampling frequency will unfortunately be limited as shown in Table III.

[0187] Other issues in scaling are the required ratio of high and low resistance states of the synaptic weights, the number of resistance levels, the cutoff frequency, and the endurance. The maximum number of bits was calculated in previous work and was four bits for the memristive devices being tested, but devices with higher HRS / LRS can be achieved. Moreover, it is shown here that device-dependent properties can be compensated by extending the training time to obtain a maximum ENOB, which is equal to (N-3) bits regardless of the switching speed. Overall, since the optimal ENOB is achieved, the FOM still improves with increasing the number of bits, as shown in Table III. Moreover, in advanced CMOS technology nodes, the FOM may be improved due to lower power consumption and higher sampling rates. These findings show that the proposed architecture is scalable both conceptually and practically even in the presence of the above-mentioned scaling issues.

[0188] This embodiment can demonstrate a real-time trainable ADC architecture for general-purpose applications that breaks the speed-power-accuracy trade-off. Inspired by the analogy between mixed-signal circuits and neuromorphic paradigms, we exploit the intelligent properties of artificial neural networks and propose a pipelined SAR-style neural network architecture ADC that is trained online by a supervised ML algorithm.

[0189] The network of this embodiment shares the Hopfield energy model, and we show the equivalence between the energy function and the conversion cost function and the training error function after training. The neural network is implemented by a hybrid CMOS memristor circuit design. The trainable mechanism successfully demonstrates the collective properties of the network when reconfigured to multiple full-scale voltages and frequencies, mismatch self-calibration, noise tolerance, stochastic resonance, power optimization, and dynamic scaling of FOM. We believe that the ADC of this embodiment can constitute a milestone of promising results for large-scale architectures and emerging real-time adaptive applications of data converters in various conditions such as wearable devices and automotive applications.

[0190] Table 3

[0191] Scalability Assessment

[0192]

[0193] It is expected that many related kinds of neural networks and artificial neural networks as well as ADC devices, memristors and memristor-like components will be developed during the life of the patent application, and the scope of the corresponding term is intended to include all such new technologies.

[0194] The terms "comprising", "including", "including", "containing", "having" and their conjugated words mean "including but not limited to".

[0195] As used herein, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise.

[0196] It should be understood that certain features of the invention described in the context of separate embodiments for clarity may also be provided in combination in a single embodiment. Conversely, various features of the invention described in the context of a single embodiment for brevity may also be provided individually or in any suitable sub-combination or in any other described embodiment of the invention as appropriate. Certain features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiment cannot function without those elements.

[0197] Although the present invention has been described in conjunction with specific embodiments of the present invention, it is apparent that many substitutions, modifications and variations will be apparent to those skilled in the art. Therefore, it is intended to cover all such substitutions, modifications and variations that fall within the spirit and broad scope of the appended claims.

[0198] All publications, patents, and patent applications mentioned in this specification are incorporated herein by reference in their entirety, to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application should not be construed as an admission that the reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.

Claims

1. An analog-to-digital conversion device, comprising: An input terminal, used to receive an analog input signal; a plurality of output terminals for outputting a plurality of parallel bits of a digital signal representing the analog input signal; and A trainable neural network layer, the neural network layer comprising a plurality of connections between each of the plurality of output terminals, wherein each connection has a weight, and the weight is adjustable for training, wherein the connection comprises a plurality of adaptive synapses to respectively provide the adjustable weights, and each adaptive synapse is provided with its own weight, and each output bit is a comparison result of a weighted sum from the plurality of output bits.

2. The device of claim 1, wherein: Each of the plurality of adaptive synapses comprises a memristor, and the memristor is provided with a respective weight.

3. The device of claim 2, wherein: The apparatus also includes a training unit having a training data set input, connected to the plurality of output bits, and configured to adjust each of the plurality of adaptive synapses until the plurality of outputs for a given input corresponds to a training data set.

4. The device of claim 3, wherein: The training data set is used in conjunction with a predetermined maximum voltage and a predetermined number of the plurality of output bits.

5. The device of claim 3, wherein: The apparatus is configured to perform the adjustment by using online gradient descent.

6. The device of claim 5, wherein: The online gradient descent contains the equation for a number of iterations k: ； Where η is the learning rate, Vi (k) is in k th A single empirical sample is provided to the input at the iteration, and the equation: 。 7. The device of claim 3, wherein: The adjustment includes minimizing a training error function and an energy cost function.

8. The device according to any one of claims 3 to 7, wherein: The adjustment includes minimizing a quality factor, wherein: ； Where P is the power consumption during conversion, fs is the sampling frequency, and; ； Where SNDR is the signal-to-noise ratio.

9. An analog-to-digital conversion method, comprising the steps of: Receiving an analog input signal at an input terminal; Outputting a plurality of parallel bits of a digital signal representing the analog input signal at a plurality of output terminals; providing a plurality of connections between each of the plurality of output terminals; providing an adjustable weight to each connection, thereby providing a trainable neural network connecting the plurality of output terminals, wherein the plurality of connections form a neural network, and providing the adjustable weights comprises adapting a synapse of the neural network; and Each adaptive synaptic weight is set respectively so that each output bit is a comparison result of a weighted sum from the plurality of output bits.

10. The method of claim 9, wherein: Each of the plurality of adaptive synapses comprises a memristor, and the memristor is provided with a respective weight.

11. The method of claim 9, wherein: The method includes setting the respective weights using training, the training including adjusting each of the plurality of adaptive synapses until a plurality of outputs for a given input corresponds to a training data set.

12. The method of claim 11, wherein: The training data set is used in conjunction with a predetermined maximum voltage and a predetermined number of the plurality of output bits.

13. The method of claim 12, wherein: The method includes performing the adjustment by using online gradient descent.

14. The method of claim 13, wherein: The online gradient descent contains the equation for a number of iterations k: ； Where η is the learning rate, Vi (k) is in k th A single empirical sample is provided to the input at the iteration, and the equation: 。 15. The method of claim 11, wherein: The adjustment includes minimizing a training error function and an energy cost function.

16. The method according to any one of claims 11 to 15, wherein: The adjustment includes minimizing a quality factor, wherein: ； Where P is the power consumption during conversion, fs is the sampling frequency, and; ； Where SNDR is the signal-to-noise ratio.

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