Semiconductor device and method of forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The semiconductor device has a first isolation trench, a second isolation trench, and a third isolation trench with different opening sizes, and the insulating materials filled in the first isolation trench, the second isolation trench, and the third isolation trench are correspondingly adjusted according to the different opening sizes. In this way, the diversity of the trench isolation structure in the semiconductor device is realized, so that different trench isolation structures can be correspondingly adopted according to different isolation regions, improving the application flexibility of the trench isolation structure; moreover, it is also beneficial to simplify the preparation difficulty of each trench isolation structure and improve the production efficiency of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] With the continuous reduction of the size of semiconductor devices and the gradual increase in the integration degree of semiconductor devices, an isolation structure buried in a substrate, namely a trench isolation structure, is introduced. The trench isolation structure has a high isolation effect and is beneficial to reducing the spacing size between device units.

[0003] For example, a trench isolation structure is usually formed in a substrate to define an active region, and then various device units (such as transistors) can be further fabricated based on the defined active region. At this time, the device units in different active regions can be separated from each other by using the trench isolation structure to avoid interference between different device units.

[0004] Currently, multiple trench isolation structures are usually provided in semiconductor devices. However, the existing trench isolation structures usually have a relatively simple structure, and even if they are applied to different isolation regions, their structures are usually the same. Summary of the Invention

[0005] The purpose of the present invention is to provide a semiconductor device to apply trench isolation structures with diversification to the semiconductor device.

[0006] To solve the above technical problems, the present invention provides a semiconductor device, including:

[0007] A substrate, in which a first isolation trench, a second isolation trench, a third isolation trench and an electrical conduction layer with sequentially increasing opening sizes are formed; wherein,

[0008] The first isolation trench is filled with a first insulating material;

[0009] The second isolation trench is filled with the first insulating material and at least part of the electrical conduction layer; and,

[0010] The third isolation trench is sequentially filled with the first insulating material, a second insulating material and a third insulating material.

[0011] Based on the semiconductor device as described above, the present invention further provides a method for forming a semiconductor device, including:

[0012] Providing a substrate, and forming a first isolation trench, a second isolation trench and a third isolation trench with sequentially increasing opening sizes in the substrate;

[0013] Form a first insulating material in the first isolation trench, the second isolation trench, and the third isolation trench, wherein the first insulating material fills the first isolation trench, and the first insulating material covers the inner walls of the second isolation trench and the third isolation trench;

[0014] Form a second insulating material in the second isolation trench and the third isolation trench, and form a third insulating material in the third isolation trench; and,

[0015] Form an electrically conductive layer in the substrate, and the electrically conductive layer is at least partially formed in the second isolation trench.

[0016] In the semiconductor device provided by the present invention, based on the first isolation trench, the second isolation trench, and the third isolation trench with different opening sizes, the insulating materials filled in the first isolation trench, the second isolation trench, and the third isolation trench are correspondingly adjusted. In this way, the diversity of the trench isolation structure in the semiconductor device is realized, so that different trench isolation structures can be adopted according to different isolation regions, improving the application flexibility of the trench isolation structure. For example, for the trench isolation structure that also accommodates an electrically conductive layer, the second trench isolation structure with a larger opening size can be used to accommodate the electrically conductive layer. In addition, for the isolation trenches with different opening sizes provided by the present invention, by correspondingly adjusting their insulating materials, the preparation difficulty of each trench isolation structure can be further simplified.

[0017] In an optional solution, a gap can also be formed in the second trench isolation structure, and accordingly, the parasitic capacitance between the electrically conductive layer and the substrate can be further improved.

[0018] In a further solution, an ion implantation region can also be formed in the part of the substrate adjacent to the first isolation trench and the second isolation trench to improve the leakage current phenomenon of the semiconductor device by using the ion implantation region. Description of the Drawings

[0019] Figure 1a It is a schematic structural diagram of the semiconductor device in the first embodiment of the present invention;

[0020] Figure 1b It is a schematic structural diagram of the semiconductor device in the second embodiment of the present invention;

[0021] Figure 1c It is a schematic structural diagram of the semiconductor device in the third embodiment of the present invention;

[0022] Figure 1d It is a schematic structural diagram of the semiconductor device in the fourth embodiment of the present invention;

[0023] Figure 2Top view of a semiconductor device in an embodiment of the present invention;

[0024] Figure 3 Flow schematic diagram of a method for forming a semiconductor device in an embodiment of the present invention;

[0025] Figures 4a - 4g Schematic structural diagram of a method for forming a semiconductor device in an embodiment of the present invention during its preparation process.

[0026] Among them, the reference numerals are as follows:

[0027] 100 - Substrate;

[0028] 110 - First isolation trench;

[0029] 120 - Second isolation trench;

[0030] 121 - Gap;

[0031] 130 - Third isolation trench;

[0032] 210 - First insulating material;

[0033] 220 - Second insulating material;

[0034] 230 - Third insulating material;

[0035] 300 - Word line;

[0036] 300a - Word line trench;

[0037] 300b - Cover layer;

[0038] 400 - Mask layer;

[0039] AA - Active region;

[0040] AA1 - First active region;

[0041] AA2 - Second active region;

[0042] AA3 - Third active region;

[0043] D - Predetermined thickness value;

[0044] H1 - First height position;

[0045] H2 - Second height position. Detailed implementation manners

[0046] The following further describes in detail the semiconductor device and its forming method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0047] Embodiment 1

[0048] Figure 1a is a schematic structural diagram of the semiconductor device in Embodiment 1 of the present invention. As Figure 1a shown, the semiconductor structure in this embodiment includes: a first isolation trench 110, a second isolation trench 120, and a third isolation trench 130 with sequentially increasing opening sizes. Specifically, the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 are all formed in a substrate 100.

[0049] As Figure 1a shown, in this embodiment, the first isolation trench 110 is filled with a first insulating material 210 to form a first trench isolation structure. The second isolation trench 120 is sequentially filled with the first insulating material 210 and a second insulating material 220 to form a second trench isolation structure. And the third isolation trench 130 is sequentially filled with the first insulating material 210, the second insulating material 220, and a third insulating material 230 to form a third trench isolation structure.

[0050] Among them, the first insulating material 210 includes, for example, silicon oxide, the second insulating material 220 includes, for example, silicon nitride, and the third insulating material 230 includes, for example, silicon oxide.

[0051] That is, based on the different opening sizes between the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130, the insulating materials filled in the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 can be further adjusted, and then the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure with different structures are formed. At this time, different trench isolation structures can be correspondingly set based on different isolation regions in the semiconductor device, realizing the application flexibility of the trench isolation structure, and also being beneficial to reducing the preparation difficulty of the trench isolation structure in the semiconductor device.

[0052] Continuing to refer to Figure 1a shown, in the second isolation trench 120, the first insulating material 210 covers the inner wall of the second isolation trench 120 and can define a gap 121.

[0053] In this embodiment, the opening size of the second isolation trench 120 gradually decreases from top to bottom. When the first insulating material 210 covers the inner wall of the second isolation trench 120, the first insulating material 210 covering the trench sidewalls can gradually approach from top to bottom, thereby defining the gap 121 at the bottom of the second isolation trench 120. For example, the second isolation trench 120 has opposite first sidewall and second sidewall, and at this time, the portions of the first insulating material 210 covering the first sidewall and the second sidewall gradually approach from top to bottom, thereby forming the gap 121.

[0054] Moreover, in the second isolation trench 120, the top opening of the gap 121 can be directly closed by the first insulating material 210, and the second insulating material 220 is formed above the gap 121 and does not contact the gap 121. Alternatively, as in this embodiment, the top opening of the gap 121 can also be closed by the second insulating material 220 located above the gap 121. In this way, in the second isolation trench 120, the gap 121 can be defined by the insulating material.

[0055] As described above, the opening size of the second isolation trench 120 in this embodiment gradually decreases from top to bottom. Further, the slope of the trench sidewall below the gap 121 in the second isolation trench 120 can be made greater than or equal to the slope of the trench sidewall above the gap 121, that is, in the second isolation trench 120, the trench sidewall near the bottom is more vertical than the trench sidewall near the top. In this way, when depositing the first insulating material 210, the first insulating material 210 will be more likely to form the gap 121 at the bottom of the second isolation trench 120.

[0056] Continue to refer to Figure 1a As shown, in the third isolation trench 130, the first insulating material 210 and the second insulating material 220 both conformally cover the sidewall and the bottom wall of the third isolation trench 130, and the third insulating material 230 fills the space defined by the second insulating material 220 in the third isolation trench 130.

[0057] Further, the first insulating material 210 in the third isolation trench 130 has a predetermined thickness value D in the direction perpendicular to the trench sidewall. The maximum opening size of the first isolation trench 110 is less than or equal to 2 times the predetermined thickness value (2*D), and the maximum opening size of the second isolation trench 120 is greater than 2 times the predetermined thickness value (2*D); and the maximum opening size of the third isolation trench 130 is, for example, greater than or equal to 3 times the predetermined thickness value (3*D).

[0058] Specifically, since the maximum opening size of the first isolation trench 110 is less than or equal to twice the predetermined thickness value, based on this, when performing the deposition process to deposit the first insulating material 210 in the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 simultaneously, the first insulating material 210 deposited in the first isolation trench 110 can fill the first isolation trench 110, and the first insulating material 210 deposited in the second isolation trench 120 and the third isolation trench 130 can cover the inner walls of the second isolation trench 120 and the third isolation trench 130.

[0059] In this embodiment, the top opening size of the second isolation trench 120 is greater than twice the predetermined thickness value (2*D), and the bottom opening size of the second isolation trench 120 can be further close to twice the predetermined thickness value (for example, equal to twice the predetermined thickness value; or slightly less than twice the predetermined thickness value; or slightly greater than twice the predetermined thickness value). At this time, the first insulating materials 210 in the second isolation trench 120 are prone to approach each other at the bottom of the second isolation trench 120 and define the gap 121.

[0060] Continue to refer to Figure 1a As shown, in this embodiment, the depths of the second isolation trench 120 and the third isolation trench 130 are both greater than the depth of the first isolation trench 110. Specifically, the depth position H2 where the second isolation trench 120 and the third isolation trench 130 extend in the substrate 100 is lower than the depth position H1 where the first isolation trench 110 extends in the substrate 100.

[0061] Moreover, the bottom of the gap 121 in the second isolation trench 120 is further lower than the bottom of the first isolation trench 110. In this embodiment, for the gap 121 in the second isolation trench 120, its bottom is between the first height position H1 and the second height position H2, and its top is higher than the first height position H1. Of course, in other embodiments, the gap 121 in the second isolation trench 120 can also be completely between the first height position H1 and the second height position H2 (that is, the top of the gap 121 is lower than the first height position H1).

[0062] It should be noted that in this embodiment, the opening size of the second isolation trench 120 gradually decreases from top to bottom, the bottom size of the second isolation trench 120 is close to twice the predetermined thickness value, and the depth of the second isolation trench 120 is relatively large, so that the gap 121 is extremely easy to form, and the formed gap 121 can be close to the bottom of the second isolation trench 120.

[0063] Continue to refer to Figure 1aAs shown, the semiconductor device further includes, for example, an electrically conductive layer buried in the substrate 100 (the electrically conductive layer is, for example, the word line 300 in a memory). The electrically conductive layer is at least partially formed in the second isolation trench 120 and is located above at least a part of the second insulating material 220 in the second isolation trench 120. Then, the electrically conductive layer is correspondingly located above the gap 121. In this embodiment, since the second isolation trench 120 has a relatively large depth, the isolation performance of the formed second trench isolation structure for the electrically conductive layer can be improved. In addition, since a gap 121 is also formed in the second trench isolation structure, it is also beneficial to improve the parasitic capacitance between the electrically conductive layer and the substrate 100.

[0064] It should be recognized that the isolation trenches with different opening sizes as described above can be applied to various semiconductor devices. In this embodiment, for example, the semiconductor device is taken as a memory for explanation.

[0065] Figure 2 This is a top view of the semiconductor device in an embodiment of the present invention. As Figure 2 shown, the semiconductor device is a memory, for example, a dynamic random access memory (DRAM). Among them, the memory has a plurality of active regions AA, and each active region AA extends along the first direction (Z direction).

[0066] In this embodiment, the second isolation trenches 120 are spaced between the active regions AA closest to each other in the first direction (Z direction). For example, Figure 2 in the shown memory, between the first active region AA1 and the third active region AA3 closest to each other in the first direction (Z direction), they are separated from each other by the second isolation trench 120.

[0067] In addition, the first isolation trenches 110 are spaced between the active regions AA closest to each other in the second direction (X direction). Among them, the second direction (X direction) intersects with the first direction (Z direction). For example, Figure 2 in the shown memory, between the first active region AA1 and the second active region AA2 closest to each other in the second direction (X direction), they are separated from each other by the first isolation trench 110; and between the second active region AA2 and the third active region AA3 closest to each other in the second direction (X direction), they can also be separated from each other by the first isolation trench 110.

[0068] It can be understood that in this embodiment, Figure 1a the structure diagram of aa’ is the cross-sectional schematic diagram in the aa’ direction of Figure 2 Figure 1a ​The structural diagram of bb’ in is Figure 2 the schematic cross-sectional view in the bb’ direction in, and Figure 2 the top view of the cc’ part not shown in.

[0069] Continuing to combine Figure 1a and Figure 2 as shown, the memory further includes a word line 300, the word line 300 is buried in the substrate 100 and extends along the second direction (X direction) so that the word line 300 intersects with the corresponding active region AA, and the word line 300 also has a part formed in the isolation region.

[0070] In this embodiment, at least part of the word line 300 is formed in the second isolation trench 120 and constitutes a first word line part, and the part of the word line 300 formed in the active region AA constitutes a second word line part. Further, at least part of the first word line part is located above the second insulating material 220 in the second isolation trench 120.

[0071] That is, in the second isolation trench 120, the first insulating material 210 covers the side wall of the second isolation trench 120 and defines the gap 121, the second insulating material 220 closes the top opening of the gap 121 and is located above the gap 121, and at least part of the first word line part is located above the second insulating material 220 in the second isolation trench 120, then the corresponding first word line part is located above the gap 121.

[0072] It should be noted that in this embodiment Figure 1a it is schematically shown that the second insulating material 220 in the second isolation trench 120 is located between the first word line part and the gap 121. However, when the top opening size of the second isolation trench 120 is relatively large, there may also be a second insulating material in the region near the top of the second isolation trench 120, and the second insulating material near the top of the second isolation trench 120 is located between the first word line part and the first insulating material 210.

[0073] It should also be noted that in this embodiment, when the semiconductor device is a memory, different trench isolation structures can be adopted in different isolation regions respectively. For example, between the active regions AA closest to each other in the second direction (X direction), the second trench isolation structure with a larger opening size relative to the first trench isolation structure can be used to separate them from each other. At this time, a part of the word line 300 can be accommodated in the second trench isolation structure, so as to avoid the contact between the first word line part formed in the second trench isolation structure and the adjacent active region AA. Moreover, in this embodiment, the second trench isolation structure can also have a larger depth, thereby improving the isolation effect between the first word line part formed in the second trench isolation structure and the adjacent active region AA. In addition, a gap 121 is also formed in the second trench isolation structure, which can effectively improve the parasitic capacitance between the word line 300 and the substrate 100 and improve the performance of the memory.

[0074] In this embodiment, the word line 300 is specifically formed in a word line trench, and the top of the word line 300 is lower than the top of the word line trench. And, a covering layer 300b is filled in the part of the word line trench above the word line 300 to cover the word line 300. Among them, the material of the covering layer 300b includes, for example, silicon nitride.

[0075] Furthermore, the semiconductor device also has a device unit area and a peripheral area located outside the device unit area. And, the third isolation trench 130 can be provided between the device unit area and the peripheral area, that is, the device unit area and the peripheral area can be separated from each other by the third isolation trench 130 with a larger opening size to improve the isolation effect between the device unit area and the peripheral area.

[0076] In this embodiment, the device unit area is the storage area of the memory (a plurality of the active regions AA are distributed in the storage area), and the peripheral area (not shown in the figure) is located outside the storage area.

[0077] In an optional solution, an ion implantation area (not shown in the figure) is also formed in the part of the substrate 100 adjacent to the first isolation trench 110 and the second isolation trench 120 to improve the leakage current phenomenon of the semiconductor device by using the ion implantation area. That is, the ion implantation area is formed in the peripheral substrate 100 of the first isolation trench 110 and the second isolation trench 120. In this embodiment, an ion implantation area can also be formed in the part of the substrate 100 adjacent to the third isolation trench 130.

[0078] Specifically, the insulating material in the isolation trench is usually prone to adsorbing charges, and the charged insulating material generates an electric field, causing the substrate near the isolation trench to be inverted under the action of the electric field, thereby causing a leakage current phenomenon. Based on this, an ion implantation region is formed in the substrate 100 near the isolation trench, so that the portion of the substrate with the ion implantation region formed therein is less likely to be inverted, thus suppressing the leakage current phenomenon.

[0079] Furthermore, the substrate 100 and the ion implantation region can both be of the first conduction type, and the ion doping concentration of the ion implantation region is higher than that of the substrate 100. That is, the substrate 100 and the ion implantation region are, for example, both P-type or both N-type.

[0080] In a specific embodiment, transistors of the second conduction type are formed, for example, in the region of the substrate 100 adjacent to the first isolation trench 110 and / or the second isolation trench 120. At this time, the first isolation trench 110 and / or the second isolation trench 120 are prone to capturing charges of the second conduction type, and when there is no ion implantation region provided, it is likely to cause the adjacent substrate to be inverted.

[0081] Hereinafter, taking the semiconductor device in this embodiment as a memory as an example for further explanation. In this embodiment, a storage transistor is formed in the active region AA, and the first isolation trench 110 and the second isolation trench 120 are formed around the active region AA. The first isolation trench 110 filled with an insulating material further constitutes a first trench isolation structure, and the second isolation trench 120 filled with an insulating material further constitutes a second trench isolation structure.

[0082] In this embodiment, the substrate 100 is of the first conduction type, and the storage transistor formed in the active region AA is of the second conduction type. Based on this, the ion implantation region formed around the first isolation trench 110 and the second isolation trench 120 can be of the first conduction type. In this embodiment, the first conduction type is, for example, P-type, the second conduction type is, for example, N-type, and the doping ions in the ion implantation region can include boron ions.

[0083] Specifically, when there is no ion implantation region around the first isolation trench 110 and the second isolation trench 120, the charges of the second conduction type of the storage transistor of the second conduction type are easily captured by the first trench isolation structure and the second trench isolation structure, making the first trench isolation structure and the second trench isolation structure present as the second conduction type. At this time, under the action of the trench isolation structure of the second conduction type, it is easy to cause the first conduction type substrate adjacent to it to be inverted, thereby triggering a leakage current phenomenon.

[0084] However, in this embodiment, an ion implantation region is provided around the first isolation trench 110 and the second isolation trench 120. In this way, even though the first trench isolation structure and the second trench isolation structure may capture charges, since the ion implantation region is formed in the substrate adjacent to the first isolation trench 110 and the second isolation trench 120, the substrate in this region is not easily inverted, that is, the inversion of the substrate near the first isolation trench 110 and the second isolation trench 120 is suppressed, thereby alleviating the leakage current phenomenon of the semiconductor device.

[0085] Embodiment Two

[0086] The difference from Embodiment One is that in this embodiment, no gap is formed in the first insulating material of the second isolation trench. That is, the first insulating material densely covers the inner wall of the second isolation trench.

[0087] Figure 1b As shown in the structural schematic diagram of the semiconductor device in Embodiment Two of the present invention, Figure 1b as shown, in the second isolation trench 120, the first insulating material 210 covers the bottom wall and the side wall of the second isolation trench 120, and the second insulating material 220 is formed on the first insulating material 210.

[0088] Wherein, the first insulating material 210 in the third isolation trench 130 has a predetermined thickness value D in the direction perpendicular to the side wall of the trench. It can be understood that the predetermined thickness value D of the first insulating material is the deposition thickness value when depositing the first insulating material. Therefore, the thickness value of the first insulating material 210 in the second isolation trench 120 in the direction perpendicular to the side wall of the trench is also close to or equal to the predetermined thickness value D. And, the height value of the first insulating material 210 in the second isolation trench 120 covering the bottom wall of the second isolation trench is also less than 2 times the predetermined thickness value (for example, the height value is close to or equal to the predetermined thickness value D).

[0089] Continue to refer to Figure 1b as shown, in this embodiment, the part of the electrically conductive layer (for example, the word line 300 in the memory) formed in the second isolation trench 120 is also located above at least part of the second insulating material 220.

[0090] Embodiment Three

[0091] The difference from Embodiment Two is that in this embodiment, the height value of the first insulating material in the second isolation trench covering the bottom wall of the second isolation trench is greater than or equal to 2 times the predetermined thickness value.

[0092] Figure 1c As shown in the structural schematic diagram of the semiconductor device in Embodiment Three of the present invention, Figure 1cAs shown, in the second isolation trench 120, the portion of the first insulating material 210 covering the sidewall of the trench gradually approaches and closes from top to bottom, and the height difference ΔH between the starting position where the first insulating materials 210 close to each other and the bottom position of the second isolation trench 120 is greater than or equal to twice the predetermined thickness value.

[0093] Embodiment 4

[0094] Similar to Embodiment 1, the second isolation trench in this embodiment is filled with a first insulating material, and a gap is also formed in the center of the first insulating material in the second isolation trench. However, different from Embodiment 1, in the second isolation trench of this embodiment, no second insulating material is provided at least in the region corresponding to the electrically conductive layer.

[0095] Figure 1d is a schematic structural diagram of the semiconductor device in Embodiment 4 of the present invention. As Figure 1d shown, the second isolation trench 120 is filled with the first insulating material 210, and in the second isolation trench 120, the first insulating material 210 covers the inner wall of the second isolation trench 120 and defines a gap 121. And, the portion of the electrically conductive layer (for example, the word line 300 of the memory) formed in the second isolation trench 120 is located above the gap 121 in the second isolation trench 120.

[0096] Among them, no second insulating material may be provided between the electrically conductive layer and the gap 121. In this embodiment, the bottom of the electrically conductive layer closes the top opening of the gap 121, that is, the electrically conductive layer is in direct contact with the gap 121. Further, for example, the conductive material of the electrically conductive layer is also present in the gap 121.

[0097] Based on the semiconductor device described above, a method for forming a semiconductor device is further provided in this embodiment.

[0098] Figure 3 is a schematic flow diagram of the method for forming a semiconductor device in an embodiment of the present invention. Figures 4a - 4g is a schematic structural diagram of the method for forming a semiconductor device in an embodiment of the present invention during its manufacturing process. The following will describe each step of the method for forming a semiconductor device in this embodiment in detail with reference to the accompanying drawings.

[0099] In step S100, specifically referring to Figure 4a shown, a substrate 100 is provided, and first isolation trenches 110, second isolation trenches 120, and third isolation trenches 130 with sequentially increasing opening sizes are formed in the substrate 100.

[0100] Among them, the preparation methods of the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 may include, for example: First, a mask layer 400 is formed on the substrate 100, and the patterns of the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 are defined in the mask layer 400; then, the substrate 100 is etched using the mask layer 400 as a mask to form the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130.

[0101] Furthermore, since the opening size of the first isolation trench 110 is small, and the opening sizes of the second isolation trench 120 and the third isolation trench 130 are large, for example, the loading effect of the etching process can be utilized to form isolation trenches with different depths.

[0102] In this embodiment, the depth values of the second isolation trench 120 and the third isolation trench 130 are greater than the depth value of the first isolation trench 110. Specifically, the depth positions where the second isolation trench 120 and the third isolation trench 130 extend in the substrate 100 are the second depth position H2, the depth position where the first isolation trench 110 extends in the substrate is the first depth position H1, and the second depth position H2 is lower than the first depth position H1.

[0103] And, as described above, the opening sizes of the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 are, for example, gradually decreasing from top to bottom.

[0104] In an alternative solution, specifically referring to Figure 4b as shown, after forming the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 using the mask layer 400, an ion implantation process can be further performed using the mask layer 400 to form an ion implantation region (not shown in the figure) in at least a part of the substrate 100 exposed to the first isolation trench 110 and the second isolation trench 120. And, after performing the ion implantation process to form the ion implantation region, the mask layer 400 can be removed.

[0105] Among them, the ion implantation process may include an inclined ion implantation process and a vertical ion implantation process, so that the formed ion implantation region covers the side walls and the bottom walls of the first isolation trench 110 and the second isolation trench 120. Specifically, through the inclined ion implantation process, doping ions can be implanted into the side walls of the first isolation trench 110 and the second isolation trench 120, and through the vertical ion implantation process, doping ions can be implanted into the bottom walls of the first isolation trench 110 and the second isolation trench 120, so that the periphery of the first isolation trench 110 and the second isolation trench 120 is covered with the ion implantation region.

[0106] In addition, in this embodiment, an ion implantation region is also formed around the third isolation trench 130.

[0107] As described in the above embodiment, the conductivity type of the doped ions implanted in the ion implantation process may be the same as the conductivity type of the substrate, for example, both are P-type. Further, the implanted doped ions may include boron ions.

[0108] In step S200, specifically referring to Figure 4c as shown, a first insulating material 210 is formed in the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130.

[0109] As Figure 4c shown, the first insulating material 210 fills the first isolation trench 110. And, the first insulating material 210 covers the inner walls of the second isolation trench 120 and the third isolation trench 130.

[0110] Specifically, the first insulating material 210 can be formed by a deposition process, and is deposited in the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 simultaneously.

[0111] It should be noted that in this embodiment, a semiconductor device as Figure 1a shown is taken as an example for explanation. At this time, a gap 121 can be defined by the first insulating material 210 in the second isolation trench 120. Among them, since the opening size of the first isolation trench 110 is small, the deposited first insulating material 210 can directly fill the first isolation trench 110. And, in the second isolation trench 120, because its depth is large, and the trench sidewalls at the bottom are steeper, the first insulating material 120 is likely to form a gap 121 in the region near the bottom of the second isolation trench 120.

[0112] Of course, in other embodiments, when a semiconductor device such as Figure 1b and Figure 1c shown needs to be formed, when depositing the first insulating material, the deposition process can be adjusted to form a first insulating material without a gap in the second isolation trench 120.

[0113] In step S300, specifically referring to Figures 4d - 4e as shown, a second insulating material 220 is formed in the second isolation trench 120 and the third isolation trench 130, and a third insulating material 230 is formed in the third isolation trench 130.

[0114] As described above, in this embodiment, a semiconductor device as Figure 1aTaking the semiconductor device shown as an example for explanation, based on this, the bottom of the second insulating material 220 in this embodiment closes the top opening of the gap 121 in the second isolation trench 120 and is located above the gap 121.

[0115] Specifically, in the second isolation trench 120 formed with the first insulating material 210, the space defined by the first insulating material 210 includes the gap 121 and a filling space located above the gap 121. When depositing the second insulating material 220, the second insulating material 220 fills the filling space located above the gap 121 to the top of the second isolation trench 120.

[0116] In addition, when depositing the second insulating material 220, the second insulating material 220 is also deposited on the top surface of the substrate 100 and covers the first insulating material 210 in the first isolation trench 110.

[0117] Continue to refer to Figure 4e As shown, in the third isolation trench 130, the second insulating material 220 conformally covers the inner wall of the third isolation trench 130, and the third insulating material 230 fills the space defined by the second insulating material 220.

[0118] Furthermore, after filling the third insulating material 230 into the third isolation trench 130, it further includes: performing a planarization process on the third insulating material 230 to planarize the top surface of the third insulating material 230. In this embodiment, the remaining third insulating material 230 after performing the planarization process fills the third isolation trench 130 and covers the top surface of the substrate 100.

[0119] So far, the first trench isolation structure can be formed by using the first isolation trench 110 filled with insulating material, the second trench isolation structure can be formed by using the second isolation trench 120 filled with insulating material, and the third trench isolation structure can be formed by using the third isolation trench 130 filled with insulating material.

[0120] It should be noted that for a specific semiconductor device, after forming the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure as described above, the device unit area and the peripheral area of the semiconductor device can be defined by using the third trench isolation structure, and a plurality of active areas can be defined in the device unit area by using the first trench isolation structure and the second trench isolation structure. And, after defining the device unit area, subsequent processes can be further performed in the device unit area.

[0121] Specifically, in step S400, specifically refer to Figure 4f andFigure 4g As shown, an electrically conductive layer is formed in the substrate 100, and the electrically conductive layer is at least partially formed in the second isolation trench 120.

[0122] For example, taking a semiconductor device as a memory as an example, the storage area of the memory can be defined by the third trench isolation structure, and a plurality of active regions can be further defined in the storage area by using the first trench isolation structure and the second trench isolation structure. Also, the electrically conductive layer constitutes, for example, the word line 300 of the memory, and the portion of the word line 300 formed in the second isolation trench 120 constitutes the first word line portion.

[0123] In this embodiment, taking the formation of Figure 1a the semiconductor device shown as an example for explanation, therefore, the first word line portion is located above at least a part of the second insulating material 220 in the second isolation trench 120.

[0124] Specifically, the method for forming the electrically conductive layer (for example, the word line 300 of the memory) includes the following steps.

[0125] The first step, specifically referring to Figure 4f as shown, a trench for the electrically conductive layer is formed in the substrate 100. Among them, the method for forming the trench for the electrically conductive layer includes: etching the second insulating material 220 and the first insulating material 210 in the second isolation trench 120.

[0126] In this embodiment, the trench for the electrically conductive layer is the word line trench 300a, the word line trench 300a extends along a predetermined direction and intersects with the corresponding active region, and the word line trench 300a is also partially located in the second trench isolation structure (that is, the word line trench 300a is also partially located in the second isolation trench 120).

[0127] Continuing to refer to Figure 4f as shown, the depth value of the word line trench 300a is less than the depth value of the first isolation trench 110, that is, the depth position where the word line trench 300a extends in the substrate 100 is higher than the depth position where the first isolation trench 110 extends in the substrate 100 (that is, higher than the first height position H1).

[0128] In addition, in this embodiment, taking the formation of the semiconductor device as shown in Figure 1a as an example, therefore the bottom of the word line trench 300a stops at the second insulating material 220 and is higher than the gap 121 in the second isolation trench 120. That is, the bottom of the word line trench 300a does not extend to the gap 121, and the gap 121 is still closed by the second insulating material 220.

[0129] It should be recognized that in other embodiments, when it is necessary to form semiconductor devices such as Figure 1b and Figure 1c as an example, the bottom of the word line trench 300a also stops at the second insulating material. Alternatively, in other embodiments, when it is necessary to form semiconductor devices such as Figure 1d as shown, the top position of the gap 121 in the second isolation trench is relatively high. At this time, the bottom of the word line trench can extend to the top of the gap so that the word line trench and the gap communicate with each other.

[0130] Second step, specifically referring to Figure 4g as shown, fill the conductive material in the trench of the electrical conduction layer. In this embodiment, that is, fill the word line material in the word line trench 300a to form the word line 300.

[0131] It should be noted that in other embodiments, when it is necessary to form semiconductor devices such as Figure 1d as shown, since the word line trench and the gap communicate with each other, the deposited conductive material may enter the gap, so that there is still a trace amount of conductive material in the gap.

[0132] In this embodiment, the top of the word line 300 is lower than the top of the word line trench 300a. Therefore, there is still an empty accommodation space in the area of the word line trench 300a above the word line 300. At this time, a covering layer 300b can be further filled in the accommodation space to cover the word line 300.

[0133] In summary, in the semiconductor device provided in this embodiment, isolation trenches with different opening sizes can be provided, and the insulating materials filled therein can be correspondingly adjusted based on the isolation trenches with different opening sizes, realizing the diversification of the trench isolation structure in the semiconductor device. In this way, different trench isolation structures with different structures can be correspondingly selected for different isolation regions, improving the application flexibility of the trench isolation structure. And based on the trench isolation structure with different insulating materials in this embodiment, it is also beneficial to simplify the preparation difficulty of each trench isolation structure and improve the production efficiency of the semiconductor device.

[0134] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.

[0135] It should also be noted that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.

[0136] Moreover, it should also be understood that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices and may include sub-steps as well as sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of logical "or", rather than the definition of logical "exclusive or", unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate, in which a first isolation trench, a second isolation trench, a third isolation trench and an electrically conductive layer with successively increasing opening sizes are formed; wherein, The first isolation trench is filled with a first insulating material; The second isolation trench is filled with the first insulating material and at least a part of the electrically conductive layer; and, The third isolation trench is successively filled with the first insulating material, a second insulating material and a third insulating material; In the second isolation trench, the first insulating material covers the inner wall of the second isolation trench and defines a gap, and the part of the electrically conductive layer formed in the second isolation trench is located above the gap; The semiconductor device is a memory, and the electrically conductive layer is a word line of the memory.

2. The semiconductor device according to claim 1, wherein The second isolation trench is further filled with the second insulating material, and the part of the electrically conductive layer formed in the second isolation trench is located above at least a part of the second insulating material in the second isolation trench.

3. The semiconductor device according to claim 2, wherein, In the second isolation trench, the first insulating material covers the inner wall of the second isolation trench and defines a gap, and the second insulating material is located above the gap.

4. The semiconductor device according to claim 2, wherein The first insulating material in the third isolation trench has a predetermined thickness value in the direction perpendicular to the trench sidewall; And, in the second isolation trench, the first insulating material covers the bottom wall and the sidewall of the second isolation trench, and the height value of the first insulating material covering the bottom wall of the second isolation trench is less than 2 times the predetermined thickness value.

5. The semiconductor device according to claim 2, characterized in that, The first insulating material in the third isolation trench has a predetermined thickness value in the direction perpendicular to the trench sidewall; And, in the second isolation trench, the parts of the first insulating material covering the trench sidewalls gradually approach each other from top to bottom until they close, and the height difference between the starting position where the first insulating materials close and the bottom position of the second isolation trench is greater than or equal to 2 times the predetermined thickness value.

6. The semiconductor device according to claim 1, wherein, The bottom of the electrically conductive layer closes the top opening of the gap.

7. The semiconductor device according to claim 6, wherein, The gap also has the conductive material of the electrically conductive layer.

8. The semiconductor device according to claim 1, wherein An ion implantation region is formed in the part of the substrate adjoining the first isolation trench and the second isolation trench.

9. The semiconductor device according to claim 1, wherein, The first insulating material in the third isolation trench has a predetermined thickness value in the direction perpendicular to the trench sidewall; wherein, the maximum opening size of the first isolation trench is less than or equal to 2 times the predetermined thickness value, and the maximum opening size of the second isolation trench is greater than 2 times the predetermined thickness value.

10. The semiconductor device according to claim 1, wherein, The opening size of the second isolation trench gradually decreases from top to bottom, and in the second isolation trench, the slope of the trench sidewall below the gap is greater than or equal to the slope of the trench sidewall above the gap.

11. The semiconductor device according to claim 1, characterized in that, The depth position of the second isolation trench extending in the substrate is lower than the depth position of the first isolation trench extending in the substrate, and the bottom of the gap is lower than the bottom of the first isolation trench.

12. The semiconductor device according to claim 1, wherein In the third isolation trench, the first insulating material and the second insulating material conformally cover the sidewalls and the bottom wall of the third isolation trench, and the third insulating material fills the space defined by the second insulating material in the third isolation trench.

13. The semiconductor device according to claim 1, characterized in that, Both the first insulating material and the third insulating material include silicon oxide, and the second insulating material includes silicon nitride.

14. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate, and forming first, second, and third isolation trenches in the substrate with sequentially increasing opening sizes; Forming a first insulating material in the first isolation trench, the second isolation trench, and the third isolation trench, wherein the first insulating material fills the first isolation trench, and the first insulating material covers the inner walls of the second isolation trench and the third isolation trench; Forming a second insulating material in the second isolation trench and the third isolation trench, and forming a third insulating material in the third isolation trench; And, Forming an electrically conductive layer in the substrate, and at least a portion of the electrically conductive layer is formed in the second isolation trench; When forming the first insulating material in the second isolation trench, the first insulating material covers the inner wall of the second isolation trench and defines a gap, and the portion of the electrically conductive layer formed in the second isolation trench is located above the gap.

15. The method for forming a semiconductor device according to claim 14, wherein, The method of forming the electrically conductive layer includes: Forming a trench for the electrically conductive layer in the substrate, including etching the second insulating material and the first insulating material in the second isolation trench to form the trench for the electrically conductive layer; And, filling a conductive material in the trench for the electrically conductive layer to form the electrically conductive layer.

16. The method for forming a semiconductor device according to claim 14, wherein, When forming the first insulating material in the second isolation trench, the first insulating material covers the inner wall of the second isolation trench and defines a gap, and the portion of the electrically conductive layer formed in the second isolation trench is located above the gap.

17. The method for forming a semiconductor device according to claim 14, characterized in that, Before forming the first insulating material, it further includes: Performing an ion implantation process to form an ion implantation region in at least a portion of the substrate exposed to the first isolation trench and the second isolation trench.

18. The method for forming a semiconductor device according to claim 17, wherein, The ion implantation process includes an inclined ion implantation process and a vertical ion implantation process, so that the formed ion implantation region covers the sidewalls and the bottom wall of the first isolation trench and the second isolation trench.

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