Gpp unidirectional transient voltage suppression diode chip and method of production thereof

Abstract

The application provides a GPP unidirectional transient voltage suppression diode chip and a production method thereof, which comprises an N++ layer 4, a P+ layer 5 and a P++ layer 6; the upper surface of the P++ layer 6 comprises a planar part and an etching groove 1 arranged around the edge of the planar part; the P+ layer 5 is arranged on the upper side of the P++ layer 6, and the N++ layer 4 is arranged on the upper side of the P+ layer 5; the side surface of the N++ layer 4, the side surface of the P+ layer 5 and the etching groove 1 are provided with a passivation glass 2. The P+ substrate is adopted, the P+ substrate has better uniformity, the product VB is more uniform, and the transient voltage suppression diode characteristics are met. The inverted trapezoidal groove shape is adopted, the bird beak shape of the photoresist mask is avoided, the uniformity of the electrophoretic glass is improved, and the risk of sharp tip discharge is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic components, in particular to a GPP unidirectional transient voltage suppression diode chip and a production method thereof. BACKGROUND

[0002] Gpp (Glassivation passivation parts, glass passivation element), glass passivation process is widely used in high reverse voltage large power diode mesa passivation due to its high reliability and stability.

[0003] Patent document CN203150557U discloses a reverse GPP high-voltage diode chip in an automobile module, the structure of the reverse GPP high-voltage diode chip is P++-P+-N-N+ type; the front cross-section structure of the reverse GPP high-voltage diode chip is in turn etching groove, passivation glass, metal layer; the cross-section structure of the reverse GPP high-voltage diode chip is in turn etching groove, passivation glass, metal layer, N+ area, base area N, P+ area, high concentration P++ area.

[0004] The traditional GPP unidirectional transient voltage suppression diode generally uses N+ as the substrate, which leads to poor uniformity of breakdown voltage VB; at the same time, the bird beak shape of the photoresist mask is easily caused in the trenching process, which reduces the uniformity of electrophoretic glass and has the risk of sharp end discharge. SUMMARY

[0005] In view of the defects in the prior art, the purpose of the present application is to provide a GPP unidirectional transient voltage suppression diode chip and a production method thereof.

[0006] The GPP unidirectional transient voltage suppression diode chip provided by the present application comprises an N++ layer 4, a P+ layer 5 and a P++ layer 6.

[0007] The upper surface of the P++ layer 6 comprises a planar part and an etching groove 1 arranged around the edge of the planar part;

[0008] The P+ layer 5 is arranged on the upper side of the P++ layer 6, and the N++ layer 4 is arranged on the upper side of the P+ layer 5.

[0009] The side surface of the N++ layer 4, the side surface of the P+ layer 5 and the etching groove 1 are provided with passivation glass 2.

[0010] Preferably, the etching groove 1 is a half inverted trapezoid.

[0011] Preferably, the width of the planar part is the same as the width of the N++ layer 4 and the P+ layer 5.

[0012] Preferably, the height of the passivation glass 2 on the side of the N++ layer 4 is higher than the upper surface of the N++ layer 4.

[0013] Preferably, the upper surface of the N++ layer 4 is provided with a first metal layer and a silicon dioxide layer 7 arranged around the edge of the first metal layer.

[0014] Preferably, the height of the passivation glass 2 on the side of the N++ layer 4 is higher than the upper surface of the N++ layer 4, and covers the edge of the upper surface of the N++ layer 4, and is connected with the silicon dioxide layer 7.

[0015] Preferably, the lower surface of the P++ layer 6 is provided with a second metal layer.

[0016] Preferably, the depth of the etching groove 1 is 80±3 microns.

[0017] Preferably, the width of the widest part of the etching groove 1 is 280±10 microns.

[0018] The production method of the GPP unidirectional transient voltage suppression diode chip provided by the application comprises the following steps:

[0019] Step 1: cleaning the surface of the P+ type silicon wafer;

[0020] Step 2: using 3L / min nitrogen gas to carry 10℃ phosphorus oxychloride, diffusing at 1000℃ for 2 hours to form an N++ layer on the surface of the silicon wafer;

[0021] Step 3: using hydrofluoric acid to soak for 30 min to remove the oxide layer caused by diffusion;

[0022] Step 4: using a sandblasting machine to remove the N++ layer on the bottom surface with a thickness of 30±3 microns;

[0023] Step 5: cleaning the surface;

[0024] Step 6: coating 10% liquid boron source on the back surface, using a speed of 3000 revolutions / min to coat the source, and diffusing at 1250℃ for 20 hours to form a P++ layer;

[0025] Step 7: using hydrofluoric acid to soak for 30 min to remove the oxide layer caused by diffusion;

[0026] Step 8: passing water vapor to oxidize at 1150℃ for 24 hours to make the thickness of the obtained oxide layer reach 3 microns;

[0027] Step 9: using a wafer saw to draw the size of the required chip;

[0028] Step 10: using nitric acid to etch at-10℃ for 10 min, using the oxide layer as a mask, and obtaining an etching groove after etching.

[0029] Step 11: washing the etching groove;

[0030] Step 12: using 100g glass powder to pour into the lanthanum nitrate solution, ultrasonic charging, electrophoresis for 2 minutes under the electrode voltage of 180V, the glass powder is uniformly grown in the groove under the action of the electric field, and the thickness reaches 20±3 microns;

[0031] Step 13: melting the grown glass powder at 800℃ for 30 minutes;

[0032] Step 14: cleaning the surface of the silicon wafer;

[0033] Step 15: growing an oxide layer with a thickness of 3000±300 angstroms on the surface of the silicon wafer at 800℃ by LPCVD to compensate for the damage to the original oxide layer caused by the groove;

[0034] Step 16: coating a negative photoresist with a viscosity of 450 on the surface of the silicon wafer, and the film thickness is 8 microns;

[0035] Step 17: using a photoetching plate to expose under a photoetching machine, leaving a width of 20 microns around the grown glass powder;

[0036] Step 18: washing away the unexposed part with a developing solution;

[0037] Step 19: baking at 135℃ for 30 minutes to harden the photoresist;

[0038] Step 20: removing the oxide layer without photoresist protection;

[0039] Step 21: using sulfuric acid and 20% hydrogen peroxide solution at 80℃ to remove the photoresist;

[0040] Step 22: electroless nickel plating, thickness 1 micron;

[0041] Step 23: diffusing part of the nickel into the silicon wafer at 600℃ to form a silicon-nickel alloy layer.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] 1. P+ substrate is adopted, and the P+ substrate has better uniformity, and the product VB is more uniform, which meets the characteristics of transient voltage suppression diode.

[0044] 2. Inverted trapezoidal groove shape is adopted, which avoids the bird beak shape of the photoresist mask, improves the uniformity of the electrophoretic glass, and reduces the risk of sharp tip discharge.

[0045] 3. The oxide layer is reserved between the passivation glass and the first metal layer, which effectively eliminates the reliability risk caused by the solder pressing to the glass during soldering. BRIEF DESCRIPTION OF DRAWINGS

[0046] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings:

[0047] Figure 1 is a sectional view of the present application;

[0048] Figure 2 is a process flow diagram of the present application;

[0049] Figures 3 to 14 is a process flow diagram of the present application. DETAILED DESCRIPTION

[0050] The present application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of changes and improvements can be made. These are within the scope of the present application.

[0051] As shown in Figure 1 , the GPP unidirectional transient voltage suppression diode chip provided by the embodiment includes an N++ layer 4, a P+ layer 5, and a P++ layer 6.

[0052] The upper surface of the P++ layer 6 includes a planar portion and an etching groove 1 arranged around the edge of the planar portion, the P+ layer 5 is arranged on the upper side of the P++ layer 6, and the N++ layer 4 is arranged on the upper side of the P+ layer 5. The side surface of the N++ layer 4, the side surface of the P+ layer 5, and the etching groove 1 are provided with a passivation glass 2.

[0053] In the embodiment, the etching groove 1 is in the shape of a half inverted trapezoid. The depth of the etching groove 1 is 80 microns, and the width of the etching groove 1 is 280 microns.

[0054] The width of the planar portion is the same as the width of the N++ layer 4 and the P+ layer 5, and the height of the passivation glass 2 on the side surface of the N++ layer 4 is higher than the upper surface of the N++ layer 4. The upper surface of the N++ layer 4 is provided with a first metal layer and a silicon dioxide layer 7 arranged around the edge of the first metal layer. The height of the passivation glass 2 on the side surface of the N++ layer 4 is higher than the upper surface of the N++ layer 4 and covers the edge of the upper surface of the N++ layer 4, and is connected with the silicon dioxide layer 7. The lower surface of the P++ layer 6 is provided with a second metal layer.

[0055] As shown in Figures 3 to 14 , the production process flow of an embodiment of the present application is as follows:

[0056] 1) Diffusion cleaning: SC1, SC2, deionized water spray quick discharge cleaning, etc. process, toFigure 3 The surface of the silicon wafer is cleaned. SC1 and SC2 are a first cleaning solution (ammonia hydrogen peroxide) and a second cleaning solution (hydrochloric acid hydrogen peroxide).

[0057] 2) POCl3 diffusion: 4 inches are used to diffuse 3L / min of nitrogen carrying 10°C of phosphorus oxychloride at 1000°C for 2 hours, to obtain Figure 4 The N++ layer is shown.

[0058] 3) Remove the oxide layer: soak in hydrofluoric acid for 30 min to remove the oxide layer caused by diffusion.

[0059] 4) Backside thinning: as shown in Figure 5 The back of the silicon wafer is removed by 30 microns using a sandblasting machine to remove the back source caused by diffusion, i.e. to remove the bottom N++ layer.

[0060] 5) Diffusion cleaning: SC1, SC2, deionized water spray quick exhaust cleaning and other processes are used to clean the surface of the silicon wafer.

[0061] 6) Backside boron diffusion: 10% concentration of liquid boron source is coated on the backside, 3000 rpm is used to coat the source, and 1250°C is used to diffuse for 20 hours to obtain Figure 6 The P++ layer is shown.

[0062] 7) Remove the oxide layer: soak in hydrofluoric acid for 30 min to remove the oxide layer caused by diffusion.

[0063] 8) Wet oxidation: water vapor is introduced at 1150°C for 24 hours to make the oxide layer thickness reach 3 microns, as shown in Figure 7 .

[0064] 9) Scribing: use a Disco321 scribe machine to scribe the size of the required chip, with a width of 200 microns and a depth of 40 microns, as shown in Figure 8 .

[0065] 10) Groove etching: use nitric acid (nitric acid: hydrofluoric acid: glacial acetic acid: sulfuric acid = 9:9:12:4) at -10°C for 10 min, use the oxide layer as a mask, after etching, the groove depth reaches 80 microns, and the width reaches 280 microns, as shown in Figure 9 .

[0066] 11) Groove cleaning: SC1, SC2, deionized water spray quick exhaust cleaning and other processes are used to clean the groove, and the electrophoresis glass is left.

[0067] 12) Electrophoresis: 100g of NEG GP230 glass powder is poured into a lanthanum nitrate solution, and electrophoresis is carried out at a voltage of 180V for 2 minutes, and the glass powder thickness reaches 20 microns, as shown in Figure 10 .

[0068] 13) Glass burning: burn for 30 minutes at 800°C furnace temperature, and the glass melts.

[0069] 14) Cleaning: SC1, SC2, deionized water spray quick exhaust cleaning and other processes.

[0070] 15) MTO: 800°C LPCVD is used to grow 3000 angstroms of oxide layer on the surface, to compensate for the damage to the original oxide layer caused by the trenching.

[0071] 16) Gluing: negative photoresist with a viscosity of 450 is applied on the surface of the silicon wafer, with a film thickness of 8 microns.

[0072] 17) Photolithography: using a photomask, exposure is performed on a photolithography machine, leaving a 20 micron wide peripheral area around the grown glass powder.

[0073] 18) Development: the developer washes away the unexposed parts.

[0074] 19) Hardening: 135°C baking for 30 minutes to completely harden the photoresist.

[0075] 20) Silicon etching: as shown in Figure 11 , the oxide layer without photoresist protection is removed, leaving it for nickel plating.

[0076] 21) Photoresist removal: using sulfuric acid and 20% hydrogen peroxide solution at 80°C to remove the photoresist.

[0077] 22) Chemical nickel plating, thickness 1 micron, as shown in Figure 12 .

[0078] 23) Sintering: 600°C nickel diffusion into the silicon part, forming a silicon-nickel alloy.

[0079] 24) Testing: using a probe station to test, and marking defective products.

[0080] 25) Dicing: as shown in Figure 13 , using a laser dicing machine to obtain a single chip as shown in Figure 14 .

[0081] 26) Packaging and storage: the chip is weighed, packaged and stored in the finished product warehouse, and the process is complete.

[0082] After testing, the parameters of the GPP unidirectional transient voltage suppression diode chip produced by the present application are as follows:

[0083] Avalanche breakdown voltage VBO≥1000V

[0084] Forward voltage V F (I F =2A)≤2.0V

[0085] Reverse leakage current IR 1 muA

[0086] Junction temperature Tj 150 DEG C

[0087] The chip production process of the GPP unidirectional transient voltage suppression diode of the application forms high-concentration PN diffusion junction with good flatness and uniformity by adopting gas-carrying source diffusion, enhances the stability and uniformity of voltage and the surge resistance, and enhances the ohmic contact with metal; the inverted-trapezoidal groove is formed by adopting the silicon dioxide mask dicing and groove digging process, the bird beak of the groove is removed, the glass passivation is more suitable, the uniformity of electrophoretic glass is improved, and the sharp-point discharge problem is eliminated; the 20-micron oxide layer is reserved between the glass and the metal by the photoetching deoxidation layer, and the reliability risk caused by the solder tin pressing to the glass during welding is effectively eliminated.

[0088] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0089] The specific embodiments of the application are described above. It should be understood that the application is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the application. The embodiments of the present application and the features in the embodiments can be arbitrarily combined with each other without conflict, provided that the combination does not conflict.

Claims

1. A method of producing a GPP unidirectional transient voltage suppression diode chip, characterized by, The method comprises the following steps: Step 1: cleaning the surface of a P+ type silicon wafer; Step 2: using 3L / min nitrogen to carry 10℃ phosphorus oxychloride, diffusing at 1000℃ for 2 hours to form an N++ layer on the surface of the silicon wafer; Step 3: using hydrofluoric acid to soak for 30 minutes to remove the oxide layer caused by diffusion; Step 4: using a sand blasting machine to remove 30±3 microns in thickness to remove the N++ layer on the bottom surface; Step 5: cleaning the surface; Step 6: coating 10% liquid boron source on the back surface, using a speed of 3000 revolutions / min to coat the source, diffusing at 1250℃ for 20 hours to form a P++ layer; Step 7: using hydrofluoric acid to soak for 30 minutes to remove the oxide layer caused by diffusion; Step 8: passing water vapor to oxidize at 1150℃ for 24 hours to make the thickness of the obtained oxide layer reach 3 microns; Step 9: using a wafer scribe machine to scribe the size of the required chip; Step 10: using nitric acid to etch at-10℃ for 10 minutes, using the oxide layer as a mask, and obtaining an etching groove after etching; The upper surface of the P++ layer (6) comprises a planar part and the etching groove (1) arranged along the edge of the planar part, the etching groove (1) is a half inverted trapezoid, and the width of the planar part is the same as the width of the N++ layer (4) and the P+ layer (5); Step 11: washing the etching groove; Step 12: using 100g glass powder to be poured into a lanthanum nitrate solution, using ultrasonic waves to electrify the glass powder, electrophoresis for 2 minutes under the condition of an electrode voltage of 180V, and the glass powder is uniformly grown in the groove under the action of the electric field, and the thickness reaches 20±3 microns; Step 13: melting the grown glass powder by burning at 800℃ for 30 minutes; Step 14: cleaning the surface of the silicon wafer; Step 15: growing an oxide layer with a thickness of 3000±300 angstroms on the surface of the silicon wafer by using LPCVD at 800℃ to compensate for the damage to the original oxide layer caused by the groove; Step 16: coating negative photoresist with a viscosity of 450 on the surface of the silicon wafer, and the film thickness is 8 microns; Step 17: using a photomask to expose under a photoetching machine, leaving a width of 20 microns around the grown glass powder; Step 18: using developing solution to wash away the unexposed part; Step 19: baking at 135℃ for 30 minutes to harden the photoresist; Step 20: removing the oxide layer without the protection of the photoresist part; Step 21: using sulfuric acid and 20% hydrogen peroxide solution at 80℃ to remove the photoresist; Step 22: chemical nickel plating, thickness 1 micron; Step 23: diffusing a part of the nickel into the silicon wafer at 600℃ to form a silicon-nickel alloy layer.

2. A GPP unidirectional transient voltage suppression diode chip, characterized in that, The GPP unidirectional transient voltage suppression diode chip is prepared by the production method of claim 1, and the GPP unidirectional transient voltage suppression diode chip comprises an N++ layer (4), a P+ layer (5) and a P++ layer (6); The upper surface of the P++ layer (6) comprises a planar part and an etching groove (1) arranged along the edge of the planar part; The P+ layer (5) is arranged on the upper side of the P++ layer (6), and the N++ layer (4) is arranged on the upper side of the P+ layer (5). The side of the N++ layer (4), the side of the P+ layer (5) and the etching groove (1) are provided with passivation glass (2); The height of the passivation glass (2) on the side of the N++ layer (4) is higher than the upper surface of the N++ layer (4); The upper surface of the N++ layer (4) is provided with a first metal layer and a silicon dioxide layer (7) arranged around the edge of the first metal layer; The lower surface of the P++ layer (6) is provided with a second metal layer; The etching groove (1) is a half inverted trapezoid. The width of the flat part is the same as the width of the N++ layer (4) and the P+ layer (5).

3. The GPP unidirectional transient voltage suppression diode chip of claim 2, wherein, The height of the passivation glass (2) on the side of the N++ layer (4) is higher than the upper surface of the N++ layer (4), and covers the edge of the upper surface of the N++ layer (4) and is connected with the silicon dioxide layer (7).

4. The GPP unidirectional transient voltage suppression diode chip of claim 2, wherein, The depth of the etching groove (1) is 80±3 microns.

5. The GPP unidirectional transient voltage suppression diode chip of claim 2, wherein, The width of the widest part of the etching groove (1) is 280±10 microns.

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