Insulated gate type semiconductor device and method for manufacturing the same

Abstract

The present invention provides an insulated gate type semiconductor device and a manufacturing method thereof, which can suppress the increase of working hours and can screen the gate insulation film of the dummy groove independently from the gate groove. The manufacturing method of the insulated gate type semiconductor device includes the following steps: digging out a dummy groove (41-45), and digging out a gate groove (40) having a planar pattern surrounding the dummy groove (41-45) in a U shape; forming a dummy electrode and a gate electrode in the dummy groove (41-45) and the gate groove (40) through the gate insulation film; forming a test protrusion and a test wiring connected to the dummy electrode through the U-shaped opening; and applying a voltage between the test wiring and the lower surface of the charge transfer region to check the insulation characteristics of the gate insulation film in the dummy groove (41-45).

Description

Technical Field

[0001] The present invention relates to an insulated gate type semiconductor device having a trench gate structure and a manufacturing method thereof. Background Art

[0002] In an insulated gate bipolar transistor (IGBT) having a trench gate structure, the following structure is known: a dummy electrode is buried in a portion of the trenches (dummy trenches) among a plurality of trenches, and the dummy electrode is electrically connected to the emitter electrode to reduce the gate-collector capacitance that causes switching loss.

[0003] Patent document 1 discloses the following method: before the gate trench and the dummy trench are separated in the device structure, the gate insulating film is screened for defects throughout the entire trench to ensure the quality of the gate insulating film of the dummy trench. Patent document 2 discloses the following method: the dummy trench is connected to the emitter electrode via a contact hole, and the gate insulating film of the dummy trench is screened for defects to ensure the quality of the gate insulating film of the dummy trench. Patent document 3 discloses the following content: in an insulated gate type semiconductor device, the ends of adjacent strip-shaped trenches are connected to each other to form a continuous shape.

[0004] However, in the method of Patent Document 1, since the gate insulating film is tested simultaneously throughout the entire trench, a relatively large voltage needs to be applied during the test, thereby generating a large number of particles when a defective element is damaged. Therefore, a screening condition matching the required resistance of the gate insulating film of the dummy trench is set to suppress the generation of particles. However, the gate insulating film of the gate trench needs to be tested again after the manufacturing process is completed, and the time-dependent dielectric breakdown (TDDB) resistance of the gate insulating film is reduced.

[0005] On the other hand, if screening is not performed after the manufacturing process is completed, it is impossible to screen for process damage after screening in the middle of manufacturing.

[0006] In addition, in the method of Patent Document 2, although the gate insulating film of the dummy trench is tested independently of the gate trench, since the insulating characteristics are checked through the contact hole, the structure becomes complicated and the man-hours of the photolithography process etc. are increased. In addition, Patent Document 3 does not disclose a screening method for the gate insulating film of the dummy trench at all.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent No. 6304445

[0010] Patent Document 2: Japanese Patent Application Publication No. 2010-50211

[0011] Patent Document 3: Japanese Patent Application Publication No. 2011-40781 Summary of the invention

[0012] Problem that the invention aims to solve

[0013] In view of the above problems, an object of the present invention is to provide an insulated gate semiconductor device and a method for manufacturing the same, which can suppress an increase in man-hours and can screen for defects in a gate insulating film of a dummy trench independently of a gate insulating film of a gate trench.

[0014] Solutions for solving problems

[0015] One embodiment of the present invention is an insulated gate type semiconductor device, the main purpose of which is to have: (a) a charge transfer region of the first conductivity type; (b) an injection control region of the second conductivity type on the charge transfer region; (c) a main charge supply region of the first conductivity type, which is selectively arranged on the injection control region; (d) a dummy electrode, which is buried in a dummy trench that penetrates the main charge supply region and the injection control region and reaches the charge transfer region through a gate insulating film; (e) a gate electrode, which is buried in the gate trench through a gate insulating film, and the gate trench is adjacent to the dummy trench in a manner of having a planar pattern that surrounds the dummy trench in a U shape, and the depth of the gate trench is the same as the depth of the dummy trench; (f) a gate surface wiring, which is connected to the gate electrode at the bottom of the U shape; and (g) a connection region, which is formed by a conductive layer, is selectively arranged on the side of the opening of the U shape, and is connected to the dummy electrode.

[0016] Another embodiment of the present invention is a method for manufacturing an insulated gate semiconductor device, the gist of which is to include the following steps: (a) forming an injection control region of a second conductivity type on a charge transfer region of a first conductivity type; (b) forming a main charge supply region of a first conductivity type on the upper part of the injection control region; (c) digging a dummy groove in a manner that penetrates the main charge supply region and the injection control region and reaches the charge transfer region, and digging a gate groove adjacent to the dummy groove in a manner that has a planar pattern that surrounds the dummy groove in a U shape; (d) burying a conductive film in the dummy groove as a dummy electrode through a gate insulating film, and burying a conductive film in the gate groove as a gate electrode through the gate insulating film; (e) forming a test protrusion connected to the dummy electrode via a U-shaped opening and a test wiring connected to the test protrusion; and (f) inspecting the insulating properties of the gate insulating film in the dummy groove by applying a voltage between the test wiring and the lower surface of the charge transfer region.

[0017] Effects of the Invention

[0018] According to the present invention, it is possible to provide an insulated gate semiconductor device and a method for manufacturing the same, which can suppress an increase in man-hours and can screen for defects in a gate insulating film of a dummy trench independently of a gate insulating film of a gate trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a plan view showing an example of a semiconductor device according to an embodiment.

[0020] Figure 2 Yes Figure 1 A magnified top view of area A.

[0021] Figure 3 is from Figure 2 Cross-sectional view obtained by observing from the AA′ direction.

[0022] Figure 4 is from Figure 2 Cross-sectional view obtained by observing from the BB′ direction.

[0023] Figure 5 is from Figure 2 Cross-sectional view observed from the CC′ direction.

[0024] Figure 6 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor device according to an embodiment.

[0025] Figure 7 Then Figure 6 A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to an embodiment.

[0026] Figure 8 Then Figure 7 A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to an embodiment.

[0027] Fig.9A Then Figure 8 A process plan view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Fig. 9B is from Fig.9A The process cross-sectional view obtained by observing from the AA′ direction.

[0029] Fig. 9C is from Fig.9A The process cross-sectional view obtained by observing from the BB′ direction.

[0030] Fig.10 Then Figures 9A to 9C A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to an embodiment.

[0031] Fig.11A Then Fig.10 A process plan view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] Fig. 11B is from Fig.11A The process cross-sectional view obtained by observing from the AA′ direction.

[0033] Fig. 11C is from Fig.11A The process cross-sectional view obtained by observing from the BB′ direction.

[0034] Fig.12 Then Figures 11A to 11C A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to an embodiment.

[0035] Fig.13 is a plan view showing a semiconductor device according to a comparative example.

[0036] Fig.14 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor device according to a first modification of the embodiment.

[0037] Fig.15 Then Fig.14 A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to a first modification example of the embodiment.

[0038] Fig.16 1 and 2 are process cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second modification of the embodiment.

[0039] Fig.17 Then Fig.16 A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to a second modification example of the embodiment.

[0040] Fig.18 The diagram is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to a third modification of the embodiment.

[0041] Fig.19 Then Fig.18 A cross-sectional view showing a process of an example of a method for manufacturing a semiconductor device according to a third modification example of the embodiment.

[0042] Fig. 20 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor device according to a fourth modification of the embodiment.

[0043] Description of Reference Numerals

[0044] 1: Charge transfer region (semiconductor substrate); 2: Injection control region; 3a, 3b, 3c, 3d: Main charge supply region; 3A, 3B: Electrode region predetermined layer; 6: Gate insulating film; 8: Field stop layer; 9: Collector region; 10: Main charge receiving electrode (collector electrode); 11: Test wiring; 12: Gate surface wiring; 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j: Lower layer connection region (test convex portion); 12a, 12b, 12c, 12d, 12e, 12f, 12g, 12h, 12i, 12j: Upper layer connection region; 12x: Gate pad ; 13: interlayer insulating film; 14: main charge supply electrode (emitter electrode); 20: etching protection film; 21: power supply; 40, 81, 82, 83, 91, 92, 121, 121, 123: gate trench; 40a, 81a, 81b, 82a, 82b, 83a, 83b, 91a, 91b, 92a, 92b: end; 41, 42, 43, 44, 45, 61, 62, 63, 64, 65, 111, 112, 113, 114, 115: dummy trench; 70: gate electrode; 72: dummy electrode; 101: semiconductor substrate; 401: strip portion; 402: connecting portion. DETAILED DESCRIPTION

[0045] The following is an explanation of the implementation mode with reference to the accompanying drawings. In the description of the accompanying drawings referred to in the following description, the same or similar parts are marked with the same or similar symbols. However, it should be noted that the accompanying drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual situation. Therefore, the specific thickness and size should be determined with reference to the following description. In addition, it goes without saying that the accompanying drawings also include parts with different size relationships and ratios.

[0046] In this specification, the "main charge supply region" of an insulated gate semiconductor device means a region for supplying carriers constituting the main current, and refers to a semiconductor region that becomes either the emitter region or the collector region in an insulated gate bipolar transistor (IGBT). In an insulated gate field effect transistor (MISFET) or an insulated gate static induction transistor (MISSIT), it refers to a semiconductor region that becomes either the source region or the drain region. In addition, in an insulated gate thyristor such as a MIS-controlled static induction thyristor (SI thyristor), it refers to a semiconductor region that becomes either the anode region or the cathode region. The "main charge receiving region" means a region for receiving the majority carriers constituting the main current, and refers to a semiconductor region that becomes either the source region or the drain region in MISFET and MISSIT, but does not become either the main charge supply region. In an IGBT, it refers to a region that becomes either the emitter region or the collector region, but does not become either the main charge supply region. In MIS controlled SI thyristors, etc., it refers to a semiconductor region that is not the main charge supply region, either the anode region or the cathode region. In addition, in semiconductor devices that perform bipolar operation such as IGBTs, minority carriers with charges opposite to those of majority carriers constituting the main current are sometimes supplied from the "main charge receiving region".

[0047] Like this, if the "main charge supply region" is the source region, the "main charge receiving region" refers to the drain region, and the "main current" flows between the main charge supply region and the main charge receiving region. For example, in the case of IGBT, the collector current is equivalent to the main current, and if the "main charge supply region" is the emitter region, the "main charge receiving region" refers to the collector region. If the "main charge supply region" is the anode region, the "main charge receiving region" refers to the cathode region. There is the following situation: if the bias relationship is interchanged, in the case of MISFET, etc., the function of the "main charge supply region" and the function of the "main charge receiving region" can be interchanged. Moreover, the electrode electrically connected to the main charge supply region through an ohmic contact or the like is defined as a "main charge supply electrode", and the electrode electrically connected to the main charge receiving region through an ohmic contact or the like is defined as a "main charge receiving electrode". In addition, a plug (Plug) and a silicide layer for connection may be included between the main charge supply region and the main charge supply electrode, and between the main charge receiving region and the main charge receiving electrode.

[0048] In addition, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type is exemplified. However, the conductivity type can also be selected to be in an opposite relationship, with the first conductivity type being set to p-type and the second conductivity type being set to n-type. In addition, the "+" and "-" attached to "n" and "p" respectively refer to semiconductor regions with relatively high or relatively low impurity concentrations compared to semiconductor regions without "+" and "-". However, even if the semiconductor regions are marked with the same "n" and "n", it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0049] In addition, the definitions of up and down directions in the following description are only for convenience of explanation and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, up and down are converted to left and right to read, and if it is rotated 180° to observe, up and down are reversed to read, which is self-evident.

[0050] <Insulated Gate Type Semiconductor Device>

[0051] As an insulated gate semiconductor device according to the embodiment, an IGBT having a trench gate structure is described as an example. The insulated gate semiconductor device according to the embodiment may be, for example, a reverse conducting IGBT (RC-IGBT) in which an IGBT and a freewheeling diode (FWD) are integrated into one chip.

[0052] like Figure 1 As shown, the insulated gate type semiconductor device involved in the embodiment is constituted based on a semiconductor substrate (semiconductor chip) 1 having a rectangular planar shape. A gate pad 12x and a gate surface wiring (gate flow channel) 12 connected to the gate pad 12x are arranged on the semiconductor substrate 1. The gate surface wiring 12 is electrically connected to the gate electrode of the IGBT. Figure 1 In FIG. 1 , an interlayer insulating film, a main charge supply electrode (emitter electrode), a protective film, and the like arranged on the semiconductor substrate 1 are omitted.

[0053] Figure 2 Yes Figure 1 A schematic top view of an area A enclosed by a single-point dashed line after enlargement. Figure 2 As shown in FIG. 1 , the insulated gate semiconductor device according to the embodiment includes a first trench (gate trench) 40 and second trenches (dummy trenches) 41 , 42 , 43 , 44 , and 45 . Figure 2 , for convenience, the portion of the gate trench 40 located below the gate surface wiring 12 and the portions of the dummy trenches 41 to 45 located below the upper connection regions 12a, 12b, 12c, 12d, and 12e are schematically shown by dotted lines.

[0054] The dummy grooves 41 to 45 have a flat O-shaped plane pattern formed by connecting the two ends of two strips extending parallel to each other with an arc. The two strips connected to the arc of each of the dummy grooves 41 to 45 extend parallel to each other. The strips of the dummy grooves 41 to 45 are periodically arranged in a direction orthogonal to the direction in which they extend. There is no particular limitation on the number of dummy grooves 41 to 45, the width as a plane dimension, the length of the strip, the aspect ratio, etc.

[0055] The planar pattern of the gate trench 40 is in a U-shaped shape that surrounds the dummy trenches 41 to 45 on three sides. Moreover, the planar pattern of the gate trench 40 has U-shaped shapes that are opposite to each other and are alternately continuous, forming a topological structure of a meander line. That is, the planar pattern of the gate trench 40 forms a meandering meander line, so that the strip portion 401 alternately passes between the dummy trenches 41 to 45 in the opposite direction.

[0056] The gate trench 40 has a stripe 401 extending parallel to the stripe of the dummy trenches 41 to 45 and a connection portion 402 that alternately connects the adjacent opposite-direction stripes 401 of the gate trench 40. The connection portion 402 includes an arc-shaped portion and is in a U-shaped shape, and the arc-shaped portion connects the adjacent opposite-direction-extending stripes 401 of the gate trench 40. The U-shaped shape is alternately arranged in opposite directions to each other, and alternately connects the upper or lower parts of the dummy trenches 41 to 45 in a planar pattern. The connection portion 402 corresponds to the bottom of the U-shape.

[0057] In addition, the "U-shape" of the planar pattern of the gate trench 40 is not limited to the letter U, but may also be a "U-shape". At least one side of the "U-shape" may not be closed, for example, it may be a chamfered shape in which the strip portion intersects with the horizontal portion above or below the dummy trenches 41 to 45 via a relay portion at an angle of 45 degrees. Figure 2 The left end 40a of the gate trench 40 is shown as a circular topological structure, but the right end not shown is also circular. There is no particular limitation on the width of the gate trench 40 as a plane dimension, the length of the stripe 401, etc. The width of the gate trench 40 and the width of the dummy trenches 41 to 45 may be the same or different.

[0058] exist Figure 2 In the planar pattern, the gate surface wiring 12 covers the pattern of the connection portion 402 above the gate trench 40 and extends in the horizontal direction, and the gate surface wiring 12 covers the pattern of the connection portion 402 below the gate trench 40 and extends in the horizontal direction. Although omitted from the illustration, in the cross section in the direction perpendicular to the main surface of the semiconductor chip, the gate surface wiring 12 is arranged on the gate trench 40. Figure 2In the planar pattern, upper connection regions 12a to 12e are provided at the ends of the dummy trenches 41 to 45 on the side of the U-shaped opening of the gate trench 40, so as to be separated from the gate surface wiring 12. The gate surface wiring 12 and the upper connection regions 12a to 12e are formed of, for example, a conductive layer such as polysilicon (doped polysilicon (DOPOS)) to which impurities such as phosphorus (P) are added at a high concentration.

[0059] Figure 3 is from Figure 2 The cross-sectional view is obtained by observing the AA′ direction. Figure 3 As shown, the insulated gate semiconductor device according to the embodiment includes a first conductivity type (n - The charge transport region 1 is a semiconductor region that can transport carriers (electrons) that become the main current by utilizing the drift electric field. An injection control region (base region) 2 of the second conductivity type (p-type) is provided on the upper portion of the charge transport region 1. The injection control region 2 is a semiconductor region that controls the amount of carriers injected into the charge transport region 1. An n-type impurity concentration higher than that of the charge transport region 1 is provided on the upper portion of the injection control region 2. + Type main charge supply regions (emitter regions) 3a, 3b, 3c, 3d.

[0060] Although not shown in the figure, a second conductivity type (p 2 ) may be provided on the upper portion of the injection control region 2 so as to be in contact with the main charge supply regions 3a to 3d. + For example, the main charge supply regions 3a to 3d and the contact regions may be connected to Figure 2 The strip portions 401 of the gate trenches 40 shown in FIG. 4 extend in parallel and are periodically alternately arranged.

[0061] like Figure 3 As shown, dummy trenches 42 and gate trenches 40 are provided from the upper surface of the main charge supply regions 3a to 3d to penetrate the main charge supply regions 3a to 3d and the injection control region 2 and reach the upper part of the charge transfer region 1. The dummy trenches 42 and gate trenches 40 have, for example, substantially the same depth.

[0062] A gate insulating film 6 is provided on the bottom and side surfaces of the dummy trench 42 and the gate trench 40. As the gate insulating film 6, in addition to being able to use a silicon oxide (SiO2) film, it is also possible to use a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, or a composite film formed by stacking a plurality of these single-layer films.

[0063] The gate insulating film 6 located on the side of the gate trench 40 functions as the following gate film: electrostatically controlling the surface potential of the injection control region 2 directly below the main charge supply region 3a to 3d, and forming a channel on the surface of the injection control region 2 facing the side of the gate trench 40. On the other hand, the gate insulating film 6 of the dummy trenches 41 to 45 does not function as a gate film. However, there is also electric field concentration at the bottom of the dummy trenches 41 to 45, so like the gate insulating film 6 of the gate trench 40, the gate insulating film 6 of the dummy trenches 41 to 45 also needs to ensure reliability against the time-varying breakdown (TDDB) phenomenon. By applying voltage, the dummy trenches 41 to 45 and the gate trench 40 are screened for abnormal shapes, the film quality of the gate insulating film 6 between the dummy trenches 41 to 45 and the gate trench 40 and the electrode is deteriorated, thereby improving the reliability against the time-varying breakdown.

[0064] exist Figure 3 A dummy electrode 72 is embedded in the inner side of the dummy trench 42 shown in FIG. Figure 2 The dummy trenches 41, 43 to 45 shown in FIG. 4 also have the same structure as the dummy trench 42. A gate electrode 70 is embedded inside the gate trench 40 via a gate insulating film 6. As the material of the dummy electrode 72 and the gate electrode 70, for example, DOPOS can be used.

[0065] An interlayer insulating film 13 is disposed on the gate electrode 70. As the interlayer insulating film 13, a high temperature oxide (HTO) film, an undoped silicon oxide (SiO2) film not containing phosphorus (P) or boron (B) called "NSG" can be used. In addition, as the interlayer insulating film 13, a silicon oxide (PSG) film to which phosphorus is added, a silicon oxide (BSG) film to which boron is added, a silicon oxide (BPSG) film to which boron and phosphorus are added, or a silicon nitride (Si3N4) film can also be used.

[0066] A main charge supply electrode (emitter electrode) 14 is disposed on the interlayer insulating film 13. The main charge supply electrode 14 is Figure 3 The main charge supply electrode 14 is electrically connected or metallurgically bonded to the main charge supply regions 3a to 3d via a contact hole opened in the interlayer insulating film 13. Figure 3 The gate surface wiring 12 located inside the paper surface (not shown) is arranged separately.

[0067] The dummy electrode 72 has a function of reducing the capacitance between the gate and the collector that causes switching loss, for example. A lower layer connection area 11b and an upper layer connection area 12b are arranged on the dummy electrode 72. The lower layer connection area 11b and the upper layer connection area 12b are formed by a conductive layer such as DOPOS. The materials of the lower layer connection area 11b and the upper layer connection area 12b may be the same or different from each other.

[0068] like Figure 2 As shown, the upper connection area 12b has a rectangular planar pattern. Figure 2 Although not shown in the figure, the lower layer connection area 11b under the upper layer connection area 12b also has a rectangular plane pattern substantially the same as that of the upper layer connection area 12b. In addition, under the upper layer connection areas 12a, 12c to 12e having the same rectangular plane pattern as that of the upper layer connection area 12b, connection areas having the same rectangular plane pattern as that of the lower layer connection area 11b are also provided.

[0069] Figure 3 The dummy electrode 72 shown in FIG. 1 is electrically connected to the main charge supply electrode 14 via a contact hole opened in the interlayer insulating film 13 on the lower connection region 11b and the upper connection region 12b. The dummy electrode 72 is electrically insulated and separated from the gate surface wiring 12 and does not contribute to the formation of a channel.

[0070] Figure 4 is from Figure 2 The cross-sectional view obtained by observing the BB′ direction. Figure 4 As shown, a test wiring (lower gate surface wiring) 11 is provided on the injection control region 2. A gate surface wiring (upper gate surface wiring) 12 is provided over the test wiring 11 and the gate electrode 70 to have a step portion.

[0071] Figure 5 is from Figure 2 The cross-sectional view obtained by observing the CC′ direction. Figure 5 As shown, a test wiring 11 is provided on the injection control region 2. A gate surface wiring 12 is provided in a manner having a step portion over the test wiring 11 and the gate electrode 70. A lower layer connection region 11b and an upper layer connection region 12b are provided on the dummy electrode 72. The lower layer connection region 11b and the upper layer connection region 12b are provided to be separated from the test wiring 11 and the gate surface wiring 12. In addition, when the insulation characteristics of the gate insulating film 6 in the dummy electrode 72 are tested in the manufacturing process, the lower layer connection region 11b constitutes a test protrusion connected to the test wiring 11 (details will be described later).

[0072] exist Figure 3 The charge transport region 1 shown is provided with n +A field stop layer 8 of the type may be provided. In addition, a buffer layer may be provided instead of the field stop layer 8, or a non-penetrating structure may be provided without the field stop layer 8. A p + A main charge receiving region (collector region) 9 of the type is provided, and a main charge receiving electrode (collector electrode) 10 is arranged under the main charge receiving region 9. As the main charge receiving electrode 10, for example, a single layer film formed of gold (Au) or a metal film in which Al, nickel (Ni), and Au are stacked in this order can be used.

[0073] When the insulated gate semiconductor device according to the embodiment operates, a positive voltage is applied to the main charge receiving electrode 10, and a positive voltage above the threshold is applied to the gate electrode 70 while the main charge supply electrode 14 is grounded. As a result, the surface potential of the injection control region 2 facing the gate trench 40 is electrostatically controlled via the gate insulating film 6 to form a channel, and the IGBT is turned on. In the on state, electrons as majority carriers are injected from the main charge supply regions 3a to 3d into the charge transfer region 1, and holes as minority carriers are injected from the main charge receiving region 9 into the charge transfer region 1. The holes and electrons injected into the charge transfer region 1 cause conductivity modulation, and the resistance in the charge transfer region 1 decreases. At this time, since the dummy electrode 72 is arranged adjacent to the gate electrode 70, a part of the gate-collector capacitance (feedback capacitance) is replaced by the collector-emitter capacitance, so that the feedback capacitance is reduced and the switching speed is improved.

[0074] On the other hand, when the voltage applied to the gate electrode 70 is less than the threshold value, the channel of electrons formed in the injection control region 2 disappears, and the IGBT becomes off. In the off state, the electrons accumulated in the charge transfer region 1 are discharged from the main charge receiving region 9, and the holes accumulated in the charge transfer region 1 are discharged from the contact region.

[0075] <Method for Manufacturing Insulated Gate Type Semiconductor Device>

[0076] Next, refer to Figure 6 to Figure 12 An example of a method for manufacturing an insulated gate type semiconductor device according to an embodiment including a screening method for an insulated gate type semiconductor device according to an embodiment is described below. Figure 3 The description will be made with reference to the cross section showing the dummy trench 42 and the gate trench 40 shown in FIG.

[0077] First, prepare n - A semiconductor substrate 1 formed of Si of type 1 is used as a base portion (refer to Figure 3). Next, p-type impurity ions are ion-implanted into the entire upper surface of the semiconductor substrate 1. Thereafter, heat treatment is performed to activate the p-type impurity ions and turn them into p-type impurities, and the p-type impurities are thermally diffused to the desired diffusion depth required for the injection control region 2. In addition, the injection control region 2 can also be formed by epitaxial growth on the upper surface of the semiconductor substrate 1. Next, a photoresist film is coated on the upper surface of the injection control region 2, and the photoresist film is patterned using photolithography technology. The patterned photoresist film is used as a mask for ion implantation, and n-type impurity ions are selectively ion-implanted into the upper surface of the injection control region 2. Thereafter, heat treatment is performed to activate the n-type impurity ions and selectively thermally diffuse them. As a result, as shown in FIG. Figure 6 As shown, n is formed on the upper part of the injection control region 2. + The electrode area of ​​the type is predetermined with layers 3A and 3B.

[0078] Next, an etching protection film 20 such as an oxide film is formed on the upper surface of the injection control region 2 and the electrode region predetermined layers 3A and 3B by chemical vapor deposition (CVD) or the like. Then, the etching protection film 20 is patterned using photolithography and dry etching such as reactive ion etching (RIE). The patterned etching protection film 20 is used as an etching mask, such as Figure 7 As shown, the dummy trench 42 and the gate trench 40 are selectively dug out by dry etching such as RIE. Figure 6 The electrode area predetermined layers 3A, 3B shown in FIG. Figure 7 The main charge supply regions 3a to 3d shown in FIG. 4 are formed periodically in one direction. Figure 2 and Figure 3 Plural dummy trenches 41 to 45 are shown in FIG. 2 . In addition, gate trench 40 is adjacent to dummy trenches 41 to 45 so as to have a planar pattern that surrounds dummy trenches 41 to 45 in a U shape. Thereafter, etching protection film 20 is removed.

[0079] Next, a gate insulating film 6 such as a SiO2 film is formed on the bottom and side surfaces of the dummy trench 42 and the gate trench 40, and the upper surfaces of the injection control region 2 and the main charge supply regions 3a to 3d by a thermal oxidation method or a CVD method. Next, a first conductive film (embedded conductive film) such as a DOPOS layer (first DOPOS layer) is deposited by a CVD method to fill the dummy trench 42 and the gate trench 40. Thereafter, the first conductive film and the gate insulating film 6 on the upper surfaces of the injection control region 2 and the main charge supply regions 3a to 3d are removed by etch back or chemical mechanical polishing (CMP), thereby exposing the upper surfaces of the injection control region 2 and the main charge supply regions 3a to 3d. As a result, Figure 8 As shown, a dummy electrode 72 and a gate electrode 70 formed of a first conductive film are embedded in the dummy trench 42 and the gate trench 40 via the gate insulating film 6 .

[0080] Next, a second conductive film formed of a new DOPOS layer (second DOPOS layer) is deposited by CVD or the like. Then, the second conductive film is patterned using photolithography and dry etching such as RIE, thereby forming a Fig.9A As shown, a test wiring 11 and test protrusions 11a to 11e connected to the test wiring 11 are formed. The test protrusions 11a to 11e are respectively located at the ends of the dummy trenches 41 to 45 on the side of the U-shaped opening of the gate trench 40. In addition, a dummy pad (not shown) connected to the test wiring 11 is also formed.

[0081] Fig. 9B is from Fig.9A The process cross-sectional view is obtained by observing the AA′ direction. Fig. 9B As shown in FIG. 1 , a test protrusion 11 b is formed on the dummy electrode 72 so as to be in contact with the dummy electrode 72 . Fig. 9C is from Fig.9A The process cross-sectional view obtained by observing the BB′ direction. Fig. 9C As shown in FIG. 1 , the test protrusion 11 b connected to the test wiring 11 is formed so as to extend onto the dummy electrode 72 .

[0082] Next, the test wiring 11 is used to check the insulation characteristics of the gate insulating film 6 of the dummy trench 42 independently of the gate insulating film 6 of the gate trench 40, thereby screening only the gate insulating film 6 of the dummy trench 42. Specifically, Fig.10As shown, the lower surface of the semiconductor substrate 1 is arranged on a conductive stage (not shown in the figure). Then, the negative side of the power supply 21 is electrically connected to the stage, and the tip of the probe (not shown in the figure) electrically connected to the positive side of the power supply 21 is crimped to the dummy pad connected to the test wiring 11. In this state, the power supply applies a voltage higher than that in the normal operation between the dummy pad and the lower surface of the semiconductor substrate 1 to perform a dummy gate impact test. The dummy gate impact test is an accelerated test for evaluating the time-varying breakdown phenomenon. The dummy gate impact test is performed by applying a voltage (for example, about 4MV / cm) higher than the normal voltage (for example, about 2MV / cm) applied between the dummy pad and the lower surface of the semiconductor substrate 1 using the test wiring 11. Thereafter, the current flowing between the dummy pad and the lower surface of the semiconductor substrate 1 is measured. When the leakage current between the dummy pad and the lower surface of the semiconductor substrate 1 is greater than the reference value, it can be determined that the film quality of the gate insulating film 6 has deteriorated, so the insulation characteristics of the gate insulating film 6 can be checked.

[0083] Next, a third conductive film formed of an updated DOPOS layer (third DOPOS layer) or the like is formed on the test wiring 11 and the test protrusions 11a to 11e by a CVD method or the like. Alternatively, the third conductive film may be formed after removing the test wiring 11 and the test protrusions 11a to 11e. Next, the third conductive film is patterned using photolithography and dry etching such as RIE. At this time, the test wiring 11 is separated from the test protrusions 11a to 11e by selectively removing a portion of the test protrusions 11a to 11e under the third conductive film. As a result, the test protrusions 11a to 11e are separated to form lower layer connection areas 11a to 11e. In addition, the dummy pad connected to the test wiring 11 is removed.

[0084] Therefore, if Fig.11A As shown, a pattern of a gate surface wiring 12 and upper layer connection regions 12a to 12e formed of a third conductive film is formed. The gate surface wiring 12 is formed to cover the test wiring 11. The gate surface wiring 12 is formed to overlap with the connection portion 402 connecting the strip portion 401 of the gate trench 40, and is electrically connected to the gate trench 40. The upper layer connection regions 12a to 12e are formed to overlap with the lower layer connection regions 11a to 11e, and are electrically connected to the dummy trenches 41 to 45.

[0085] Fig. 11B is from Fig.11A The process cross-sectional view is obtained by observing the AA′ direction. Fig. 11B As shown, on the dummy electrode 72 , a lower layer connection region 11 b and an upper layer connection region 12 b are formed in contact with the dummy electrode 72 . Fig. 11C is from Fig.11AThe process cross-sectional view obtained by observing the BB′ direction. Fig. 11C As shown in FIG. 1 , the test wiring 11 is separated from the lower layer connection region 11 b . The gate surface wiring 12 extends to a position closer to the dummy electrode 72 than the test wiring 11 .

[0086] Next, an interlayer insulating film 13 is deposited on the upper surfaces of the dummy electrode 72, the gate electrode 70, the injection control region 2, and the main charge supply regions 3a to 3d by a CVD method or the like. Then, a portion of the interlayer insulating film 13 is selectively removed by photolithography and dry etching, thereby opening contact holes in the interlayer insulating film 13 to expose the upper surfaces of the main charge supply regions 3a to 3d and the upper connection region 12b.

[0087] Next, a metal layer such as an Al film is deposited on the interlayer insulating film 13, the main charge supply regions 3a to 3d, and the upper connection region 12b by sputtering or evaporation, etc. Then, the Al film or other metal layer is patterned using photolithography and dry etching such as RIE to form the main charge supply electrode 14.

[0088] Next, the thickness of the semiconductor substrate 1 is adjusted by CMP or the like. Then, p-type impurity ions are ion-implanted into the lower surface of the semiconductor substrate 1. In addition, n-type impurity ions are ion-implanted into the lower surface of the semiconductor substrate 1 with a projection range deeper than that of the p-type impurity ions. After that, the implanted impurity ions are activated and thermally diffused by heat treatment, thereby Fig.12 As shown, forming n + Type field stop layer 8 and p + In addition, the field stop layer 8 and the main charge receiving region 9 can also be formed by epitaxial growth in sequence on the lower surface of the semiconductor substrate 1.

[0089] Then, if Figure 3 As shown, a main charge receiving electrode 10 made of Au or the like is formed on the lower surface of the main charge receiving region 9 by sputtering or evaporation. Then, the semiconductor substrate 1 is divided into a plurality of semiconductor chips by dicing, and the insulated gate semiconductor device according to the embodiment is completed.

[0090] After that, a gate impact test is performed for each semiconductor chip to check the insulation characteristics of gate insulating film 6 in gate trench 40 , thereby screening for defects in gate insulating film 6 in gate trench 40 . This screening is the first gate impact test for gate insulating film 6 in gate trench 40 .

[0091] According to the method for manufacturing an insulated gate semiconductor device according to the embodiment, by inspecting the insulation characteristics of gate insulating film 6 in dummy trenches 41 to 45 , the quality of gate insulating film 6 in dummy trenches 41 to 45 can be appropriately ensured.

[0092] In addition, by checking only the insulating properties of the gate insulating film 6 of the dummy trenches 41 to 45 independently of the gate insulating film 6 of the gate trench 40, the influence on the gate insulating film 6 of the gate trench 40 can be eliminated. In addition, the insulating properties required of the gate insulating film 6 of the dummy trenches 41 to 45 are lower than the insulating properties required of the gate insulating film 6 of the gate trench 40, so the electric field of the screening condition can be relaxed to match the resistance required of the gate insulating film 6 of the dummy trenches 41 to 45. Therefore, the defective occurrence rate can be reduced, and the amount of particles generated when the defect occurs can be suppressed, so the pollution of the environment in the process can be suppressed. On the other hand, for the gate insulating film 6 of the gate trench 40, the insulating properties of the gate insulating film 6 of the gate trench 40 are checked by the gate impact test after the process is completed, thereby screening for damage in the middle of the process.

[0093] Furthermore, in the screening of the gate insulating film 6 of the dummy trenches 41 to 45, the test protrusions 11a to 11e connect the dummy trenches 41 to 45 to the test wiring 11 via the U-shaped opening of the gate trench 40, thereby connecting the dummy trenches 41 to 45 to the dummy pads via the test wiring 11 without forming a contact hole. Therefore, the increase in man-hours for the photolithography process and the like can be suppressed, and the cost increase caused by the increase in man-hours can be suppressed.

[0094] <Comparative Example>

[0095] Next, an insulated gate semiconductor device according to a comparative example is described. Fig.13 As shown, the insulated gate semiconductor device according to the comparative example includes dummy trenches 111, 112, 113, 114, 115 and gate trenches 121, 122, 123 provided on the upper portion of the semiconductor substrate 101. When viewed in a planar pattern, the gate trenches 121 to 123 are configured in an O-shape that is closed in a manner that completely surrounds the periphery of the dummy trenches 111, 113, 115.

[0096] Therefore, in the screening method of the insulated gate type semiconductor device involved in the comparative example, when only the gate insulating film of the dummy trenches 111, 113, and 115 is tested, multiple photolithography steps are required to form contact holes for wiring so as to lead the dummy trenches 111, 113, and 115 to the outside of the gate trenches 121 to 123, which has a great impact on the cost increase. On the other hand, when a DOPOS film is formed on the entire surface of the semiconductor substrate 101 to screen the gate insulating film of the entire trench including the dummy trenches 111 to 115 and the gate trenches 121 to 123, although the increase in man-hours and the increase in cost can be suppressed, it is impossible to independently screen only the gate insulating film of the dummy trenches 111 to 115.

[0097] In contrast, in the screening method of the insulated gate type semiconductor device according to the embodiment of the present invention, the gate trench 40 has a planar pattern that surrounds the dummy trenches 41 to 45 in a U-shape so as not to completely surround the periphery of the dummy trenches 41 to 45. Thus, the dummy trenches 41 to 45 can be led out to the outside from the U-shaped opening of the gate trench 40. Therefore, it is not necessary to form a contact hole for leading the dummy trenches 41 to 45 to the outside, and only one additional photolithography process can be added to independently screen only the gate insulating film 6 of the dummy trenches 41 to 45.

[0098] (First Modification)

[0099] As a method for manufacturing an insulated gate semiconductor device according to a first modification of the embodiment, referring to Figure 1 The area B enclosed by the double-dashed line is enlarged Fig.14 Regarding the insulated gate type semiconductor device involved in the first variant of the embodiment, as shown in FIG. Fig.14 As shown, when viewed in a planar pattern, the periodic arrangement of the dummy trenches 41, 42, 43, 44, 45 and the dummy trenches 61, 62, 63, 64, 65 and the gate trench 40 is arranged in two rows with the strip-shaped gate surface wiring 12 interposed therebetween. The gate trench 40 is formed by a zigzag line in a manner passing through the dummy trenches 41 to 45 and the dummy trenches 61 to 65. The ends of the gate trenches 40 in each of the two rows are connected to each other in the direction in which the strip portion 401 of the gate trench 40 extends. The ends 40a and 40b of the gate trench 40 are respectively set to be round.

[0100] In the method for manufacturing an insulated gate semiconductor device according to the first variant of the embodiment, Fig.14As shown, a test wiring 11 and test protrusions 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, and 11j for connecting the ends of the dummy grooves 41 to 45 and the dummy grooves 61 to 65 to the test wiring 11 are formed. The test protrusions 11a to 11j connect the dummy grooves 41 to 45 and the dummy grooves 61 to 65 to the test wiring 11 via the U-shaped opening of the gate groove 40. Next, a voltage is applied between the test wiring 11 and the lower surface of the semiconductor substrate, thereby selectively inspecting the insulation characteristics of the gate insulating film 6 of the dummy grooves 41 to 45 and the dummy grooves 61 to 65. Thereafter, as Fig.15 As shown, the gate surface wiring 12 is formed on the connection portion connecting the strip portion of the gate trench 40, and the test protrusions 11a to 11j are separated from the test wiring 11 to form the lower layer connection areas 11a to 11j. In addition, the upper layer connection areas 12a to 12j are formed on the ends of the dummy trenches 41 to 45 and the dummy trenches 61 to 65 and on the lower layer connection areas 11a to 11j. Fig.12 The processes shown are the same, so repeated descriptions are omitted.

[0101] (Second Modification)

[0102] In a method for manufacturing an insulated gate semiconductor device according to a second variation of the embodiment, Fig.16 As shown, the planar pattern of the gate trenches 81, 82, and 83 is different from the manufacturing method of the insulated gate type semiconductor device involved in the embodiment. The gate trenches 81, 82, and 83 are provided to have a planar pattern that surrounds the dummy trenches 41, 43, and 45 in a U shape and are separated from each other. The end portions 81a and 81b of the gate trench 81, the end portions 82a and 82b of the gate trench 82, and the end portions 83a and 83b of the gate trench 83 are provided to be circular.

[0103] In a method for manufacturing an insulated gate semiconductor device according to a second variation of the embodiment, Fig.16 As shown, the test wiring 11 and the test protrusions 11a to 11e that connect the ends of the dummy grooves 41 to 45 to the test wiring 11 are formed. The test protrusions 11a, 11c, and 11e connect the dummy grooves 41, 43, and 45 to the test wiring 11 via the U-shaped openings of the gate grooves 81, 82, and 83. Next, by applying a voltage between the test wiring 11 and the lower surface of the semiconductor substrate, the insulation characteristics of the gate insulating film 6 of the dummy grooves 41 to 45 are selectively checked. Thereafter, as shown in FIG. Fig.17As shown, the gate surface wiring 12 is formed on the connection portion connecting the strip portions of the gate trenches 81, 82, and 83, and the test protrusions 11a to 11e are separated from the test wiring 11 to form lower layer connection areas 11a to 11e. In addition, upper layer connection areas 12a to 12e are formed on the ends of the dummy trenches 41 to 45 and the lower layer connection areas 11a to 11e. Fig.12 The processes shown are the same, so repeated descriptions are omitted.

[0104] (Third Modification)

[0105] In a method for manufacturing an insulated gate semiconductor device according to a third variant of the embodiment, Fig.18 As shown in FIG. 1 , the dummy trenches 41 to 45 have an I-shaped planar pattern, which is different from the method for manufacturing an insulated gate semiconductor device according to the embodiment. The dummy trenches 41 to 45 are arranged parallel to each other.

[0106] In a method for manufacturing an insulated gate semiconductor device according to a third variant of the embodiment, Fig.18 As shown, the test wiring 11 and the test protrusions 11a to 11e that connect the ends of the dummy trenches 41 to 45 to the test wiring 11 are formed. The test protrusions 11a to 11e connect the dummy trenches 41 to 45 to the test wiring 11 via the U-shaped opening of the gate trench 40. Next, by applying a voltage between the test wiring 11 and the lower surface of the semiconductor substrate, the insulation characteristics of the gate insulating film 6 of the dummy trenches 41 to 45 are selectively checked. Thereafter, as shown in FIG. Fig.19 As shown, the gate surface wiring 12 is formed on the connection portion connecting the strip portions of the gate trench 40, and the test protrusions 11a to 11e are separated from the test wiring 11 to form lower layer connection areas 11a to 11e. In addition, upper layer connection areas 12a to 12e are formed on the ends of the dummy trenches 41 to 45 and the lower layer connection areas 11a to 11e. Fig.12 The processes shown are the same, so repeated descriptions are omitted.

[0107] (Fourth Modification)

[0108] Regarding the insulated gate semiconductor device according to the fourth modification of the embodiment, Fig. 20As shown in the figure, the gate trenches 91 and 92 have an N-shaped planar pattern, which is different from the insulated gate type semiconductor device involved in the embodiment. The gate trench 91 has an N-shaped planar pattern, which is formed by connecting the planar patterns surrounding the dummy trenches 41 and 42 in a U shape in reverse. The gate trench 92 has an N-shaped planar pattern, which is formed by connecting the planar patterns surrounding the dummy trenches 44 and 45 in a U shape in reverse. The end portions 91a and 91b of the gate trench 91 and the end portions 92a and 92b of the gate trench 92 are set to be circular.

[0109] In a method for manufacturing an insulated gate semiconductor device according to a fourth variation of the embodiment, Fig. 20 As shown, a test wiring 11 and test protrusions 11a to 11e that connect the ends of the dummy grooves 41 to 45 to the test wiring 11 are formed. The test protrusions 11a, 11b, 11d, 11e connect the dummy grooves 41, 42, 44, 45 to the test wiring 11 via the U-shaped openings of the gate grooves 91 and 92. Next, by applying a voltage between the test wiring 11 and the lower surface of the semiconductor substrate, the insulation characteristics of the gate insulating film 6 of the dummy grooves 41 to 45 are selectively checked. Afterwards, although not shown in the figure, a gate surface wiring is formed on the connection portion that connects the strip portions of the gate grooves 91 and 92, and the test protrusions 11a to 11e are separated from the test wiring 11 to form a lower layer connection area. Furthermore, an upper layer connection area is formed on the ends of the dummy grooves 41 to 45 and the lower layer connection area. Later, Fig.12 The processes shown are the same, so repeated descriptions are omitted.

[0110] (Other embodiments)

[0111] As described above, the present invention is described through the embodiments, but it should not be understood that the discussion and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, various alternative embodiments, examples, and application technologies can be clearly identified by those skilled in the art.

[0112] For example, although a trench gate IGBT is exemplified as the insulated gate semiconductor device according to the embodiment, the present invention is not limited thereto and can be applied to various insulated gate semiconductor devices such as a trench gate MISFET.

[0113] In the description of the insulated gate type semiconductor device involved in the embodiment, an insulated gate type semiconductor device using Si is exemplified. However, in addition to being applicable to the insulated gate type semiconductor device using Si, it can also be applied to an insulated gate type semiconductor device using a semiconductor material (wide bandgap semiconductor) having a wider bandgap width than Si, such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN).

[0114] As described above, it is needless to say that the present invention includes various embodiments and the like that are not described here. Therefore, the technical scope of the present invention is determined only by the technical features of the invention according to the claims that are appropriate based on the above description.

Claims

1. An insulated gate semiconductor device, characterized in that: have: a charge transport region of a first conductivity type; an injection control region of the second conductivity type on the charge transport region; A main charge supply region of a first conductivity type, which is selectively disposed on the injection control region; a dummy electrode buried in a dummy trench penetrating the injection control region and reaching the charge transfer region via a gate insulating film; a gate electrode embedded in a gate trench via the gate insulating film, the gate trench being adjacent to the dummy trench in a manner of having a planar pattern surrounding the dummy trench in a U-shape, and having the same depth as that of the dummy trench; a gate surface wiring connected to the gate electrode at the bottom of the U-shape; The connection area is formed of a conductive layer, is selectively arranged on the side of the U-shaped opening, and is connected to the dummy electrode.

2. The insulated gate semiconductor device according to claim 1, wherein: The stripe portions of the dummy trenches and the stripe portions of the gate trenches extend in parallel with each other and are periodically arranged in a direction orthogonal to the extending direction.

3. The insulated gate semiconductor device according to claim 1 or 2, wherein: Planar patterns of the gate trenches that are in opposite directions and surround the dummy trenches in the U shape are alternately connected to form a zigzag line that meanders between the dummy trenches.

4. The insulated gate semiconductor device according to claim 1 or 2, wherein: The dummy groove has an O-shaped or I-shaped plane pattern.

5. The insulated gate semiconductor device according to claim 2, wherein: The periodic arrangement of the dummy trenches and the gate trenches in the orthogonal direction is provided in two rows with the gate surface wiring in a strip shape parallel to the orthogonal direction interposed therebetween. Ends of the gate trenches in each of the two columns are connected to each other in the extending direction.

6. A method for manufacturing an insulated gate type semiconductor device, characterized in that: Including the following processes: forming an injection control region of a second conductivity type on the charge transport region of the first conductivity type; forming a main charge supply region of a first conductivity type on the injection control region; digging a dummy trench so as to penetrate the injection control region and reach the charge transfer region, and digging a gate trench adjacent to the dummy trench so as to have a planar pattern surrounding the dummy trench in a U shape; A conductive film is buried in the dummy trench via a gate insulating film to serve as a dummy electrode, and a conductive film is buried in the gate trench via the gate insulating film to serve as a gate electrode; forming a test protrusion connected to the dummy electrode via the U-shaped opening and a test wiring connected to the test protrusion; as well as The insulating property of the gate insulating film in the dummy trench is checked by applying a voltage between the test wiring and the lower surface of the charge transfer region.

7. The method for manufacturing an insulated gate semiconductor device according to claim 6, wherein: After the inspection step, the method further includes forming a gate surface wiring that covers the test wiring and is connected to the gate electrode, and separating the test wiring from the test protrusion.

8. The method for manufacturing an insulated gate semiconductor device according to claim 7, wherein: The stripe portions of the dummy trenches and the stripe portions of the gate trenches extend in parallel with each other and are periodically arranged in a direction orthogonal to the extending direction.

9. The method for manufacturing an insulated gate semiconductor device according to any one of claims 6 to 8, wherein: Planar patterns of the gate trenches that are in opposite directions and surround the dummy trenches in the U shape are alternately connected to form a zigzag line that meanders between the dummy trenches.

10. The method for manufacturing an insulated gate semiconductor device according to any one of claims 6 to 8, wherein: The dummy groove has an O-shaped or I-shaped plane pattern.

11. The method for manufacturing an insulated gate semiconductor device according to claim 8, wherein: The periodic arrangement of the dummy trenches and the gate trenches in the orthogonal direction is provided in two rows with the gate surface wiring interposed therebetween. Ends of the gate trenches in each of the two columns are connected to each other in the extending direction.

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