Display device

Abstract

A display device includes a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern on the buffer layer and spaced apart from each other; a first gate insulating layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulating layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulating layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulating layer, the capacitor electrode overlapping the first gate electrode, wherein a dielectric constant of the first gate insulating layer is greater than a dielectric constant of the buffer layer.

Description

Technical Field

[0001] Some aspects of example implementations relate to display devices. Background Technology

[0002] Recently, flat panel display devices, such as liquid crystal displays (LCDs), plasma displays, organic light-emitting diode (OLEDs), field emission displays (FETs), and electrophoretic displays, have become widely used. OLEDs are self-emissive display devices, and unlike LCDs, they do not require a separate light source, thus reducing thickness and weight. Furthermore, OLEDs exhibit high-quality characteristics, such as relatively low power consumption, relatively high brightness, and relatively fast response times, and are therefore being emphasized as the next generation of display devices.

[0003] As the limitations of organic light-emitting display devices increase, the pixel area decreases. When the pixel area decreases, the area used to form the driving transistors can be reduced, and therefore, the driving range of the driving transistors can be reduced. This can lead to problems such as ghosting, image retention, and flickering in organic light-emitting display devices.

[0004] The information disclosed above in this Background Art section is intended only to enhance the understanding of the background art, and therefore the information discussed in this Background Art section does not necessarily constitute prior art. Summary of the Invention

[0005] Some exemplary embodiments relate to display devices. For example, some exemplary embodiments relate to display devices that include an insulating layer having a relatively high dielectric constant.

[0006] Some example implementations include a display device that includes transistors with enhanced characteristics.

[0007] Some example implementations include display devices in which image persistence is reduced.

[0008] According to some exemplary embodiments of this disclosure, a display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern spaced apart from each other on the buffer layer; a first gate insulating layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulating layer, the first gate electrode and the second gate electrode overlapping the first active pattern and the second active pattern, respectively; a second gate insulating layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulating layer, the capacitor electrode overlapping the first gate electrode. The dielectric constant of the first gate insulating layer may be greater than the dielectric constant of the buffer layer.

[0009] According to some example implementations, the first gate insulating layer may include an inorganic insulating layer and a high dielectric constant insulating layer having a dielectric constant greater than that of the inorganic insulating layer.

[0010] According to some example embodiments, the first gate insulating layer may include a first high dielectric constant insulating layer and an inorganic insulating layer, the inorganic insulating layer being on the first high dielectric constant insulating layer and having a dielectric constant smaller than that of the first high dielectric constant insulating layer.

[0011] According to some example implementations, the first high dielectric constant insulating layer may be patterned to overlap with the first active pattern.

[0012] According to some example implementations, the thickness of the first high dielectric constant insulating layer may be less than the thickness of the inorganic insulating layer.

[0013] According to some example embodiments, the first gate insulating layer may further include a second high dielectric constant insulating layer on the inorganic insulating layer and having a dielectric constant greater than that of the inorganic insulating layer.

[0014] According to some example implementations, the second high dielectric constant insulating layer may be patterned to overlap with the second active pattern.

[0015] According to some example implementations, the thickness of the second high dielectric constant insulating layer may be less than the thickness of the inorganic insulating layer.

[0016] According to some example embodiments, the first gate insulating layer may include at least one of zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and niobium oxide (Nb2O5).

[0017] According to some example implementations, the dielectric constant of the second gate insulating layer may be greater than the dielectric constant of the buffer layer.

[0018] According to some example implementations, the second gate insulating layer may include an inorganic insulating layer and a high dielectric constant insulating layer having a dielectric constant greater than that of the inorganic insulating layer.

[0019] According to some example embodiments, the display device may further include a high dielectric constant insulating layer between a substrate and a buffer layer, the high dielectric constant insulating layer having a dielectric constant greater than that of the buffer layer.

[0020] According to some example implementations, the substrate may include plastic.

[0021] According to some example embodiments, the display device may further include an insulating interlayer on capacitor electrodes and source and drain electrodes on the insulating interlayer, the source and drain electrodes being connected to a first active pattern through a first gate insulating layer, a second gate insulating layer, and the insulating interlayer. The dielectric constant of the first gate insulating layer may be greater than the dielectric constant of the insulating interlayer.

[0022] According to some example embodiments, the display device may further include a planarization layer on the source electrode and the drain electrode, a first electrode on the planarization layer and connected to the drain electrode through the planarization layer, an emitter layer on the first electrode, and a second electrode on the emitter layer.

[0023] According to some exemplary embodiments of this disclosure, a display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern spaced apart from each other on the buffer layer; a first gate insulating layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulating layer, the first gate electrode and the second gate electrode overlapping the first active pattern and the second active pattern, respectively; a second gate insulating layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulating layer, the capacitor electrode overlapping the first gate electrode. The dielectric constant of the second gate insulating layer may be greater than the dielectric constant of the buffer layer.

[0024] According to some example implementations, the second gate insulating layer may include an inorganic insulating layer and a high dielectric constant insulating layer having a dielectric constant greater than that of the inorganic insulating layer.

[0025] According to some example implementations, the high dielectric constant insulating layer may be on an inorganic insulating layer.

[0026] According to some example implementations, the high dielectric constant insulating layer can be patterned to overlap with the first gate electrode.

[0027] According to some example implementations, the thickness of the high dielectric constant insulating layer can be less than the thickness of the inorganic insulating layer.

[0028] According to some example embodiments, the second gate insulating layer may include at least one of zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and niobium oxide (Nb2O5).

[0029] According to some example embodiments, the display device may further include a high dielectric constant insulating layer between a substrate and a buffer layer, the high dielectric constant insulating layer having a dielectric constant greater than that of the buffer layer.

[0030] According to some example implementations, the substrate may include plastic.

[0031] According to some exemplary embodiments of this disclosure, a display device includes: a substrate; a high-dielectric-constant insulating layer on the substrate; a buffer layer on the high-dielectric-constant insulating layer; a first active pattern and a second active pattern spaced apart from each other on the buffer layer; a first gate insulating layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulating layer, the first gate electrode and the second gate electrode overlapping the first active pattern and the second active pattern, respectively; a second gate insulating layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulating layer, the capacitor electrode overlapping the first gate electrode. The dielectric constant of the high-dielectric-constant insulating layer may be greater than the dielectric constant of the buffer layer.

[0032] According to some example implementations, the density of the high dielectric constant insulating layer can be greater than the density of the buffer layer.

[0033] According to some example implementations, the substrate may include plastic.

[0034] According to some example embodiments, the substrate may have a multilayer structure, which includes a first organic layer, a second organic layer on the first organic layer, and an inorganic layer between the first organic layer and the second organic layer.

[0035] According to some example embodiments, the substrate may have a single-layer structure including an organic layer.

[0036] According to some example embodiments, the high dielectric constant insulating layer may include at least one of zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and niobium oxide (Nb2O5).

[0037] According to some example embodiments, the display device may further include a barrier layer between a high dielectric constant insulating layer and a buffer layer.

[0038] A display device according to some example embodiments may include a gate insulating layer having a relatively high dielectric constant and located between the active pattern and the gate electrode in each of the transistors. Therefore, the driving range of the driving transistors can be increased, and the driving speed of the switching transistors can be increased.

[0039] The display device according to some example embodiments may include an insulating layer having a relatively high dielectric constant and located between the electrodes of a capacitor. Therefore, ghosting and flicker in the display device can be reduced.

[0040] Display devices according to some example embodiments may include a high dielectric constant insulating layer between a substrate and a buffer layer. Therefore, image retention in the display device can be reduced. Attached Figure Description

[0041] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0042] Figure 1 A circuit diagram illustrating pixels included in a display device according to some example embodiments.

[0043] Figure 2 A cross-sectional view of a display device according to some example embodiments is shown.

[0044] Figure 3 A cross-sectional view of the first gate insulating layer according to some example embodiments is shown.

[0045] Figure 4 To show Figure 2 A diagram illustrating the characteristics of a transistor.

[0046] Figure 5 A cross-sectional view of the second gate insulating layer according to some example embodiments is shown.

[0047] Figure 6 A cross-sectional view of the second gate insulating layer according to some example embodiments is shown.

[0048] Figure 7A and Figure 7B The diagrams illustrate the afterimage of a display device according to a comparative example and the afterimage of a display device according to some exemplary embodiments of the present invention.

[0049] Figure 8 A cross-sectional view of a display device according to some example embodiments is shown.

[0050] Figure 9 A cross-sectional view of a substrate according to some example embodiments is shown.

[0051] Figure 10 A cross-sectional view of a substrate according to some example embodiments is shown.

[0052] Figure 11 The diagram illustrates image retention of a display device according to a comparative example and image retention of a display device according to some exemplary embodiments of the present invention.

[0053] Figure 12 A circuit diagram illustrating pixels included in a display device according to some example embodiments. Detailed Implementation

[0054] The following will explain in more detail the display device according to some exemplary embodiments with reference to the accompanying drawings.

[0055] Figure 1 A circuit diagram illustrating pixels included in a display device according to some example embodiments.

[0056] refer to Figure 1 A display device according to some example embodiments may include a plurality of pixels (PX). Each of the pixels (PX) may include a driving transistor (TDR), a switching transistor (TSW), a storage capacitor (CST), and an organic light-emitting diode (OLED).

[0057] The gate electrode of the driving transistor TDR is electrically connected to the drain electrode of the switching transistor TSW and the first electrode of the storage capacitor CST. The source electrode of the driving transistor TDR can receive the driving voltage ELVDD, and the drain electrode of the driving transistor TDR is electrically connected to the anode of the organic light-emitting diode OLED. The driving transistor TDR can receive the data signal DT from the switching transistor TSW and can supply driving current to the organic light-emitting diode OLED.

[0058] The gate electrode of the switching transistor TSW can receive the scan signal SC. The source electrode of the switching transistor TSW can receive the data signal DT, and the drain electrode of the switching transistor TSW can be electrically connected to the gate electrode of the driving transistor TDR. The switching transistor TSW can be turned on in response to the scan signal SC and can transmit the data signal DT to the gate electrode of the driving transistor TDR.

[0059] The first electrode of the storage capacitor CST is electrically connected to the gate electrode of the driving transistor TDR, and the second electrode of the storage capacitor CST can receive the driving voltage ELVDD. When the switching transistor TSW is turned off, the storage capacitor CST can maintain the voltage between the gate electrode and the source electrode of the driving transistor TDR.

[0060] The anode of an organic light-emitting diode (OLED) can be electrically connected to the drain electrode of a driving transistor (TDR), and the cathode of the OLED can receive a common voltage ELVSS. The OLED emits light based on the driving current supplied from the TDR.

[0061] Figure 2 A cross-sectional view of a display device according to some example embodiments is shown. For example, Figure 2 Can be shown Figure 1 An example of the cross-sectional structure of a medium pixel PX.

[0062] refer to Figure 2 According to some example embodiments, the display device may include a first transistor TR1, a second transistor TR2, a capacitor CAP, and an organic light-emitting diode (OLED) disposed on a substrate 100. The first transistor TR1, the second transistor TR2, and the capacitor CAP may respectively correspond to... Figure 1 The driving transistor TDR, the switching transistor TSW, and the storage capacitor CST are included.

[0063] The substrate 100 may be a transparent insulating substrate. According to some exemplary embodiments, the substrate 100 may include plastics such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc.

[0064] A buffer layer 110 may be disposed on the substrate 100. The buffer layer 110 can prevent or reduce the penetration of impurities onto the substrate 100 and can improve the flatness of the substrate 100. The buffer layer 110 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y )wait.

[0065] The first active pattern 121 and the second active pattern 122 may be placed on the buffer layer 110. The first active pattern 121 and the second active pattern 122 may be spaced apart from each other.

[0066] According to some example embodiments, the first active pattern 121 and the second active pattern 122 may comprise amorphous silicon or polycrystalline silicon. Each of the first active pattern 121 and the second active pattern 122 may include a source region and a drain region doped with P-type or N-type impurities at their opposite ends. A channel region without impurities may be defined between the source region and the drain region.

[0067] According to some example embodiments, the first active pattern 121 and the second active pattern 122 may include an oxide semiconductor. In this embodiment, the source and drain regions may be omitted in each of the first active pattern 121 and the second active pattern 122. The oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO), etc.

[0068] A first gate insulating layer 130 may be placed on the first active pattern 121 and the second active pattern 122. The first gate insulating layer 130 may cover the first active pattern 121 and the second active pattern 122, and may be formed on the buffer layer 110. The first gate insulating layer 130 may insulate between the first active pattern 121 and the first gate electrode 141, and between the second active pattern 122 and the second gate electrode 142.

[0069] The first gate insulating layer 130 may have a relatively high dielectric constant. The dielectric constant of the first gate insulating layer 130 may be greater than that of the buffer layer 110. According to some exemplary embodiments, the first gate insulating layer 130 may include a material with a relatively high dielectric constant, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), etc. Therefore, the dielectric constant of the first gate insulating layer 130 may be greater than that of materials including those with relatively low dielectric constants (such as silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The dielectric constant of the buffer layer 110 (etc.).

[0070] According to some exemplary embodiments, the first gate insulating layer 130 may include an inorganic insulating layer and a high-dielectric-constant insulating layer having a dielectric constant greater than that of the inorganic insulating layer. When the first gate insulating layer 130 includes only the high-dielectric-constant insulating layer, the leakage current through the high-dielectric-constant insulating layer may increase. Therefore, the first gate insulating layer 130 may include an inorganic insulating layer to prevent an increase in the leakage current through the first gate insulating layer 130. Reference will be made below. Figure 3 Detailed description of the components of the first gate insulating layer 130.

[0071] The first gate electrode 141 and the second gate electrode 142 may be placed on the first gate insulating layer 130. The first gate electrode 141 and the second gate electrode 142 may be spaced apart from each other. The first gate electrode 141 may overlap with the first active pattern 121, and the second gate electrode 142 may overlap with the second active pattern 122. The first gate electrode 141 and the second gate electrode 142 may comprise metals, such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), scandium (Sc), etc., alloys thereof, or nitrides thereof. According to some exemplary embodiments, the first gate electrode 141 and the second gate electrode 142 may comprise the same material.

[0072] The second gate insulating layer 150 may be disposed on the first gate electrode 141 and the second gate electrode 142. The second gate insulating layer 150 may cover the first gate electrode 141 and the second gate electrode 142, and may be formed on the first gate insulating layer 130. The second gate insulating layer 150 may insulate between the first gate electrode 141 and the capacitor electrode 160.

[0073] The second gate insulating layer 150 may have a relatively high dielectric constant. The dielectric constant of the second gate insulating layer 150 may be greater than that of the buffer layer 110. According to some example embodiments, the second gate insulating layer 150 may include a material with a relatively high dielectric constant, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), etc. Therefore, the dielectric constant of the second gate insulating layer 150 may be greater than that of materials including those with relatively low dielectric constants (such as silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The dielectric constant of the buffer layer 110 (etc.).

[0074] According to some exemplary embodiments, the second gate insulating layer 150 may include an inorganic insulating layer and a high-dielectric-constant insulating layer having a dielectric constant greater than that of the inorganic insulating layer. When the second gate insulating layer 150 includes only the high-dielectric-constant insulating layer, the leakage current through the high-dielectric-constant insulating layer may increase. Therefore, the second gate insulating layer 150 may include an inorganic insulating layer to prevent an increase in the leakage current through the second gate insulating layer 150. Reference will be made below. Figure 5 and Figure 6 The detailed components of the second gate insulating layer 150 are described in more detail.

[0075] Capacitor electrode 160 may be placed on the second gate insulating layer 150. Capacitor electrode 160 may overlap with the first gate electrode 141. Capacitor electrode 160 may comprise a metal, such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), scandium (Sc), or their alloys, or nitrides. Capacitor electrode 160, together with the first gate electrode 141 and the second gate insulating layer 150, may form a capacitor CAP. Therefore, the first gate electrode 141 can be used as an electrode of the capacitor CAP.

[0076] An insulating interlayer 170 may be placed on the capacitor electrode 160. The insulating interlayer 170 may cover the capacitor electrode 160 and may be formed on the second gate insulating layer 150. The insulating interlayer 170 may insulate the first source electrode 181 and the first drain electrode 182 from the first gate electrode 141 and the capacitor electrode 160, and may insulate the second source electrode 183 and the second drain electrode 184 from the second gate electrode 142. The insulating interlayer 170 may comprise an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), or organic insulating materials.

[0077] According to some exemplary embodiments, the dielectric constant of the first gate insulating layer 130 and the dielectric constant of the second gate insulating layer 150 may be greater than the dielectric constant of the insulating interlayer 170. The dielectric constant of the first gate insulating layer 130 and the dielectric constant of the second gate insulating layer 150 may be greater than that of materials including those with relatively low dielectric constants (such as silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The dielectric constant of the insulating interlayer 170 (etc.).

[0078] A first source electrode 181, a first drain electrode 182, a second source electrode 183, and a second drain electrode 184 may be placed on an insulating interlayer 170. The first source electrode 181, the first drain electrode 182, the second source electrode 183, and the second drain electrode 184 may be spaced apart from each other. The first source electrode 181 and the first drain electrode 182 may pass through the first gate insulating layer 130, the second gate insulating layer 150, and the insulating interlayer 170, and may be connected to the first active pattern 121. The second source electrode 183 and the second drain electrode 184 may pass through the first gate insulating layer 130, the second gate insulating layer 150, and the insulating interlayer 170, and may be connected to the second active pattern 122.

[0079] The first source electrode 181, the first drain electrode 182, the second source electrode 183, and the second drain electrode 184 may comprise metals, such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), scandium (Sc), alloys thereof, or nitrides thereof. According to some exemplary embodiments, the first source electrode 181, the first drain electrode 182, the second source electrode 183, and the second drain electrode 184 may comprise the same material. The first source electrode 181 and the first drain electrode 182 may form a first transistor TR1 together with the first active pattern 121, the first gate insulating layer 130, and the first gate electrode 141. The second source electrode 183 and the second drain electrode 184 may form a second transistor TR2 together with the second active pattern 122, the first gate insulating layer 130, and the second gate electrode 142.

[0080] A planarization layer 190 may be placed on the first source electrode 181, the first drain electrode 182, the second source electrode 183, and the second drain electrode 184. The planarization layer 190 may cover the first source electrode 181, the first drain electrode 182, the second source electrode 183, and the second drain electrode 184, and may be formed on the insulating interlayer 170. The planarization layer 190 may protect the first transistor TR1 and the second transistor TR2, and may provide a planarized surface for the first electrode 200. The planarization layer 190 may include an organic insulating material, such as acrylic resin, polyimide resin, siloxane resin, benzocyclobutene (BCB), etc.

[0081] An organic light-emitting diode (OLED) electrically connected to a first transistor TR1 can be provided on a planarization layer 190. The OLED may include a first electrode 200, an intermediate layer 220, and a second electrode 230.

[0082] The first electrode 200 may be placed on the planarization layer 190. The first electrode 200 may pass through the planarization layer 190 and may be connected to the first drain electrode 182. The first electrode 200 may include a transparent conductive material, such as indium tin oxide (ITO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide, tin oxide, etc., and / or metals, such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, neodymium, etc. The first electrode 200 may serve as the anode of an organic light-emitting diode (OLED).

[0083] A pixel defining layer 210 may be placed on the first electrode 200. The pixel defining layer 210 may cover the edge of the first electrode 200 and may be formed on the planarization layer 190. The pixel defining layer 210 may have an opening that exposes the central portion of the first electrode 200 to define a pixel, and may increase the distance between the edge of the first electrode 200 and the second electrode 230 above the first electrode 200 to prevent the occurrence of arcing or the like at the edge of the first electrode 200. The pixel defining layer 210 may include an organic insulating material, such as an acrylic resin, a polyimide resin, a siloxane resin, benzocyclobutene (BCB), or an inorganic insulating material.

[0084] Intermediate layer 220 may be disposed on the first electrode 200 and pixel defining layer 210. Intermediate layer 220 may include an emitter layer comprising a low-molecular-weight organic material or a high-molecular-weight organic material. According to some example embodiments, intermediate layer 220 may further include a hole injection layer (“HIL”), a hole transport layer (“HTL”), an electron transport layer (“ETL”), and / or an electron injection layer (“EIL”) disposed on or below the emitter layer.

[0085] The second electrode 230 can be placed on the intermediate layer 220. The second electrode 230 may include metals such as lithium (Li), calcium (Ca), lithium fluoride-calcium (LiF-Ca), lithium fluoride-aluminum (LiF-Al), Al, Mg, Ag, Cr, W, Mo, Ti, and their alloys. Alternatively, the second electrode 230 may include transparent conductive materials such as ITO, IZO, ZTO, zinc oxide, tin oxide, etc. The second electrode 230 can serve as the cathode of an organic light-emitting diode (OLED).

[0086] Figure 3 A cross-sectional view of the first gate insulating layer according to some example embodiments is shown. Figure 3 Can be shown Figure 2 The cross-sectional structure of the first gate insulating layer 130.

[0087] refer to Figure 3 The first gate insulating layer 130 may include a first high dielectric constant insulating layer 131, a first inorganic insulating layer 132, and a second high dielectric constant insulating layer 133.

[0088] A first high dielectric constant insulating layer 131 may be placed on the first active pattern 121. The first high dielectric constant insulating layer 131 may cover the first active pattern 121 and may be formed on the buffer layer 110. The first high dielectric constant insulating layer 131 may include a material with a relatively high dielectric constant, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), etc.

[0089] According to some exemplary embodiments, the first high-dielectric-constant insulating layer 131 may be patterned to overlap with the first active pattern 121. In other words, the first high-dielectric-constant insulating layer 131 may not overlap with the second active pattern 122. For example, a material having a relatively high dielectric constant may be deposited on the buffer layer 110 by atomic layer deposition (ALD), chemical vapor deposition (CVD), etc., and may be patterned to form the first high-dielectric-constant insulating layer 131, on which the first active pattern 121 and the second active pattern 122 are formed.

[0090] A first inorganic insulating layer 132 may be placed on a first high-dielectric-constant insulating layer 131. The first inorganic insulating layer 132 may cover the second active pattern 122 and the first high-dielectric-constant insulating layer 131, and may be formed on a buffer layer 110. The first inorganic insulating layer 132 may overlap with the first active pattern 121 and the second active pattern 122. The first inorganic insulating layer 132 may comprise a material having a relatively low dielectric constant, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x Ny Therefore, the dielectric constant of the first inorganic insulating layer 132 can be less than the dielectric constant of the first high dielectric constant insulating layer 131.

[0091] The thickness of the first inorganic insulating layer 132 can be greater than the thickness of the first high-dielectric-constant insulating layer 131. In other words, the thickness of the first high-dielectric-constant insulating layer 131 can be less than the thickness of the first inorganic insulating layer 132. For example, the thickness of the first high-dielectric-constant insulating layer 131 can be approximately... Furthermore, the thickness of the first inorganic insulating layer 132 can be approximately [missing information]. to approximately

[0092] A second high dielectric constant insulating layer 133 may be placed on the first inorganic insulating layer 132. The second high dielectric constant insulating layer 133 may include a material with a relatively high dielectric constant, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), etc. Therefore, the dielectric constant of the second high dielectric constant insulating layer 133 may be greater than the dielectric constant of the first inorganic insulating layer 132.

[0093] According to some exemplary embodiments, the second high-dielectric-constant insulating layer 133 may be patterned to overlap with the second active pattern 122. In other words, the second high-dielectric-constant insulating layer 133 may not overlap with the first active pattern 121. For example, a material having a relatively high dielectric constant may be deposited on the first inorganic insulating layer 132 by atomic layer deposition (ALD), chemical vapor deposition (CVD), etc., and may be patterned to form the second high-dielectric-constant insulating layer 133.

[0094] The second high-dielectric-constant insulating layer 133 can be formed with a thickness less than that of the first inorganic insulating layer 132. In other words, the thickness 133 of the second high-dielectric-constant insulating layer can be less than the thickness of the first inorganic insulating layer 132. For example, the thickness 133 of the second high-dielectric-constant insulating layer can be approximately...

[0095] The first high-dielectric-constant insulating layer 131 can be patterned to overlap with the first active pattern 121, such that the first high-dielectric-constant insulating layer 131 and the first inorganic insulating layer 132 can be sequentially stacked between the first active pattern 121 and the first gate electrode 141. The first high-dielectric-constant insulating layer 131 can be placed at the interface between the first gate insulating layer 130 and the first active pattern 121, thereby increasing the driving range of the first transistor TR1.

[0096] The second high-dielectric-constant insulating layer 133 can be patterned to overlap with the second active pattern 122, so that the first inorganic insulating layer 132 and the second high-dielectric-constant insulating layer 133 can be sequentially stacked between the second active pattern 122 and the second gate electrode 142. This increases the capacitance between the second active pattern 122 and the second gate electrode 142, thereby increasing the driving speed of the second transistor TR2.

[0097] Figure 4 To show Figure 2 A graph showing the characteristics of the transistor. Curve A illustrates the characteristics of the transistor according to the comparative example, where the first gate insulating layer includes approximately... The voltage (V)-current (I) characteristics of a transistor with a silicon oxide layer of approximately [thickness] are shown, and curve B illustrates the voltage (V)-current (I) characteristics of a first gate insulating layer 130 according to some exemplary embodiments of the invention. A zirconium oxide layer of approximately [thickness value missing] and having [value missing] The voltage (V)-current (I) characteristics of the first transistor TR1, which has a silicon oxide layer of approximately [thickness missing]. Curve C illustrates the voltage (V)-current (I) characteristics of [thickness missing] in some exemplary embodiments of the invention, wherein the first gate insulating layer 130 comprises [thickness missing]... A zirconium oxide layer of approximately [thickness value missing] and having [value missing] The voltage (V)-current (I) characteristics of the first transistor TR1 with a silicon oxide layer of approximately [thickness value missing] are shown, and curve D illustrates the voltage (V)-current (I) characteristics of the first transistor TR1 with a silicon oxide layer of approximately [thickness value missing] according to some exemplary embodiments of the invention. A silicon oxide layer of approximately [thickness] and having [a certain thickness] Voltage (V)-current (I) characteristics of the second transistor TR2 with a zirconium oxide layer of a certain thickness.

[0098] refer to Figure 4 The slope of the voltage (V)-current (I) curve of the first transistor TR1 according to some exemplary embodiments may be less than the slope of the voltage (V)-current (I) curve of the transistor according to the comparative example. Therefore, the driving range of the first transistor TR1 according to some exemplary embodiments may be greater than the driving range of the transistor according to the comparative example. Generally, it is advantageous for the driving transistor to have a large driving range to express various gray levels. The first high dielectric constant insulating layer 131 and the first inorganic insulating layer 132 may be formed between the first active pattern 121 and the first gate electrode 141 of the first transistor TR1 used as the driving transistor according to this embodiment, thereby increasing the driving range of the first transistor TR1 and enabling the display device to display more detailed colors.

[0099] The slope of the voltage (V)-current (I) curve of the second transistor TR2 according to some exemplary embodiments can be greater than the slope of the voltage (V)-current (I) curve of the transistor according to the comparative example. Generally, it is advantageous for the voltage-current curve of the switching transistor to have a large slope for fast drive speed. The first inorganic insulating layer 132 and the second high dielectric constant insulating layer 133 can be formed between the second active pattern 122 and the second gate electrode 142 of the second transistor TR2 used as a switching transistor according to this embodiment, thereby increasing the drive speed of the second transistor TR2.

[0100] Figure 5 A cross-sectional view of the second gate insulating layer according to some example embodiments is shown. Figure 5 Can be shown Figure 2 Example of the cross-sectional structure of the second gate insulating layer 150.

[0101] refer to Figure 5 The second gate insulating layer 150 may include a second inorganic insulating layer 151 and a third high dielectric constant insulating layer 152.

[0102] A second inorganic insulating layer 151 may be disposed on the first gate electrode 141 and the second gate electrode 142. The second inorganic insulating layer 151 may cover the first gate electrode 141 and the second gate electrode 142, and may be formed on the first gate insulating layer 130. The second inorganic insulating layer 151 may overlap with the first gate electrode 141 and the second gate electrode 142. The second inorganic insulating layer 151 may comprise a material having a relatively low dielectric constant, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y )wait.

[0103] A third high dielectric constant insulating layer 152 may be placed on the second inorganic insulating layer 151. The third high dielectric constant insulating layer 152 may include a material with a relatively high dielectric constant, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), etc. Therefore, the dielectric constant of the third high dielectric constant insulating layer 152 may be greater than the dielectric constant of the second inorganic insulating layer 151.

[0104] The third high-dielectric-constant insulating layer 152 can be formed with a thickness less than that of the second inorganic insulating layer 151. In other words, the thickness of the third high-dielectric-constant insulating layer 152 can be less than the thickness of the second inorganic insulating layer 151. For example, the thickness of the second inorganic insulating layer 151 can be approximately... to approximately Furthermore, the thickness of the third high dielectric constant insulating layer 152 can be approximately [missing information].

[0105] According to some exemplary embodiments, the third high-dielectric-constant insulating layer 152 may be formed entirely on the first gate electrode 141 and the second gate electrode 142. In other words, the third high-dielectric-constant insulating layer 152 may overlap with the first gate electrode 141 and the second gate electrode 142.

[0106] Figure 6 A cross-sectional view of the second gate insulating layer according to some example embodiments is shown. Figure 6 Can be shown Figure 2 Another example of the cross-sectional structure of the second gate insulating layer 150.

[0107] refer to Figure 6 According to some exemplary embodiments, the third high-dielectric-constant insulating layer 152 may be patterned to overlap with the first gate electrode 141. In other words, the third high-dielectric-constant insulating layer 152 may not overlap with the second gate electrode 142. For example, a material having a relatively high dielectric constant may be deposited on the second inorganic insulating layer 151 by atomic layer deposition (ALD), chemical vapor deposition (CVD), etc., and may be patterned to form the third high-dielectric-constant insulating layer 152.

[0108] When a third high-dielectric-constant insulating layer 152 is formed on the second inorganic insulating layer 151, excluding the portion between the first gate electrode 141 and the capacitor electrode 160, the leakage current through the third high-dielectric-constant insulating layer 152 can be increased. Therefore, the third high-dielectric-constant insulating layer 152 can be patterned to be formed between the first gate electrode 141 and the capacitor electrode 160, thereby not increasing the leakage current through the second gate insulating layer 150.

[0109] According to some exemplary embodiments, a second gate insulating layer 150 having a relatively high dielectric constant can be placed between electrodes 141 and 160 of capacitor CAP, thereby increasing the capacitance of capacitor CAP. Therefore, the response speed of pixel PX can be increased, and ghosting and flicker of the display device can be reduced.

[0110] Figure 7A and Figure 7B The diagrams illustrate the afterimage of a display device according to a comparative example and the afterimage of a display device according to some exemplary embodiments of the present invention.

[0111] Generally speaking, when a specific grayscale data is applied to a pixel that displays black or white, the afterimage can be evaluated experimentally by measuring the time required for the pixel to emit light with a brightness corresponding to the specific grayscale data. Figure 7A The measurement results of the afterimage of the display device according to the comparative example are shown, and Figure 7B The measurement results of the afterimage of a display device according to some example embodiments are shown.

[0112] refer to Figure 7A and Figure 7B The time it takes for the persistence index (e.g., the difference in brightness between black or white and the brightness of data corresponding to a specific grayscale) to reach a predetermined value (e.g., 0.004) is approximately 5.3 seconds in a display device according to a comparative example, and approximately 2.0 seconds in a display device according to some example embodiments. According to some example embodiments, a second gate insulating layer 150 having a relatively high dielectric constant may be formed between the electrodes 141 and 160 of the capacitor CAP, thereby increasing the capacitance of the capacitor CAP and reducing the persistence of the display device.

[0113] Table 1

[0114]

[0115] Table 1 illustrates the flicker of a display device according to a comparative example and the flicker of a display device according to some exemplary embodiments of the present invention. For example, Table 1 shows the flicker index of the display device according to the comparative example and the display device according to some exemplary embodiments for multiple gray levels and multiple frequencies.

[0116] Referring to Table 1, at the same grayscale and frequency, the flicker index of the display device according to some example embodiments can be less than the flicker index of the display device according to the comparative example. As the flicker index decreases, flicker becomes undetectable. According to some example embodiments, a second gate insulating layer 150 having a relatively high dielectric constant can be formed between the electrodes 141 and 160 of the capacitor CAP, thereby increasing the capacitance of the capacitor CAP and reducing the flicker of the display device.

[0117] Figure 8 A cross-sectional view of a display device according to some example embodiments is shown. For example, Figure 8 Can be shown Figure 1 Another example of the cross-sectional structure of a medium pixel PX.

[0118] refer to Figure 8 The described display device is compatible with the reference. Figure 2 The described display device is essentially the same or similar, except for the addition of a fourth high-dielectric-constant insulating layer 105. Therefore, it is not necessary to repeat the reference. Figure 2 Those display devices described that are substantially the same or similar to those in the reference Figure 8 A detailed description of the components of the described display device.

[0119] refer to Figure 8The fourth high dielectric constant insulating layer 105 may be additionally placed between the substrate 100 and the buffer layer 110. The fourth high dielectric constant insulating layer 105 may be entirely placed on the substrate 100 and may overlap with the first active pattern 121 and the second active pattern 122.

[0120] The fourth high-dielectric-constant insulating layer 105 may include materials with relatively high dielectric constants, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), etc. Therefore, the dielectric constant of the fourth high-dielectric-constant insulating layer 105 may be greater than that of materials including those with relatively low dielectric constants (such as silicon oxide (SiO2)). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The dielectric constant of the buffer layer 110 (etc.).

[0121] During the formation of the display device, a support substrate for supporting the substrate 100 can be formed beneath the substrate 100, and charges can penetrate from the support substrate into the substrate 100. Furthermore, when the substrate 100 comprises an organic material, charges can be stored in the substrate 100. In this case, an electric field can be formed between the charged substrate 100 and the active patterns 121 and 122, and image retention can occur on the display device. However, in the display device according to some example embodiments, a fourth high-dielectric-constant insulating layer 105 having a relatively high dielectric constant can be formed between the substrate 100 and the buffer layer 110, and the fourth high-dielectric-constant insulating layer 105 can reduce the electric field between the substrate 100 and the active patterns 121 and 122. Therefore, image retention on the display device according to this embodiment can be reduced.

[0122] The fourth high-dielectric-constant insulating layer 105 can be deposited on the substrate 100 by atomic layer deposition (ALD) or the like, thus allowing for a relatively high density. For example, the density of the fourth high-dielectric-constant insulating layer 105 can be greater than that of the buffer layer 110. The relatively high density of the fourth high-dielectric-constant insulating layer 105 can effectively block impurities that penetrate through the substrate 100. For example, by blocking charged impurities that penetrate through the substrate 100, the electric field between the substrate 100 and the active patterns 121 and 122 can be reduced, thereby reducing image retention on the display device.

[0123] Figure 9 A cross-sectional view of a substrate according to some example embodiments is shown. Figure 9 Can be shown Figure 8 Example of the cross-sectional structure of the middle substrate 100.

[0124] refer to Figure 9 According to some example embodiments, the substrate 100 may have a multilayer structure, which includes a first organic layer 101, a second organic layer 103 disposed on the first organic layer 101, and an inorganic layer 102 disposed between the first organic layer 101 and the second organic layer 103.

[0125] The first organic layer 101 and the second organic layer 103 may comprise plastics, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc. The first organic layer 101 and the second organic layer 103 may be flexible.

[0126] Inorganic layer 102 may include inorganic insulating materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y (e.g., and / or amorphous silicon). The inorganic layer 102 prevents impurities from penetrating through the substrate 100.

[0127] According to some exemplary embodiments, barrier layer 108 may be additionally placed between fourth high-dielectric-constant insulating layer 105 and buffer layer 110. Barrier layer 108 may include inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y Barrier layer 108 prevents impurities from penetrating through substrate 100.

[0128] Figure 10 A cross-sectional view of a substrate according to some example embodiments is shown. Figure 10 Can be shown Figure 8 Another example of the cross-sectional structure of the middle substrate 100.

[0129] refer to Figure 10 According to some exemplary embodiments, substrate 100 may have a single-layer structure including an organic layer. The organic layer may include plastics such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc. The organic layer may be flexible.

[0130] A fourth high-dielectric-constant insulating layer 105 with relatively high density can be formed between the substrate 100 and the buffer layer 110, thereby blocking impurities that penetrate through the substrate 100. Because the inorganic layer that can block impurities from penetrating into the substrate 100 is omitted, the substrate 100 can have a single-layer structure including an organic layer, thus reducing the thickness of the substrate 100.

[0131] Figure 11 The diagram illustrates image retention of a display device according to a comparative example and image retention of a display device according to some exemplary embodiments of the present invention.

[0132] Generally, when a black or white image is displayed after a predetermined time has elapsed since a checkerboard pattern was displayed on a display device, image retention can be evaluated experimentally by measuring the brightness difference between black and white over time. Figure 11 The results show the measurement of the brightness difference between black and white over time when a checkerboard pattern is displayed for 20 seconds on a display device according to a comparative example and a display device according to some example embodiments, and then a white image is displayed.

[0133] refer to Figure 11 After displaying a white image, the brightness difference of the display device according to some example embodiments can be less than that of the display device according to the comparative example. As the brightness difference between black and white decreases, image retention can be reduced. A fourth high-dielectric-constant insulating layer 105 with relatively high density can be formed between the substrate 100 and the buffer layer 110 of the display device according to some example embodiments, thereby reducing the electric field between the substrate 100 and the active patterns 121 and 122, and blocking impurities penetrating through the substrate 100. Therefore, image retention of the display device can be reduced.

[0134] Figure 12 A circuit diagram illustrating pixels included in a display device according to some example embodiments.

[0135] refer to Figure 12 Each of the pixels PX included in a display device according to some example embodiments may include a driving transistor TDR, a switching transistor TSW, a compensation transistor TCM, a first initialization transistor TIN1, a second initialization transistor TIN2, a first emission control transistor TEC1, a second emission control transistor TEC2, a storage capacitor CST, and an organic light-emitting diode OLED.

[0136] The gate electrode of the driving transistor TDR is electrically connected to the drain electrode of the first initialization transistor TIN1, the drain electrode of the compensation transistor TCM, and the first electrode of the storage capacitor CST. The source electrode of the driving transistor TDR receives the driving voltage ELVDD via the first emitter control transistor TEC1, and the drain electrode of the driving transistor TDR is electrically connected to the anode of the organic light-emitting diode OLED via the second emitter control transistor TEC2. The driving transistor TDR can receive the data signal DT from the switching transistor TSW and can supply driving current to the organic light-emitting diode OLED.

[0137] The gate electrode of the switching transistor TSW can receive the scan signal SC. The source electrode of the switching transistor TSW can receive the data signal DT, and the drain electrode of the switching transistor TSW can be electrically connected to the source electrode of the driving transistor TDR. The switching transistor TSW can be turned on in response to the scan signal SC and can transmit the data signal DT to the source electrode of the driving transistor TDR.

[0138] The gate electrode of the compensation transistor TCM can receive the scan signal SC. The source electrode of the compensation transistor TCM can be electrically connected to the drain electrode of the driving transistor TDR, and the drain electrode of the compensation transistor TCM can be electrically connected to the gate electrode of the driving transistor TDR. The compensation transistor TCM can be turned on in response to the scan signal SC, and can be diode-connected to the gate and drain electrodes of the driving transistor TDR.

[0139] The gate electrode of the first initialization transistor TIN1 can receive the previous scan signal PSC. The source electrode of the first initialization transistor TIN1 can receive the initialization voltage VINT, and the drain electrode of the first initialization transistor TIN1 can be electrically connected to the gate electrode of the driving transistor TDR. The first initialization transistor TIN1 can be turned on in response to the previous scan signal PSC and can transmit the initialization voltage VINT to the gate electrode of the driving transistor TDR.

[0140] The gate electrode of the second initialization transistor TIN2 can receive the previous scan signal PSC. The source electrode of the second initialization transistor TIN2 can receive the initialization voltage VINT, and the drain electrode of the second initialization transistor TIN2 can be electrically connected to the anode of the organic light-emitting diode (OLED). The second initialization transistor TIN2 can be turned on in response to the previous scan signal PSC and can transmit the initialization voltage VINT to the anode of the OLED.

[0141] The gate electrode of the first emitter control transistor TEC1 can receive the emitter control signal EMC. The source electrode of the first emitter control transistor TEC1 can receive the drive voltage ELVDD, and the drain electrode of the first emitter control transistor TEC1 can be electrically connected to the source electrode of the drive transistor TDR.

[0142] The gate electrode of the second emitter control transistor TEC2 can receive the emitter control signal EMC. The source electrode of the second emitter control transistor TEC2 can be electrically connected to the drain electrode of the driving transistor TDR, and the drain electrode of the second emitter control transistor TEC2 can be electrically connected to the anode of the organic light-emitting diode OLED. The first emitter control transistor TEC1 and the second emitter control transistor TEC2 can be turned on in response to the emitter control signal EMC, and the driving voltage ELVDD can be transmitted to the organic light-emitting diode OLED, so that the driving current can pass through the organic light-emitting diode OLED.

[0143] The first electrode of the storage capacitor CST is electrically connected to the gate electrode of the driving transistor TDR, and the second electrode of the storage capacitor CST can receive the driving voltage ELVDD. When the switching transistor TSW is turned off, the storage capacitor CST can maintain the voltage between the gate electrode and the source electrode of the driving transistor TDR.

[0144] The anode of an organic light-emitting diode (OLED) can be electrically connected to the drain electrode of a driving transistor TDR via a second emission control transistor TEC2, and the cathode of the OLED can receive a common voltage ELVSS. The OLED can emit light based on the driving current supplied from the driving transistor TDR.

[0145] refer to Figure 2 or Figure 8 The first transistor TR1, the second transistor TR2, and the capacitor CAP of the described display device can respectively correspond to Figure 12 The driving transistor TDR, the switching transistor TSW, and the storage capacitor CST are included. However, embodiments according to this disclosure are not limited thereto, and each of the first transistor TR1 and the second transistor TR2 may correspond to... Figure 12 The compensation transistor TCM, the first initialization transistor TIN1, the second initialization transistor TIN2, the first emitter control transistor TEC1 or the second emitter control transistor TEC2 are included.

[0146] The display device according to the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0147] Although a display device according to some exemplary embodiments has been described with reference to the accompanying drawings, the embodiments shown are exemplary and may be modified and altered by those skilled in the art without departing from the spirit of the technology described in the following claims and their equivalents.

Claims

1. A display device comprising: a substrate; a buffer layer over the substrate; a first active pattern and a second active pattern over the buffer layer and spaced apart from each other; a first gate insulating layer over the first active pattern and the second active pattern; a first gate electrode and a second gate electrode over the first gate insulating layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulating layer over the first gate electrode and the second gate electrode; and a capacitor electrode over the second gate insulating layer, the capacitor electrode overlapping the first gate electrode, wherein a dielectric constant of the first gate insulating layer is greater than a dielectric constant of the buffer layer, wherein the first gate insulating layer comprises a first high dielectric constant insulating layer, the first high dielectric constant insulating layer is patterned to overlap the first active pattern, and has a width wider than a width of the first active pattern.

2. The display device according to claim 1, wherein the first gate insulating layer further comprises an inorganic insulating layer over the first high dielectric constant insulating layer and having a dielectric constant smaller than a dielectric constant of the first high dielectric constant insulating layer.

3. The display device according to claim 2, wherein the first gate insulating layer further comprises a second high dielectric constant insulating layer over the inorganic insulating layer and having a dielectric constant greater than a dielectric constant of the inorganic insulating layer.

4. The display device according to claim 3, wherein the second high dielectric constant insulating layer is patterned to overlap the second active pattern.

5. A display device comprising: a substrate; a buffer layer over the substrate; a first active pattern and a second active pattern over the buffer layer and spaced apart from each other; a first gate insulating layer over the first active pattern and the second active pattern; a first gate electrode and a second gate electrode over the first gate insulating layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulating layer over the first gate electrode and the second gate electrode; and a capacitor electrode over the second gate insulating layer, the capacitor electrode overlapping the first gate electrode, wherein a dielectric constant of the second gate insulating layer is greater than a dielectric constant of the buffer layer, wherein the second gate insulating layer comprises a high dielectric constant insulating layer, the high dielectric constant insulating layer is patterned to overlap the first gate electrode, and has a width wider than a width of the first gate electrode.

6. The display device according to claim 5, wherein the second gate insulating layer further comprises an inorganic insulating layer, a dielectric constant of the inorganic insulating layer is smaller than a dielectric constant of the high dielectric constant insulating layer.

7. The display device according to any one of claims 1 to 6, further comprising: a third high dielectric constant insulating layer over the substrate, wherein the buffer layer is over the third high dielectric constant insulating layer, and wherein a dielectric constant of the third high dielectric constant insulating layer is greater than a dielectric constant of the buffer layer. 8.The display device of claim 7, wherein the third high dielectric constant insulating layer comprises at least one of zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and niobium oxide (Nb2O5). 9.The display device of claim 7, wherein a density of the third high dielectric constant insulating layer is greater than a density of the buffer layer.

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