Quickly enabled power supply

Abstract

A method for fast enabling a power supply includes conducting a first current through a first branch, the first branch including a first transistor connected in series with a first switch in response to enabling the first switch by an enable signal. A first charge is removed from a bias rail through a first capacitance between a first gate and a first source of the first transistor. A second current is conducted through a second branch, the second branch including the second switch connected in series with a second transistor in response to enabling the second switch by the enable signal. A second charge is added to the bias rail through a second capacitance between a second drain and a second gate of the second transistor, wherein the first gate and the second gate are connected to the bias rail and biased by a mirror reference voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to switchable power supplies, and more specifically to power supplies that can be quickly started while minimizing the settling time. BACKGROUND

[0002] Low power integrated circuits ("integrated circuits, ICs") often use groups of circuits or blocks that are periodically enabled and disabled to save power. For example, in a DC / DC power converter operating in a Pulse Frequency Modulation (PFM) mode, at each clock cycle, the circuit blocks are switched between an active state and an inactive state. Generally, these circuit blocks include digital circuits that are turned on or off, as well as analog circuits that have power supplies that are also switched. For high performance analog circuits that require fast and stable response, these power supplies must be quickly turned on and stabilized to a stable value in a short period of time.

[0003] Prior attempts to address the problem of quickly enabling power supplies include using current control circuits that waste current and are not suitable for low power circuits. Another solution utilizes a closed loop circuit, which reduces the settling time of the output current and in some cases consumes a large amount of quiescent power. Finally, another prior solution uses a large capacitor that is area large, slow, and often sensitive to load conditions. SUMMARY

[0004] According to a first aspect of the present invention, there is provided a fast- enabled power supply, comprising:

[0005] a bias chain configured to generate a mirrored reference voltage on a bias rail;

[0006] a first branch comprising a first transistor having a first drain connected to a first node, a first source connected to a first switch, and a first gate connected to the bias rail, the first switch configured to short the first source to a second node in response to an enable signal;

[0007] a first capacitor between the first gate and the first source;

[0008] a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to the second node, and a second gate connected to the bias rail, the second switch configured to short the second drain to the first node in response to the enable signal; and

[0009] a second capacitor between the second drain and the second gate, wherein a first charge removed from the bias rail by the first capacitor is canceled by a second charge added to the bias rail by the second capacitor in response to the enable signal.

[0010] According to one or more embodiments, the first charge is equal to the second charge, and a first width of the first transistor divided by a second width of the second transistor defines an optimal transistor ratio.

[0011] According to one or more embodiments, the optimal transistor ratio is one-half, wherein each of the transistors of the fast-enabled power supply comprises an n-channel field effect transistor.

[0012] According to one or more embodiments, the first switch comprises an n-channel field effect transistor comprising: a first switch drain connected to the first source; a first switch gate connected to the enable signal, the enable signal configured to enable the first switch; and a first switch source connected to the second node.

[0013] According to one or more embodiments, the second switch comprises a high-voltage n-channel field effect transistor comprising: a second switch drain connected to the first node; a second switch gate connected to the enable signal, the enable signal configured to enable the second switch; and a second switch source connected to the second drain.

[0014] According to one or more embodiments, the bias chain comprises a bias transistor comprising a bias drain connected to a power supply, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

[0015] According to one or more embodiments, further comprising a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has a same voltage drop as the first switch when the first switch is enabled.

[0016] According to one or more embodiments, further comprising a protection device connected between the first node and the first drain, wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

[0017] According to one or more embodiments, further comprising a compensation device connected between the second source and the second node, wherein the compensation device has a same voltage drop as the first switch when the first switch is enabled.

[0018] According to one or more embodiments, the first capacitance is a first parasitic capacitance of the first transistor, and the second capacitance is a second parasitic capacitance of the second transistor.

[0019] According to a second aspect of the application, there is provided a method for fast enabling a power supply, comprising:

[0020] generating a mirrored reference voltage on a bias rail;

[0021] conducting a first current through a first branch between a first node and a second node, the first branch comprising a first transistor connected in series with a first switch in response to the first switch being enabled by an enable signal;

[0022] removing a first charge from the bias rail through a first capacitance between a first gate and a first source of the first transistor, wherein the first gate is biased by the mirrored reference voltage;

[0023] conducting a second current through a second branch between the first node and the second node, the second branch comprising the second switch connected in series with a second transistor in response to the second switch being enabled by the enable signal; and

[0024] adding a second charge to the bias rail through a second capacitance between a second drain and a second gate of the second transistor, wherein the second gate is biased by the mirrored reference voltage.

[0025] According to one or more embodiments, further comprising determining an optimal transistor ratio by dividing a first width of the first transistor by a second width of the second transistor, wherein the optimal transistor ratio results in the first charge being equal to the second charge.

[0026] According to one or more embodiments, determining the optimal transistor ratio results in the first width being half of the second width, wherein each of the transistors of the power supply comprises an n-channel field effect transistor.

[0027] According to one or more embodiments, further comprising compensating for an impedance of the second switch by a protection device between the first node and the first drain, wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

[0028] According to one or more embodiments, further comprising compensating for an impedance of the first switch by a compensation device between the second source and the second node, wherein the compensation device has a same voltage drop as the first switch when the first switch is enabled.

[0029] According to one or more embodiments, generating the mirror reference voltage comprises supplying a current through a bias transistor, the bias transistor comprising a bias drain connected to a power supply, a bias gate connected to the bias drain and to the bias rail, and a bias source connected to the second node.

[0030] According to one or more embodiments, further comprising compensating for an impedance of the first switch by a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has the same voltage drop as the first switch when the first switch is enabled.

[0031] According to a third aspect of the invention, there is provided a fast- enabling power supply, comprising:

[0032] a first branch comprising a first transistor having a first drain connected to a protection device, a first source connected to a first switch, and a first gate connected to a bias rail, the protection device being connected to a first node, the first switch being configured to short the first source to a second node in response to an enable signal;

[0033] a first parasitic capacitance between the first gate and the first source;

[0034] a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to a compensation device, and a second gate connected to the bias rail, the compensation device being connected to the second node, the second switch being configured to short the second drain to the first node in response to the enable signal; and

[0035] a second parasitic capacitance between the second drain and the second gate, wherein in response to the enable signal, a first charge removed from the bias rail by the first capacitance is cancelled by a second charge added to the bias rail by the second capacitance.

[0036] According to one or more embodiments, the protection device has the same voltage drop as the second switch when the second switch is enabled.

[0037] According to one or more embodiments, the compensation device has the same voltage drop as the first switch when the first switch is enabled. BRIEF DESCRIPTION OF DRAWINGS

[0038] The invention is illustrated by way of example and not limitation in the figures in which like references indicate similar elements. Elements in the figures are shown for simplicity and clarity and have not necessarily been drawn to scale.

[0039] Figure 1 This is a schematic diagram of a fast-start power supply according to an exemplary embodiment of the present disclosure.

[0040] Figure 2 This is a schematic diagram of a fast-start power supply according to an exemplary embodiment of the present disclosure.

[0041] Figure 3 Is using Figure 2 A graphical view of the timing waveform of the enable signal in an embodiment.

[0042] Figure 4 Is using Figure 2 A graphical view of the timing waveform of the current generated in the embodiment.

[0043] Figure 5 It is a graphical view of the timing waveform of the enable signal without using a fast-start power supply.

[0044] Figure 6 It is a graphical view of the timing waveform of the current generated without using a fast-start power supply.

[0045] Figure 7 This is a flowchart representation of a method for generating a fast-enabled power supply according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0046] The various embodiments described herein provide fast enablement of switching power supplies to minimize settling time and thereby provide a stable and accurate current output more quickly. Specifically, the circuits and methods of embodiments of this disclosure use two switching current branches combined to provide a stable power output with negligible area increase and minimal impact on quiescent current. Each branch, referred to as a bias current branch, includes a switched drain or switched source of a corresponding transistor to counteract charge removal (e.g., mirror reference) on the bias line, while charge injection occurs on the same bias line. Counteracting charge removal, wholly or partially, by charge injection involves designing the corresponding transistor on each branch to have an optimal transistor ratio. In one embodiment, the width of the corresponding transistor defines the optimal transistor ratio, which in turn defines the corresponding parasitic capacitance of the transistor. Charge removal or injection occurs through these parasitic capacitances in response to the corresponding transistor enabling the current branch.

[0047] Figure 1An embodiment 10 of a fast-start power supply according to the present disclosure is shown. Embodiment 10 includes a bias chain 12 connected between a bias power supply 14 and a second node 16. A power supply 18 is connected between the bias power supply 14 and a bias transistor 20. The bias transistor 20 includes a bias drain 22 connected to the power supply 18, a bias source 24 connected to the second node 16, and a bias gate 26 connected to the bias drain 22 and a bias rail 28.

[0048] Embodiment 10 further includes a first branch 30 between the first node 32 and the second node 16. The first branch 30 includes a first transistor 40. The first transistor 40 includes a first drain 42 connected to the first node 32, a first source 44 connected to the first switch 60, and a first gate 46 connected to the bias rail 28. The first transistor 40 also includes a first capacitance 50 (CGS) between the first gate 46 and the first source 44. In some embodiments, the first capacitance 50 is a parasitic capacitance of the first transistor and is therefore scaled proportionally to a first width (e.g., channel width) of the first transistor 40. The first switch 60 includes a first switch drain 62 connected to the first source 44, a first switch source 64 connected to the second node 16, and a first switch gate 66 connected to an enable signal 68.

[0049] Embodiment 10 further includes a second branch 70 between the first node 32 and the second node 16. The second branch 70 includes a second transistor 80. The second transistor 80 includes a second drain 82 connected to the second switch 90, a second source 84 connected to the second node 16, and a second gate 86 connected to the bias rail 28. In one embodiment, the second switch 90 includes a high-voltage transistor. The second transistor 80 also includes a second capacitor 88 (CDG) between the second drain 82 and the second gate 86. In some embodiments, the second capacitor 88 is a parasitic capacitance of the second transistor and is therefore scaled proportionally to a second width (e.g., channel width) of the second transistor 80. The second switch 90 includes a second switch source 94 connected to the second drain 82, a second switch drain 92 connected to the first node 32, and a first switch gate 96 connected to an enable signal 68.

[0050] The first branch 30 and the second branch 70 are mirrored to the bias chain 12 and complementaryly compensate for the voltage offset on the bias rail 28, thereby producing a faster settling time for the mirrored reference voltage on the bias rail 28 with negligible overshoot. This compensation occurs because the first source 44 of the first branch 30 performs a negative switch, thereby drawing charge from the bias rail 28 through the first capacitor 50, while the second drain 82 of the second branch 70 performs a positive switch, thereby adding or injecting charge into the bias rail 28 through the second capacitor 88. In one example, Embodiment 10 provides a 100µA current through the first node 32 from the combination of the first branch 30 and the second branch 70, which stabilizes to an acceptable level within 10 nanoseconds.

[0051] By appropriately dividing the size, voltage swing, and parasitic capacitance of the two branches, the charge removed from the bias rail 28 by the first branch 30 will substantially offset the charge added to the bias rail 28 by the second branch 70. This appropriate division defines an optimal transistor ratio between the first transistor 40 and the second transistor 80. In one example embodiment, the optimal transistor ratio is determined by a first width of the first transistor 40, which is approximately half the second width of the second transistor 80. In one example, the first transistor 40 comprises 16 instances of transistors connected in parallel, while the second transistor 80 comprises 33 instances of the same transistor size connected in parallel. In this context, "connected in parallel" means that each of the drains is connected together, each of the sources is connected together, and each of the gates is connected together. The determination of the optimal transistor ratio is process-specific and can be determined by simulation or by determining the resulting parasitic capacitances 50 and 88 of the first transistor 40 and the second transistor 80 from manufacturing process parameters, respectively.

[0052] When the enable signal 68 is deactivated, the first switch 60 and the second switch 90 are deactivated (e.g., "open"). In response to deactivating the first switch 60, the first source 44 rises to a value approximately equal to a threshold voltage (e.g., VTH of the first transistor 40) below the mirror reference voltage on bias rail 28. This occurs because the first transistor 40 continues to conduct until the gate-to-source voltage equals the threshold voltage of the first transistor 40. For simplicity, we will also refer to the mirror reference voltage as "nbias". In response to deactivating the second switch 90, the second drain 82 discharges to the potential of the second node 16 (zero volts in one example). This occurs because the second transistor 80 continues to conduct current while nbias is applied to the second gate 86. Therefore, the first capacitor 50 (CGS) charges to approximately VTH (e.g., the threshold voltage of the first transistor 40), and the second capacitor 88 (CDG) charges to nbias.

[0053] When enable signal 68 is activated, the first switch 60 is activated, thereby driving the first source 44 to the potential of the second node 16 (e.g., zero volts in one example) and causing the first transistor 40 to conduct current. Therefore, activation of the first switch 60 removes charge from the bias rail 28 through capacitive coupling of the first capacitor 50. The removed charge is equal to CGS*(nbias-VTH). Simultaneously, the second switch 90 is activated, thereby clamping the second drain 82 to a threshold voltage VTH2 (the threshold voltage of the second switch 90, which may differ from the threshold voltage of the first switch 60) of the potential of the first node 32 (VDD in one example), and causing the second transistor 80 to conduct current. Therefore, activation of the second switch 90 adds charge to the bias rail 28 through capacitive coupling of the second capacitor 88. The added charge is equal to CDG*(VDD-VTH2). By selecting an optimal transistor ratio (and thus limiting the values ​​of CGS and CDG), the net charge removed and added on the bias rail 28 will be substantially zero. This occurs when CGS*(nbias-VTH) equals CDG*(VDD-VTH2).

[0054] Now for reference Figure 2 Continue to refer to Figure 1 This describes an embodiment 100 of a fast-start power supply according to the present disclosure. Figure 2 The operation of Embodiment 100 is similar to that of Embodiment 10, wherein an additional transistor is used to improve the parasitic resistance balance between bias chain 12, first branch 30, and second branch 70 by compensating for the channel resistance of the activating transistor (e.g., the "RDSon" value). The bias chain 12 of Embodiment 100 includes a bias power supply transistor 110 connected between the bias power supply 102 and the bias rail 28. Similar to... Figure 1 The power supply 18, bias power transistor 110 includes a bias power drain connected to bias power supply 102, a bias power source 114 connected to bias rail 28, and a bias power gate 116, which is biased by the bias power transistor voltage to supply current from bias power supply 102 to bias rail 28. In another embodiment, Figure 1 bias chain 12 and Figure 2 The first branch 30 and the second branch 70 are used together.

[0055] The bias chain 12 of embodiment 100 also includes a bias compensation device 120. The bias compensation device 120 includes a bias compensation drain 122 connected to the source 24 of the bias transistor, a bias compensation drain 124 connected to the second node 16, and a bias compensation gate 126 connected to a bias compensation voltage equal to VDD (e.g., a high voltage on the enable signal 68), wherein the bias compensation device 120 is designed to have the same voltage drop (e.g., current * RDSON) as the first switch 60 when the first switch 60 is enabled. In one embodiment, VDD is 1.5 volts.

[0056] The first branch 30 of embodiment 100 also includes a protection device 130. The protection device 130 includes a protection drain 132 connected to the first node 32, a protection source 134 connected to the first drain 42, and a protection gate 136 connected to VDD, wherein the protection device 130 is designed to have the same voltage drop (e.g., current *RDSON) as the second switch 90 when the second switch 90 is enabled.

[0057] The second branch 70 of embodiment 100 further includes a compensation device 140. The compensation device 140 includes a compensation drain 142 connected to the second source 84, a compensation source 144 connected to the second node 16, and a compensation gate 146 connected to VDD, wherein the compensation device 140 is designed to have the same voltage drop (e.g., current * RDSON) as the first switch 60 when the first switch 60 is enabled. In one embodiment, achieving the same voltage drop across the compensation device 140 and the first switch 60 is achieved by scaling the relative size of the compensation device 140 compared to the first switch 60 to the same relative size as the second transistor 80 compared to the first transistor 40 (e.g., 2:1 in one example).

[0058] In one embodiment, each of the transistors in Embodiment 100 is an N-channel field-effect transistor (NFET). In one embodiment, the bias power supply transistor 110, the protection device 130, and the second switch 90 are high-voltage NFETs. In another embodiment, the bias compensation voltage, the first voltage, and the second voltage are each equal to VDD. In yet another embodiment, the fast-start power supply includes one or more of the bias compensation device 120, the protection device 130, and the compensation device 140.

[0059] Figure 3 and Figure 4 Show Figure 2 Example timing waveforms of embodiment 100. It should be understood that... Figure 3 and Figure 4 The timing shown is similarly applied to Figure 1 Example 10. See reference. Figure 2 , Figure 3The activation of enable signal 68 is shown to enable fast-start power 100. Starting one microsecond, enable signal 68 transitions from low state 150 to high state 152.

[0060] refer to Figure 2 and Figure 3 , Figure 4 The diagram illustrates the output current flowing through the first node 32 in response to the activation enable signal 68. Specifically, the output current flowing into the first node 32 starts substantially from 0 µA at a quiescent level 160. The output current may undershoot to an undershoot level 162 in response to the removal of charge from the bias rail 28 via the first capacitor 50. In one embodiment, the output current overshoots to an overshoot level 164 in response to the addition of charge to the bias rail 28 via the second capacitor 88, and then quickly stabilizes within 3 ns. Figure 4 The operating level shown is 166, which is 100uA. Figure 4 The timing diagram illustrates an example of the interaction between charge removal from bias rail 28 and charge addition to bias rail 28. It should be understood that in other embodiments, undershoot level 162 and overshoot level 164 may be slightly ahead or slightly behind due to typical manufacturing and environmental variations, but are closely timed to minimize any resulting voltage variations on bias rail 28.

[0061] Figure 5 and Figure 6 Example timing waveforms are shown for an embodiment that does not use a fast-start power supply. Similar to... Figure 3 , Figure 5 This illustrates the transition of the enable signal from low state 170 to high state 172 within one microsecond to activate the power supply. Compared to Figure 4 , Figure 6 This shows the output current with significant overshoot on the bias rail used to mirror the reference voltage. Typically, Figure 1 or Figure 2 The bias rail 28 can be a long trace on a large integrated circuit, which essentially increases the parasitic capacitance of the bias rail (not shown). This parasitic capacitance of the bias rail can significantly affect the performance of the switchable power supply, resulting in slow settling times or unstable compensation techniques. Figure 1 Example 10 and Figure 2 Example 100 is independent of bias track parasitic capacitance.

[0062] exist Figure 6 During operation, the output current starts from the quiescent level 180. In response to the enable signal, the output can undershoot to the undershoot level 182 and significantly overshoot to overshoot levels 184, 186, and 188, corresponding to the bias rail parasitic capacitances of 50fF, 200fF, and 500fF, respectively. Finally, the output stabilizes at the operating level 190. Figure 6This illustrates the high cost due to the routing length of bias track 28 and the circuitry and methods sensitive to the parasitic capacitance of the bias track. Figure 4 The current overshoot achieved is 10 times the current overshoot. Even with the short route length of bias rail 28, the overshoot level of 184 is still significant. Figure 4 The overshoot level is 164% and the settling time is over 20 nanoseconds.

[0063] Figure 7 This is a flowchart view of a method 200 for quickly enabling power according to an exemplary embodiment of the present disclosure. Continue referring to... Figure 2 and Figure 7 At 202, a mirror reference voltage is generated on bias rail 28. At 204, a first current is conducted through first branch 30 in response to enable signal 68. At 206, a first charge (e.g., CGS*(nbias-VTH)) is removed from bias rail 28 through first capacitor 50. At 208, a second current is conducted through second branch 70 in response to enable signal 68. At 210, a second charge (e.g., CDG*(VDD-VTH2)) is added to bias rail 28 through second capacitor 88, thereby substantially offsetting the power supply 100 (or...) that was rapidly enabled due to enable signal 68. Figure 1 Any change in net charge on bias track 28 caused by Example 10. It should be understood that in the various embodiments, 204, 206, 208, and 210 (and specifically 206 and 210) occur substantially simultaneously. Although micro-level misalignment, specifically with 206 and 210, may occur due to typical manufacturing and environmental variations, closely aligning 206 with 210 will reduce undesirable overshoot and undershoot on bias track 28.

[0064] It should be understood that the disclosed embodiments include at least the following. In one embodiment, the fast-start power supply includes a bias chain configured to generate a mirror reference voltage on a bias rail. A first branch includes a first transistor having a first drain connected to a first node, a first source connected to a first switch, and a first gate connected to the bias rail. The first switch is configured to short the first source to a second node in response to an enable signal. A first capacitor is located between the first gate and the first source. A second branch includes a second transistor having a second drain connected to a second switch, a second source connected to a second node, and a second gate connected to the bias rail. The second switch is configured to short the second drain to the first node in response to an enable signal. A second capacitor is located between the second drain and the second gate, wherein in response to the enable signal, a first charge removed from the bias rail by the first capacitor is offset by a second charge added to the bias rail by the second capacitor.

[0065] In another embodiment, the method for rapidly enabling a power supply includes generating a mirror reference voltage on a bias rail. A first current is conducted through a first branch between a first node and a second node. The first branch includes a first transistor connected in series with a first switch in response to enabling a first switch by an enable signal. A first charge is removed from the bias rail through a first capacitance between the first gate and the first source of the first transistor, wherein the first gate is biased by the mirror reference voltage. A second current is conducted through a second branch between the first node and the second node. The second branch includes a second switch connected in series with a second transistor in response to enabling a second switch by an enable signal. A second charge is added to the bias rail through a second capacitance between the second drain and the second gate of the second transistor, wherein the second gate is biased by the mirror reference voltage.

[0066] In another embodiment, the fast-start power supply includes a first branch comprising a first transistor having a first drain connected to a protection device, a first source connected to a first switch, and a first gate connected to a bias rail. The protection device is connected to a first node. The first switch is configured to short the first source to a second node in response to an enable signal. A first parasitic capacitance is located between the first gate and the first source. The second branch includes a second transistor having a second drain connected to a second switch, a second source connected to a compensation device, and a second gate connected to a bias rail. The compensation device is connected to a second node. The second switch is configured to short the second drain to the first node in response to an enable signal. A second parasitic capacitance is located between the second drain and the second gate, wherein in response to the enable signal, a first charge removed from the bias rail by the first capacitor is offset by a second charge added to the bias rail by the second capacitor.

[0067] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with reference to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0068] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements.

Claims

1. A fast enabling power supply, characterized by, comprises: a bias chain configured to generate a mirrored reference voltage on a bias rail; a first branch comprising a first transistor having a first drain connected to a first node, a first source connected to a first switch, and a first gate connected to the bias rail, the first switch configured to short the first source to a second node in response to an enable signal; the first transistor comprises a first capacitance between the first gate and the first source; a second branch comprising a second transistor having a second drain connected to a second switch, a second source connected to the second node, and a second gate connected to the bias rail, the second switch configured to short the second drain to the first node in response to the enable signal; and the second transistor comprises a second capacitance between the second drain and the second gate, wherein a first charge removed from the bias rail by the first capacitance is offset by a second charge added to the bias rail by the second capacitance in response to the enable signal; the first charge is equal to the second charge, and a first width of the first transistor divided by a second width of the second transistor defines an optimal transistor ratio. the optimal transistor ratio is one-half, wherein each of the transistors of the fast- enabled power supply comprises an n-channel field effect transistor.

2. The quick-enabled power supply of claim 1, wherein, the first switch comprises an n-channel field effect transistor comprising: a first switch drain connected to the first source; a first switch gate connected to the enable signal, the enable signal configured to enable the first switch; and a first switch source connected to the second node.

3. The quick-enabled power supply of claim 1, wherein, the second switch comprises a high-voltage n-channel field effect transistor comprising: a second switch drain connected to the first node; a second switch gate connected to the enable signal, the enable signal configured to enable the second switch; and a second switch source connected to the second drain.

4. The quick-enabled power supply of claim 1, wherein, the bias chain comprises a bias transistor comprising a bias drain connected to a power supply, a bias gate connected to the bias drain and the bias rail, and a bias source connected to the second node.

5. The quick-enabled power supply of claim 1, wherein, further comprising a bias compensation device connected between the bias source and the second node, wherein the bias compensation device has a same voltage drop as the first switch when the first switch is enabled.

6. The fast enable power supply of claim 5, wherein, further comprising a protection device connected between the first node and the first drain, wherein the protection device has a same voltage drop as the second switch when the second switch is enabled.

7. The quick-enabled power supply of claim 1, wherein, comprises:

8. A method for fast enabling a power supply, characterized by, generating a mirrored reference voltage on a bias rail; conducting a first current through a first branch between a first node and a second node, the first branch comprising a first transistor and a first switch connected in series with the first switch in response to enabling the first switch through an enable signal; ​ a first charge is removed from the bias rail by a first capacitance of the first transistor between a first gate and a first source of the first transistor, wherein the first gate is biased by the mirror reference voltage; a second current is conducted through a second branch between the first node and the second node, the second branch including a second switch and a second transistor connected in series with the second transistor in response to the second switch being enabled by the enable signal; and a second charge is added to the bias rail by a second capacitance of the second transistor between a second drain and a second gate of the second transistor, wherein the second gate is biased by the mirror reference voltage; an optimal transistor ratio is determined by dividing a first width of the first transistor by a second width of the second transistor, wherein the optimal transistor ratio results in the first charge being equal to the second charge.

9. A fast enabling power supply, characterized by comprising: a first branch including a first transistor having a first drain connected to a protection device, a first source connected to a first switch, and a first gate connected to a bias rail, the protection device connected to a first node, the first switch configured to short the first source to a second node in response to an enable signal; a first parasitic capacitance between the first gate and the first source; a second branch including a second transistor having a second drain connected to a second switch, a second source connected to a compensation device, and a second gate connected to the bias rail, the compensation device connected to the second node, the second switch configured to short the second drain to the first node in response to the enable signal; and a second parasitic capacitance between the second drain and the second gate, wherein a first charge removed from the bias rail by a first capacitance in response to the enable signal is offset by a second charge added to the bias rail by a second capacitance; the first charge is equal to the second charge, and a first width of the first transistor divided by a second width of the second transistor defines an optimal transistor ratio.

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