Level circuit and emission control driver having the level circuit

Abstract

The present disclosure relates to a stage circuit and a transmission control driver including the stage circuit. The stage circuit includes: an output circuit for supplying the voltage of a first power supply or the voltage of a second power supply to an output terminal in response to the voltage of a first node and the voltage of a second node; an input circuit for controlling the voltage of the second node and the voltage of a third node; a first signal processor for controlling the voltage of the first node; a second signal processor for controlling the voltage of the first node in response to the output voltage of a third signal processor and a signal supplied to a third input terminal; and a third signal processor for controlling the voltage of the second node. The third signal processor includes: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0030721, filed on Mar. 18, 2019, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present disclosure generally relate to a stage circuit (stage) and an emission control driver having the stage circuit. Background Art

[0004] An organic light emitting display (OLED) has advantages over other types of displays in that the organic light emitting display (OLED) has a higher response speed and the organic light emitting display (OLED) has lower power consumption.

[0005] An emission control driver provided in an OLED may control the emission time of pixels by supplying an emission control signal to an emission control line. For such an operation, the emission control driver includes a plurality of stages coupled to respective emission control lines. Each of the stages may include a plurality of transistors and capacitors.

[0006] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus, the above information may include information that does not constitute the prior art. Summary of the Invention

[0007] Exemplary embodiments of the present disclosure provide a stage circuit and an emission control driver having the stage circuit, the stage circuit being capable of stably maintaining the voltage of a node for controlling the output of an emission control signal at a high voltage while maintaining the emission control signal at a low voltage.

[0008] Exemplary embodiments of the present disclosure also provide a stage circuit and an emission control driver having the stage circuit, the stage circuit being configured to prevent a capacitor provided in the stage circuit from being charged or discharged while maintaining the emission control signal at a low voltage.

[0009] Additional features of the inventive concept will be set forth in the following description, and the additional features will become partially apparent from the description, or may be learned by practicing the inventive concept.

[0010] Exemplary embodiments of the present disclosure provide a stage circuit, the stage circuit including: an output circuit configured to supply a voltage of a first power supply or a voltage of a second power supply to an output terminal in response to a voltage of a first node and a voltage of a second node; an input circuit configured to control the voltage of the second node and the voltage of a third node in response to respective signals supplied to a first input terminal and a second input terminal; a first signal processor configured to control the voltage of the first node in response to the voltage of the second node; a second signal processor coupled between the first node and the third node and configured to control the voltage of the first node in response to an output voltage of a third signal processor and a signal supplied to a third input terminal; and the third signal processor configured to control the voltage of the second node in response to a signal supplied to the first input terminal. The third signal processor includes: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node.

[0011] When the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, the third transistor may be turned off, so as to block a path of current flowing from the second input terminal to the second node.

[0012] While the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, a potential difference between opposite ends of the third capacitor may be kept constant.

[0013] The third signal processor may further include: a second transistor coupled between the first power supply and a common node between the third capacitor and the third transistor, the second transistor including a gate electrode coupled to the third node. When the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, the voltage of the first power supply may be applied to the second node via the second transistor and the third capacitor.

[0014] The first clock signal may be supplied to the second input terminal, the second clock signal may be supplied to the third input terminal, and the first clock signal and the second clock signal may have the same waveform with a phase difference of half a period or more.

[0015] A gate turn-on voltage portion of the signal supplied to the first input terminal may overlap at least once with a gate turn-on voltage portion of the first clock signal.

[0016] The third signal processor may further include: a fourth transistor coupled between the third node and the second input terminal and including a gate electrode coupled to the second node; and a fifth transistor coupled between the third node and the second power supply and including a gate electrode coupled to the second input terminal.

[0017] The fourth transistor may include a plurality of sub-transistors coupled in series between the third node and the second input terminal. The gate electrodes of the plurality of sub-transistors may be coupled to the second node.

[0018] The third signal processor may include: a thirteenth transistor coupled between the first power supply and the eighth node and including a gate electrode coupled to the third node; and a fourteenth transistor coupled between the eighth node and the second node and including a gate electrode coupled to the third input terminal.

[0019] The input circuit may include a first transistor coupled between the first input terminal and the second node, the first transistor including a gate electrode coupled to the second input terminal.

[0020] The second signal processor may include: a second capacitor coupled between the third node and the sixth node; a sixth transistor coupled between the sixth node and the third input terminal and including a gate electrode coupled to the third node; and a seventh transistor coupled between the first node and the sixth node and including a gate electrode coupled to the third input terminal.

[0021] The first signal processor may include: a first capacitor coupled between the first power supply and the first node; and an eighth transistor coupled between the first power supply and the first node and including a gate electrode coupled to the second node.

[0022] The output circuit may include: a ninth transistor coupled between the first power supply and the output terminal and including a gate electrode coupled to the first node; and a tenth transistor coupled between the output terminal and the second power supply and including a gate electrode coupled to the second node.

[0023] The stage circuit may further include: a first stabilizer coupled between the second signal processor and the third signal processor and configured to control the voltage drop width of the third node.

[0024] The stage circuit may further include: a second stabilizer coupled between the second node and a fourth node coupled to the first input terminal, the second stabilizer configured to control the voltage drop width of the second node.

[0025] The stage circuit may further include: a first gate insulating layer configured to cover a source electrode and a drain electrode of at least one transistor; a second gate insulating layer configured to cover a gate electrode of the at least one transistor and a first electrode of at least one capacitor; and an interlayer insulating layer configured to cover a second electrode of at least one capacitor. The second gate insulating layer may cover a line extending from the gate electrode of the third transistor to the second node. The line may be arranged not to overlap with the source electrode and the drain electrode covered by the first gate insulating layer, or not to overlap with the second electrode covered by the interlayer insulating layer.

[0026] Another exemplary embodiment of the present disclosure provides a transmission control driver, which includes a plurality of stage circuits configured to supply a transmission signal to a transmission control line. Each stage circuit of the plurality of stage circuits may include: an output circuit configured to supply a voltage of a first power supply or a voltage of a second power supply to an output terminal in response to a voltage of a first node and a voltage of a second node; an input circuit configured to control the voltage of the second node and the voltage of a third node in response to respective signals supplied to a first input terminal and a second input terminal; a first signal processor configured to control the voltage of the first node in response to the voltage of the second node; a second signal processor connected between the first node and the third node and configured to control the voltage of the first node in response to a signal supplied to the second input terminal and a signal supplied to a third input terminal; and a third signal processor configured to control the voltage of the second node in response to a signal supplied to the first input terminal. The third signal processor may include: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node.

[0027] When the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, the third transistor may be turned off, so as to block a path for current flowing from the second input terminal to the second node.

[0028] While the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, a potential difference between opposite ends of the third capacitor may be kept constant.

[0029] It will be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the inventive concept.

[0031] Figure 1 is a diagram showing a display device according to an exemplary embodiment of the present disclosure.

[0032] Figure 2 schematically shows Figure 1 the emission control driver shown in

[0033] Figure 3 is of a stage according to a first exemplary embodiment of the present disclosure Figure 2 the circuit diagram of the stage shown in

[0034] Figure 4 is of a stage according to a second exemplary embodiment of the present disclosure Figure 2 the circuit diagram of the stage shown in

[0035] Figure 5 shows Figure 3 the waveform of the operation of the stage shown in

[0036] Figure 6 is of a stage according to a third exemplary embodiment of the present disclosure Figure 2 the circuit diagram of the stage shown in

[0037] Figure 7 is of a stage according to a fourth exemplary embodiment of the present disclosure Figure 2 the circuit diagram of the stage shown in

[0038] Figure 8 shows Figure 7 the waveform of the operation of the stage shown in

[0039] Figure 9 is a plan view showing the layout of a stage according to an exemplary embodiment of the present disclosure.

[0040] Figure 10 is a cross-sectional view taken along line I-I' of Figure 9 Detailed Description

[0041] ​In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, "embodiment" is a non-limiting example of an apparatus or method that employs one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Additionally, the various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0042] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of variable details of some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be additionally combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0043] Cross-hatching and / or shading are generally provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless stated otherwise, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the element. Additionally, in the drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, a particular process order may be performed differently from the order described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the order described. Additionally, the same reference numerals denote the same elements.

[0044] When an element such as a layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For the purposes of this disclosure, the term “connected” can refer to physical, electrical, and / or fluid connection with or without intervening elements. Further, the D1 axis, D2 axis, and D3 axis are not limited to the three axes of a rectangular coordinate system such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the D1 axis, D2 axis, and D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as being only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as by way of example XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of this disclosure.

[0046] For descriptive purposes, spatially relative terms such as “under,” “below,” “beneath,” “lower,” “above,” “upper,” “on top of,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element (or elements) to another element (or elements) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as “under” or “beneath” other elements or features will then be oriented “on top of” the other elements or features. Thus, the exemplary term “under” can encompass both an orientation of “on top of” and “under.” Further, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and so the spatially relative descriptors used herein are to be interpreted accordingly.

[0047] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms. Additionally, when used in this specification, the terms "comprises," "comprising," "includes," "including," "has," "having" and / or the like specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about" and other similar terms are used as approximate terms and not as terms of degree, and thus are used to account for the inherent deviations of measured, calculated, and / or provided values that would be recognized by one of ordinary skill in the art.

[0048] In this document, various exemplary embodiments are described with reference to sectional views and / or exploded views of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shapes of the specific regions shown, but will include deviations in shape due to, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature and the shapes of these regions may not reflect the actual shape of the regions of the device and, thus, are not necessarily intended to be limiting.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not as having an idealized or overly formal meaning, unless expressly so defined herein.

[0050] Figure 1 is a diagram showing a display device according to an exemplary embodiment of the present disclosure.

[0051] Referring to Figure 1 , a display device according to an exemplary embodiment of the present disclosure may include a pixel unit 10, a scan driver 20, a data driver 30, an emission control driver 40, and a timing controller 50.

[0052] The pixel unit 10 may include a plurality of pixels PX, which are coupled to scan lines S1 to Sn, data lines D1 to Dm, and emission control lines E1 to En and arranged in a matrix form. The pixel PX may receive a scan signal through the scan lines S1 to Sn, receive a data signal through the data lines D1 to Dm, and receive an emission control signal through the emission control lines E1 to En. When the scan signal is supplied from the scan lines S1 to Sn to the pixel PX, the pixel PX may emit light at a brightness level corresponding to the data signal supplied from the data lines D1 to Dm.

[0053] The scan driver 20 may be coupled to a plurality of scan lines Sl to Sn, generate a scan signal in response to a scan driving control signal SCS of the timing controller 50, and output the generated scan signal to the scan lines Sl to Sn. The scan driver 20 may be formed of multiple-stage circuits. When the scan signal is sequentially supplied to the scan lines S1 to Sn, the pixel PX may be selected based on the horizontal line.

[0054] The data driver 30 may be coupled to a plurality of data lines D1 to Dm, generate a data signal based on the image data DATA’ and the data driving control signal DCS of the timing controller 50, and output the generated data signal to the data lines D1 to Dm. Each time the scan signal is supplied, the data signal supplied to the data lines D1 to Dm may be supplied to the pixel PX selected by the scan signal. Then, the pixel PX may be charged with a voltage corresponding to the data signal.

[0055] The emission control driver 40 may be coupled to the emission control lines E1 to En, generate an emission control signal in response to the emission driving control signal ECS of the timing controller 50, and output the generated emission control signal to the emission control lines E1 to En. The emission control driver 40 may be formed of multiple-stage circuits and control the emission period of the pixel PX by supplying the emission control signal to the emission control lines E1 to En.

[0056] The timing controller 50 can receive image data DATA, synchronization signals Hsync and Vsync, a clock signal CLK, etc., to control the display of an image corresponding to the image data DATA. The timing controller 50 can perform image processing on the input image data DATA to generate compensated image data DATA' suitable for image display of the pixel unit 10, and output the image data DATA' to the data driver 30. The timing controller 50 can generate drive control signals SCS, DCS, and ECS to control the operations of the scan driver 20, the data driver 30, and the emission control driver 40 based on the synchronization signals Hsync and Vsync and the clock signal CLK. Specifically, the timing controller 50 can generate a scan drive control signal SCS and supply the scan drive control signal SCS to the scan driver 20, can generate a data drive control signal DCS and supply the data drive control signal DCS to the data driver 30, can generate an emission drive control signal ECS, and can supply the emission drive control signal ECS to the emission control driver 40.

[0057] Figure 2 schematically shows Figure 1 the emission control driver 40 shown in

[0058] Referring jointly to Figure 1 and Figure 2 , the emission control driver 40 according to an exemplary embodiment of the present disclosure can include a plurality of stages 401, 402, 403,... to supply emission control signals to emission control lines E1 to En. In the present exemplary embodiment, for illustration purposes, only three stages 401, 402, and 403 are shown.

[0059] The stages 401, 402, and 403 can be driven by a start signal FLM and a first clock signal CLK1 and a second clock signal CLK2, and respectively output emission control signals EM1, EM2, and EM3. The start signal FLM and the first clock signal CLK1 and the second clock signal CLK2 can be received through the emission drive control signal ECS provided from the timing controller 50.

[0060] In the exemplary embodiment of the present disclosure, the stages 401, 402, and 403 can be formed of the same or different circuits.

[0061] Each of the stages 401, 402, 403,... can include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0062] The first input terminal 101 may be supplied with a start signal FLM or transmission control signals EM1, EM2, EM3, … of a previous stage. The second input terminal 102 and the third input terminal 103 may be supplied with any one of a first clock signal CLK1 and a second clock signal CLK2. The signal output to the output terminal 104 may be used as the transmission control signals EM1, EM2, EM3, ….

[0063] In an exemplary embodiment, each of the first clock signal CLK1 and the second clock signal CLK2 may be set as a square wave signal having repeatedly formed logic high levels and logic low levels. The first clock signal CLK1 and the second clock signal CLK2 may be signals having the same waveform having two horizontal periods 2H per cycle. In an exemplary embodiment, the first clock signal CLK1 and the second clock signal CLK2 may be set such that gate conduction voltage periods of the first clock signal CLK1 and the second clock signal CLK2 do not overlap each other and have a phase difference of a half cycle or greater. However, this is merely for illustrative purposes, and the waveform relationship between the first clock signal CLK1 and the second clock signal CLK2 is not limited thereto.

[0064] The first stage 401 of the stages 401, 402, 403, … may receive the start signal FLM, and each of the stages 402, 403, … other than the first stage 401 may receive the transmission control signals EM1, EM2, EM3, … of the previous stage.

[0065] In an exemplary embodiment, the first stage 401 may directly receive the first clock signal CLK1 and the second clock signal CLK2, and each of the stages 402, 403, … other than the first stage 401 may receive any one of the first clock signal CLK1 and the second clock signal CLK2 from the previous stage. Specifically, each of the odd-numbered stages 403, … other than the first stage 401 may receive the first clock signal CLK1 from the previous stage and directly receive the second clock signal CLK2. Each of the even-numbered stages 402, … may directly receive the first clock signal CLK1 and receive the second clock signal CLK2 from the previous stage. However, the inventive concept is not limited thereto, and all the stages 401, 402, 403, … may directly receive the first clock signal CLK1 and the second clock signal CLK2.

[0066] In Figure 2In an exemplary embodiment, the first stage 401 may output a first emission control signal EM1 in response to a start signal FLM and a first clock signal CLK1 and a second clock signal CLK2, and transmit the second clock signal CLK2 and the first emission control signal EM1 to the second stage 402. The second stage 402 may output a second emission control signal EM2 in response to the first clock signal CLK1 and the second clock signal CLK2 and the first emission control signal EM1 transmitted from the first stage 401, and transmit the first clock signal CLK1 and the second emission control signal EM2 to the third stage 403. The third stage 403 may output a third emission control signal EM3 in response to the second clock signal CLK2 and the first clock signal CLK1 and the second emission control signal EM2 transmitted from the second stage 402, and transmit the second clock signal CLK2 and the third emission control signal EM3 to a fourth stage (not shown).

[0067] Figure 3 is a circuit diagram of the stage shown in the first exemplary embodiment, and Figure 2 and Figure 4 is a circuit diagram of the stage shown in the second exemplary embodiment. Although, for illustrative purposes,[[]] Figure 2 only the i-th stage is shown, but Figure 3 and Figure 4 the stage shown in Figure 2 may have the same structure as the structure of the i-th stage to be described below.

[0068] Referring to Figures 1 to 3 , the stage 400 according to the first exemplary embodiment of the present disclosure may include an input circuit 410, an output circuit 420, a first signal processor 430, a second signal processor 440, a third signal processor 450, a first stabilizer 461, and a second stabilizer 462.

[0069] The output circuit 420 may supply the voltage of the first power supply VDD or the second power supply VSS to the output terminal 104 in response to the voltages of the first node N1 and the second node N2. For this purpose, the output circuit 420 may include a ninth transistor M9 and a tenth transistor M10.

[0070] The ninth transistor M9 is coupled between the first power supply VDD and the output terminal 104. The gate electrode of the ninth transistor M9 may be coupled to the first node Nl. The ninth transistor M9 may be turned on or off according to the voltage of the first node N1. Here, when the ninth transistor M9 is turned on, the voltage of the first power supply VDD supplied to the output terminal 104 may be supplied to the i-th emission control line Ei, and may be used as an emission control signal EM[i] having a gate conduction level.

[0071] The tenth transistor M10 is coupled between the output terminal 104 and the second power supply VSS. The gate electrode of the tenth transistor M10 is coupled to the second node N2. The tenth transistor M10 can be turned on or off according to the voltage of the second node N2. Here, when the tenth transistor M10 is turned on, the voltage of the second power supply VSS supplied to the output terminal 104 can be supplied to the i-th emission control line Ei and can be used as the emission control signal EM[i] having a gate cutoff level. In an exemplary embodiment, when the emission control signal EM[i] has a gate cutoff level, it can be understood that the emission control signal EM[i] is not supplied.

[0072] The input circuit 410 can control the voltages of the second node N2 and the fourth node N4 in response to the signals supplied to the first input terminal 101 and the second input terminal 102. For this purpose, the input circuit 410 can include a first transistor M1.

[0073] The first transistor M1 is coupled between the first input terminal 101 and the fourth node N4. The gate electrode of the first transistor M1 is coupled to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the first transistor M1 can be turned on to electrically couple the first input terminal 101 to the fourth node N4.

[0074] The first signal processor 430 can control the voltage of the first node N1 in response to the voltages of the second node N2 and the fourth node N4. For this purpose, the first signal processor 430 can include an eighth transistor M8 and a first capacitor C1.

[0075] The eighth transistor M8 is coupled between the first power supply VDD and the first node N1. The gate electrode of the eighth transistor M8 can be coupled to the fourth node N4. The eighth transistor M8 can be turned on or off according to the voltage of the fourth node N4. Here, when the eighth transistor M8 is turned on, the voltage of the first power supply VDD can be supplied to the first node N1.

[0076] The first capacitor C1 is coupled between the first power supply VDD and the first node N1. The first capacitor C1 can be charged with the voltage to be applied to the first node N1. In addition, the first capacitor C1 can stably hold the voltage of the first node N1.

[0077] The second signal processor 440 is coupled to the fifth node N5 and can control the voltage of the first node N1 in response to the signal input to the third input terminal 103. For this purpose, the second signal processor 440 can include a sixth transistor M6, a seventh transistor M7, and a second capacitor C2.

[0078] The first terminal of the second capacitor C2 is coupled to the fifth node N5, and the second terminal of the second capacitor C2 is coupled to the sixth node N6, which is a common node between the sixth transistor M6 and the seventh transistor M7.

[0079] The sixth transistor M6 is coupled between the sixth node N6 and the third input terminal 103. The gate electrode of the sixth transistor M6 is coupled to the fifth node N5. The sixth transistor M6 can be turned on according to the voltage of the fifth node N5 so that a voltage corresponding to the second clock signal CLK2 supplied to the third input terminal 103 can be applied to the sixth node N6.

[0080] The seventh transistor M7 is coupled between the first power supply VDD and the sixth node N6. The gate electrode of the seventh transistor M7 is coupled to the third input terminal 103. The seventh transistor M7 can be turned on in response to the second clock signal CLK2 supplied to the third input terminal 103, and thus, the voltage of the first power supply VDD is applied to the sixth node N6.

[0081] The third signal processor 450 can control the voltage of the third node N3. For this purpose, the third signal processor 450 may include a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a third capacitor C3.

[0082] The first electrode of the third capacitor C3 is coupled to the second node N2, and the second electrode of the third capacitor C3 is coupled to the seventh node N7, which is a common node between the second transistor M2 and the third transistor M3.

[0083] The second transistor M2 is coupled between the first power supply VDD and the seventh node N7. The gate electrode of the second transistor M2 is coupled to the third node N3. The second transistor M2 can be turned on or off according to the voltage of the third node N3.

[0084] The third transistor M3 is coupled between the seventh node N7 and the third input terminal 103. The gate electrode of the third transistor M3 is coupled to the second node N2. The third transistor M3 can be turned on or off according to the voltage of the second node N2.

[0085] The fourth transistor M4 is coupled between the third node N3 and the second input terminal 102. The gate electrode of the fourth transistor M4 is coupled to the fourth node N4. In an exemplary embodiment of the present disclosure, as Figure 4As shown, the fourth transistor M4 may include a 4-1 sub-transistor M4-1 and a 4-2 sub-transistor M4-2 connected in series between the third node N3 and the second input terminal 102. In the present exemplary embodiment, the gate electrodes of each of the 4-1 sub-transistor M4-1 and the 4-2 sub-transistor M4-2 are coupled to the fourth node N4. If the fourth transistor M4 is formed by a plurality of sub-transistors M4-1 and M4-2, even when there is a large potential difference between the third node N3 and the fourth node N4, a current path can be reliably formed between the third node N3 and the second input terminal 102 in response to the potential difference between the third node N3 and the fourth node N4.

[0086] The fifth transistor M5 is coupled between the third node N3 and the second power supply VSS. The gate electrode of the fifth transistor M5 is coupled to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the fifth transistor M5 can be turned on, so that the voltage of the second power supply VSS can be supplied to the third node N3.

[0087] The first stabilizer 461 is coupled between the second signal processor 440 and the third signal processor 450. The first stabilizer 461 can limit the voltage drop width of the third node N3. For this purpose, the first stabilizer 461 may include an eleventh transistor M11.

[0088] The eleventh transistor M11 is coupled between the third node N3 and the fifth node N5. The gate electrode of the eleventh transistor M11 is coupled to the second power supply VSS. Since the second power supply VSS has a gate-conducting level voltage, the eleventh transistor M11 can always remain on. Therefore, the third node N3 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node.

[0089] The second stabilizer 462 is coupled between the second node N2 and the fourth node N4. The second stabilizer 462 can limit the voltage drop width of the second node N2. For this purpose, the second stabilizer 462 may include a twelfth transistor M12.

[0090] The twelfth transistor M12 is coupled between the second node N2 and the fourth node N4. The gate electrode of the twelfth transistor M12 is coupled to the second power supply VSS. Since the second power supply VSS has a gate-cutoff level voltage, the twelfth transistor M12 can always remain on. Therefore, the second node N2 and the fourth node N4 can be maintained at the same voltage and operate as substantially the same node.

[0091] In an exemplary embodiment of the present disclosure, each of the first transistor M1 to the twelfth transistor M12 may be formed of a p-type transistor. In these exemplary embodiments, the gate conduction voltage of the first transistor M1 to the twelfth transistor M12 may be set to a low level, and the gate cut-off voltage of the first transistor M1 to the twelfth transistor M12 may be set to a high level.

[0092] Figure 5 is a waveform diagram showing Figure 3 the operation of the stage shown in. For illustrative purposes, Figure 5 only the operation of the i-th stage is shown.

[0093] Referring to Figure 5 , each of the first clock signal CLK1 and the second clock signal CLK2 may have a period of two horizontal periods (2H) and have a gate conduction level during different horizontal periods. In other words, the second clock signal CLK2 may be set to a signal that is offset by half a period (i.e., one horizontal period (1H)) from the first clock signal CLK1.

[0094] When the clock signals CLK1 and CLK2 are supplied, the second input terminal 102 and the third input terminal 103 may be set to a low level, i.e., the voltage of the second power supply VSS. When the clock signals CLK1 and CLK2 are not supplied, the second input terminal 102 and the third input terminal 103 may be set to a high level, i.e., the voltage of the first power supply VDD.

[0095] When the start signal FLM or the emission control signal EM[i-1] of the previous stage is supplied, the first input terminal 101 may be set to a high level, i.e., the voltage of the first power supply VDD. When the start signal FLM or the emission control signal EM[i-1] of the previous stage is not supplied, the first input terminal 101 may be set to a low level, i.e., the voltage of the second power supply VSS.

[0096] In addition, the start signal FLM or the emission control signal EM[i-1] to be supplied to the first input terminal 101 may be set to overlap with the first clock signal CLK1 to be supplied to the second input terminal 102 at least once. For this purpose, the start signal FLM (or the emission control signal EM[i-1] of the previous stage) may have a width greater than the width of the first clock signal CLK1. For example, the start signal FLM (or the emission control signal EM[i-1] of the previous stage) may be supplied during four horizontal periods (4H). In this case, the first emission control signal to be supplied to the first input terminal 101 of the next stage may also overlap with the second clock signal CLK2 to be supplied to the second input terminal 102 of the next stage at least once.

[0097] The process of the operation will be described. First, during the first time period t1, the first clock signal CLK1 can be supplied to the second input terminal 102. Thus, the first transistor M1 and the fifth transistor M5 can be turned on. In addition, during the first time period t1, the second clock signal CLK2 may not be supplied to the third input terminal 103. Therefore, the seventh transistor M7 can be turned off.

[0098] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 can be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 can also be electrically coupled to the second node N2 via the fourth node N4.

[0099] Since during the first time period t1, the start signal FLM to be supplied to the first input terminal 101 or the emission control signal EM[i - 1] of the previous stage has a low level, a low level (e.g., the voltage of the second power supply VSS) can be applied to the fourth node N4 and the second node N2. When the fourth node N4 and the second node N2 are set to a low voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can be turned on.

[0100] When the third transistor M3 is turned on, the third input terminal 103 and the seventh node N7 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the first time period t1, a high voltage can be supplied to the seventh node N7. However, the third capacitor C3 can be charged with a voltage corresponding to the on state of the third transistor M3.

[0101] When the fourth transistor M4 is turned on, the fifth transistor M5 can be connected between the third node N3 and the second power supply VSS in the form of a diode. Therefore, even when the fifth transistor M5 is turned on during the first time period t1, the voltage of the second power supply VSS is not transmitted to the third node N3, and the voltage of the third node N3 can be maintained at the voltage of the previous state, e.g., a high voltage. Since the eleventh transistor M11 remains turned on, the high voltage of the third node N3 can be applied to the fifth node N5, and the fifth node N5 can be set to a high voltage. Thus, the second transistor M2 and the sixth transistor M6 can be turned off.

[0102] When the eighth transistor M8 is turned on, the voltage of the first power supply VDD can be supplied to the first node N1. Therefore, the ninth transistor M9 can be turned off.

[0103] When the tenth transistor M10 is turned on, the voltage of the second power supply VSS can be supplied to the output terminal 104. Therefore, during the first time period t1, the emission control signal EM[i] may not be supplied to the emission control line Ei.

[0104] During the second time period t2, the supply of the first clock signal CLK1 to the second input terminal 102 can be interrupted. When the supply of the first clock signal CLK1 is interrupted, the first transistor M1 and the fifth transistor M5 can be turned off. Here, the first node N1 and the second node N2 can maintain the voltages of the previous time period through the first capacitor C1 and the third capacitor C3. Since the first node N1 is maintained at a high voltage state, the ninth transistor M9 can remain turned off. Since the second node N2 is maintained at a low voltage state, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can remain turned on.

[0105] During the second time period t2, the second clock signal CLK2 can be supplied to the third input terminal 103. The seventh transistor M7 can be turned on through the second clock signal CLK2 supplied to the third input terminal 103. When the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 can be electrically coupled to each other. Therefore, the sixth node N6 can be set to a high voltage.

[0106] During the second time period t2, the second clock signal CLK2 can be supplied to the seventh node N7 via the turned-on third transistor M3. Therefore, a low voltage is supplied to the seventh node N7. Then, through the coupling of the third capacitor C3, the voltage of the second node N2 can be maintained at a voltage less than the voltage of the second power supply VSS (two-stage low voltage).

[0107] During the third time period t3, the supply of the second clock signal CLK2 to the third input terminal 103 can be interrupted. If the supply of the second clock signal CLK2 is interrupted, the seventh transistor M7 can be turned off.

[0108] During the third time period t3, the start signal FLM or the emission control signal EM[i - 1] of the previous stage can be supplied to the first input terminal 101, and the first clock signal CLK1 can be supplied to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the first transistor M1 and the fifth transistor M5 can be turned on.

[0109] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 can be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 can also be electrically coupled to the second node N2 via the fourth node N4. Then, the fourth node N4 and the second node N2 can be set to a high voltage through the start signal FLM or the emission control signal EM[i - 1] supplied to the first input terminal 101. When the fourth node N4 and the second node N2 are set to a high voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can be turned off.

[0110] If the fifth transistor M5 is turned on, the low voltage of the second power supply VSS can be applied to the third node N3, so that the third node N3 and the fifth node N5 are set to a low voltage. Accordingly, the second transistor M2 and the sixth transistor M6 can be turned on.

[0111] If the second transistor M2 is turned on, the voltage of the first power supply VDD can be applied to the seventh node N7. Therefore, the seventh node N7 can be maintained at a high voltage. Here, since the third transistor M3 remains off, the voltage of the second clock signal CLK2 to be applied to the third input terminal 103 may not be transmitted to the seventh node N7. In addition, since both the seventh node N7, which is the opposite end of the third capacitor C3, and the second node N2 are maintained at a high voltage, the third capacitor C3 may not be charged or discharged. Here, a current path can be formed from the first power supply VDD via the second transistor M2 to the second node N2, and the high voltage of the first power supply VDD can be transmitted to the second node N2. Therefore, the voltage of the second node N2 can be stably maintained at a high level.

[0112] If the sixth transistor M6 is turned on, the third input terminal 103 and the sixth node N6 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the third period t3, the sixth node N6 can be maintained at a high voltage. Here, since the seventh transistor M7 remains off, the voltage of the sixth node N6 may not affect the voltage of the first node N1. The second capacitor C2 can store a voltage corresponding to the conduction level of the sixth transistor M6.

[0113] During the fourth period t4, the second clock signal CLK2 can be supplied to the third input terminal 103. If the second clock signal CLK2 is supplied to the third input terminal 103, the seventh transistor M7 can be turned on.

[0114] If the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 can be electrically coupled to each other. Here, the low voltage of the second clock signal CLK2 supplied to the third input terminal 103 via the sixth transistor M6 that remains on can be supplied to the sixth node N6 and the first node N1. When a low voltage is provided to the first node N1, the ninth transistor M9 can be turned on.

[0115] If the ninth transistor M9 is turned on, the voltage of the first power supply VDD can be supplied to the output terminal 104. The voltage of the first power supply VDD supplied to the output terminal 104 can be supplied as the emission control signal EM[i] to the i-th emission control line Ei.

[0116] During the fifth time period t5, the supply of the second clock signal CLK2 to the third input terminal 103 can be interrupted. If the supply of the second clock signal CLK2 is interrupted, the seventh transistor M7 can be turned off. Here, the first node N1 can be stably held at a high voltage through the first capacitor C1. Accordingly, the ninth transistor M9 can remain turned on, and the voltage of the first power supply VDD can be supplied as the emission control signal EM[i] to the i-th emission control line Ei.

[0117] Although the supply of the second clock signal CLK2 is interrupted during the fifth time period t5, the third transistor M3 remains turned off. Accordingly, the voltage of the second clock signal CLK2 may not be supplied to the seventh node N7 and may not affect the voltage of the second node N2.

[0118] As described above, in the exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third transistor M3 that remains turned off can prevent the change in the voltage of the second clock signal CLK2 from affecting the second node N2, so that the second node N2 can be stably held at a high voltage. In addition, in the exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], charging or discharging of the third capacitor C3 can be prevented. In other words, the third capacitor C3 may not perform a charging or discharging operation at any time other than when the voltage of the second node N2 is set to a low level through the coupling of the third capacitor C3. Therefore, in the exemplary embodiment of the present disclosure, the third capacitor C3 may not act as a load during the supply of the emission control signal EM[i]. Accordingly, power consumption can be reduced, and reliable output of the emission control signal EM[i] can be ensured.

[0119] Figure 6 is of a stage according to the third exemplary embodiment of the present disclosure Figure 2 shown in the circuit diagram of the stage. In Figure 6 the same reference numerals are used to denote components identical to those of Figure 3 and a detailed description thereof will be omitted.

[0120] Referring to Figure 6 according to the third exemplary embodiment of the present disclosure, the stage 400-1 may include an input circuit 410, an output circuit 420, a first signal processor 430, a second signal processor 440, and a third signal processor 450.

[0121] Except for omitting the first stabilizer 461 and the second stabilizer 462, the stage 400-1 according to the third exemplary embodiment has the same configuration as that of Figure 3 Therefore, a detailed description of the operation process will be omitted.

[0122] In Figure 3In the exemplary embodiment shown, each of the first stabilizer 461 and the second stabilizer 462 may include a transistor that is always turned on. The transistors of the first stabilizer 461 and the second stabilizer 462 may be provided to reliably control Figure 3 the voltage drop widths of the third node N3 and the second node N2 shown therein, and basically do not affect the operation of the circuit. Therefore, even if the first stabilizer 461 and the second stabilizer 462 are omitted, Figure 5 the operation process of the circuit shown therein remains unchanged, but the second node N2 and the fourth node N4 may be substantially the same node, and the third node N3 and the fifth node N5 may be substantially the same node.

[0123] Although Figure 6 an example in which both the first stabilizer 461 and the second stabilizer 462 are omitted is shown, the inventive concept is not limited thereto. In other words, in the exemplary embodiment of the present disclosure, stage 400-1 may be configured such that only the first stabilizer 461 or the second stabilizer 462 is omitted.

[0124] Figure 7 is a circuit diagram of a stage according to a fourth exemplary embodiment of the present disclosure Figure 2 shown therein. Although Figure 7 only the i-th stage is shown, the other stages to be described below may have the same structure as the structure of the i-th stage shown Figure 2 therein.

[0125] Referring to Figure 1 , Figure 2 and Figure 7 , stage 400-2 according to the fourth embodiment of the present disclosure may include an input circuit 410, an output circuit 420, a first signal processor 430, a second signal processor 440, a third signal processor 450-1, a first stabilizer 461, and a second stabilizer 462.

[0126] Except that the third signal processor 450-1 further includes a thirteenth transistor M13 and a fourteenth transistor M14, the configuration of stage 400-2 according to the fourth exemplary embodiment is the same as the configuration of the Figure 3 exemplary embodiment. Therefore, the detailed description of other components will be omitted.

[0127] The thirteenth transistor M13 is coupled between the first power supply VDD and the eighth node N8. The gate electrode of the thirteenth transistor M13 is coupled to the third node N3. The thirteenth transistor M13 may be turned on in response to the voltage of the fifth node N5, so that the voltage of the first power supply VDD can be supplied to the eighth node N8.

[0128] The fourteenth transistor M14 is coupled between the eighth node N8 and the fourth node N4. The gate electrode of the fourteenth transistor M14 is coupled to the third input terminal 103. When the second clock signal CLK2 is supplied to the third input terminal 103, the fourteenth transistor M14 can be turned on to electrically couple the eighth node N8 and the fourth node N4.

[0129] In an exemplary embodiment of the present disclosure, each of the thirteenth transistor M13 and the fourteenth transistor M14 can be formed of a p-type transistor. In these exemplary embodiments, the gate turn-on voltage of the thirteenth transistor M13 and the fourteenth transistor M14 can be set to a low level, and the gate cut-off voltage of the thirteenth transistor M13 and the fourteenth transistor M14 can be set to a high level.

[0130] Figure 8 is a waveform diagram showing Figure 7 the operation of the stage shown in. For illustrative purposes, Figure 8 only the operation of the i-th stage is shown.

[0131] The process of the operation will be described. First, during a first time period t1, the first clock signal CLK1 can be supplied to the second input terminal 102. Accordingly, the first transistor M1 and the fifth transistor M5 can be turned on. In addition, during the first time period t1, the second clock signal CLK2 can be not supplied to the third input terminal 103. Accordingly, the seventh transistor M7 and the fourteenth transistor M14 can be turned off.

[0132] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 can be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 can also be coupled to the second node N2 via the fourth node N4.

[0133] Since during the first time period t1, the start signal FLM to be supplied to the first input terminal 101 or the emission control signal EM[i - 1] of the previous stage has a low level, a low voltage (e.g., the voltage of the second power supply VSS) can be applied to the fourth node N4 and the second node N2. When the fourth node N4 and the second node N2 are set to a low voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can be turned on.

[0134] When the third transistor M3 is turned on, the third input terminal 103 and the seventh node N7 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the first time period t1, a high voltage can be supplied to the seventh node N7. Here, the third capacitor C3 can be charged with a voltage corresponding to the on state of the third transistor M3.

[0135] When the fourth transistor M4 is turned on, the fifth transistor M5 can be connected between the third node N3 and the second power supply VSS in the form of a diode. Therefore, even when the fifth transistor M5 is turned on during the first period t1, the voltage of the second power supply VSS is not transmitted to the third node N3, and the voltage of the third node N3 can be maintained at the voltage of the previous state, for example, a high voltage. Since the eleventh transistor M11 remains turned on, the high voltage of the third node N3 can be applied to the fifth node N5, and the fifth node N5 can be set to a high voltage. Thus, the second transistor M2, the sixth transistor M6, and the thirteenth transistor M13 can be turned off.

[0136] When the eighth transistor M8 is turned on, the voltage of the first power supply VDD can be supplied to the first node N1. Therefore, the ninth transistor M9 can be turned off.

[0137] When the tenth transistor M10 is turned on, the voltage of the second power supply VSS can be supplied to the output terminal 104. Therefore, during the first period t1, the emission control signal EM[i] may not be supplied to the emission control line Ei.

[0138] During the second period t2, the supply of the first clock signal CLK1 to the second input terminal 102 can be interrupted. When the supply of the first clock signal CLK1 is interrupted, the first transistor M1 and the fifth transistor M5 can be turned off. Here, the first node N1 and the second node N2 can maintain the voltage of the previous period through the first capacitor C1 and the third capacitor C3. Since the first node N1 remains in the high voltage state, the ninth transistor M9 can remain turned off. Since the second node N2 remains in the low voltage state, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can remain turned on.

[0139] During the second period t2, the second clock signal CLK2 can be supplied to the third input terminal 103. The seventh transistor M7 and the fourteenth transistor M14 can be turned on by the second clock signal CLK2 supplied to the third input terminal 103. If the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 can be electrically coupled to each other. Since the eighth transistor M8 remains turned on, the voltage of the first node N1 can be maintained at a high level, and the sixth node N6 coupled to the first node N1 through the seventh transistor M7 can be maintained at a high voltage.

[0140] When the fourteenth transistor M14 is turned on, the fourth node N4 and the eighth node N8 can be electrically connected to each other, and the eighth node N8 can be set to a low voltage.

[0141] During the second period t2, the second clock signal CLK2 can be supplied to the seventh node N7 via the turned-on third transistor M3. Accordingly, a low voltage is supplied to the seventh node N7. Then, through the coupling of the third capacitor C3, the voltage of the second node N2 can be maintained at a voltage less than the voltage of the second power supply VSS (two-stage low voltage).

[0142] During the third period t3, the supply of the second clock signal CLK2 to the third input terminal 103 can be interrupted. When the supply of the second clock signal CLK2 is interrupted, the seventh transistor M7 and the fourteenth transistor M14 can be turned off.

[0143] During the third period t3, the start signal FLM or the emission control signal EM[i - 1] of the previous stage can be supplied to the first input terminal 101, and the first clock signal CLK1 can be supplied to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the first transistor M1 and the fifth transistor M5 can be turned on.

[0144] When the first transistor M1 is turned on, the first input terminal 101 and the fourth node N4 can be electrically coupled to each other. Since the twelfth transistor M12 remains turned on, the first input terminal 101 can also be electrically coupled to the second node N2 via the fourth node N4. Then, the fourth node N4 and the second node N2 can be set to a high voltage by the start signal FLM or the emission control signal EM[i - 1] supplied to the first input terminal 101. When the fourth node N4 and the second node N2 are set to a high voltage, the third transistor M3, the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 can be turned off.

[0145] If the fifth transistor M5 is turned on, the low voltage of the second power supply VSS can be applied to the third node N3, such that the third node N3 and the fifth node N5 are set to a low voltage. Accordingly, the second transistor M2, the sixth transistor M6, and the thirteenth transistor M13 can be turned on.

[0146] If the second transistor M2 is turned on, the voltage of the first power supply VDD can be applied to the seventh node N7. Accordingly, the seventh node N7 can be maintained at a high voltage. Here, since the third transistor M3 remains turned off, the voltage of the second clock signal CLK2 to be applied to the third input terminal 103 may not be transmitted to the seventh node N7. Further, since both the seventh node N7, which is the opposite end of the third capacitor C3, and the second node N2 are maintained at a high voltage, the third capacitor C3 may not be charged or discharged. Here, a current path can be formed from the first power supply VDD via the second transistor M2 to the second node N2, and the high voltage of the first power supply VDD can be transmitted to the second node N2. Accordingly, the voltage of the second node N2 can be stably maintained at a high level.

[0147] If the sixth transistor M6 is turned on, the third input terminal 103 and the sixth node N6 can be electrically coupled to each other. Since the second clock signal CLK2 is not supplied to the third input terminal 103 during the third period t3, the sixth node N6 can be maintained at a high voltage. Here, since the seventh transistor M7 remains turned off, the voltage of the sixth node N6 may not affect the voltage of the first node N1. The second capacitor C2 can store a voltage corresponding to the conduction level of the sixth transistor M6.

[0148] If the thirteenth transistor M13 is turned on, the voltage of the first power supply VDD can be applied to the eighth node N8. Accordingly, the eighth node N8 can be set to a high voltage.

[0149] During the fourth period t4, the second clock signal CLK2 can be supplied to the third input terminal 103. When the second clock signal CLK2 is supplied to the third input terminal 103, the seventh transistor M7 and the fourteenth transistor M14 can be turned on.

[0150] If the seventh transistor M7 is turned on, the first node N1 and the sixth node N6 can be electrically coupled to each other. Here, the low voltage of the second clock signal CLK2 supplied to the third input terminal 103 via the sixth transistor M6 that remains turned on can be supplied to the sixth node N6 and the first node N1. When a low voltage is supplied to the first node N1, the ninth transistor M9 can be turned on.

[0151] If the ninth transistor M9 is turned on, the voltage of the first power supply VDD can be supplied to the output terminal 104. The voltage of the first power supply VDD supplied to the output terminal 104 can be supplied as the emission control signal EM[i] to the i-th emission control line Ei.

[0152] When the fourteenth transistor M14 is turned on, a current path can be formed from the first power supply VDD via the thirteenth transistor M13 and the fourteenth transistor M14 to the second node N2, and the high voltage of the first power supply VDD can be transmitted to the second node N2. Therefore, the voltage of the second node N2 can be more stably maintained at a high level.

[0153] As described above, in the exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third transistor M3 that remains cut off can prevent the change in the voltage of the second clock signal CLK2 from affecting the second node N2, so that the second node N2 can be stably maintained at a high voltage. In addition, in the exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], charging or discharging of the third capacitor C3 can be prevented. In other words, the third capacitor C3 can not perform a charging or discharging operation at any time other than when the voltage of the second node N2 is set to a low level through the coupling of the third capacitor C3. Therefore, in the exemplary embodiment of the present disclosure, during the supply of the emission control signal EM[i], the third capacitor C3 can not be used as a load. Therefore, power consumption can be reduced, and reliable output of the emission control signal EM[i] can be ensured.

[0154] Figure 9 is a plan view showing an example of the layout of a stage according to an exemplary embodiment of the present disclosure. Figure 10 is a cross-sectional view taken along line I-I'. Specifically, Figure 9 and Figure 10 show Figure 4 the layout of the stage shown in

[0155] Referring to Figure 4 , Figure 9 and Figure 10 , the substrate SUB can be formed of a rigid substrate or a flexible substrate. Examples of the rigid substrate can include a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0156] Examples of the flexible substrate can include a film substrate and a plastic substrate, and each of the film substrate and the plastic substrate includes a polymer organic material. For example, the flexible substrate can include one of polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). In addition, the flexible substrate can include fiberglass-reinforced plastic (FRP).

[0157] The buffer layer BUF can cover the substrate SUB. The buffer layer BUF can prevent impurities from diffusing from the substrate SUB to the active layer ACT. The buffer layer BUF can be an inorganic insulating layer. For example, the buffer layer BUF can be formed of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or a combination thereof. Depending on the material and processing conditions of the substrate SUB, the buffer layer BUF can be omitted.

[0158] The active layer ACT can be provided on the buffer layer BUF. The active layer ACT is formed of a semiconductor material. For example, the active layer ACT can be formed of a material such as polysilicon, amorphous silicon, or an oxide semiconductor. The undoped portion of the active layer ACT can form the channels (e.g., CH10) of the transistors M1 to M12. The impurity-doped portion of the active layer ACT can form the electrodes SE1 to SE12 and DE1 to DE12 or the wires. The impurity can be a p-type impurity. In some exemplary embodiments, the impurity can include at least one of a p-type impurity, an n-type impurity, and other metals.

[0159] The first gate insulating layer GI1 can cover the active layer ACT. The first gate insulating layer GI1 can cover the source electrodes SE1 to SE12, the drain electrodes DE1 to DE12, and the channels (e.g., CH10) of the transistors M1 to M12. The first gate insulating layer GI1 can be an inorganic insulating layer. For example, the first gate insulating layer GI1 can be formed of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or a combination thereof.

[0160] The gate electrodes GE1 to GE12 of the transistors M1 to M12 and the first electrodes LE1 to LE3 of the storage capacitors C1 to C3 can be provided on the first gate insulating layer GI1. The electrodes provided on the first gate insulating layer GI1 can be formed of the same conductive material. For example, the electrodes located on the first gate insulating layer GI1 can be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or a combination thereof.

[0161] The second gate insulating layer GI2 can cover the first gate insulating layer GI1, the gate electrodes GE1 to GE12 of the transistors M1 to M12, and the first electrodes LE1 to LE3 of the storage capacitors C1 to C3. The second gate insulating layer GI2 can be an inorganic insulating layer. For example, the second gate insulating layer GI2 can be formed of silicon nitride (SiN x ), silicon oxide (SiO x)、silicon oxynitride (SiO x N y ) or a combination thereof.

[0162] The second electrodes VE1 to VE3 of the storage capacitors C1 to C3 and the emission control line Ei may be provided on the second gate insulating layer GI2. The electrodes and lines provided on the second gate insulating layer GI2 may be formed of the same conductive material. For example, the electrodes and lines provided on the second gate insulating layer GI2 may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or a combination thereof.

[0163] The interlayer insulating layer ILD may cover the second gate insulating layer GI2, the second electrodes VE1 to VE3 of the storage capacitors C1 to C3, and the emission control line Ei. The interlayer insulating layer ILD may be an inorganic insulating layer. For example, the interlayer insulating layer ILD may be formed of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or a combination thereof.

[0164] The first power supply VDD, the second power supply VSS, and the power supply lines for the first clock signal CLK1 and the second clock signal CLK2 may be provided on the interlayer insulating layer ILD. The lines provided on the interlayer insulating layer ILD may be made of the same conductive material. For example, the lines provided on the first gate insulating layer GI1 may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or a combination thereof.

[0165] The via layer VIA may cover the interlayer insulating layer ILD. The via layer VIA may be an organic insulating layer. For example, the via layer VIA may include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyaryl ether (PAE), heterocyclic polymers, parylene, epoxy resin, benzocyclobutene (BCB), silicone-based resins, and silane-based resins. In an exemplary embodiment, the via layer VIA may be an inorganic insulating layer, or may have a multilayer structure formed by alternately stacking an organic insulating layer and an inorganic insulating layer.

[0166] In an exemplary embodiment of the present disclosure, other electrodes or lines may not be disposed above or below a line extending from one electrode LE3 of the third capacitor C3 to the second node N2. Accordingly, the second node N2 can be prevented from being affected by a field effect caused by electrodes and / or lines that may be disposed above or below the second node N2. Due to the above structure, the voltage of the second node N2 can be reliably maintained at a voltage to be controlled by the transistors M1 to M12.

[0167] In a stage and an emission control driver having the stage according to an exemplary embodiment of the present disclosure, when an emission control signal is held at a low voltage, the voltage of a node for controlling the output of the emission control signal can be stably held at a high voltage. Accordingly, a flicker phenomenon of a display device due to an abnormal emission control signal can be prevented.

[0168] In addition, in a stage and an emission control driver having the stage according to an exemplary embodiment of the present disclosure, charging or discharging of a capacitor provided in the stage can be prevented while the emission control signal is held at a low voltage, so that power consumption can be reduced regardless of a non-emission section ratio (referred to as an off ratio) in a frame period.

[0169] The present disclosure should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0170] Although certain exemplary embodiments have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but to the broader scope of the present disclosure and various apparent modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A level circuit, wherein, The stage circuit includes: An output circuit configured to supply the voltage of a first power supply or the voltage of a second power supply to an output terminal in response to the voltage of a first node and the voltage of a second node; An input circuit configured to control the voltage of the second node and the voltage of a third node in response to respective signals supplied to a first input terminal and a second input terminal; A first signal processor configured to control the voltage of the first node in response to the voltage of the second node; A second signal processor coupled between the first node and the third node and configured to control the voltage of the first node in response to the output voltage of a third signal processor and a signal supplied to a third input terminal; The third signal processor configured to control the voltage of the second node in response to a signal supplied to the first input terminal; and A second stabilizer coupled between the second node and a fourth node coupled to the first input terminal, the second stabilizer configured to control the voltage drop width of the second node, wherein the third signal processor includes: A third capacitor coupled between the first power supply and the second node; and A third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node, and wherein the input circuit includes a first transistor directly coupled between the first input terminal and the fourth node, the first transistor including a gate electrode coupled to the second input terminal, wherein the stage circuit further includes: A first gate insulating layer configured to cover the source electrode and the drain electrode of at least one transistor; A second gate insulating layer configured to cover the gate electrode of the at least one transistor and the first electrode of at least one capacitor; and An interlayer insulating layer configured to cover the second electrode of the at least one capacitor, wherein: The second gate insulating layer covers a line extending from the gate electrode of the third transistor to the second node; and The line is arranged not to overlap with the source electrode and the drain electrode covered by the first gate insulating layer or not to overlap with the second electrode covered by the interlayer insulating layer.

2. The stage circuit according to claim 1, wherein When supplying the voltage of the first power supply to the output terminal in response to the voltage of the second node, the third transistor is turned off, such that a path for blocking current flowing from the second input terminal to the second node is formed.

3. The stage circuit according to claim 1, wherein, While supplying the voltage of the first power supply to the output terminal in response to the voltage of the second node, the potential difference between opposite ends of the third capacitor remains constant.

4. The stage circuit according to claim 1, wherein: The third signal processor further includes: a second transistor coupled between the first power supply and a common node between the third capacitor and the third transistor, the second transistor including a gate electrode coupled to the third node; and When supplying the voltage of the first power supply to the output terminal in response to the voltage of the second node, the voltage of the first power supply is applied to the second node via the second transistor and the third capacitor.

5. The stage circuit according to claim 1, wherein The second input terminal is supplied with a first clock signal, the third input terminal is supplied with a second clock signal, and the first clock signal and the second clock signal have the same waveform with a phase difference of half a cycle or more.

6. The stage circuit according to claim 5, wherein, The gate turn-on voltage portion of the signal supplied to the first input terminal overlaps the gate turn-on voltage portion of the first clock signal at least once.

7. The stage circuit according to claim 4, wherein, The third signal processor further includes: a fourth transistor coupled between the third node and the second input terminal and including a gate electrode coupled to the second node; and a fifth transistor coupled between the third node and the second power supply and including a gate electrode coupled to the second input terminal.

8. The stage circuit according to claim 7, wherein: the fourth transistor includes a plurality of sub-transistors connected in series between the third node and the second input terminal; and the gate electrodes of the plurality of sub-transistors are coupled to the second node.

9. The stage circuit according to claim 7, wherein, The third signal processor includes: a thirteenth transistor coupled between the first power supply and the eighth node and including a gate electrode coupled to the third node; and a fourteenth transistor coupled between the eighth node and the second node and including a gate electrode coupled to the third input terminal.

10. The stage circuit according to claim 1, wherein, The second signal processor includes: a second capacitor coupled between the third node and the sixth node; a sixth transistor coupled between the sixth node and the third input terminal and including a gate electrode coupled to the third node; and a seventh transistor coupled between the first node and the sixth node and including a gate electrode coupled to the third input terminal.

11. The stage circuit according to claim 1, wherein, The first signal processor includes: a first capacitor coupled between the first power supply and the first node; and an eighth transistor coupled between the first power supply and the first node and including a gate electrode coupled to the second node.

12. The stage circuit according to claim 1, wherein, The output circuit includes: a ninth transistor coupled between the first power supply and the output terminal and including a gate electrode coupled to the first node; and a tenth transistor coupled between the output terminal and the second power supply and including a gate electrode coupled to the second node.

13. The stage circuit according to claim 1, wherein, The stage circuit further includes: a first stabilizer coupled between the second signal processor and the third signal processor and configured to control the voltage drop width of the third node.

14. A transmission control driver, including a plurality of stage circuits configured to supply a transmission signal to a transmission control line, wherein: each of the plurality of stage circuits includes: an output circuit configured to supply the voltage of the first power supply or the voltage of the second power supply to the output terminal in response to the voltage of the first node and the voltage of the second node; An input circuit configured to control the voltage of the second node and the voltage of the third node in response to respective signals supplied to a first input terminal and a second input terminal; A first signal processor configured to control the voltage of the first node in response to the voltage of the second node; A second signal processor connected between the first node and the third node and configured to control the voltage of the first node in response to a signal supplied to the second input terminal and a signal supplied to a third input terminal; A third signal processor configured to control the voltage of the second node in response to a signal supplied to the first input terminal; and A second stabilizer coupled between the second node and a fourth node coupled to the first input terminal, the second stabilizer configured to control the voltage drop width of the second node, The third signal processor includes: A third capacitor coupled between the first power supply and the second node; and A third transistor coupled between the first power supply and the third input terminal and including a gate electrode coupled to the second node, and Wherein, the input circuit includes a first transistor directly coupled between the first input terminal and the fourth node, the first transistor including a gate electrode coupled to the second input terminal, Wherein, each stage circuit of the plurality of stage circuits further includes: A first gate insulating layer configured to cover a source electrode and a drain electrode of at least one transistor; A second gate insulating layer configured to cover a gate electrode of the at least one transistor and a first electrode of at least one capacitor; and An interlayer insulating layer configured to cover a second electrode of the at least one capacitor, Wherein: The second gate insulating layer covers a line extending from the gate electrode of the third transistor to the second node; and The line is arranged not to overlap with the source electrode and the drain electrode covered by the first gate insulating layer, or not to overlap with the second electrode covered by the interlayer insulating layer.

15. The emission control driver according to claim 14, wherein, When the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, the third transistor is turned off, so as to block the path of the current flowing from the second input terminal to the second node.

16. The emission control driver according to claim 14, wherein While the voltage of the first power supply is supplied to the output terminal in response to the voltage of the second node, the potential difference between opposite ends of the third capacitor remains constant.

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