Semiconductor device including upper selector and lower selector

Abstract

A semiconductor device includes: a lower stack structure including a lower word line; an upper stack structure on the lower stack structure and including the upper word line; a decoder adjacent to the lower stack structure and the upper stack structure; a signal interconnect connected to the decoder; a lower selector connected to the signal interconnect and also connected to the lower word line; and an upper selector connected to the signal interconnect, not in direct contact with the lower selector, and also connected to the upper word line.

Description

Technical Field

[0001] Devices and methods consistent with example embodiments relate to a semiconductor device having one or more selectors and a method of forming the semiconductor device. Background Art

[0002] As the integration density of semiconductor devices increases, technologies for vertically forming multiple stacked structures have been attempted. The number (amount) of address signal interconnects has gradually increased. The increase in the number of interconnects makes it difficult to improve the integration density. The technology of connecting two components to one interconnect leads to unnecessary increase in power consumption. Summary of the Invention

[0003] Some example embodiments of the inventive concepts are directed to providing a semiconductor device that facilitates high integration density and exhibits low power consumption, and a method of forming the semiconductor device.

[0004] According to some example embodiments, a semiconductor device may include: a lower stacked structure including a plurality of lower word lines and a plurality of lower insulating layers stacked alternately; a plurality of lower channel structures configured to extend through the lower stacked structure; an upper stacked structure on the lower stacked structure, the upper stacked structure including a plurality of upper word lines and a plurality of upper insulating layers stacked alternately; a plurality of upper channel structures not in direct contact with the plurality of lower channel structures, the plurality of upper channel structures configured to extend through the upper stacked structure; a decoder adjacent to the lower stacked structure and the upper stacked structure; a plurality of signal interconnects connected to the decoder; a plurality of lower selectors connected to the plurality of lower word lines; and a plurality of upper selectors connected to the plurality of upper word lines. Each of the plurality of signal interconnects may be connected to a corresponding lower selector among the plurality of lower selectors and a corresponding upper selector among the plurality of upper selectors.

[0005] According to some example embodiments, a semiconductor device may include: a lower stack structure comprising a plurality of lower word lines and a plurality of lower insulating layers stacked alternately; a plurality of lower channel structures configured to extend through the lower stack structure; an upper stack structure on the lower stack structure, the upper stack structure comprising a plurality of upper word lines and a plurality of upper insulating layers stacked alternately; a plurality of upper channel structures not in direct contact with the plurality of lower channel structures, the plurality of upper channel structures being configured to extend through the upper stack structure; a decoder adjacent to the lower stack structure and the upper stack structure; a signal interconnection connected to the decoder; a lower selector connected to the signal interconnection and also connected to one of the plurality of lower word lines; and an upper selector not in direct contact with the lower selector, connected to the signal interconnection, and also connected to one of the plurality of upper word lines.

[0006] According to some example embodiments, a semiconductor device may include: a lower stack structure including a lower word line; an upper stack structure on the lower stack structure, the upper stack structure including an upper word line; a decoder adjacent to the lower stack structure and the upper stack structure; a signal interconnect connected to the decoder; a lower selector connected to the signal interconnect and to the lower word line; and an upper selector connected to the signal interconnect, not in direct contact with the lower selector, and also connected to the upper word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram of a semiconductor device according to some example embodiments.

[0008] Figure 2 is a cross-sectional view illustrating a semiconductor device according to some example embodiments.

[0009] Figure 3 、 Figure 4 、 Figure 5 and Figure 6 According to some example embodiments Figure 2 A magnified view of a portion of the .

[0010] Figure 7 、 Figure 8 and Figure 9 are cross-sectional views illustrating some components of a semiconductor device according to some example embodiments.

[0011] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 According to some example embodiments Figure 2 A magnified view of a portion of the .

[0012] Figure 15 and Figure 16 is a cross-sectional view illustrating a semiconductor device according to some example embodiments.

[0013] Figure 17 is a circuit diagram illustrating a semiconductor device according to some example embodiments.

[0014] Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 and Figure 22 is a cross-sectional view illustrating a method of forming a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0015] Figure 1is a circuit diagram of a semiconductor device according to some example embodiments.A semiconductor device according to some example embodiments may include a nonvolatile memory such as a VNAND or a three-dimensional (3D) flash memory.

[0016] Reference Figure 1 According to some example embodiments, a semiconductor device may include a lower stacked structure ST1, a plurality of lower bit lines B11 and B12, a plurality of upper bit lines B21 and B22, an upper stacked structure ST2, a plurality of lower selectors SS11, SS12, SS13, and SS14, a plurality of upper selectors SS21, SS22, SS23, and SS24, and a decoder XD. In some example embodiments, the decoder XD may correspond to an address decoder or an X-decoder.

[0017] The lower stacked structure ST1 may include a lower source line C11 and a plurality of lower strings NS11, NS12, NS13, and NS14. Each of the plurality of lower strings NS11, NS12, NS13, and NS14 may include a lower ground selection transistor GST1, a plurality of lower memory cells MC11, MC12, MC13, and MC14, and a lower string selection transistor SST1. The lower ground selection transistor GST1 may be connected to the lower ground selection line G11. Each of the plurality of lower memory cells MC11, MC12, MC13, and MC14 may be connected to a corresponding one of the plurality of lower word lines W11, W12, W13, and W14. The lower string selection transistor SST1 may be connected to a corresponding one of the plurality of lower string selection lines S11 and S12.

[0018] The upper stacked structure ST2 may include an upper source line C21 and a plurality of upper strings NS21, NS22, NS23, and NS24. Each of the plurality of upper strings NS21, NS22, NS23, and NS24 may include an upper ground selection transistor GST2, a plurality of upper memory cells MC21, MC22, MC23, and MC24, and an upper string selection transistor SST2. The upper ground selection transistor GST2 may be connected to the upper ground selection line G21. Each of the plurality of upper memory cells MC21, MC22, MC23, and MC24 may be connected to a corresponding one of the plurality of upper word lines W21, W22, W23, and W24. The upper string selection transistor SST2 may be connected to a corresponding one of the plurality of upper string selection lines S21 and S22.

[0019] Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 may be connected to a corresponding one of the plurality of signal interconnects D1, D2, D3, and D4. Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 may be connected to a corresponding one of the plurality of lower word lines W11, W12, W13, and W14. The plurality of lower selectors SS11, SS12, SS13, and SS14 may include a lower select line SSG1. Each of the plurality of upper selectors SS21, SS22, SS23, and SS24 may be connected to a corresponding one of the plurality of signal interconnects D1, D2, D3, and D4. Each of the plurality of upper selectors SS21, SS22, SS23, and SS24 may be connected to a corresponding one of the plurality of upper word lines W24, W23, W22, and W21. The plurality of upper selectors SS21, SS22, SS23, and SS24 may include an upper select line SSG2.

[0020] Figure 2 is a cross-sectional view illustrating a semiconductor device according to some example embodiments.

[0021] Reference Figure 2 The semiconductor device according to some example embodiments may include a first substrate 21, a buried conductive layer 23, a replacement conductive line 25, a support portion 27, a plurality of lower insulating layers 31, a lower ground selection line G11, a plurality of lower word lines W11, W12, W13, and W14, a lower string selection line S11, a plurality of lower channel structures 32, a plurality of lower bit lines B11, a first insulating layer 41, a plurality of lower contact plugs 43, a second insulating layer 45, a plurality of intermediate pads 47, a plurality of upper bit lines B21, a plurality of upper insulating layers 51, an upper string selection line S21, a plurality of upper word lines W21, W22, W23, and W24, an upper ground selection line G21, a plurality of upper channel structures 52, an upper source line C 21, a third insulating layer 61, a fourth insulating layer 62, a plurality of upper contact plugs 64, a fifth insulating layer 66, a plurality of upper pads 67, a plurality of first electrodes 71A, a plurality of lower selection channel structures 73A, a plurality of second electrodes 79A, a plurality of third electrodes 71B, a plurality of upper selection channel structures 73B, a plurality of fourth electrodes 79B, a lower selection line SSG1, an upper selection line SSG2, a sixth insulating layer 81, a seventh insulating layer 82, an eighth insulating layer 83, a ninth insulating layer 84, a tenth insulating layer 89, a plurality of bonding pads 90, an eleventh insulating layer 91, a plurality of signal interconnections D1, D2, D3 and D4, a decoder XD, a plurality of transistors 93, a device isolation layer 95 and a second substrate 99.

[0022] Each of the plurality of upper channel structures 52 may include an upper source pad 59. The buried conductive layer 23 and the replacement conductive line 25 may at least partially constitute a lower source line C11. The plurality of first electrodes 71A, the plurality of lower selection channel structures 73A, the plurality of second electrodes 79A, and the lower selection line SSG1 may at least partially constitute a plurality of lower selectors SS11, SS12, SS13, and SS14. The plurality of third electrodes 71B, the plurality of upper selection channel structures 73B, the plurality of fourth electrodes 79B, and the upper selection line SSG2 may at least partially constitute a plurality of upper selectors SS21, SS22, SS23, and SS24.

[0023] In some example embodiments, the lower stacked structure ST1 may include a buried conductive layer 23, a replacement conductive line 25, a support portion 27, a plurality of lower insulating layers 31, a lower ground selection line G11, a plurality of lower word lines W11, W12, W13, and W14, and a lower string selection line S11. Figure 2 As shown, in some example embodiments, the lower stacked structure ST1 may include a plurality of lower word lines W11, W12, W13, and W14 and a plurality of lower insulating layers 31, wherein the plurality of lower word lines W11, W12, W13, and W14 and the plurality of lower insulating layers 31 are alternately stacked, so that it will be understood that, as shown in FIG. Figure 2 As shown, the lower stacked structure ST1 may include a plurality of lower word lines W11, W12, W13, and W14 and a plurality of lower insulating layers 31 that are alternately stacked, such that the lower insulating layers 31 are interposed between adjacent lower word lines, and the lower word lines are interposed between adjacent lower insulating layers 31. Figure 2 As shown, the upper stack structure ST2 may be on the lower stack structure ST1. The upper stack structure ST2 may include a plurality of upper insulating layers 51, an upper string selection line S21, a plurality of upper word lines W21, W22, W23, and W24, an upper ground selection line G21, a plurality of upper channel structures 52, and an upper source line C21. Figure 2 As shown, in some example embodiments, the upper stacked structure ST2 may include a plurality of upper word lines W21, W22, W23, and W24 and a plurality of upper insulating layers 51, wherein the plurality of upper word lines W21, W22, W23, and W24 and the plurality of upper insulating layers 51 are alternately stacked, so that it will be understood that, as shown in FIG. Figure 2 As shown, the upper stacked structure ST2 may include a plurality of upper word lines W21, W22, W23 and W24 alternately stacked and a plurality of upper insulating layers 51, so that upper insulating layers 51 are inserted between adjacent upper word lines and upper word lines are inserted between adjacent upper insulating layers 51.

[0024] It will be understood that an element "on" another element can be above or below the other element. It will also be understood that an element "on" another element can be "directly" on the other element such that the elements are in direct contact with each other, or can be "indirectly" on the other element such that the elements are not in direct contact with each other via one or more intervening spaces and / or structures.

[0025] Figure 3 、 Figure 4 、 Figure 5 and Figure 6 According to some example embodiments Figure 2 An enlarged view of a portion or a variation thereof.

[0026] Reference Figure 3 , the first lower selector SS11 may include a lower selection channel structure 73A disposed between a first electrode 71A and a second electrode 79A. In some example embodiments, Figure 2 Each of the plurality of lower selection channel structures 73A and the plurality of upper selection channel structures 73B shown may include Figure 3 The structure of the lower selection channel structure 73A is shown. The lower selection channel structure 73A may pass through the lower selection line SSG1. The lower selection channel structure 73A may include a gate dielectric layer 74, a channel layer 75, and a core layer 76. The channel layer 75 may partially or completely surround the outer side of the core layer 76 (for example, as shown in FIG. Figure 3 The gate dielectric layer 74 may partially or completely surround the outer side of the channel layer 75 (e.g., as shown in FIG. Figure 3 As shown, the gate dielectric layer 74 completely surrounds the outer longitudinal surface 75S of the channel layer 75. The gate dielectric layer 74 may be interposed between the lower selection line SSG1 and the channel layer 75. Figure 3 As shown, the channel layer 75 may be connected to the first electrode 71A and the second electrode 79A (eg, in the lower selection channel structure 73A), or the channel layer 75 may be connected to the third electrode 71B and the fourth electrode 79B (eg, in the upper selection channel structure 73B).

[0027] The gate dielectric layer 74 may include silicon oxide, a high-k dielectric, or a combination thereof. The channel layer 75 may include a semiconductor layer including polycrystalline silicon, amorphous silicon, single crystal silicon, or a combination thereof. The channel layer 75 may include P-type impurities. In some example embodiments, semiconductor layers including N-type impurities may be formed at both ends of the channel layer 75. The core layer 76 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, polycrystalline silicon, or a combination thereof.

[0028] Each of the gate dielectric layer 74, the channel layer 75, and the core layer 76 may be in direct contact with the first electrode 71A and the second electrode 79A. Each of the first electrode 71A and the second electrode 79A may include a conductive layer containing a metal, a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a combination thereof. In some example embodiments, each of the first electrode 71A and the second electrode 79A may include a polysilicon layer containing N-type impurities. Each of the first electrode 71A and the second electrode 79A may function as a source or a drain. The lower select line SSG1 may function as a gate electrode. The lower select line SSG1, the lower select channel structure 73A, the first electrode 71A, and the second electrode 79A may at least partially constitute a transistor. Figure 2 Each of the other lower selectors SS12 , SS13 , and SS14 shown may include substantially the same configuration as the first lower selector SS11 .

[0029] The first upper selector SS21 may include an upper selection channel structure 73B disposed between the third electrode 71B and the fourth electrode 79B. The upper selection channel structure 73B may pass through the upper selection line SSG2. The upper selection channel structure 73B may include a configuration substantially the same as the lower selection channel structure 73A. Each of the gate dielectric layer 74, the channel layer 75, and the core layer 76 may be in direct contact with the third electrode 71B and the fourth electrode 79B. Each of the third electrode 71B and the fourth electrode 79B may include a configuration substantially the same as the first electrode 71A or the second electrode 79A. Each of the third electrode 71B and the fourth electrode 79B may function as a source or a drain. The upper selection line SSG2 may function as a gate electrode. Figure 2 Each of the other upper selectors SS22 , SS23 , and SS24 shown may include substantially the same configuration as the first upper selector SS21 .

[0030] Reference Figure 4 , the channel layer 75 may surround one end of the core layer 76. In some example embodiments, Figure 2 Each of the illustrated plurality of lower selection channel structures 73A and the plurality of upper selection channel structures 73B may be modified to include Figure 4 The structure of the lower selection channel structure 73A is shown.

[0031] The first electrode 71A or the third electrode 71B may be in direct contact with the gate dielectric layer 74 and the channel layer 75. Figure 4 As shown, the channel layer 75 may be connected to the first electrode 71A and the second electrode 79A (eg, in the lower selection channel structure 73A), or the channel layer 75 may be connected to the third electrode 71B and the fourth electrode 79B (eg, in the upper selection channel structure 73B).

[0032] Reference Figure 5 , the lower selection channel structure 73A (and / or the upper selection channel structure 73B) may include a gate dielectric layer 74, a channel layer 75, a core layer 76, and a selection pad 77. The selection pad 77 may be disposed between the channel layer 75 and the second electrode 79A (when included in the lower selection channel structure 73A), or between the channel layer 75 and the fourth electrode 79B (when included in the upper selection channel structure 73B). The selection pad 77 may include a polysilicon layer containing N-type impurities. The selection pad 77 may serve as a source or a drain. The upper selection channel structure 73B may include a configuration substantially the same as the lower selection channel structure 73A. In some example embodiments, Figure 2 Each of the illustrated plurality of lower selection channel structures 73A and the plurality of upper selection channel structures 73B may be modified to include Figure 5 The structure of the lower selection channel structure 73A is shown.

[0033] Reference Figure 6 The lower selection channel structure 73A (and / or the upper selection channel structure 73B) may include a channel layer 75 and a gate dielectric layer 74, the gate dielectric layer 74 being configured to partially or completely surround the outer side of the channel layer 75 (e.g., as shown in FIG. 1 ). Figure 6 As shown, it completely surrounds the outer longitudinal surface 75S of the channel layer 75. In some example embodiments, Figure 2 Each of the illustrated plurality of lower selection channel structures 73A and the plurality of upper selection channel structures 73B may be modified to include Figure 6 The structure of the lower selection channel structure 73A is shown. Figure 6 As shown, the channel layer 75 may be connected to the first electrode 71A and the second electrode 79A (eg, in the lower selection channel structure 73A), or the channel layer 75 may be connected to the third electrode 71B and the fourth electrode 79B (eg, in the upper selection channel structure 73B).

[0034] Figure 7 、 Figure 8 and Figure 9 are cross-sectional views illustrating some components of a semiconductor device according to some example embodiments.

[0035] Reference Figure 7The first lower selector SS11 may include a plurality of first electrodes 71AA and 71AB, a plurality of lower selection channel structures 73AA, 73AB, and 73AC, and a plurality of second electrodes 79AA and 79AB. Each of the plurality of lower selection channel structures 73AA, 73AB, and 73AC may pass through a lower selection line SSG1. The plurality of first electrodes 71AA and 71AB, the plurality of lower selection channel structures 73AA, 73AB, and 73AC, the plurality of second electrodes 79AA and 79AB, and the lower selection line SSG1 may at least partially constitute a plurality of vertical transistors. The first lower selector SS11 may include a plurality of vertical transistors connected in series.

[0036] Figure 2 Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 shown may be modified to include Figure 7 The configuration of the first lower selector SS11 shown is substantially the same or similar configuration. Therefore, it will be understood that each of the plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 may include one or more transistors.

[0037] Reference Figure 8 The first lower selector SS11 may include a first electrode 71A, a plurality of lower selection channel structures 73AA and 73AB, and a second electrode 79A. Each of the plurality of lower selection channel structures 73AA and 73AB may pass through the lower selection line SSG1. The first lower selector SS11 may include a plurality of vertical transistors connected in parallel. Figure 2 Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 shown may be modified to include Figure 8 The configuration of the first lower selector SS11 shown is substantially the same or similar to that of the first lower selector SS11. Therefore, it will be understood that each of the plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 may include one or more transistors. In addition, as at least Figure 8 As shown, each selector may include a plurality of vertical transistors, and at least one pair of vertical transistors among the plurality of vertical transistors may be connected in parallel.

[0038] Reference Figure 9The first lower selector SS11 may include a plurality of first electrodes 71AA and 71AB, a plurality of lower selection channel structures 73AA, 73AB, 73AC, 73AD, 73AE, and 73AF, and a plurality of second electrodes 79AA and 79AB. Each of the plurality of lower selection channel structures 73AA, 73AB, 73AC, 73AD, 73AE, and 73AF may pass through the lower selection line SSG1. Figure 2 Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 shown may be modified to include Figure 9 The configuration of the first lower selector SS11 shown is substantially the same or similar to that of the first lower selector SS11. Figure 9 As shown, each selector may include a plurality of vertical transistors, and the plurality of vertical transistors may be connected in parallel first and then in series.

[0039] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 According to some example embodiments Figure 2 A magnified view of a portion of the .

[0040] Reference Figure 10 , the lower channel structure 32 may pass through the first lower word line W11. The lower channel structure 32 may include a lower information storage pattern 36, a lower channel pattern 37, and a lower core pattern 38. The lower channel pattern 37 may surround the outer side of the lower core pattern 38. The lower information storage pattern 36 may surround the outer side of the lower channel pattern 37. The lower information storage pattern 36 may include a lower tunnel insulating layer 33 configured to surround the outer side of the lower channel pattern 37, a lower charge storage layer 34 configured to surround the outer side of the lower tunnel insulating layer 33, and a lower barrier layer 35 configured to surround the outer side of the lower charge storage layer 34. The lower barrier layer 35 may be interposed between the lower charge storage layer 34 and the first lower word line W11.

[0041] The lower tunnel insulating layer 33 may include an insulating layer comprising silicon oxide. The lower charge storage layer 34 may include an insulating layer comprising silicon nitride. The lower barrier layer 35 may include an insulating layer comprising silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. The lower channel pattern 37 may include a semiconductor layer comprising polycrystalline silicon, amorphous silicon, single crystal silicon, or a combination thereof. The lower channel pattern 37 may include P-type impurities. The lower core pattern 38 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, polycrystalline silicon, or a combination thereof.

[0042] Reference Figure 11, the upper channel structure 52 may pass through the first upper word line W21. The upper channel structure 52 may include an upper information storage pattern 56, an upper channel pattern 57, and an upper core pattern 58. The upper channel pattern 57 may surround the outer side of the upper core pattern 58. The upper information storage pattern 56 may surround the outer side of the upper channel pattern 57. The upper information storage pattern 56 may include an upper tunnel insulating layer 53 configured to surround the outer side of the upper channel pattern 57, an upper charge storage layer 54 configured to surround the outer side of the upper tunnel insulating layer 53, and an upper barrier layer 55 configured to surround the outer side of the upper charge storage layer 54. The upper barrier layer 55 may be interposed between the upper charge storage layer 54 and the first upper word line W21. The upper tunnel insulating layer 53, the upper charge storage layer 54, the upper blocking layer 55, the upper channel pattern 57 and the upper core pattern 58 may respectively include materials similar to those used for the lower tunnel insulating layer 33, the lower charge storage layer 34, the lower blocking layer 35, the lower channel pattern 37 and the lower core pattern 38.

[0043] Reference Figure 12 , a lower bit line B11 may be disposed on the lower channel structure 32. To reiterate, each of the plurality of lower bit lines B11 may be connected to a corresponding lower channel structure 32 among the plurality of lower channel structures 32. The lower channel structure 32 may pass through the lower string select line S11. The lower channel structure 32 may include a lower information storage pattern 36, a lower channel pattern 37, a lower core pattern 38, and a lower pad 39. The lower pad 39 may be disposed between the lower channel pattern 37 and the lower bit line B11. The lower pad 39 may include a polysilicon layer containing N-type impurities. The lower pad 39 may function as a source or a drain.

[0044] Reference Figure 13 , the upper channel structure 52 may be disposed on the upper bit line B21. To reiterate, each of the plurality of upper bit lines B21 may be connected to a separate corresponding upper channel structure 52 among the plurality of upper channel structures 52. The upper channel structure 52 may pass through the upper string selection line S21.

[0045] Reference Figure 14 , the replacement conductive line 25 may pass through the lower information storage pattern 36 and directly contact the side surface of the lower channel pattern 37. The buried conductive layer 23 and the replacement conductive line 25 may at least partially constitute the lower source line C11. The lower channel pattern 37 may be electrically connected to the lower source line C11.

[0046] Refer again Figures 1 to 14, the lower stacked structure ST1 may be disposed on the first substrate 21. The lower stacked structure ST1 may include a plurality of lower insulating layers 31 and a plurality of lower word lines W11, W12, W13, and W14 that are alternately and repeatedly stacked. A lower ground selection line G11 may be disposed between the first substrate 21 and the plurality of lower word lines W11, W12, W13, and W14. A buried conductive layer 23, a replacement conductive line 25, and a support portion 27 may be sequentially stacked between the first substrate 21 and the lower ground selection line G11. A plurality of lower string selection lines S11 and S12 may be disposed on the plurality of lower word lines W11, W12, W13, and W14.

[0047] If at least Figure 2 As shown, a plurality of lower channel structures 32 may pass through (extend through) the lower stacked structure ST1. Each of the plurality of lower channel structures 32 may vertically pass through the plurality of lower insulating layers 31, the lower string selection line S11, the plurality of lower word lines W11, W12, W13, and W14, the lower ground selection line G11, the support portion 27, and the replacement conductive line 25 and penetrate into the buried conductive layer 23. Each of the plurality of lower channel structures 32 may include a plurality of lower insulating layers 31, the lower string selection line S11, the plurality of lower word lines W11, W12, W13, and W14, the lower ground selection line G11, the support portion 27, and the replacement conductive line 25 and penetrate into the buried conductive layer 23. Figure 2 、 Figure 10 、 Figure 12 and Figure 14 The configuration described is similar to the one described above.

[0048] An edge of the lower ground selection line G11, edges of the plurality of lower word lines W11, W12, W13, and W14, and edges of the plurality of lower string selection lines S11 and S12 may be covered by the first insulating layer 41. Each of the plurality of lower contact plugs 43 may pass through the first insulating layer 41 and directly contact a corresponding one of the lower ground selection line G11, the plurality of lower word lines W11, W12, W13, and W14, and the plurality of lower string selection lines S11 and S12.

[0049] The second insulating layer 45 may cover the lower stacked structure ST1 and the first insulating layer 41. A plurality of lower bit wires B11 and B12, a plurality of upper bit wires B21 and B22, and a plurality of intermediate pads 47 may be provided in the second insulating layer 45. For example, as at least Figure 2 As shown, the plurality of lower bit wires B11 and the plurality of upper bit wires B21 may be adjacent to each other between the lower stack structure ST1 and the upper stack structure ST2. The plurality of lower bit wires B11 and B12, the plurality of upper bit wires B21 and B22, and the plurality of intermediate pads 47 may be disposed at substantially the same level. Figure 2As shown, the plurality of upper bit lines B21 and B22 may be spaced apart from (not in direct contact with) the plurality of lower bit lines B11 and B12. Each of the plurality of upper bit lines (B21 and B22) may be disposed between adjacent lower bit lines among the plurality of lower bit lines (B11 and B12). The plurality of lower bit lines (B11 and B12) may respectively contact the upper ends of the plurality of lower channel structures 32. The plurality of intermediate pads 47 may respectively contact the upper ends of the plurality of lower contact plugs 43.

[0050] The upper stacked structure ST2 may be disposed on the second insulating layer 45. The upper stacked structure ST2 may include a plurality of upper insulating layers 51 and a plurality of upper word lines W21, W22, W23, and W24 that are alternately and repeatedly stacked. A plurality of upper string selection lines S21 and S22 may be disposed between the second insulating layer 45 and the plurality of upper word lines W21, W22, W23, and W24. Figure 2 As shown, the plurality of upper string selection lines S21 and S22 may be between the plurality of upper bit lines B21 and B22 and the plurality of upper word lines W21, W22, W23, and W24. Figure 2 As shown, the upper ground selection line G21 may be disposed on the plurality of upper word lines W21, W22, W23, and W24. The upper source line C21 may be disposed on the upper ground selection line G21.

[0051] If at least Figure 2 As shown, the plurality of upper channel structures 52 may pass through (extend through) the upper stacked structure ST2. The plurality of upper channel structures 52 may be spaced apart from (not in direct contact with) the plurality of lower channel structures 32. Each of the plurality of upper channel structures 52 may vertically pass through the plurality of upper insulating layers 51, the upper ground selection line G21, the plurality of upper word lines W21, W22, W23 and W24, and the upper string selection line S21, and contact a corresponding one of the plurality of upper bit lines B21 and B22. Each of the plurality of upper channel structures 52 may include a plurality of upper channel structures 52 and a plurality of lower channel structures 32. Figure 2 、 Figure 11 and Figure 13 The upper source line C21 may contact upper ends of the plurality of upper channel structures 52. The plurality of lower bit lines B11 and B12 and the plurality of upper bit lines B21 and B22 may be disposed adjacent to each other between the lower stacked structure ST1 and the upper stacked structure ST2.

[0052] A fourth insulating layer 62 may be disposed on the second insulating layer 45 and cover edges of the upper ground selection line G21, edges of the plurality of upper word lines W21, W22, W23, and W24, and edges of the plurality of upper string selection lines S21 and S22. Some of the plurality of upper contact plugs 64 may pass through the fourth insulating layer 62 and respectively contact the upper ground selection line G21, the plurality of upper word lines W21, W22, W23, and W24, and the plurality of upper string selection lines S21 and S22. Others of the plurality of upper contact plugs 64 may pass through the fourth insulating layer 62 and respectively contact the plurality of intermediate pads 47.

[0053] A plurality of lower selectors SS11, SS12, SS13, and SS14 and a plurality of upper selectors SS21, SS22, SS23, and SS24 may be provided on the upper stack structure ST2. Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 may include a reference Figures 2 to 9 The configuration described is similar to the one described above.

[0054] For example, the plurality of lower selectors SS11, SS12, SS13, and SS14 may include: a lower selection line SSG1; a plurality of lower selection channel structures 73A, adjacent to the lower selection line SSG1 and configured to pass through (extend through) the lower selection line SSG1; a plurality of first electrodes 71A, respectively disposed between the plurality of lower selection channel structures 73A and the plurality of lower word lines W11, W12, W13, and W14; and a plurality of second electrodes 79A, respectively disposed between the plurality of lower selection channel structures 73A and the plurality of signal interconnections D1, D2, D3, and D4. The plurality of upper selectors SS21, SS22, SS23, and SS24 may include: an upper selection line SSG2 spaced apart from (not in direct contact with) the lower selection line SSG1; a plurality of upper selection channel structures 73B adjacent to the upper selection line SSG2 and configured to pass through (extend through) the upper selection line SSG2; a plurality of third electrodes 71B disposed between the plurality of upper selection channel structures 73B and the plurality of upper word lines W21, W22, W23, and W24; and a plurality of fourth electrodes 79B disposed between the plurality of upper selection channel structures 73B and the plurality of signal interconnections D1, D2, D3, and D4. The upper selection line SSG2 may be disposed at substantially the same level as the lower selection line SSG1. To reiterate, and as Figures 1 to 14As shown, the upper selection line SSG2 and the lower selection line SSG1 may be coplanar with each other such that they both extend along a common plane extending parallel to the upper surface 21U of the first substrate 21. Each of the plurality of lower selection channel structures 73A may extend through the lower selection line SSG1, and each of the plurality of upper selection channel structures 73B may extend through the upper selection line SSG2.

[0055] Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 can be connected to a corresponding one of the plurality of lower word lines W11, W12, W13, and W14. For example, each of the plurality of lower selection channel structures 73A can be connected to a corresponding one of the plurality of lower word lines W11, W12, W13, and W14 via a corresponding one of the plurality of first electrodes 71A, the plurality of upper contact plugs 64, the plurality of intermediate pads 47, and the plurality of lower contact plugs 43. Each of the plurality of upper selectors SS21, SS22, SS23, and SS24 can be connected to a corresponding one of the plurality of upper word lines W21, W22, W23, and W24. For example, each of the plurality of upper selection channel structures 73B can be connected to a corresponding one of the plurality of upper word lines W21, W22, W23, and W24 via a corresponding one of the plurality of third electrodes 71B and the plurality of upper contact plugs 64.

[0056] like Figures 1 to 14As shown, the decoder XD may be adjacent to the lower stack structure ST1 and the upper stack structure ST2. The decoder XD may be disposed on a plurality of lower selectors SS11, SS12, SS13, and SS14 and a plurality of upper selectors SS21, SS22, SS23, and SS24. Each of the plurality of signal interconnects D1, D2, D3, and D4 may be in contact with the decoder XD, such that the plurality of signal interconnects D1, D2, D3, and D4 are connected to the decoder XD. Each of the plurality of signal interconnects D1, D2, D3, and D4 may be connected to a corresponding one of the plurality of lower selectors SS11, SS12, SS13, and SS14, and to a corresponding one of the plurality of upper selectors SS21, SS22, SS23, and SS24. Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 may be connected to a separate word line among the plurality of lower word lines W11, W12, W13, and W14, such that the plurality of lower selectors SS11, SS12, SS13, and SS14 are respectively connected to the plurality of lower word lines W11, W12, W13, and W14. Each of the plurality of signal interconnects D1, D2, D3, and D4 may be connected to a separate corresponding lower selector among the plurality of lower selectors SS11, SS12, SS13, and SS14. Each of the plurality of signal interconnects D1, D2, D3, and D4 may be connected to a corresponding (e.g., separate corresponding) lower word line among the plurality of lower word lines W11, W12, W13, and W14 via a separate corresponding lower selector among the plurality of lower selectors SS11, SS12, SS13, and SS14. Each of the plurality of upper selectors SS21, SS22, SS23, and SS24 can be connected to a separate word line among the plurality of upper word lines W21, W22, W23, and W24, so that the plurality of upper selectors SS21, SS22, SS23, and SS24 are connected to the plurality of upper word lines W21, W22, W23, and W24, respectively. Each of the plurality of signal interconnects D1, D2, D3, and D4 can be connected to a separate corresponding upper selector among the plurality of upper selectors SS21, SS22, SS23, and SS24. In addition, each of the plurality of signal interconnects D1, D2, D3, and D4 can be connected to a corresponding (e.g., separate corresponding) upper word line among the plurality of upper word lines W21, W22, W23, and W24 via a separate corresponding upper selector among the plurality of upper selectors SS21, SS22, SS23, and SS24.In some example embodiments, the semiconductor device may include: a single signal interconnect D1 connected to the decoder XD; a single lower selector SS11 connected to the signal interconnect D1 and also connected to one lower word line W11 among a plurality of lower word lines W11, W12, W13 and W14; and a single upper selector SS21 not in direct contact with the single lower selector SS11, connected to the single signal interconnect D1, and also connected to one upper word line W24 among a plurality of upper word lines W21, W22, W23 and W24. In some example embodiments, the lower stack structure ST1 may include a single lower word line W11, and the upper stack structure ST2 may include a single upper word line W24, and the semiconductor device may include: a single signal interconnect D1, connected to the decoder XD; a single lower selector SS11, connected to the signal interconnect D1, and also connected to the lower word line W11; and a single upper selector SS21, not in direct contact with the single lower selector SS11, connected to the signal interconnect D1, and also connected to the upper word line W24.

[0057] In some example embodiments, the first signal interconnect D1 may be connected to the first lower selector SS11 and the first upper selector SS21. The first signal interconnect D1 may be connected to the first lower word line W11 via a corresponding one of the plurality of bonding pads 90, a corresponding one of the plurality of second electrodes 79A, a corresponding one of the plurality of lower selection channel structures 73A, a corresponding one of the plurality of first electrodes 71A, a corresponding one of the plurality of upper contact plugs 64, a corresponding one of the plurality of intermediate pads 47, and a corresponding one of the plurality of lower contact plugs 43. Alternatively, the first signal interconnect D1 may be connected to the first lower word line W11 via the first lower selector SS11. Furthermore, the first signal interconnect D1 may be connected to the fourth upper word line W24 via a corresponding one of the plurality of bonding pads 90, a corresponding one of the plurality of fourth electrodes 79B, a corresponding one of the plurality of upper selection channel structures 73B, a corresponding one of the plurality of third electrodes 71B, and a corresponding one of the plurality of upper contact plugs 64. The first lower word line W11 may correspond to the lowest layer among the plurality of lower word lines W11, W12, W13, and W14. The fourth upper word line W24 may correspond to the highest layer among the plurality of upper word lines W21, W22, W23, and W24.

[0058] The second signal interconnect D2 may be connected to the second lower selector SS12 and the second upper selector SS22. In a manner similar to the first signal interconnect D1, the second signal interconnect D2 may be connected to the second lower word line W12 via the second lower selector SS12. Furthermore, the second signal interconnect D2 may be connected to the third upper word line W23 via the second upper selector SS22. The third signal interconnect D3 may be connected to the third lower selector SS13 and the third upper selector SS23. The third signal interconnect D3 may be connected to the third lower word line W13 via the third lower selector SS13. Furthermore, the third signal interconnect D3 may be connected to the second upper word line W22 via the third upper selector SS23.

[0059] The fourth signal interconnect D4 may be connected to a fourth lower selector SS14 and a fourth upper selector SS24. The fourth signal interconnect D4 may be connected to a fourth lower word line W14 via the fourth lower selector SS14. Furthermore, the fourth signal interconnect D4 may be connected to the first upper word line W21 via the fourth upper selector SS24. The fourth lower word line W14 may correspond to the uppermost layer of the plurality of lower word lines W11, W12, W13, and W14. The first upper word line W21 may correspond to the lowermost layer of the plurality of upper word lines W21, W22, W23, and W24.

[0060] The plurality of lower selectors SS11, SS12, SS13, and SS14 and the plurality of upper selectors SS21, SS22, SS23, and SS24 may be referred to as a ladder selector. The plurality of lower selectors SS11, SS12, SS13, and SS14 may be turned on and off by an electrical signal applied to the lower select line SSG1. The plurality of upper selectors SS21, SS22, SS23, and SS24 may be turned on and off by an electrical signal applied to the upper select line SSG2. For example, the plurality of lower selectors SS11, SS12, SS13, and SS14 may be turned on by an electrical signal applied to the lower select line SSG1, and the plurality of upper word lines W21, W22, W23, and W24 may be turned off during operation of the plurality of lower word lines W11, W12, W13, and W14. According to some example embodiments of the present invention, the connection configuration of multiple signal interconnections D1, D2, D3 and D4, multiple lower selectors SS11, SS12, SS13 and SS14, and multiple upper selectors SS21, SS22, SS23 and SS24 can be beneficial for reducing power consumption while reducing or minimizing the number (amount) of interconnections.

[0061] Figure 15 and Figure 16 is a cross-sectional view illustrating a semiconductor device according to some example embodiments.

[0062] Reference Figure 15The semiconductor device according to some example embodiments may include a twelfth insulating layer 97, a buried conductive layer 23, a replacement conductive line 25, a support portion 27, a plurality of lower insulating layers 31, a lower ground selection line G11, a plurality of lower word lines W11, W12, W13, and W14, a lower string selection line S11, a plurality of lower channel structures 32, a plurality of lower bit lines B11, a first insulating layer 41, a plurality of lower contact plugs 43, a second insulating layer 45, a plurality of intermediate pads 47, a plurality of upper bit lines B21, a plurality of upper insulating layers 51, an upper string selection line S21, a plurality of upper word lines W21, W22, W23, and W24, an upper ground selection line G21, a plurality of upper channel structures 52, an upper source line C21, a third insulating layer 61, a fourth insulating layer 62, multiple upper contact plugs 64, a fifth insulating layer 66, multiple upper pads 67, multiple first electrodes 71A, multiple lower selection channel structures 73A, multiple second electrodes 79A, multiple third electrodes 71B, multiple upper selection channel structures 73B, multiple fourth electrodes 79B, lower selection line SSG1, upper selection line SSG2, a sixth insulating layer 81, a seventh insulating layer 82, an eighth insulating layer 83, a ninth insulating layer 84, a tenth insulating layer 89, multiple bonding pads 90, an eleventh insulating layer 91, multiple signal interconnections D1, D2, D3 and D4, a decoder XD, multiple transistors 93, a device isolation layer 95 and a second substrate 99.

[0063] Reference Figure 16The semiconductor device according to some example embodiments may include a first substrate 21, a buried conductive layer 23, a replacement conductive line 25, a support portion 27, a plurality of lower insulating layers 31, a lower ground selection line G11, a plurality of lower word lines W11, W12, W13, and W14, a lower string selection line S11, a plurality of lower channel structures 32, a plurality of lower bit lines B11, a first insulating layer 41, a plurality of lower contact plugs 43, a second insulating layer 45, a plurality of intermediate pads 47, a plurality of upper bit lines B21, a plurality of upper insulating layers 51, an upper string selection line S21, a plurality of upper word lines W21, W22, W23, and W24, an upper ground selection line G11, and a plurality of lower word lines W11, W12, W13, and W14. 21, a plurality of upper channel structures 52, an upper source line C21, a third insulating layer 61, a fourth insulating layer 62, a plurality of upper contact plugs 64, a fifth insulating layer 66, a plurality of upper pads 67, a plurality of first electrodes 71A, a plurality of lower selection channel structures 73A, a plurality of second electrodes 79A, a plurality of third electrodes 71B, a plurality of upper selection channel structures 73B, a plurality of fourth electrodes 79B, a lower selection line SSG1, an upper selection line SSG2, a sixth insulating layer 81, a seventh insulating layer 82, an eighth insulating layer 83, a ninth insulating layer 84, an eleventh insulating layer 91, a plurality of signal interconnections D1, D2, D3, and D4, and a decoder XD. The decoder XD may be directly disposed on the first substrate 21. The plurality of signal interconnections D1, D2, D3, and D4 may be connected to the decoder XD.

[0064] Figure 17 is a circuit diagram illustrating a semiconductor device according to some example embodiments.

[0065] Reference Figure 17 , a semiconductor device according to some example embodiments may include a lower stacked structure ST1, a plurality of lower bit lines B11 and B12, an upper stacked structure ST2, a plurality of upper bit lines B21 and B22, a plurality of lower selectors SS11, SS12, SS13, and SS14, a plurality of upper selectors SS21, SS22, SS23, and SS24, and a decoder XD.

[0066] The lower stacked structure ST1 may include a lower source line C11 and a plurality of lower strings NS11, NS12, NS13, and NS14. Each of the plurality of lower strings NS11, NS12, NS13, and NS14 may include a lower ground selection transistor GST1, a plurality of lower memory cells MC11, MC12, MC13, and MC14, and a lower string selection transistor SST1. The lower ground selection transistor GST1 may be connected to the lower ground selection line G11. Each of the plurality of lower memory cells MC11, MC12, MC13, and MC14 may be connected to a corresponding one of the plurality of lower word lines W11, W12, W13, and W14. The lower string selection transistor SST1 may be connected to a corresponding one of the plurality of lower string selection lines S11 and S12.

[0067] The upper stacked structure ST2 may include an upper source line C21 and a plurality of upper strings NS21, NS22, NS23, and NS24. Each of the plurality of upper strings NS21, NS22, NS23, and NS24 may include an upper ground selection transistor GST2, a plurality of upper memory cells MC21, MC22, MC23, and MC24, and an upper string selection transistor SST2. The upper ground selection transistor GST2 may be connected to the upper ground selection line G21. Each of the plurality of upper memory cells MC21, MC22, MC23, and MC24 may be connected to a corresponding one of the plurality of upper word lines W21, W22, W23, and W24. The upper string selection transistor SST2 may be connected to a corresponding one of the plurality of upper string selection lines S21 and S22.

[0068] Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 may be connected to a corresponding one of the plurality of signal interconnects D1, D2, D3, and D4. Each of the plurality of lower selectors SS11, SS12, SS13, and SS14 may be connected to a corresponding one of the plurality of lower word lines W11, W12, W13, and W14. The plurality of lower selectors SS11, SS12, SS13, and SS14 may include a lower select line SSG1. Each of the plurality of upper selectors SS21, SS22, SS23, and SS24 may be connected to a corresponding one of the plurality of signal interconnects D1, D2, D3, and D4. Each of the plurality of upper selectors SS21, SS22, SS23, and SS24 may be connected to a corresponding one of the plurality of upper word lines W21, W22, W23, and W24. The plurality of upper selectors SS21, SS22, SS23, and SS24 may include an upper select line SSG2. The upper source line C21 may be disposed closer to the plurality of lower bit lines B11 and B12 than to the plurality of upper bit lines B21 and B22. The upper source line C21 may be adjacently disposed between the lower and upper stacked structures ST1 and ST2.

[0069] Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 and Figure 22 is a cross-sectional view illustrating a method of forming a semiconductor device according to some example embodiments.

[0070] Reference Figure 18 , a buried conductive layer 23, an alternative conductive line 25, a support portion 27, a plurality of lower insulating layers 31, a lower ground selection line G11, a plurality of lower word lines W11, W12, W13 and W14, a lower string selection line S11, a plurality of lower channel structures 32, a plurality of lower bit lines B11, a first insulating layer 41, a plurality of lower contact plugs 43, a second insulating layer 45, a plurality of intermediate pads 47 and a plurality of upper bit lines B21 can be formed on the first substrate 21.

[0071] The first substrate 21 may include a semiconductor substrate such as a silicon wafer. The buried conductive layer 23 may be formed by implanting N-type impurities into the first substrate 21. The replacement conductive line 25 may include a conductive layer containing metal, metal nitride, metal oxide, metal silicide, polysilicon, or a combination thereof. The support portion 27 may include a polysilicon layer. Each of the lower ground selection line G11, the plurality of lower word lines W11, W12, W13, and W14, the lower string selection line S11, the plurality of lower bit lines B11, the plurality of lower contact plugs 43, the plurality of intermediate pads 47, and the plurality of upper bit lines B21 may include a conductive layer containing metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. The plurality of lower channel structures 32 may include the same conductive layer as the reference layer. Figure 2 、 Figure 10 、 Figure 12 and Figure 14 Each of the plurality of lower insulating layers 31 , the first insulating layer 41 , and the second insulating layer 45 may include an insulating layer containing silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, a low-k dielectric, or a combination thereof.

[0072] Reference Figure 19 , a plurality of upper insulating layers 51, an upper string selection line S21, a plurality of upper word lines W21, W22, W23, and W24, an upper ground selection line G21, a plurality of upper channel structures 52, an upper source line C21, a third insulating layer 61, a fourth insulating layer 62, and a plurality of upper contact plugs 64 may be formed on the plurality of lower bit lines B11, the plurality of upper bit lines B21, the plurality of intermediate pads 47, and the second insulating layer 45. Each of the plurality of upper channel structures 52 may include an upper source pad 59.

[0073] Each of the upper string selection line S21, the plurality of upper word lines W21, W22, W23, and W24, the upper ground selection line G21, the upper source line C21, and the plurality of upper contact plugs 64 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. Each of the plurality of upper channel structures 52 may include a reference Figure 2 、 Figure 11 and Figure 13 The upper source pad 59 may include a polysilicon layer containing N-type impurities. The upper source pad 59 may function as a source or drain. Each of the plurality of upper insulating layers 51, the third insulating layer 61, and the fourth insulating layer 62 may include an insulating layer containing silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, a low-k dielectric, or a combination thereof.

[0074] Reference Figure 20 , a fifth insulating layer 66, multiple upper pads 67, multiple first electrodes 71A, multiple lower selection channel structures 73A, multiple second electrodes 79A, multiple third electrodes 71B, multiple upper selection channel structures 73B, multiple fourth electrodes 79B, lower selection line SSG1, upper selection line SSG2, a sixth insulating layer 81, a seventh insulating layer 82, an eighth insulating layer 83 and a ninth insulating layer 84 can be formed on the third insulating layer 61, the fourth insulating layer 62 and the multiple upper contact plugs 64.

[0075] The plurality of first electrodes 71A, the plurality of lower selection channel structures 73A, the plurality of second electrodes 79A, the plurality of third electrodes 71B, the plurality of upper selection channel structures 73B, and the plurality of fourth electrodes 79B may include a plurality of electrodes 71A, 73A, 79B, and 79B. Figures 2 to 9 Each of the plurality of upper pads 67, the lower selection line SSG1, and the upper selection line SSG2 may include a conductive layer containing metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. Each of the fifth insulating layer 66, the sixth insulating layer 81, the seventh insulating layer 82, the eighth insulating layer 83, and the ninth insulating layer 84 may include an insulating layer containing silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, a low-k dielectric, or a combination thereof.

[0076] Reference Figure 21 , a plurality of transistors 93 , a device isolation layer 95 , a decoder XD, an eleventh insulating layer 91 , a plurality of signal interconnections D1 , D2 , D3 , and D4 , a tenth insulating layer 89 , and a plurality of bonding pads 90 may be formed on a second substrate 99 .

[0077] The second substrate 99 may include a semiconductor substrate such as a silicon wafer. Each of the plurality of signal interconnects D1, D2, D3, and D4 and the plurality of bonding pads 90 may include a conductive layer containing metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. Each of the device isolation layer 95, the tenth insulating layer 89, and the eleventh insulating layer 91 may include an insulating layer containing silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, a low-k dielectric, or a combination thereof.

[0078] Reference Figure 22 , the second substrate 99 may be bonded to the first substrate 21. The ninth insulating layer 84, the plurality of second electrodes 79A, and the plurality of fourth electrodes 79B may be bonded to the tenth insulating layer 89 and the plurality of bonding pads 90, respectively. Each of the plurality of bonding pads 90 may be connected to a corresponding one of the plurality of second electrodes 79A and the plurality of fourth electrodes 79B.

[0079] According to some example embodiments of the present invention, a plurality of signal interconnects, a plurality of lower selectors, and a plurality of upper selectors are provided. The connection configuration of the plurality of lower selectors and the plurality of upper selectors can be advantageous in reducing power consumption while reducing or minimizing the number (amount) of interconnects. A semiconductor device that is advantageous in high integration density and low power consumption can be realized.

[0080] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing its essential characteristics. Therefore, the above embodiments should be considered in a descriptive sense only and not for the purpose of limitation.

[0081] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0030843, filed on March 19, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a lower stack structure comprising an alternating stack of a plurality of lower word lines and a plurality of lower insulating layers; a plurality of lower channel structures configured to extend through the lower stacked structure; an upper stack structure on the lower stack structure, the upper stack structure comprising an alternating stack of a plurality of upper word lines and a plurality of upper insulating layers; a plurality of upper channel structures not in direct contact with the plurality of lower channel structures, the plurality of upper channel structures being configured to extend through the upper stack structure; a decoder adjacent to the lower stacked structure and the upper stacked structure; a plurality of signal interconnects coupled to the decoder; a plurality of lower selectors connected to the plurality of lower word lines; as well as a plurality of upper selectors connected to the plurality of upper word lines, Wherein each of the plurality of signal interconnections is connected to a separate corresponding lower selector among the plurality of lower selectors and a separate corresponding upper selector among the plurality of upper selectors.

2. The semiconductor device of claim 1 , wherein each of the plurality of signal interconnections is connected to a separately corresponding lower word line among the plurality of lower word lines via the separately corresponding lower selector among the plurality of lower selectors, and is connected to a separately corresponding upper word line among the plurality of upper word lines via the separately corresponding upper selector among the plurality of upper selectors.

3. The semiconductor device according to claim 1, wherein The plurality of lower selectors include: lower selection line; a plurality of lower selection channel structures disposed adjacent to the lower selection line; a plurality of first electrodes between the plurality of lower selection channel structures and the plurality of lower word lines; and a plurality of second electrodes disposed between the plurality of lower selection channel structures and the plurality of signal interconnections, and The plurality of upper selectors include: an upper selection line that is not in direct contact with the lower selection line, a plurality of upper selection channel structures adjacent to the upper selection line, a plurality of third electrodes between the plurality of upper selection channel structures and the plurality of upper word lines, and A plurality of fourth electrodes are between the plurality of upper selection channel structures and the plurality of signal interconnections.

4. The semiconductor device according to claim 3, wherein Each of the plurality of lower selection channel structures extends through the lower selection line, and Each of the plurality of upper selection channel structures extends through the upper selection line.

5. The semiconductor device according to claim 4, wherein each of the plurality of lower selection channel structures and the plurality of upper selection channel structures comprises: channel layer; as well as A gate dielectric layer is configured to surround an outer longitudinal surface of the channel layer. The semiconductor device according to claim 5 , wherein The channel layer is connected to the plurality of first electrodes and the plurality of second electrodes, or The channel layer is connected to the plurality of third electrodes and the plurality of fourth electrodes.

7. The semiconductor device according to claim 5, wherein Each of the plurality of lower selection channel structures and the plurality of upper selection channel structures further includes a core layer, and The channel layer surrounds an outer longitudinal surface of the core layer.

8. The semiconductor device according to claim 7, wherein Each of the plurality of lower selection channel structures and the plurality of upper selection channel structures further includes a selection pad, and The selection pad is between the channel layer and the plurality of second electrodes, or between the channel layer and the plurality of fourth electrodes. 9 . The semiconductor device according to claim 3 , wherein the upper selection line and the lower selection line are coplanar with each other.

10. The semiconductor device according to claim 1, further comprising: a plurality of lower bit lines connected to individual corresponding lower channel structures of the plurality of lower channel structures; as well as A plurality of upper bit lines are connected to individual corresponding upper channel structures of the plurality of upper channel structures. 11 . The semiconductor device according to claim 10 , wherein the plurality of lower bit wires and the plurality of upper bit wires are adjacent to each other between the lower stacked structure and the upper stacked structure. 12 . The semiconductor device according to claim 11 , wherein the plurality of upper bit wires are not in direct contact with the plurality of lower bit wires.

13. The semiconductor device according to claim 11, further comprising: A plurality of upper string selection lines are between the plurality of upper bit lines and the plurality of upper word lines.

14. The semiconductor device according to claim 11, further comprising: An upper ground select line is provided on the plurality of upper word lines.

15. A semiconductor device comprising: a lower stack structure comprising an alternating stack of a plurality of lower word lines and a plurality of lower insulating layers; a plurality of lower channel structures configured to extend through the lower stacked structure; an upper stack structure on the lower stack structure, the upper stack structure comprising an alternating stack of a plurality of upper word lines and a plurality of upper insulating layers; a plurality of upper channel structures not in direct contact with the plurality of lower channel structures, the plurality of upper channel structures being configured to extend through the upper stack structure; a decoder adjacent to the lower stacked structure and the upper stacked structure; a signal interconnect connected to the decoder; a lower selector connected to the signal interconnect and also connected to one of the plurality of lower word lines; as well as An upper selector, not in direct contact with the lower selector, is connected to the signal interconnection and is also connected to one of the plurality of upper word lines.

16. A semiconductor device comprising: a lower stacked structure including a lower word line; an upper stack structure on the lower stack structure, the upper stack structure comprising an upper word line; a decoder adjacent to the lower stacked structure and the upper stacked structure; a signal interconnect connected to the decoder; a lower selector connected to the signal interconnect and to the lower word line; as well as An upper selector is connected to the signal interconnection, is not in direct contact with the lower selector, and is also connected to the upper word line, wherein each of the lower selector and the upper selector includes one or more transistors.

17. The semiconductor device according to claim 16, wherein Each of the lower selector and the upper selector includes a plurality of vertical transistors, and At least one pair of the plurality of vertical transistors is connected in parallel.

18. The semiconductor device according to claim 16, further comprising: a lower channel structure configured to extend through the lower word line; a lower wiring connected to the lower channel structure; an upper channel structure configured to extend through the upper word line; and An upper bit line connected to the upper channel structure. 19 . The semiconductor device according to claim 18 , wherein the lower bit line and the upper bit line are adjacent to each other between the lower stack structure and the upper stack structure.

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