Fully differential operational amplifier common-mode current sensing feedback

Abstract

A method and apparatus for sensing common-mode feedback current are provided. The common-mode feedback current can flow through the common-mode resistive divider of a piezoresistive bridge. A first current mirror mirrors the common-mode feedback current and provides a first mirrored common-mode current. A current-converging stage receives the first mirrored common-mode current and determines the bridge current of the piezoresistive bridge based on the first mirrored common-mode feedback current. Before determining the bridge current, a second current mirror can be used to mirror the first current mirror.

Description

Technical Field

[0001] This application relates to a device for sensing common-mode feedback current, and more particularly to a device for sensing common-mode feedback current and using the common-mode feedback current to determine the bridge current of a piezoresistive bridge. Background Art

[0002] Piezoresistive bridges (which can be Wheatstone bridges) are used in microelectromechanical systems (MEMS) devices (such as micromirrors). Piezoresistive bridges are temperature-sensitive, and the current flowing through them can vary with temperature. Due to their temperature sensitivity, it is important to accurately determine the current flowing through a piezoresistive bridge and, consequently, its temperature. Summary of the Invention

[0003] In a current-to-voltage (I²V) converter configuration, a fully differential operational amplifier can be used to bias a piezoresistive bridge, which is coupled in parallel with a common-mode resistor divider between the two nodes. The total current at one node of the output is the sum of three currents: the first current flows through the piezoresistive bridge, the second current flows through the common-mode resistor divider, and the third current is provided by the current source of the fully differential operational amplifier.

[0004] The initial current flowing through the piezoresistive bridge can be used to determine its sensitivity. Accurate and precise determination of the initial current leads to an accurate and precise determination of the piezoresistive bridge's sensitivity.

[0005] This article describes a bridge current determination stage for determining the first current flowing through a piezoresistive bridge. The bridge current determination stage initially determines the second current flowing through the common-mode resistive voltage divider. Then, the bridge current determination stage receives an indication of a third current provided by the current source of the fully differential operational amplifier. The bridge current determination stage determines the first current flowing through the piezoresistive bridge as the difference between the total current and the sum of the second and third currents. Attached Figure Description

[0006] Figure 1 A schematic circuit diagram of a MEMS system is shown.

[0007] Figure 2 A schematic circuit of a MEMS system, including a bridge current determination stage, is shown in further detail. Detailed Implementation

[0008] Figure 1A schematic circuit diagram of a MEMS system 100 is shown. The MEMS system 100 includes a piezoresistive bridge driver stage 102, a piezoresistive bridge 103, a bridge current determination stage 104, a common-mode resistor divider 105, and a piezoresistive bridge sensitivity compensation stage 106. The bridge current determination stage 104 is coupled to the driver stage 102. The bridge current determination stage 104 determines the current (Ibridge) flowing through the piezoresistive bridge 103. The bridge current determination stage 104 outputs the current (Ibridge) flowing through the piezoresistive bridge 103 to the piezoresistive bridge sensitivity compensation stage 106. The sensitivity compensation stage 106 compensates for the temperature sensitivity of the piezoresistive bridge 103. The piezoresistive bridge 103 may be a Wheatstone bridge.

[0009] Figure 1 The schematic diagram illustrates a driver stage 102. Driver stage 102 includes: a fully differential drive operational amplifier 108, first and second current sources 110, 112, first and second resistors 114, 116, and a feedback amplifier 118. A common-mode resistor divider 105 has first and second feedback resistors 120, 122, with a tap node 121 between the first and second feedback resistors. The common-mode resistor divider 105 may be part of the operational amplifier 108 and may be a substructure of the operational amplifier 108. The fully differential structure of the operational amplifier 108, the first and second feedback resistors 120, 122, and the feedback amplifier 118 can fix the common-mode output of the operational amplifier 108.

[0010] The first current source 110 has a first terminal coupled to a power supply voltage node 124 and a second terminal coupled to the non-inverting input of the driving operational amplifier 108. The power supply voltage node 124 can provide a power supply voltage (Vs) to the system 100. The second current source 112 has a first terminal coupled to a reference voltage node 126 and a second terminal coupled to the inverting input of the driving operational amplifier 108. The reference voltage node 126 can provide a reference voltage or a ground voltage to the system 100.

[0011] The first resistor 114 has a first terminal coupled to the non-inverting input of the operational amplifier 108 and a second terminal coupled to the first output node 115 of the driver stage 102, providing a first output voltage (Voutp) at the second terminal. The operational amplifier 108 has an inverting output terminal coupled to the first output node 115. The second resistor 116 has a first terminal coupled to the inverting input of the operational amplifier 108 and a second terminal coupled to the second output node 117 of the driver stage 102, providing a second output voltage (Voutn) at the second terminal. The non-inverting output terminal of the operational amplifier 108 is coupled to the second output node 117.

[0012] The first feedback resistor 120 of the common-mode resistive voltage divider 105 has a first terminal coupled to the first output node 115 and a second terminal coupled to the tap node 121. The second feedback resistor 122 has a first terminal coupled to the second output node 117 and a second terminal coupled to the tap node 121. The feedback amplifier 118 has a second input for receiving the common-mode voltage (Vcm). The feedback amplifier 118 has an output coupled to the control input of the driving operational amplifier 108.

[0013] A piezoresistive bridge 103 is coupled between the first and second output nodes 115, 117. Specifically, the piezoresistive bridge 103 includes first, second, third, and fourth resistors 128, 130, 132, and 134, wherein the first and second resistors 128 and 130 are coupled in series between the first and second output nodes 115, 117, and the third and fourth resistors 132 and 134 are coupled in series between the first and second output nodes 115, 117. Resistors 128, 130, 132, and 134 can have equal resistance values, and therefore, piezoresistive bridge current (Ibridge) can flow through each branch of the piezoresistive bridge 103.

[0014] System 100 can be used in a micromirror of a microelectromechanical system (MEMS). The position of the micromirror can be determined based on the output of a piezoresistive bridge 103. For example, an analog front end (not shown) can read the common network of first and second resistors 128, 130 and third and fourth resistors 132, 134. The analog front end can be coupled to the common network. Micromirror movement causes a mismatch (or change) between the values ​​of resistors 128, 130, 132, 134, resulting in an effective voltage between the two common networks. Depending on the placement of the piezoresistive bridge 103 on the micromirror, the mismatch results in an effective signal between the two output terminals of the piezoresistive bridge 103. The sensitivity of the micromirror can be considered as the “gain” between the physical movement of the mirror and the change in resistance. Sensitivity (or sensitivity parameter) can be thought of as the tendency or ability of the piezoresistive bridge 103 to mismatch with a given movement of the micromirror. Therefore, sensitivity (or its parameter) can be a coefficient that links the movement of the micromirror to the generated electrical signal. This sensitivity is temperature-dependent. Tracking the temperature (or its changes) allows for compensation of the sensitivity.

[0015] As described in this article, reading the current through the piezoresistive bridge (Ibridge) allows for the determination of temperature and extrapolation of updated sensitivity values. It is assumed that the relationships between resistance (and measured current) and temperature, as well as between sensitivity and temperature, are known and have been correctly calibrated.

[0016] The piezoresistive bridge 103 exhibits sensitivity to temperature-related changes. To determine the sensitivity of the bridge 103, the bridge current (Ibridge) is determined and initially used to determine the temperature. It is desirable to accurately estimate the bridge current (Ibridge) to compensate for variations in the sensitivity of the bridge 103, and thus to precisely determine the position (motion) of the micromirror.

[0017] As described herein, the bridge current determination stage 104 determines the bridge current (Ibridge). The bridge current determination stage 104 outputs the bridge current (Ibridge) to the piezoresistive bridge sensitivity compensation stage 106. The piezoresistive bridge sensitivity compensation stage 106 uses the bridge current (Ibridge) to characterize the temperature of the piezoresistive bridge 103, and therefore uses the piezoresistive bridge 103 to characterize the sensitivity of the micromirror or other device. The piezoresistive bridge sensitivity compensation stage 106 can be a controller or processor, particularly for MEMS devices such as micromirrors.

[0018] It is advantageous to have a fully differential operational amplifier 108 and bias circuitry with a piezoresistive bridge 103 for current-voltage (I²V) configuration. Thus, the output of operational amplifier 108 is a known current supplied by the first and second current sources 110, 112, and a resistive current (I²V) flowing through resistors 114, 116. R The function is called . The output can be determined from this known quantity.

[0019] Figure 2 A circuit diagram of the MEMS system 100, including the bridge current determination stage 104, is shown in further detail. References herein... Figure 1 Similar elements of the described drive stage 102 and piezoresistive bridge 103 have the same reference numerals.

[0020] The bridge current determination stage 104 includes: first and second total current transistors 136 and 138 in a trans-diode configuration within a common-mode resistor divider 105; first and second total current mirror transistors 140 and 142; first and second feedback transistors 144 and 146; first, second, third, and fourth mirror transistors 148, 150, 156, and 158; first and second reference transistors 152 and 154; a mirror feedback amplifier 160; and a capacitor 162. The bridge current determination stage 104 also includes a current aggregation stage 164. The current aggregation stage 164 may be a current adder and / or subtractor. The current aggregation stage 164 may further be a controller or processor. Although in Figure 2The first and second total current transistors 136 and 138 are extrapolated, but in various implementations, the first and second total current transistors 136 and 138 can be the output devices of operational amplifier 108. The first and second reference transistors 152 and 154 are configured as references to the third and fourth mirror transistors 156 and 158 in a cross-diode topology.

[0021] The first total current transistor 136 has a source coupled to a power supply voltage node 124, a drain coupled to a first output node 115, and a gate connected to an internal network of the operational amplifier 108 according to a specific architecture of the operational amplifier 108. The second total current transistor 138 has a source coupled to a reference voltage node 126, a drain coupled to a second output node 117, and a gate connected to an internal network of the operational amplifier 108. The first and second total current mirror transistors 140 and 142 are configured as current mirrors of the first and second total current transistors 136 and 138, respectively. The first total current mirror transistor 140 has a source coupled to a power supply voltage node 124, a gate coupled to the gate of the first total current transistor 136, and a drain coupled to a first input of the current pooling stage 164. The second total current mirror transistor 138 has a source coupled to a reference voltage node 126, a gate coupled to the gate of the second total current transistor 138, and a drain coupled to a second input of the current pooling stage 164.

[0022] The first feedback transistor 144 is coupled in series with the first feedback resistor 120 and is in a trans-diode configuration, whereby the first feedback transistor 144 has a drain and a gate both coupled to the second terminal of the first feedback resistor 120 and a source coupled to the tap node 121. The second feedback transistor 146 is coupled in series with the second feedback resistor 122 and is in a trans-diode configuration, whereby the second feedback transistor 146 has a drain and a gate both coupled to the tap node 121 and a source coupled to the second terminal of the second feedback resistor 122.

[0023] First and second mirror transistors 148 and 150 are configured in a current mirror configuration with first and second feedback transistors 144 and 146, respectively, such that first mirror transistor 148 has a gate coupled to the gate of first feedback transistor 144, and second mirror transistor 150 has a gate coupled to the gate of second feedback transistor 146. The drain of second mirror transistor 150 is coupled to the non-inverting input of mirror feedback amplifier 160. The drain of first mirror transistor 148 is coupled to the control terminal (and drain) of first reference transistor 152 described herein. The source of first mirror transistor 148 is coupled to the non-inverting input of mirror feedback amplifier 160, and the source of second mirror transistor 150 is coupled to the drain of second reference transistor 154 described herein.

[0024] The first reference transistor 152 has a source coupled to the power supply voltage node 124, and its gate and drain are coupled to each other and together to the drain of the first mirror transistor 148. The second reference transistor 154 has a source coupled to the reference voltage node 126 and a drain coupled to the source of the second mirror transistor 150.

[0025] The third and fourth mirror transistors 156 and 158 are configured in a current mirror configuration with the first and second reference transistors 152 and 154, respectively. The third mirror transistor 156 has a source coupled to the power supply voltage node 124, a gate coupled to the gate of the first reference transistor 152, and a drain coupled to the third input of the current-converging stage 164. The fourth mirror transistor 158 has a source coupled to the reference voltage node 126, a gate coupled to the gate of the second reference transistor 154, and a drain coupled to the fourth input of the current-converging stage 164.

[0026] The output of the mirror feedback amplifier 160 is coupled to the gates of the second reference transistor 154 and the fourth mirror transistor 158. A capacitor 162 is coupled between the gates of the second reference transistor 154 and the fourth mirror transistor 158 and the reference voltage node 126. Additionally, the current focusing stage 164 has fifth and sixth inputs coupled to replicas of the first and second current sources 110 and 112, respectively. The current focusing stage 164 receives indications (or replicas) of the currents supplied by the first and second current sources 110 and 112.

[0027] The piezoresistive bridge current (Ibridge) can be expressed as the total current (Iptot) flowing through the first total current transistor 136, the common-mode feedback current (Icm) flowing through the common-mode resistor divider 105 composed of the first and second feedback resistors 120 and 122, and the resistive current (I) flowing through the first resistor 114. R The difference between the sums of the two currents. The total current (Iptot) through the first total current transistor 136 is distributed to the resistor divider (as common-mode feedback current (Icm)), the bridge 103 (as piezoresistive bridge current (Ibridge)), and the resistor current (I) flowing through the first resistor 114. R ).

[0028] The piezoresistive bridge current (Ibridge) can be determined as the total current (Iptot) multiplied by the common-mode feedback current (Icm) and the resistor current (I). R The difference between the sums of the two piezoresistive bridge currents (Ibridge) can be determined as:

[0029] Ibridge = Iptot – Icm – I R Equation (1)

[0030] Resistance current (I) R It is entirely provided by the first current source 110 and can be determined based on data or information from the first current source 110.

[0031] The total current (Iptot) flows completely through the first output node 115. Since the first total current mirror transistor 140 is placed in a current mirror configuration with the first total current transistor 136, the total current (Iptot) is replicated to the first total current mirror transistor 140 and can be obtained (or determined) at the drain of the first total current mirror transistor 140.

[0032] To determine the common-mode feedback current (Icm) flowing through the common-mode resistor divider 105, the conductive terminals of the first and second feedback transistors 144 and 146 are inserted into the path of the common-mode feedback current (Icm). The first and second mirror transistors 148 and 150 are configured as current mirrors with the first and second feedback transistors 144 and 146, respectively.

[0033] First and second reference transistors 152 and 154 supply current to or draw current from first and second mirror transistors 148 and 150, respectively. Mirror feedback amplifier 160 may be a replica of the feedback amplifier or may be a different amplifier. Due to this feedback, mirror feedback amplifier 160 allows the intermediate node between the first and second mirror transistors 148 and 150 to be set to Vcm. The matching between mirror feedback amplifier 160 and feedback amplifier 118 can (in a second order) provide a better (e.g., more equal) bias at Vcm between tap node 121 and the common network between the first and second mirror transistors 148 and 150.

[0034] Tap node 121, serving as an intermediate node between the first and second feedback transistors 144 and 146, is also set to Vcm in the common-mode feedback of operational amplifier 108. Since the first and second mirror transistors 148 and 150 mirror the first and second feedback transistors 144 and 146 respectively, and since they have the same gate voltage, it is important that they also have the same supply voltage. This is achieved through the feedback managed by the mirror feedback amplifier 160.

[0035] Furthermore, the first and second feedback transistors 144, 146 and the first and second mirror transistors 148, 150 have a body-source connection to avoid body effects that would affect the mirror factor. Additionally, transistors 144, 146, 148, 150 may be further cascode to improve matching and may advantageously be of the same or proportional size.

[0036] The current flowing through the first reference transistor 152 (denoted as "Icm_mirr") is itself a mirror image of the common-mode feedback current (Icm), which is replicated by the third mirror transistor 156. The third mirror transistor 156 is configured with the first reference transistor 152 as a current mirror, and therefore the current flowing through the first reference transistor 152 (Icm_mirr) is again mirrored by the third mirror transistor 156 as the current Icmp_mirr. The third mirror transistor 156 provides the mirrored current (Icmp_mirr) of the common-mode feedback current (Icm) to the current aggregation stage 164.

[0037] The current pooling stage 164 receives a mirror current (Icmp_mirr) of the common-mode feedback current (Icm) from the third mirror transistor 156, and a mirror current (Iptot_mirr) of the total current (Iptot) from the first total current mirror transistor 140. The current pooling stage 164 also receives a resistive current (I...) from the first current source 110. R The current gathering stage 164 can generate a resistive current (I) based on the received indication. R The current-gathering stage 164 subtracts the mirror current of the common-mode feedback current (Icm) (Icmp_mirr) and the resulting resistive current (I) from the mirror current (Iptot_mirr) of the total current (Iptot). R ), to generate a mirror copy of the piezoresistive bridge current (Ibridge). The current gathering stage 164 determines the piezoresistive bridge current (Ibridge) according to equation (1) and based on the measured current.

[0038] Due to the symmetry between the driver stage 102 and the current determination stage 104, the current gathering stage 164 can also receive current from the "negative" side of both the driver stage 102 and the current determination stage 104. The current determination stage 104 receives the mirror current (Intot_mirr) of the total current (Intot) flowing through the second total current transistor 138, the mirror current (Icmn_mirr) of the common-mode feedback current (Icm) flowing through the second feedback transistor 146, and the resistive current (I) flowing through the second resistor 116. R The current gathering stage 164 determines the piezoresistive bridge current (Ibridge) in a manner similar to that described herein:

[0039] Ibridge=Intot_mirr–Icmn_mirr-I R Equation (2)

[0040] The current focusing stage 164 can output a piezoresistive bridge current (Ibridge). The piezoresistive bridge current (Ibridge) can be used to determine the sensitivity of the piezoresistive bridge 103 or a device associated with the bridge 103 (such as a MEMS device). As described herein, the piezoresistive bridge current (Ibridge) indicates the temperature of the bridge 103. The piezoresistive bridge current (Ibridge) can be used to determine the temperature of the bridge 103. The temperature of the bridge 103 can then be used to determine the sensitivity of the bridge 103, which varies with temperature. The temperature of the bridge 103 can then be used to compensate for the sensitivity of the bridge 103. The current determination stage 104 accurately determines the common-mode feedback current (Icm), thus resulting in an accurate determination of the piezoresistive bridge current (Ibridge).

[0041] In one embodiment, power consumption can be minimized by scaling the mirror currents (Iptot_mirr and Intot_mirr) of the total currents (Iptot and Intot) by a factor (e.g., k). The mirror currents (Iptot_mirr and Intot_mirr) can be multiplied by this factor to compensate for the scaling of the mirror currents. With the mirror currents (Iptot_mirr and Intot_mirr) scaled by factor k, the piezoresistive bridge current (Ibridge) can be determined as:

[0042] Ibridge=k*(Iptot_mirr–Icmn_mirr-I R Equation (3)

[0043] Sensitivity compensation stage 106 can perform the temperature sensitivity compensation described herein. The relationship between the resistance of piezoresistive bridge 103 and temperature can be expressed as:

[0044] R(T)=T(T0)(1+A(T-T0)+B(T-T0) 2 Equation (4)

[0045] Where T represents temperature, T0 is a reference temperature (e.g., 27°C), and A and B are technology-dependent thermal coefficients.

[0046] Therefore, the bridge current can be expressed as:

[0047] I(T)=V / R(T) Equation (5)

[0048] Where V is the bias voltage applied to the bridge.

[0049] Assuming A and B are known (e.g., after calibration), the measurement of I(T) allows the determination of temperature T. The sensitivity of the bridge itself can be defined by the following formula:

[0050] S(T)=R(T0)(1+C(T-T0)+D(T-T0) 2 Equation (6)

[0051] C and D are thermal coefficients that depend on the technology.

[0052] When C and D are known, the sensitivity can be determined after the temperature T is determined. Furthermore, the motion (or position) of the micromirror can be determined from the output of the bridge. The angle (θ) of the micromirror at a given instant can be expressed as:

[0053] Vout = VSθ Equation (7)

[0054] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A device for sensing common-mode feedback current, comprising: A common-mode resistor divider, the common-mode resistor divider comprising a first resistor and a second resistor coupled in series; Piezoresistive bridge; A first current mirror is coupled to the common-mode resistor divider. The first current mirror is configured to mirror the common-mode current flowing through the common-mode resistor divider and to provide a first mirrored common-mode current. The first current mirror includes a first feedback transistor, which is coupled in series with the first resistor and the second resistor and has the common-mode current flowing through the first feedback transistor. Drive an operational amplifier operable to bias the piezoresistive bridge; as well as The current-collecting stage is configured as follows: Receive the common-mode current of the first image: Receive a mirror image of the output current of the driving operational amplifier used to bias the piezoresistive bridge; Receives an indication of the feedback current of the driving operational amplifier; as well as The bridge current of the piezoresistive bridge is determined based on the output current and feedback current of the driving operational amplifier and the common-mode feedback current of the first mirror.

2. The device according to claim 1, wherein the piezoresistive bridge is coupled in parallel with the common-mode resistor divider.

3. The device of claim 2, wherein the current aggregation stage is configured to determine the bridge current as the difference between the mirror image of the output current and the sum of the common-mode feedback current of the first mirror image and the feedback current of the driving operational amplifier.

4. The device according to claim 1, wherein: The first resistor has a second terminal and a first terminal coupled to a first voltage node; as well as The second resistor has a second terminal and a first terminal coupled to a second voltage node.

5. The device according to claim 4, wherein the first current mirror comprises: The first feedback transistor has a first conductive terminal and a control terminal both coupled to the second terminal of the first resistor, and a second conductive terminal coupled to the center node; The second feedback transistor has a first conductive terminal and a control terminal coupled to the central node, and a second conductive terminal coupled to the second terminal of the second resistor; The first mirror transistor has a control terminal coupled to the control terminal of the first feedback transistor, and a first conductive terminal and a second conductive terminal; as well as The second mirror transistor has a control terminal coupled to the control terminal of the second feedback transistor, a first conductive terminal coupled to the first conductive terminal of the first mirror transistor, and a second conductive terminal.

6. The device according to claim 5, comprising: A mirror feedback amplifier has a first input coupled to the first conductive terminal of the first mirror transistor and the second mirror transistor, a second input for receiving a common-mode voltage, and an output.

7. The device according to claim 6, comprising: The second current mirror includes: The first current source transistor has a first conductive terminal and a control terminal both coupled to the second conductive terminal of the first mirror transistor, and a second conductive terminal coupled to a power supply voltage node; and The second current source transistor has a first conductive terminal coupled to the second conductive terminal of the second mirror transistor, a second conductive terminal coupled to the reference voltage node, and a control terminal coupled to the output of the mirror feedback amplifier.

8. The device of claim 7, wherein the second current mirror comprises: The third mirror transistor has a control terminal coupled to the control terminal of the first current source transistor, a first conductive terminal coupled to the power supply voltage node, and a second conductive terminal coupled to the current gathering stage. The fourth mirror transistor has a control terminal coupled to the control terminal of the second current source transistor, a first conductive terminal coupled to the reference voltage node, and a second conductive terminal coupled to the current gathering stage; as well as A capacitor is coupled between the output of the mirror feedback amplifier and the reference voltage node.

9. A method for sensing common-mode feedback current, comprising: A first current mirror mirrors the common-mode current flowing through a common-mode resistor divider used in a piezoresistive bridge to generate a first mirrored common-mode current. The common-mode resistor divider includes a first resistor and a second resistor coupled in series, and the first current mirror includes a first feedback transistor coupled in series with the first resistor and the second resistor, and has the common-mode current flowing through the first feedback transistor. The piezoresistive bridge is biased by an operational amplifier; Determine the mirror image of the output current of the driving operational amplifier used to bias the piezoresistive bridge; Receives an indication of the feedback current from the operational amplifier; as well as The bridge current of the piezoresistive bridge is determined based on the output current and feedback current of the driving operational amplifier and the common-mode feedback current of the first mirror.

10. The method of claim 9, comprising: The common-mode current of the first mirror is mirrored to generate the common-mode current of the second mirror based on the common-mode current of the first mirror; as well as The bridge current is determined as the difference between the output current and the sum of the common-mode feedback current of the second mirror and the feedback current of the driving operational amplifier.

11. A microelectromechanical system, comprising: A first current mirror is coupled to a common-mode resistor divider of a piezoresistive bridge. The first current mirror is configured to mirror the common-mode current flowing through the common-mode resistor divider and provide a first mirrored common-mode current. The common-mode resistor divider includes a first resistor and a second resistor coupled in series, and the first current mirror includes a first feedback transistor coupled in series with the first resistor and the second resistor and having the common-mode current flowing through the first feedback transistor. Drive an operational amplifier operable to bias the piezoresistive bridge; The current-collecting stage is configured as follows: Receive the common-mode current of the first image; Receive a mirror image of the output current of the driving operational amplifier used to bias the piezoresistive bridge; Receives an indication of the feedback current of the driving operational amplifier; The bridge current of the piezoresistive bridge is determined based on the output current and feedback current of the driving operational amplifier and the common-mode feedback current of the first mirror. as well as A piezoresistive bridge sensitivity compensation stage is configured to receive the bridge current and compensate the sensitivity of the MEMS device based on the bridge current.

12. The microelectromechanical system of claim 11, wherein the current aggregation stage is configured to determine the bridge current as the difference between the output current and the sum of the common-mode feedback current of the first mirror and the feedback current of the driving operational amplifier.

13. The microelectromechanical system according to claim 11, wherein: The first resistor has a second terminal and a first terminal coupled to a first voltage node; The second resistor has a second terminal and a first terminal coupled to a second voltage node; as well as The common-mode resistor divider includes a center node; as well as The first feedback transistor has a first conductive terminal and a control terminal both coupled to the second terminal of the first resistor, and a second conductive terminal coupled to the central node; The first current mirror includes: The second feedback transistor has a first conductive terminal and a control terminal coupled to the central node, and a second conductive terminal coupled to the second terminal of the second resistor; A first mirror transistor has a control terminal coupled to the control terminal of the first feedback transistor, and a first conductive terminal and a second conductive terminal; and The second mirror transistor has a control terminal coupled to the control terminal of the second feedback transistor, a first conductive terminal coupled to the first conductive terminal of the first mirror transistor, and a second conductive terminal.

14. The microelectromechanical system according to claim 11, comprising: A second current mirror is coupled to the first current mirror, and the second current mirror is configured to mirror the common-mode current of the first mirror and provide the common-mode current of the second mirror.

15. The microelectromechanical system according to claim 13, comprising: A mirror feedback amplifier has a first input coupled to the first conductive terminal of the first mirror transistor and the second mirror transistor, a second input for receiving a common-mode voltage, and an output.

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