Optimized handling of multiple copies in storage management

Abstract

The present invention is entitled "Optimized Handling of Multiple Copies in Storage Management". The present invention as a whole relates to relocating data in a storage device, and updating a compressed logical-to-physical (L2P) table in response without invalidating cache entries in the L2P table. After relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address, a version indicator of a cache entry corresponding to the first physical address in the L2P table is incremented. One or more cache entries associated with the data relocated to the second physical block are added to the L2P table without invalidating the cache entry corresponding to the first physical address. When a command to read or write the relocated data is received, the storage device searches the L2P table and reads the data from the first memory block or the second memory block.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to storage devices, such as solid-state drives (SSDs). Background Art

[0002] Description of Related Technology

[0003] SSDs can be used as storage devices to achieve higher quality read and device performance. For example, SSDs can exhibit lower latency than hard disk drives (HDDs), especially for random reads and writes. This allows SSDs to have greater throughput for random reads and random writes than HDDs. In addition, SSDs can use multiple parallel data channels to read and write to memory devices, giving them higher sequential read and write speeds.

[0004] However, achieving higher device performance may require implementing complex management schemes and operations. One such management operation for increasing device performance includes relocating data to and from memory blocks in a flash memory device. Relocating data may be advantageous, such as for enhancing wear leveling and data recycling, and may avoid data loss, such as during weak and hard memory failures. However, data relocation may result in reduced performance.

[0005] To support such complex management operations, management tables such as logical-to-physical tables may be used. A logical-to-physical (L2P) table is a table that stores logical-to-physical address mappings to identify the location of user data in a physical entity such as a flash memory device. Each time data is relocated, cache entries corresponding to the relocated data in the L2P table may become invalid, and new entries may be added. As a result, cache coherence failures may occur, and the size of the L2P table may increase, thereby reducing read performance and disrupting host operations.

[0006] Therefore, there is a need to provide a method of operating a storage device that can improve read performance while reducing cache coherency failures and host operation interruptions. Summary of the invention

[0007] The present disclosure as a whole relates to relocating data in a storage device, and updating a compressed logical-to-physical (L2P) table in response without invalidating a cache entry in the L2P table. After relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address, a version indicator corresponding to a cache entry for the first physical address in the L2P table is incremented. One or more cache entries associated with the data relocated to the second physical block are then added to the L2P table without invalidating the cache entry corresponding to the first physical address. When a command to read or write the relocated data is received, the storage device searches the L2P table and reads the data from the first memory block or the second memory block.

[0008] In one embodiment, a method of operating a storage device having a plurality of memory blocks includes relocating data stored in a first memory block to a second memory block, receiving a request to read the data, reading a logical to physical table to determine in which memory block of the plurality of memory blocks the data is stored, and reading the data from the first memory block or the second memory block. After relocating the data, a controller of the storage device is able to read the first memory block and the second memory block.

[0009] In another embodiment, a method of operating a storage device includes relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address. The first physical address is recorded in a first cache entry in a compressed logical-to-physical table. The method also includes incrementing a version indicator of the first cache entry in the compressed logical-to-physical table, adding one or more updated cache entries to the compressed logical-to-physical table in response to relocating the data to the second physical address, searching the compressed logical-to-physical table to determine the location of the data, reading the first cache entry before reading the one or more updated cache entries, and reading the data from the first physical address.

[0010] In one embodiment, a storage device includes a plurality of memory blocks. Each memory block in the plurality of memory blocks includes a flash memory cell. The storage device also includes a controller coupled to the plurality of memory blocks. The controller is configured to store a compressed logical-to-physical table. The compressed logical-to-physical table records the location of data in one or more memory blocks in the plurality of memory blocks. The controller is further configured to sort the validity counter array according to a validity count. The validity count is the number of valid flash memory cells in the memory block. The controller is further configured to prioritize one or more memory blocks to be erased in the plurality of memory blocks. A memory block with a low validity count has a higher priority than a memory block with a high validity count. A memory block that does not record data in the compressed logical-to-physical table has a higher priority than a memory block that records data in the compressed logical-to-physical table. The controller is further configured to schedule one or more memory blocks to be erased in the plurality of memory blocks according to a priority order. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief overview, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0012] Figure 1 is a schematic block diagram showing a storage system having a host device and a storage device according to one embodiment.

[0013] Figure 2 is a schematic block diagram showing a storage system having a host device and a storage device according to another embodiment.

[0014] Figure 3A A method of relocating data during a host random read operation according to one embodiment is shown.

[0015] Figure 3B A conventional method of relocating data during a host random read operation is shown for comparison purposes.

[0016] Figure 4 A flow chart is shown of a method of updating an L2P cache of a controller of a storage device when the controller relocates data according to one embodiment.

[0017] Figure 5 A flow chart is shown of a method for scheduling memory blocks to be erased using a compressed controller L2P cache according to one embodiment.

[0018] Figure 6 A flow chart of a method of updating an L2P cache of outstanding update operations of a controller of a storage device is shown according to one embodiment.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0020] Hereinafter, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the embodiments specifically described. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0021] The present disclosure as a whole relates to relocating data in a storage device, and updating a compressed logical-to-physical (L2P) table in response without invalidating a cache entry in the L2P table. After relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address, a version indicator of a cache entry corresponding to the first physical address in the L2P table is incremented. One or more cache entries associated with the data relocated to the second physical block are then added to the L2P table without invalidating the cache entry corresponding to the first physical address. When a command to read or write the relocated data is received, the storage device searches the L2P table and reads the data from the first memory block or the second memory block.

[0022] Figure 11 is a schematic block diagram illustrating a storage system 100 in accordance with one or more techniques of the present disclosure, wherein a storage device 106 may be used as a storage device for a host device 104. For example, the host device 104 may utilize a non-volatile memory device included in the storage device 106 to store and retrieve data. In some examples, the storage system 100 may include multiple storage devices, such as the storage device 106, that may operate as a storage array. For example, the storage system 100 may include multiple storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that are collectively used as a mass storage device for the host device 104.

[0023] Storage system 100 includes a host device 104 that can store data to and / or retrieve data from one or more storage devices, such as storage device 106. Figure 1 As shown, host device 104 can communicate with storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet computer, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, etc.

[0024] like Figure 1 As shown, the storage device 106 includes a controller 108, a non-volatile memory 110 (NVM 110), a power supply 111, a volatile memory 112, and an interface 114. In some examples, for clarity, the storage device 106 may include Figure 1 106. For example, the storage device 106 may include a printed board (PB) to which the components of the storage device 106 are mechanically attached, and the printed board includes conductive traces that electrically interconnect the components of the storage device 106, etc. In some examples, the physical size and connector configuration of the storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., an HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the storage device 106 can be directly coupled (e.g., directly soldered) to a motherboard of the host device 104.

[0025] The interface 114 of the storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), etc. The electrical connection of the interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the storage device 106 to receive power from the host device 104. For example, as Figure 1 As shown, power supply 111 may receive power from host device 104 via interface 114 .

[0026] The storage device 106 includes an NVM 110, which may include multiple memory devices. The NVM 110 may be configured to store and / or retrieve data. For example, the memory device of the NVM 110 may receive data and a message indicating that the memory device stores data from the controller 108. Similarly, the memory device of the NVM 110 may receive a message indicating that the memory device retrieves data from the controller 108. In some examples, each memory device in the memory device may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory devices). In some examples, each memory device may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0027] In some examples, each memory device of NVM 110 may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0028] NVM 110 may include one or more flash memory devices. Flash memory devices may include NAND and NOR based flash memory devices, and may store data based on the charge contained in the floating gate of the transistor for each flash memory unit. In some flash memory devices, such as NAND memory devices, the flash memory device may be divided into a plurality of blocks, which may be divided into a plurality of pages. Each block may include 128KB of data, 256KB of data, 2MB of data, 8MB of data, etc. In some cases, each page may include 1 kilobyte (KB) of data, 4KB of data, 8KB of data, etc. Each page may include zero or more flash memory units (FMUs). In some cases, each FMU may include 1 kilobyte (KB) of data, 4KB of data, 8KB of data, etc. The controller 108 may write data to the flash memory device and read data from the flash memory device at the FMU level, and erase data from the flash memory device at the block level.

[0029] The storage device 106 includes a power supply 111 that can provide power to one or more components of the storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as a host device 104 to power one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to power one or more components. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0030] Storage device 106 also includes volatile memory 112, which can be used by controller 108 to store information. Volatile memory 112 can include one or more volatile memory devices. In some examples, controller 108 can use volatile memory 112 as a cache. For example, controller 108 can store cached information in volatile memory 112 until the cached information is written to non-volatile memory 110. Figure 1 As shown, the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM, e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, etc.).

[0031] The storage device 106 includes a controller 108 that can manage one or more operations of the storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM 110. In some embodiments, when the storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110.

[0032] Figure 2 2 is a schematic block diagram showing a storage system 200 having a host device 204 and a storage device 206 according to another embodiment. The storage system 200 may be Figure 1 A storage system 100 having a host device 104 and a storage device 106 is shown.

[0033] The storage device 206 includes a controller 208 and one or more flash memory devices 220. The controller 208 may be Figure 1 The flash memory device 220 may be a controller 108 in FIG. Figure 1 10 in the NVM 110. Each of the one or more flash memory devices 220 may include a plurality of blocks; each block may include a plurality of pages; each page may contain zero or more flash management units (FMUs); and each FMU may contain a plurality of bytes. As used herein, an FMU refers to an addressable memory unit in the flash memory device 220. The flash memory device 220 stores a master logical to physical address translation (L2P) table 222 that translates a logical address into a physical address in the flash memory device 220 where data is stored. A physical address may correspond to one or more FMUs of a memory block.

[0034] During operation, the controller 208 may receive a read command or a write request from the host device 204, and may determine the storage location of the data included in the write request. The controller 208 may also determine to relocate the data without receiving a command to perform a management operation from the host device 204. The read and write requests may include data, a logical address, and / or a physical address. The controller 208 may determine in which flash memory device of the one or more flash memory devices 220 to store the data. The controller 208 stores the data in the one or more flash memory devices 220, so that the controller 208 may then associate the data with a logical address mapped to a physical address of the flash memory device 220. The controller 208 may then update the master L2P table 222 after storing the data. Since the master L2P table 222 tracks and records all read, write, and erase data in the flash memory device 220, the size of the master L2P table 222 may be quite large, which may result in more time required to traverse the master L2P table 222.

[0035] To help reduce the time required to search the main L2P table 222, the controller 208 includes an L2P cache 224 and an outstanding update operation (OUO) L2P cache 226 stored in the internal RAM 218 of the controller 208. The L2P cache 224 and the OUO cache 226 record and cache the data recently read or written in the flash memory device 220. Since the size of the internal RAM 218 is limited, the L2P cache 224 and the OUO cache 226 can be compressed to record more information. Compressing the L2P cache 224 and the OUO cache 226 allows a larger cache, resulting in an improved hit rate. The compressed L2P table condenses one or more logical addresses or physical addresses into a cache entry in the table. For example, a cache entry can save a recent logical address that has been read and a future logical address that can be read, such as a sequential logical address.

[0036] Table 1 shows an example of a compressed L2P cache 224 .

[0037] Table 1

[0038] Item Number First logical address First physical address The number of concurrent entries that are valid Version 1 5 1000 50 2 200 1050 14 3 110 1070 3 4 500 100 100 … … … … n

[0039] The exemplary compressed L2P cache 224 of Table 1 includes an entry number column, a column showing a first logical address within a certain range, a column showing a first physical address within a certain range, a concurrent entry number column, and a version indicator column. The physical address is associated with the FMU of the memory block. The concurrent entry number is the number of logical addresses and physical addresses recorded in the corresponding cache entry. For example, in the first cache entry with entry number 1, logical addresses 5-55 and physical addresses 1000-1050 are recorded. If the data corresponding to the logical address or physical address recorded in the cache entry is relocated, the version indicator of the cache entry can be incremented. One or more entries can be added to the compressed L2P cache 224 or OUO cache 226 in response to data relocation. The OUO cache 226 can be configured to be similar to the exemplary compressed L2P cache 224 of Table 1.

[0040] In one embodiment, such as when the controller 208 relocates data, the L2P cache 224 records the most recently read or written data in the flash memory device 220, while the OUO cache 226 records any updates or changes made to the entries in the L2P cache 224. By utilizing the L2P cache 224 and the OUO cache 226, recently read and written data can be quickly searched in the L2P cache 224 and the OUO cache 226 without having to search the main L2P table 222, which reduces the total time spent searching the physical address of the data. When performing management operations, the entries and information recorded in the L2P cache 224 and the OUO cache 226 can be written or refreshed to the main L2P table 222. The L2P cache 224 and the OUO cache 226 can then be cleaned to record the new entries. Management operations are performed periodically because updates to the main L2P table 222 may be accompanied by delays and may have a lower priority than host operations.

[0041] In some embodiments, the controller 208 reads or writes data to one or more flash memory devices 220 at the FMU level. In some storage devices, rewriting a single data FMU to one or more flash memory devices 220 may involve writing the FMU to a new physical location, updating (e.g., by a flash translation layer) a mapping between a logical address and the new physical address of the FMU, and marking the old FMU as obsolete. The main L2P table 222, the L2P cache 224, and / or the OUO cache 226 may be updated to record the changes to the rewritten FMU.

[0042] The host device 204 includes an optional host L2P cache 228. The host device 204 can optionally record recently read or written data to the storage device 206 in the host L2P cache 228. The host device 204 can optionally traverse or search the host L2P cache 228 and send the physical address of the data with the read or write command. If the physical address sent by the host device 204 from the host L2P cache 228 is consistent, the controller 208 can use the physical address and does not need to search the main L2P table 222 or the L2P cache 224. The OUO cache 226 can record any updates or changes made to the entries in the host L2P cache 228.

[0043] Figure 3A A method 300 of relocating data during a host random read operation is shown according to one embodiment. Figure 3B A conventional method 350 of relocating data during a host random read operation is shown for comparison purposes. Figure 3A Can be used with Figure 1 The present invention is used in conjunction with a storage system 100 including a host device 104 and a storage device 106. Figure 3A Also available with Figure 2 The controller L2P cache may be used in conjunction with a storage system 200 including a host device 204 and a storage device 206. Figure 2 The L2P cache 224 and / or the OUO cache 226 in.

[0044] In operation 302, the controller of the storage device receives a read request from the host device and converts the logical address associated with the data to be read into a physical address. The storage device may use the controller L2P cache to convert the logical address into a physical address. In operation 304, if necessary, the cache entry corresponding to the physical address of the data in the controller L2P cache is updated. Each time the data is read, the cache entry may need to be updated. For example, the cache entry may be updated to reflect the time when the data was last read. When the data is moved to a different physical address (i.e., to one or more FMUs in a new memory block), the controller L2P cache may be further updated. In operation 306, the FMU corresponding to the physical address of the data is read. The controller L2P cache can be used to determine the location of the FMU of the data.

[0045] In operation 308, the controller determines whether the management operation is prioritized. Host operations such as read requests have a higher priority than management operations. Therefore, controller management operations such as data relocation are interleaved between multiple read operations so that the host operation is completed first. Controller management operations can be performed in the background over time, so as not to reduce host latency. If the management operation is not prioritized, the method 300 returns to operation 302 to continue to perform the host operation. If the management operation is prioritized, the method 300 proceeds to operation 310 to begin relocating data.

[0046] In operation 310, the controller reads a subsequent FMU for relocation. The subsequent FMU for relocation is a FMU that is currently available for programming (i.e., empty or erased). In operation 312, the controller relocates the data by writing the data to the subsequent FMU read in operation 310. Relocating data from one memory block to another memory block does not erase the data in the original memory block, but only copies the data to the new memory block.

[0047] In operation 314, a move operation is inserted into the controller L2P cache in response to the data relocation. The move operation may include incrementing or decrementing a version indicator of a cache entry in the controller L2P cache. Inserting the move operation into the controller L2P cache updates the controller L2P cache to show that the logical address associated with the data has been linked to a new physical address corresponding to the relocated FMU storing the data. Inserting the move operation into the controller L2P cache adds one or more new cache entries to the controller L2P cache without invalidating any cache entries already in the controller L2P cache. For example, cache entries in the controller L2P cache associated with physical addresses corresponding to old or previously relocated FMUs remain valid. Thus, the controller L2P cache maintains multiple copies or locations of the relocated data in each cache entry and an indication of the version of the cache entry. In one embodiment, the move operation is inserted into Figure 2 In another embodiment, the move operation is inserted into the L2P cache 224. Figure 2 In yet another embodiment, the move operation is inserted into the OUO cache 226. Figure 2 The L2P cache 224 and the OUO cache 226 are stored in the L2P cache 224 and the OUO cache 226.

[0048] The move operation inserted into the controller L2P cache will update the controller L2P cache to reflect the new physical address recorded to the data logical address without invalidating the data. Therefore, when receiving a read request, the old cache entry corresponding to the pre-relocated FMU or the new cache entry added in response to the data relocation can be read. For example, in operation 306, the controller can search the logical address associated with the data in the controller L2P cache. The controller can read the old cache entry corresponding to the pre-relocated FMU or the new cache entry added in response to the data relocation, because both cache entries will be recorded to the logical address of the data. Therefore, the controller can read data from the pre-relocated FMU or the relocated FMU, depending on which cache entry recorded to the data logical address is read first. In addition, the controller does not need to search the OUO table composed of the relocation entry, because the original cache entry in the controller L2P cache is still valid. Therefore, the processor read overhead can be reduced.

[0049] Conventional method 350 comprises at least one additional operation that method 300 does not comprise.After inserting move operation to update L2P high-speed cache in L2P high-speed cache, thereby display relocation data has been linked to new physical address, conventional method 350 advances to operation 352.In operation 352, controller invalidates the cache entry corresponding to the pre-relocation physical address associated with data in L2P high-speed cache.By invalidating the cache entry, controller will no longer be able to read this cache entry when searching L2P high-speed cache.Therefore, controller may need to read OUO table to find the relocation entry of data, because the cache entry corresponding to this data in L2P high-speed cache has invalidated.In addition, if L2P high-speed cache is the L2P high-speed cache of compression, then the cache entry of whole compression will invalidate.

[0050] Figure 4 A flow chart of a method 400 for updating an L2P cache of a controller of a storage device when the controller relocates data according to one embodiment is shown. The method 400 may be used in conjunction with the method 300. The method 400 may be used in conjunction with Figure 1 The method 400 may also be used with a storage system 100 including a host device 104 and a storage device 106. Figure 2 The present invention is used together with a storage system 200 including a host device 204 and a storage device 206.

[0051] In operation 402 of method 400, a controller (such as Figure 1 The controller 108 or Figure 2The controller 208 of the controller relocates data stored in a first memory block associated with a first physical address to a second memory block associated with a second physical address. The first physical address is recorded in a first cache entry in a compressed L2P cache stored in the controller, such as Figure 2 The L2P cache 224 and / or OUO cache 226 of the first memory block are associated with one or more FMUs in the first memory block, and the second physical address is associated with one or more FMUs in the second memory block. Relocating data from the first memory block to the second memory block does not erase or invalidate the data stored in the first memory block. Instead, the data is stored in the first memory block and the second memory block until the first memory block is erased. Since memory blocks are erased in block units rather than FMUs, data is typically relocated to a new memory block to prepare the pre-relocated memory block to be erased.

[0052] In operation 404, a version indicator of a first cache entry in the compressed logical-to-physical table is incremented without invalidating the first cache entry. The version indicator indicates that the cache entry is currently storing at least partially outdated information and that a newer version of the information is available in the L2P cache.

[0053] In operation 406, one or more updated cache entries are added to the L2P cache in response to relocating the data to the second physical address. The one or more updated cache entries are added without invalidating the first cache entry. The one or more updated cache entries may be added to the controller L2P cache such as Figure 2 The L2P cache 224 and / or outstanding updates to the L2P table such as Figure 2 OUO cache 226. The number of updated cache entries added to the L2P cache depends on the number of entries recorded in the first cache entry. For example, if the first physical address falls in the middle of the physical address range of the first cache entry, the information of the first cache entry may be divided into three new cache entries, as described below with respect to Table 2.

[0054] In operation 408, the controller receives a request to read relocation data from the host device. The host device can send the logical address associated with the data and the request and / or the physical address associated with the data to the storage device. In addition, the controller can send a write request, which will be processed in the same manner as in method 400.

[0055] In operation 410, the controller searches the L2P cache to determine the location of the data. The controller may search the L2P cache for a logical address associated with the data. Since the data has been relocated, the logical address associated with the data may be recorded in multiple cache entries of the L2P cache. Therefore, whichever cache entry corresponds to the logical address associated with the data first read by the controller may be used to determine the location of the data, regardless of the version indicator of the cache entry.

[0056] In operation 412, the controller reads data from the first memory block or the second memory block. The controller may read the first memory block or the second memory block according to the cache entry of the L2P cache that is first read or found in operation 410. For example, if the controller reads the first cache entry corresponding to the first physical address of the data, the controller may read the data in the first memory block. If the controller reads one or more updated cache entries corresponding to the second physical address of the data, the controller may read the data in the second memory block.

[0057] An example is described using Table 2 to illustrate the implementation method 400. Table 2 is a compressed L2P cache stored in the controller, such as Figure 2 In the example described below, it is assumed that data corresponding to logical address 10 is being relocated to the FMU corresponding to physical address 1100.

[0058] Table 2

[0059] Item Number First logical address First physical address The number of concurrent entries that are valid Version 1 5 1000 50 1 2 200 1050 14 … … … … n 5 1000 4 n+1 10 1100 1 n+2 11 1006 44

[0060] As shown in Table 2, logical address 10 is recorded in the first cache entry (entry number 1). After the data corresponding to logical address 10 is relocated, the version indicator of the first cache entry is incremented, as described in operations 402 and 404 of method 400. Then, in operation 406 of method 400, three new updated cache entries are added to the compressed L2P cache, with entry numbers n, n+1, and n+2. The first updated cache entry (entry number n) records logical addresses 5 to 9 to physical addresses 1000 to 1004, as shown by the number of valid concurrent entries. The second updated cache entry (entry number n+1) records logical address 10 to the new relocated physical address 1100. The third updated cache entry (entry number n+2) records the remaining logical addresses of the first cache entry (entry number 1). The third updated cache entry (entry number n+2) records logical addresses 11 to 50 to physical addresses 1006 to 1050. In one embodiment, the updated cache entry is added to the L2P table of outstanding update operations, such as Figure 2 OUO cache 226. In another embodiment, the updated cache entry is added to an L2P cache (such as L2P cache 224) and an L2P table of outstanding update operations (such as OUO cache 226).

[0061] The latest version of the data corresponding to logical address 10 is now relocated to the FMU of the memory block associated with physical address 1100. However, the data is still stored in the memory block associated with physical address 1005, although it may not be the latest version of the data. Therefore, when the controller receives a request to read the data associated with logical address 10 (operation 408 of method 400), the controller may search for logical address 10 in Table 2, and may read the first cache entry (entry number 1) or the second updated cache entry (entry number n+1) to determine the location of the data (operation 410 of method 400). Then, according to operation 412 of method 400, the controller may read the data from the relocated memory block associated with physical address 1100 or the pre-relocated memory block associated with physical address 1005.

[0062] The version indicator (entry number 1) in the first cache entry simply signals to the controller that at least a portion of the information recorded in the first cache entry is out of date or not the latest available version. Although the information corresponding to logical address 10 and physical address 1005 in the first cache entry is not the latest version, the remaining information recorded in the first cache entry is the latest (e.g., information associated with logical addresses 5 to 9 and 11 to 50). When the controller is ready to erase the memory block associated with the first physical address, the version indicator (entry number 1) of the first cache entry can be decremented. The version indicator can be decremented to 0. Decrementing the version indicator of the first cache entry can invalidate or remove the cache entry in the L2P cache.

[0063] Figure 5 A flow chart of a method 500 for scheduling memory blocks to be erased using a compressed L2P cache stored in a controller according to one embodiment is shown. The method 500 may be used in conjunction with the method 300 and / or the method 400. For example, the method 500 may be used after relocating data in operation 402 of the method 400. In addition, the method 500 may be used in conjunction with Figure 1 The method 500 may also be used with a storage system 100 including a host device 104 and a storage device 106. Figure 2Method 500 may be used with a storage system 200 including a host device 204 and a storage device 206. Method 500 may be implemented using a controller of a storage device that stores a compressed L2P table or cache that records the location of data in the FMU of a memory block, such as Figure 2 L2P cache 224 and / or OUO cache 226.

[0064] In operation 502, the validity counter array is sorted according to the validity count. The validity count is the number of valid FMUs in the memory block. If the data stored in the FMU of the first memory block has been relocated to the second memory block, the FMU in the first memory block storing the data can be marked as invalid after the relocation. Marking the FMU as invalid indicates that the FMU is ready to be erased. However, since the erasure of data is performed in block units, the FMU marked as invalid cannot be erased before the memory block containing the invalid FMU is ready to be erased.

[0065] The memory blocks are grouped into banks or cells in the validity counter array by validity count in operation 504. For example, if the memory blocks are composed of 32 FMUs, the memory blocks are grouped into 32 banks based on the validity count of each memory block.

[0066] In operation 506, one or more memory blocks in the bank are prioritized and scheduled for erasure in a priority order. Scheduling memory blocks for erasure may include decrementing a version indicator of a cache entry in the compressed L2P cache. High priority blocks are scheduled for erasure over low priority blocks. The priority order is described in operations 508, 510, and 512.

[0067] In operation 508, the storage with a low validity count is prioritized over the storage with a high validity count. Therefore, the storage with the lowest validity count or the lowest valid FMU number will be the highest priority storage to be erased.

[0068] In operation 510, within each storage unit, memory blocks that do not record data in the compressed L2P cache have a higher priority than memory blocks that record data in the compressed L2P cache. Therefore, within the highest priority storage unit with the lowest validity count, memory blocks that do not record data in the L2P cache have a higher priority than memory blocks that record data in the L2P cache.

[0069] In operation 512, in each storage body, the priority of the memory block that has not been read in the compressed L2P cache recently is higher than the memory block that has been read in the compressed L2P cache recently. Therefore, in the highest priority storage body with the lowest validity count, after the memory block that is not recorded in the L2P cache is scheduled to be erased, the memory block that is recorded in the L2P cache but has not been read recently will be scheduled next. The erasure priority of the memory block that has been read in the L2P cache recently in the storage body is the lowest. The version indicator of the cache entry in the L2P cache can be used to determine the time of the most recent reading of the memory block. For example, if the version indicator of the cache entry indicates that the cache entry is storing some outdated information, the priority of the memory block corresponding to the cache entry can be higher than the memory block corresponding to the current cache entry.

[0070] Figure 6 A flow chart of a method 600 for updating an L2P cache of outstanding update operations of a controller of a storage device according to one embodiment is shown. The method 600 may be used in conjunction with the method 300, the method 400, and / or the method 500. The method 600 may be used in conjunction with Figure 1 The method 600 may also be used with a storage system 100 including a host device 104 and a storage device 106. Figure 2 Method 600 may be used with a storage system 200 including a host device 204 and a storage device 206. Method 600 may be used with a controller of a storage system that stores an outstanding update operation L2P table or cache that records updates made to a host L2P table, such as Figure 2 OUO cache 226.

[0071] In operation 602, a controller of a storage device updates an OUO cache in response to an update of a region of a host L2P table. The host L2P table, such as Figure 2The host L2P cache 228 is a host memory-based cache stored in the host device. The host L2P table can be composed of cache areas, each of which has a version indicator and multiple cache entries for the area. The cache entries in each cache area can record the logical address to the physical address. A single management operation that changes a single cache entry may require the system to invalidate the entire cache area of ​​the host L2P table and then update the cache area. The host device may not use the cache area until it is fully updated. Therefore, when relocating data, the physical address corresponding to the logical address of the relocated data changes, and when updating the corresponding area in the host L2P, the update can be recorded in the OUO cache stored in the controller of the storage device. The controller can record all cache entries in the area being updated to the OUO cache. The controller can also only record the updated cache entries in the area being updated to the OUO cache. The controller can update the OUO cache after relocating the data. In one embodiment, the controller receives a command from the host device to update the OUO cache. The OUO cache may also include a version indicator for the cache entry.

[0072] In operation 604, the controller receives a command to read data. The command may also be a write command, in which case method 600 will continue in the same manner. When the host device sends a command to read or write data, the host device can optionally include a physical address and a logical address associated with the data, such as an address stored in a host L2P table.

[0073] In operation 606, the controller determines whether the current physical address of the data has been sent via a read command. The host device may send the physical address associated with the data to the storage device via a read command, such as by sending a cache area of ​​the host L2P table corresponding to the logical address of the data to the physical address to the storage device. However, if the cache area is currently being updated, the information in the cache area may not be the latest. In one embodiment, the cache entries in the host L2P table will not fail when updated. The cache area of ​​the host L2P table currently being updated may have some outdated information when received by the controller. The controller will read the version indicator of the cache area to determine whether the information recorded in the cache entry of the cache area is outdated.

[0074] If the version indicator indicates that the cache area is up to date, and therefore the physical address received by the command is up to date, the method 600 proceeds to operation 608. In operation 608, the controller reads data from a location corresponding to the current physical address received by the command. The controller may read the data without searching for the location of the data in the controller L2P cache or the main L2P table stored in the flash memory.

[0075] If the physical address in the sent command is out of date or does not have a physical address, method 600 proceeds to operation 610. In operation 610, the controller reads a portion of the host L2P table associated with the data and a portion of the outstanding update operation L2P cache associated with the data to determine the location of the data.

[0076] Since only some of the cache entries in the cache area may have changed or been updated, other cache entries will still be up to date and some of the information recorded in the cache area will also be up to date. Therefore, the controller may read the cache area of ​​the host L2P table sent with the command to determine the location of the data recorded in the cache entry corresponding to the current physical address. The controller will then read the OUO cache to determine the location of the data corresponding to the physical address being updated in the cache area. Therefore, the controller may read the outdated version of the cache area and the updated version in the OUO cache to determine the location of the data.

[0077] By not invalidating cache entries in the controller L2P cache when relocating data, cache coherency issues may be reduced or eliminated and overall read performance may be improved. Maintaining multiple copies of data or information in the controller L2P cache reduces the amount of processing required for data relocation activities and allows for a simpler, non-intrusive method of updating the controller L2P cache to be implemented. Additionally, since the memory blocks to be erased may be selected based on the version indicator of the L2P cache, the life of the memory blocks may be extended.

[0078] In one embodiment, a method of operating a storage device having a plurality of memory blocks includes relocating data stored in a first memory block to a second memory block, receiving a request to read the data, reading a logical to physical table to determine in which memory block of the plurality of memory blocks the data is stored, and reading the data from the first memory block or the second memory block. After relocating the data, a controller of the storage device is able to read the first memory block and the second memory block.

[0079] The logical-to-physical table may be stored in a controller. The logical-to-physical table may be compressed. The method may also include updating the logical-to-physical table in response to relocating data stored in the first memory block to the second memory block. Updating the logical-to-physical table may include incrementing a version indicator of a first cache entry in the logical-to-physical table. A first physical address associated with the first memory block may be recorded to the data in the first cache entry. Updating the logical-to-physical table may include adding one or more cache entries to the logical-to-physical table. The one or more cache entries may record a second physical address associated with the second memory block to the data.

[0080] In another embodiment, a method of operating a storage device includes relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address. The first physical address is recorded in a first cache entry in a compressed logical-to-physical table. The method also includes incrementing a version indicator of the first cache entry in the compressed logical-to-physical table, adding one or more cache entries to the compressed logical-to-physical table in response to relocating the data to the second physical address, searching the compressed logical-to-physical table to determine the location of the data, reading the first cache entry before reading the one or more updated cache entries, and reading the data from the first physical address.

[0081] The method may also include: scheduling a first memory block to be erased, and decrementing a version indicator of a first cache entry in a compressed logical-to-physical table in response to scheduling the first memory block to be erased. The first cache entry in the compressed logical-to-physical table may remain valid until the version indicator is decremented. The compressed logical-to-physical table may be stored in a controller of a storage device. The compressed logical-to-physical table may be searched in response to receiving a command to read or write data. One or more updated cache entries may include a second cache entry corresponding to the relocation of data in a second memory block. In the compressed logical-to-physical table, both the first cache entry and the second cache entry may be valid cache entries. The version indicator of the first cache entry may indicate that the information recorded in the first cache entry is an outdated version of the information recorded in the second cache entry.

[0082] In one embodiment, a storage device includes a plurality of memory blocks. Each memory block in the plurality of memory blocks includes a flash memory cell. The storage device also includes a controller coupled to the plurality of memory blocks. The controller is configured to store a compressed logical-to-physical table. The compressed logical-to-physical table records the location of data in one or more of the plurality of memory blocks. The controller is further configured to sort the validity counter array according to a validity count. The validity count is the number of valid flash memory cells in the memory block. The controller is further configured to prioritize one or more memory blocks to be erased in the plurality of memory blocks. A memory block with a low validity count has a higher priority than a memory block with a high validity count. A memory block that does not record data in the compressed logical-to-physical table has a higher priority than a memory block that records data in the compressed logical-to-physical table. The controller is further configured to schedule one or more memory blocks to be erased in the plurality of memory blocks according to a priority order.

[0083] A memory block that has not been read recently in the compressed logical-to-physical table may have a higher priority than a memory block that has been read recently in the compressed logical-to-physical table. A memory block with a low validity count may have a higher priority than a memory block that has not recorded data in the compressed logical-to-physical table. A memory block that has not recorded data in the compressed logical-to-physical table may have a higher priority than a memory block that has not been read recently in the compressed logical-to-physical table. The controller may also be configured to group the memory blocks according to the validity count before prioritizing one or more memory blocks to be erased from a plurality of memory blocks. The controller may also be configured to store an unfinished update operation table, wherein the unfinished update operation table records updates to the compressed logical-to-physical table.

[0084] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A method of operating a storage device having a plurality of memory blocks, comprising: relocating data stored in a first memory block to a second memory block; receiving a request to read the data; reading a first logical-to-physical table configured to convert a logical address to a physical address to determine in which memory block of the plurality of memory blocks the data is stored, wherein the first logical-to-physical table records most recently read and written data to the plurality of memory blocks; as well as The data is read from the first memory block or the second memory block, wherein a controller of the storage device is capable of reading the first memory block and the second memory block after relocating the data, and wherein the storage device includes a master logical-to-physical table configured to convert logical addresses to physical addresses and record all read, write, and erase data in the plurality of memory blocks. 2 . The method of claim 1 , wherein the first logical-to-physical table is stored in the controller, and wherein the master logical-to-physical table is stored in one or more memory blocks of the plurality of memory blocks. The method of claim 2 , wherein the first logical-to-physical table is compressed.

4. The method according to claim 1, further comprising: The first logical-to-physical table is updated in response to relocating the data stored in the first memory block to the second memory block.

5. The method of claim 4 , wherein updating the first logical-to-physical table comprises incrementing a version indicator of a first cache entry in the first logical-to-physical table in which a first physical address associated with the first memory block is recorded to the data.

6. The method of claim 4, wherein updating the first logical-to-physical table comprises adding one or more cache entries to the first logical-to-physical table, wherein the one or more cache entries record a second physical address associated with the second memory block to the data.

7. A method of operating a storage device, comprising: relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address, wherein the first physical address is recorded in a first cache entry in a compressed logical-to-physical table configured to translate logical addresses to physical addresses, wherein the compressed logical-to-physical table records recently read and written data to the memory block, and wherein the storage device includes a master logical-to-physical table configured to translate logical addresses to physical addresses and record all read, written, and erased data in the memory block; incrementing a version indicator of the first cache entry in the compressed logical-to-physical table; adding one or more updated cache entries to the compressed logical-to-physical table in response to relocating the data to the second physical address; searching the compressed logical-to-physical table to determine the location of the data; reading the first cache entry before reading the one or more updated cache entries; and The data is read from the first physical address.

8. The method according to claim 7, further comprising: scheduling the first memory block to be erased; as well as The version indicator of the first cache entry in the compressed logical-to-physical table is decremented in response to scheduling the first memory block to be erased.

9. The method of claim 8, wherein the first cache entry in the compressed logical-to-physical table remains valid until the version indicator is decremented.

10. The method of claim 7, wherein the compressed logical-to-physical table is stored in a controller of the storage device.

11. The method of claim 7, wherein the compressed logical-to-physical table is searched in response to receiving a command to read or write data.

12. The method of claim 7, wherein the one or more updated cache entries include a second cache entry corresponding to relocating the data to the second memory block.

13. The method of claim 12, wherein the first cache entry and the second cache entry are both valid cache entries in the compressed logical-to-physical table.

14. The method of claim 13, wherein the version indicator of the first cache entry indicates that information recorded in the first cache entry is an outdated version of information recorded in the second cache entry.

15. A storage device comprising: a plurality of memory blocks, wherein each memory block of the plurality of memory blocks comprises flash memory cells; a master logical-to-physical table configured to convert logical addresses to physical addresses and record all read, write, and erase data in the plurality of memory blocks; and a controller coupled to the plurality of memory blocks, wherein the controller is configured to: storing a compressed logical-to-physical table configured to convert logical addresses to physical addresses, wherein the compressed logical-to-physical table records locations of recently read and written data in one or more memory blocks of the plurality of memory blocks; sorting the validity counter array according to a validity count, wherein the validity count is a number of valid flash memory cells in the memory block; Prioritizing one or more memory blocks to be erased from the plurality of memory blocks, wherein memory blocks with low validity counts have higher priorities than memory blocks with high validity counts, and wherein memory blocks with data not recorded in the compressed logical-to-physical table have higher priorities than memory blocks with data recorded in the compressed logical-to-physical table; as well as One or more memory blocks of the plurality of memory blocks are scheduled to be erased according to a priority order.

16. The storage device of claim 15, wherein a memory block that has not been recently read in the compressed logical-to-physical table has a higher priority than a memory block that has been recently read in the compressed logical-to-physical table. 17 . The storage device of claim 16 , wherein a memory block having a low validity count has a higher priority than a memory block having data not recorded to the compressed logical-to-physical table.

18. The storage device of claim 17, wherein a memory block for which data is not recorded in the compressed logical-to-physical table has a higher priority than a memory block that has not been recently read in the compressed logical-to-physical table.

19. The memory device of claim 15, wherein the controller is further configured to group the memory blocks according to validity counts before prioritizing one or more memory blocks to be erased from the plurality of memory blocks.

20. The storage device of claim 15, wherein the controller is further configured to store an unfinished update operation table, wherein the unfinished update operation table records updates made to the compressed logical-to-physical table.

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