Display panel

Abstract

A display panel is disclosed. The display panel includes a substrate having pixels, and each of the pixels has an emission region, a first circuit region, and a second circuit region. Each of the pixels includes: a light-emitting element disposed on the substrate in the emission region; a pixel circuit disposed on the substrate in the first circuit region, the pixel circuit including sub-pixel circuits configured to respectively supply drive current to the light-emitting element; and a test circuit disposed on the substrate in the second circuit region, the test circuit including auxiliary transistors connected in parallel to the respective light-emitting elements, wherein each of the first circuit region and the second circuit region is disposed adjacent to the emission region.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application Nos. 10 - 2019 - 0032503, filed on Mar. 21, 2019, and 10 - 2019 - 0095106, filed on Aug. 05, 2019, and for all purposes, the above - mentioned Korean patent applications are hereby incorporated by reference as if fully set forth herein. Technical field

[0003] Exemplary embodiments / implementations of the present invention generally relate to a display panel and a method of testing the display panel. Background art

[0004] A display device displays an image on a display panel using a control signal applied from an external device.

[0005] A display device may include a plurality of pixels. Each of the pixels may include: a line unit having a scan line, a data line, and a power line; a switching transistor coupled to the line unit; and a light - emitting element and a capacitor coupled to the switching transistor. The switching transistor may be turned on in response to a signal provided through the line unit, such that a driving current flows to the light - emitting element.

[0006] If the switching transistor in a pixel is defective, the pixel may malfunction.

[0007] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus, it may include information that does not constitute the prior art. Summary of the invention

[0008] Devices and methods according to exemplary embodiments of the present invention relate to a display panel capable of testing whether pixels are defective and a method of testing the display panel.

[0009] Additional features of the inventive concept will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0010] According to one or more exemplary embodiments of the present invention, a method of testing a display panel is provided. The display panel includes pixels coupled to a first power line, a second power line, a third power line, a data line, a scan line, an emission control line, and a test line. The method includes: applying a first power supply voltage and a second power supply voltage to the first power line and the second power line, respectively; applying a test voltage having a conduction voltage level to the third power line; sequentially applying scan signals having a conduction voltage level to the scan lines through a scan driver, and applying an emission control signal having a conduction voltage level to the emission control line; applying a gate signal having a conduction voltage level to a test transistor through the test line, the test transistor being coupled between a first pixel electrode and a second pixel electrode of a light-emitting element included in the pixel; measuring a sensed voltage output through the data line; and determining whether the pixel is defective based on the voltage level of the sensed voltage.

[0011] The pixel may include: a first transistor including a first electrode coupled to a first node, a second electrode coupled to a second node, and a gate electrode coupled to a third node; a second transistor including a first electrode coupled to the data line, a second electrode coupled to the first node, and a gate electrode coupled to a first scan line; a third transistor including a first electrode coupled to the second node, a second electrode coupled to the third node, and a gate electrode coupled to the first scan line; a fourth transistor including a first electrode coupled to the third power line, a second electrode coupled to the third node, and a gate electrode coupled to a second scan line; a fifth transistor including a first electrode coupled to the first power line, a second electrode coupled to the first node, and a gate electrode coupled to the emission control line; a sixth transistor including a first electrode coupled to the second node, a second electrode coupled to a fourth node, and a gate electrode coupled to the emission control line; a seventh transistor including a first electrode coupled to the third power line, a second electrode coupled to the fourth node, and a gate electrode coupled to a third scan line; and a capacitor coupled between the first power line and the third node. The light-emitting element may be coupled between the fourth node and the second power line.

[0012] The scan signals may be sequentially provided to the second scan line, the first scan line, and the third scan line.

[0013] A scan signal having one pulse may be applied during each frame period.

[0014] Applying the scan signal and the emission control signal may include: during a first period, applying a scan signal having a conduction voltage level to the second scan line; and during a second period, applying a scan signal having a conduction voltage level to the first scan line, applying an emission control signal having a conduction voltage level to the emission control line, and applying a gate signal having a conduction voltage level to the test line.

[0015] Applying the scan signal and the emission control signal may further include: turning on the fifth transistor, the first transistor, the sixth transistor, and the test transistor during a second period.

[0016] A sensed voltage may be formed at the first node, be proportional to the on-resistances of the first transistor, the sixth transistor, and the test transistor, and be inversely proportional to the on-resistance of the fifth transistor.

[0017] Determining that the pixel is defective may include: determining that the sixth transistor is defective in response to the voltage level of the sensed voltage being equal to or less than a reference voltage level.

[0018] The method may further include: before applying the first power supply voltage and the second power supply voltage, applying a test voltage having a turn-on voltage level to the third power line, sequentially applying scan signals having a turn-on voltage level to the scan lines through a scan driver and applying an emission control signal having a cut-off voltage level to the emission control line, measuring a second sensed voltage output through the test line, and determining whether the first transistor to the fourth transistor are defective based on the second sensed voltage.

[0019] Applying the first power supply voltage and the second power supply voltage may include: applying the first power supply voltage to the first power line; applying a test voltage having a cut-off voltage level to the third power line; sequentially applying scan signals having a turn-on voltage level to the scan lines through a scan driver and applying an emission control signal having a turn-on voltage level to the emission control line; measuring a third sensed voltage output through the data line; and determining whether the fifth transistor is defective based on the third sensed voltage.

[0020] According to one or more exemplary embodiments of the present invention, there is provided a method of testing a display panel including pixels coupled to a first power line, a second power line, a third power line, a data line, a scan line, an emission control line, and a test line, the method including: applying a first power supply voltage to the first power line; applying a test voltage having a turn-on voltage level to the second power line; sequentially applying scan signals having a turn-on voltage level to the scan lines through a scan driver and applying an emission control signal having a turn-on voltage level to the emission control line; applying a gate signal having a turn-on voltage level to a test transistor through the test line, the test transistor being coupled between a first pixel electrode and a second pixel electrode of a light-emitting element included in the pixel; measuring a sensed voltage output through the data line; and determining whether the pixel is defective based on the voltage level of the sensed voltage measured through the data line.

[0021] The pixel may include: a first transistor including a first electrode coupled to a first node, a second electrode coupled to a second node, and a gate electrode coupled to a third node; a second transistor including a first electrode coupled to a data line, a second electrode coupled to the first node, and a gate electrode coupled to a first scan line; a third transistor including a first electrode coupled to the second node, a second electrode coupled to the third node, and a gate electrode coupled to the first scan line; a fourth transistor including a first electrode coupled to a third power line, a second electrode coupled to the third node, and a gate electrode coupled to a second scan line; a fifth transistor including a first electrode coupled to a first power line, a second electrode coupled to the first node, and a gate electrode coupled to an emission control line; a sixth transistor including a first electrode coupled to the second node, a second electrode coupled to a fourth node, and a gate electrode coupled to the emission control line; a seventh transistor including a first electrode coupled to the third power line, a second electrode coupled to the fourth node, and a gate electrode coupled to a third scan line; and a capacitor coupled between the first power line and the third node. A light-emitting element may be coupled between the fourth node and a second power line.

[0022] Scan signals may be sequentially provided to the second scan line, the first scan line, and the third scan line.

[0023] A scan signal having two pulses may be applied during each frame period.

[0024] A gate signal having a pulse in a section between two pulses may be applied during each frame period.

[0025] Applying the scan signal and the emission control signal may include: during a first period, applying a scan signal having a conduction voltage level to the second scan line and the third scan line, and applying a gate signal having a conduction voltage level to a test line; and during a second period, applying a scan signal having a conduction voltage level to the first scan line.

[0026] Determining that a pixel is defective may include: determining that the seventh transistor is defective in response to a voltage level of a sense voltage being equal to or less than a reference voltage level.

[0027] The method may further include: before applying a first power supply voltage, applying a test voltage having a conduction voltage level to the third power line, sequentially applying a scan signal having a conduction voltage level to the scan lines through a scan driver and applying an emission control signal having a cut-off voltage level to the emission control line, measuring a second sense voltage output through the data line, and determining whether the first transistor to the fourth transistor are defective based on the second sense voltage.

[0028] According to one or more exemplary embodiments of the present invention, a display panel includes a first scan line, a second scan line, a third scan line, and a fourth scan line, data lines, an emission control line, a first power line, a second power line, a third power line, and pixels. Each pixel includes: a first transistor including a first electrode coupled to a first node, a second electrode coupled to a second node, and a gate electrode coupled to a third node; a second transistor including a first electrode coupled to the data line, a second electrode coupled to the first node, and a gate electrode coupled to the first scan line; a third transistor including a first electrode coupled to the second node, a second electrode coupled to the third node, and a gate electrode coupled to the first scan line; a fourth transistor including a first electrode coupled to the third power line, a second electrode coupled to the third node, and a gate electrode coupled to the second scan line; a fifth transistor including a first electrode coupled to the first power line, a second electrode coupled to the first node, and a gate electrode coupled to the emission control line; a sixth transistor including a first electrode coupled to the second node, a second electrode coupled to a fourth node, and a gate electrode coupled to the emission control line; a seventh transistor including a first electrode coupled to the third power line, a second electrode coupled to the fourth node, and a gate electrode coupled to the third scan line; an eighth transistor including a first electrode coupled to the fourth node, a second electrode coupled to the second power line, and a gate electrode coupled to the fourth scan line; a storage capacitor coupled between the first power line and the third node; and a light-emitting element coupled between the fourth node and the second power line.

[0029] According to one or more exemplary embodiments of the present invention, a display panel includes a substrate having pixels. Each of the pixels has an emission region, a first circuit region, and a second circuit region. Each of the pixels includes: a light-emitting element disposed on the substrate in the emission region; a pixel circuit disposed on the substrate in the first circuit region, the pixel circuit including sub-pixel circuits configured to respectively provide drive current to the light-emitting element; and a test circuit disposed on the substrate in the second circuit region, the test circuit including auxiliary transistors connected in parallel to corresponding light-emitting elements. Each of the first circuit region and the second circuit region may be disposed adjacent to the emission region.

[0030] The display panel may further include scan lines and data lines disposed on the substrate. Each of the pixels is defined by the scan lines and the data lines. Each of the sub-pixel circuits may include at least one transistor coupled to the scan lines and the data lines.

[0031] The pixel circuit may be disposed in a first direction with respect to the light-emitting element. The test circuit may be disposed in a second direction with respect to the light-emitting element, the second direction being perpendicular to the first direction.

[0032] Each of the pixels may also have a peripheral region. Each of the pixels may also include a connection line extending from a first circuit region to a second circuit region in the peripheral region. The auxiliary transistors may be respectively coupled to the light-emitting elements through the connection lines.

[0033] The display panel may further include an emission capacitor formed by at least a part of each of the connection lines extending to the emission region and overlapping with the cathode electrode of the corresponding light-emitting element. The width of the portion of the connection line overlapping with the cathode electrode may be greater than the width of the portion of the connection line not overlapping with the cathode electrode.

[0034] The light-emitting elements may include a first light-emitting element configured to emit light having a first color, a second light-emitting element configured to emit light having a second color, and a third light-emitting element configured to emit light having a third color.

[0035] The cathode electrode of each of the light-emitting elements may be coupled to a second power line. The second power line may be disposed on the entire surface of the substrate and include an opening formed in the emission region. The anode electrode of the light-emitting element may be disposed in the opening.

[0036] The second power line may include a first opening and a second opening formed in the emission region, and the first opening and the second opening are spaced apart from each other with respect to the cathode electrode. At least one of the light-emitting elements may be disposed in the first opening, and the remaining light-emitting elements may be disposed in the second opening.

[0037] Each of the sub-pixel circuits may include a first semiconductor pattern that forms a channel region of at least one transistor. The test circuit may include a second semiconductor pattern that forms a channel region of each of the auxiliary transistors. The second semiconductor pattern may be spaced apart from the first semiconductor pattern.

[0038] Each in the sub-pixel circuit may include: a first transistor including a first electrode coupled to a first node, a second electrode coupled to a second node, and a gate electrode coupled to a third node; a second transistor including a first electrode coupled to a data line, a second electrode coupled to the first node, and a gate electrode coupled to a first scan line; a third transistor including a first electrode coupled to the second node, a second electrode coupled to the third node, and a gate electrode coupled to the first scan line; a fourth transistor including a first electrode coupled to a third power line, a second electrode coupled to the third node, and a gate electrode coupled to a second scan line; a fifth transistor including a first electrode coupled to a first power line, a second electrode coupled to the first node, and a gate electrode coupled to an emission control line; a sixth transistor including a first electrode coupled to the second node, a second electrode coupled to a fourth node, and a gate electrode coupled to the emission control line; a seventh transistor including a first electrode coupled to the third power line, a second electrode coupled to the fourth node, and a gate electrode coupled to a third scan line; and a storage capacitor coupled between the first power line and the third node. An anode electrode of one of the light-emitting elements may be coupled to the fourth node.

[0039] The display panel may further include a pixel circuit layer disposed on the substrate and a light-emitting element layer disposed on the pixel circuit layer. The pixel circuit layer may include the first transistor to the seventh transistor, an auxiliary transistor, and a storage capacitor. The light-emitting element layer may include light-emitting elements, and the anode electrode and the cathode electrode of the light-emitting element may be disposed on the same layer.

[0040] Each of the light-emitting elements may include a first semiconductor layer, an intermediate layer, and a second semiconductor layer stacked in sequence. Each of the anode electrodes may be coupled to the first semiconductor layer through a first contact electrode. The cathode electrode may be coupled to the second semiconductor layer through a second contact electrode.

[0041] The pixel circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked in sequence on the substrate. A semiconductor pattern of the auxiliary transistor may be disposed between the substrate and the first insulating layer. A gate electrode of the auxiliary transistor may be disposed between the first insulating layer and the second insulating layer. A third data line may be disposed between the second insulating layer and the third insulating layer. A first electrode and a second electrode of the auxiliary transistor may be disposed between the third insulating layer and the fourth insulating layer. A first power line may be disposed between the fourth insulating layer and the fifth insulating layer.

[0042] The first electrode of the sixth transistor may be coupled to the anode electrode of the light-emitting element through a bridging pattern interposed between the fourth insulating layer and the fifth insulating layer. The cathode electrode of the light-emitting element may be integrally formed with a second power line disposed on the same layer as the layer on which the cathode electrode is disposed.

[0043] The bridging pattern may partially overlap with the second power line. The second power line, the fifth insulating layer, and the bridging pattern may form an emission capacitor.

[0044] According to one or more exemplary embodiments of the present invention, a display panel includes: data lines extending in a first direction; scan lines extending in a second direction intersecting the first direction; and unit pixels coupled to the data lines and the scan lines. Each of the unit pixels may include a first pixel, a second pixel, a third pixel, and a fourth pixel disposed adjacent to each other in the first direction and the second direction. Each of the first to fourth pixels may include: a light-emitting element disposed in an emission region; a pixel circuit disposed in a first circuit region, the pixel circuit including sub-pixel circuits configured to respectively provide driving current to the light-emitting element; and a test circuit disposed in a second circuit region, the test circuit including auxiliary transistors connected in parallel to the corresponding light-emitting element.

[0045] The first circuit region may be disposed between the emission regions of two adjacent pixels in the first direction. The second circuit region may be disposed between the emission regions of two adjacent pixels in the second direction. Each of the sub-pixel circuits may include at least one transistor coupled to the scan line and the data line.

[0046] The display panel may further include a scan driver coupled to the scan lines and configured to provide scan signals to the scan lines. The scan driver may be disposed between two unit pixels adjacent to each other in the second direction among the unit pixels.

[0047] According to one or more exemplary embodiments of the present invention, a display panel includes: a substrate including an emission region, a first circuit region, and a second circuit region; a light-emitting element disposed in the emission region; a first pixel circuit disposed in the first circuit region and including at least one transistor, the first pixel circuit configured to provide a driving current corresponding to a data signal provided through the data line to the light-emitting element in response to a scan signal provided through the scan line; and a test circuit disposed in the second circuit region and including at least one auxiliary transistor connected in parallel to the light-emitting element.

[0048] The substrate may include a pixel region defined by the scan lines and the data lines. The pixel region may include an emission region, a first circuit region, and a second circuit region.

[0049] The emission region may be disposed between the first circuit region and the second circuit region.

[0050] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the specification, are used to explain the inventive concept.

[0052] Figure 1A and Figure 1B are diagrams showing a display device according to an exemplary embodiment of the present disclosure.

[0053] Figure 2 is a diagram showing Figure 1A an example of a pixel included in the display device.

[0054] Figure 3 is a waveform diagram showing signals measured in a pixel according to an exemplary embodiment during Figure 2 the pixel.

[0055] Figure 4 is a diagram for describing the operation of a pixel in response to a signal of Figure 3 the pixel.

[0056] Figure 5 is a waveform diagram showing signals measured in a pixel according to an exemplary embodiment during Figure 2 the pixel.

[0057] Figure 6 is a diagram for describing the operation of a pixel in response to a signal of Figure 5 the pixel.

[0058] Figure 7A and Figure 7B is a waveform diagram showing signals measured in a pixel according to an exemplary embodiment during Figure 2 the pixel.

[0059] Figure 8 is a diagram for describing the operation of a pixel in response to a signal of Figure 7A the pixel.

[0060] Figure 9A and Figure 9B is a waveform diagram showing signals measured in a pixel according to an exemplary embodiment during Figure 2 the pixel.

[0061] Figure 10 is a diagram for describing the operation of a pixel in response to a signal of Figure 9A the pixel.

[0062] Figure 11A and Figure 11B is a diagram showing Figure 2 an example of a pixel.

[0063] Figure 12 is a diagram showing Figure 11ALayout of an example of pixels.

[0064] Figure 13 is a diagram showing Figure 12 a plan view of an example of a semiconductor layer included in a pixel of

[0065] Figure 14 is a plan view of a conductive layer included in a pixel of Figure 12 according to an exemplary embodiment.

[0066] Figure 15 is a cross-sectional view showing an example of a pixel taken along Figure 12 section line I-I' and section line II-II' of

[0067] Figure 16A , Figure 16B , Figure 16C and Figure 16D is a layout of pixels included in a display device of Figure 1B according to an exemplary embodiment.

[0068] Figure 17 is a plan view of pixels included in a display device of Figure 1B according to an exemplary embodiment.

[0069] Figure 18 is a plan view of pixels included in a display device of Figure 1B according to an exemplary embodiment.

[0070] Figure 19 is a diagram of a display device according to an exemplary embodiment of the present disclosure.

[0071] Figure 20 is a diagram showing Figure 19 a plan view of an example of a display device of Detailed Description

[0072] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of devices or methods that use one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Additionally, the various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations, and features of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0073] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter, collectively or individually referred to as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0074] The cross-hatching and / or shading used in the drawings are generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. Additionally, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the elements may be exaggerated. When the exemplary embodiments may be implemented differently, a specific process may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. Furthermore, the same reference numerals denote the same elements.

[0075] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. For this reason, the term "connected" can refer to physical, electrical, and / or fluid connection with or without intervening elements. Additionally, the DR1-axis, DR2-axis, and DR3-axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis), and can be interpreted in a broader sense. For example, the DR1-axis, DR2-axis, and DR3-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0076] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of this disclosure.

[0077] For descriptive purposes, spatial relative terms such as "under", "below", "beneath", "low", "above", "on", "over", "high", "side" (e.g., as in "sidewall") may be used herein, and thereby to describe the relationship of one (some) element(s) to another (other) element(s) as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "under" can include both an orientation of "above" and "under". Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0078] The terms used in this specification are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, when the terms "comprises", "comprising", "includes", and / or "including" are used in the specification, it is stated that there are the features, integers, steps, operations, elements, components, and / or groups thereof described, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not terms of degree, and are thus used to account for the inherent deviations in the measurements, calculations, and / or values provided that would be recognized by one of ordinary skill in the art.

[0079] In this document, various exemplary embodiments are described with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Accordingly, variations in the shape of the figures due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the exemplary embodiments disclosed herein are not necessarily to be construed as limited to the specific shapes of the regions shown, but will include, for example, deviations in shape due to manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shape of the regions of the device and are thus not necessarily intended to be limiting.

[0080] As is customary in the art, some exemplary embodiments are described and illustrated in the drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections) that can be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, without departing from the scope of the inventive concept, each block, unit, and / or module in some exemplary embodiments can be physically divided into two or more mutually interacting and discrete blocks, units, and / or modules. Further, without departing from the scope of the inventive concept, the blocks, units, and / or modules in some exemplary embodiments can be physically combined into more complex blocks, units, and / or modules.

[0081] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Unless expressly so defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0082] Figure 1A and Figure 1B is a diagram showing a display device 10 according to an exemplary embodiment of the present disclosure.

[0083] Referring to Figure 1A and Figure 1B FIGS., the display device 10 may include a display panel 100, a timing controller 200, a data driver 300, and a scan driver 400.

[0084] The display panel 100 may include a display area DA on which an image is displayed and a non-display area NDA excluding the display area DA. The non-display area NDA may be provided on one side of the display area DA or formed to surround the display area DA, but is not limited thereto.

[0085] The display panel 100 may include signal lines and pixels PX. The signal lines may include data lines DL1 to DLm (where m is a positive integer), scan lines SL1 to SLn (where n is a positive integer), emission control lines EL1 to ELn, and test lines TL1 to TLn. The pixels PX may be disposed in the display area DA and may be disposed in an area defined by the data lines DL1 to DLm, the scan lines SL1 to SLn, and the emission control lines EL1 to ELn. The pixels PX may be electrically connected to the data lines DL1 to DLm, the scan lines SL1 to SLn, the emission control lines EL1 to ELn, and the test lines TL1 to TLn.

[0086] For example, the pixel PX disposed on the first row and the first column may be connected to the first data line DL1, the first scan line SL1, the first emission control line EL1, and the first test line TL1. For example, the pixel PX disposed on the n-th row and the m-th column may be connected to the m-th data line DLm, the n-th scan line SLn, the n-th emission control line ELn, and the n-th test line TLn. However, the connection of the pixel PX is not limited thereto. For example, each pixel PX may be electrically connected to scan lines corresponding to rows adjacent to the row including the pixel PX (e.g., scan lines corresponding to the row before the row including the pixel PX and scan lines corresponding to the row after the row including the pixel PX). Although not shown, the pixel PX may be electrically connected to power lines such as a first power line (e.g., “PL1” in Figure 2 ), a second power line (e.g., “PL2” in Figure 2 ), and an initialization power line (e.g., “PL3” in Figure 2 ) to receive a first power supply voltage VDD, a second power supply voltage VSS, and an initialization voltage VINT. Here, the first power supply voltage VDD and the second power supply voltage VSS may be voltages required to drive the pixel PX. The initialization voltage VINT may be a voltage for initializing the pixel PX (or internal components of the pixel PX). The first power supply voltage VDD, the second power supply voltage VSS, and the initialization voltage VINT may each be provided from separate power supplies.

[0087] Each pixel PX may emit light with a brightness corresponding to a data signal provided through a corresponding data line in response to a scan signal provided through a scan line and an emission control signal provided through a corresponding emission control line. The detailed configuration and operation of the pixel PX will be described later herein with reference to Figure 2 description of the pixel PX.

[0088] The timing controller 200 may receive a control signal and input image data (e.g., RGB data) from an external device (e.g., a graphics processor), and generate a scan control signal GCS and a data control signal DCS based on the control signal. Here, the control signal may include a clock signal, a horizontal sync signal, a data enable signal, etc. The scan control signal GCS may be a signal for controlling the operation of the scan driver 400, and includes a start signal (or scan start signal), a clock signal (or scan clock signal), etc. The scan control signal GCS may also include a emission start signal, an emission clock signal, etc. The data control signal DCS may be a signal for controlling the operation of the data driver 300, and includes a load signal (or data enable signal) for indicating an output valid data signal.

[0089] The timing controller 200 may convert the input image data into image data D-RGB corresponding to the pixel array of the display panel 100, and output the image data D-RGB.

[0090] The data driver 300 may generate a data signal based on the data control signal DCS and the image data D-RGB, and provide the data signal to the data lines DL1 to DLm.

[0091] The data driver 300 may be implemented as an IC, and may be connected to the display panel 100 in the form of a tape carrier package (TCP), or formed in the non-display area NDA of the display panel 100.

[0092] The scan driver 400 may generate a scan signal based on the scan control signal GCS, and provide the scan signal to the scan lines SL1 to SLn. For example, the scan driver 400 may sequentially generate and output a scan signal corresponding to the start signal (e.g., a scan signal having a waveform identical or similar to the waveform of the start signal) using the clock signal. The scan driver 400 may include a shift register. Although the scan driver 400 may be formed in the non-display area NDA of the display panel 100, it is not limited thereto. The scan driver 400 may be implemented as an IC, and connected to the display panel 100 in the form of a TCP.

[0093] The scan driver 400 may generate an emission control signal, and provide the emission control signal to the emission control lines EL1 to ELn. For example, the scan driver 400 may sequentially generate and output an emission control signal corresponding to the emission start signal using the emission clock signal.

[0094] In an embodiment, the scan driver 400 may generate a gate signal (or test control signal), and sequentially provide the gate signal to the test lines TL1 to TLn. For example, the scan driver 400 may sequentially generate and output a gate signal corresponding to the test start signal.

[0095] Although Figure 1A it is shown that the scan driver 400 generates the emission control signal, the present disclosure is not limited thereto. For example, the display device 10 may include an emission driver separate from the scan driver 400 to generate the emission control signal.

[0096] In addition, although Figure 1A it is shown that the test lines TL1 to TLn are coupled to the scan driver 400, the present disclosure is not limited thereto. For example, as Figure 1B shown, the test lines TL1 to TLn may be electrically coupled to each other and receive the gate signal GT from an external device (e.g., a test device for testing the display device 10). The operation of the display panel 100 (or the pixel PX) in response to the gate signal GT will be described later herein with reference to Figure 8 , Figure 9A , Figure 9B , Figure 10 , Figure 11A and Figure 11B .

[0097] Figure 2 is a circuit diagram showing an example of the pixel PX included in the display device 10 Figure 1A .

[0098] Referring to Figure 1A and Figure 2 , the pixel PX may include first to eighth transistors M1 to M8, a storage capacitor CST, and a light-emitting element LD. The pixel PX may also include an emission capacitor (or capacitor) CLD.

[0099] Each of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may be formed of a P-type transistor (e.g., a PMOS transistor), but the present disclosure is not limited thereto. For example, at least some of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may be formed of an N-type transistor (e.g., an NMOS transistor).

[0100] The first transistor (or driving transistor) M1 may include a first electrode electrically coupled to the first node N1, a second electrode electrically coupled to the second node N2, and a gate electrode electrically coupled to the third node N3.

[0101] The second transistor (or switching transistor) M2 may include a first electrode coupled to the data line DL, a second electrode coupled to the first node N1, and a gate electrode coupled to the first scan line SLi (where i is an integer greater than or equal to 2). The second transistor M2 may be turned on in response to a first scan signal GW[N] provided through the first scan line SLi (where N is a positive integer), and may transfer a data signal VDATA provided through the data line DL to the first node N1. For example, the first scan signal GW[N] may be a pulse signal including at least one pulse having a conduction voltage level for turning on the transistor.

[0102] The third transistor M3 may include a first electrode coupled to the second node N2, a second electrode coupled to the third node N3, and a gate electrode coupled to the first scan line SLi. The third transistor M3 may be turned on in response to the first scan signal GW[N], and may transfer the data signal VDATA transferred from the first node N1 through the first transistor M1 to the third node N3.

[0103] The storage capacitor CST may be coupled between the first power line PL1 and the third node N3. Here, a first power supply voltage VDD may be applied to the first power line PL1. The storage capacitor CST may store the data signal VDATA transferred to the third node N3.

[0104] The fourth transistor M4 may include a first electrode coupled to the third node N3, a second electrode coupled to an initialization power line (or third power line) PL3, and a gate electrode coupled to the second scan line (or previous scan line) SLi-1. The second scan line SLi-1 may be a scan line that is disposed adjacent to the first scan line SLi and receives a scan signal earlier than the first scan line SLi. The fourth transistor M4 may be turned on in response to a second scan signal GI[N] provided through the second scan line SLi-1, and may initialize the third node N3 using an initialization voltage VINT provided through the initialization power line PL3. In other words, the node voltage of the third node N3 (or the data signal VDATA stored in the storage capacitor CST during the previous frame) may be initialized by the initialization voltage VINT.

[0105] The fifth transistor M5 may include a first electrode coupled to the first power line PL1, a second electrode coupled to the first node N1, and a gate electrode coupled to the emission control line EL. Similarly, the sixth transistor M6 may include a first electrode coupled to the second node N2, a second electrode coupled to the fourth node N4, and a gate electrode coupled to the emission control line EL. The fifth transistor M5 and the sixth transistor M6 may be turned on in response to an emission control signal EM[N] provided through the emission control line EL, and form a current flow path for driving a current between the first power line PL1 and the fourth node N4 (or between the first power line PL1 and the second power line PL2).

[0106] The light-emitting element (or light-emitting diode) LD may include an anode electrode (or a first pixel electrode) coupled to the fourth node N4 and a cathode electrode (or a second pixel electrode) coupled to the second power line PL2. For example, the light-emitting element LD may be an organic light-emitting diode or an inorganic light-emitting diode. The light-emitting element LD may emit light with a brightness corresponding to a driving current (or an amount of the driving current).

[0107] The emission capacitor CLD may be coupled in parallel with the light-emitting element LD, and prevent or suppress the light-emitting element LD from emitting light due to, for example, a leakage current introduced into the fourth node N4 through the sixth transistor M6.

[0108] The seventh transistor M7 may include a first electrode coupled to the fourth node N4, a second electrode coupled to the initialization power line PL3, and a gate electrode coupled to the third scan line (subsequent scan line) SLi+1. The third scan line SLi+1 may be a scan line that is disposed adjacent to the first scan line SLi and receives a scan signal later than the first scan line SLi. The seventh transistor M7 may initialize the fourth node N4 (or the emission capacitor CLD) in response to the third scan signal GB[N].

[0109] The eighth transistor (or test transistor) M8 may include a first electrode electrically coupled to the fourth node N4, a second electrode coupled to the second power line PL2, and a gate electrode coupled to the test line (or fourth scan line) TL. In response to a gate signal GT[N] provided through the test line TL, the eighth transistor M8 may form a current flow path bypassing the light-emitting element LD. During a normal driving operation of the display device 10 (in other words, when the display device 10 normally displays an image after completing a test), the eighth transistor M8 may not operate.

[0110] In an embodiment, the eighth transistor M8 may include a first sub-transistor M8-1 and a second sub-transistor M8-2 connected in series between a fourth node N4 and a second power line PL2. The first sub-transistor M8-1 and the second sub-transistor M8-2 may be turned on / off in response to a gate signal GT[N] provided through a test line TL. In other words, the eighth transistor M8 may be implemented as a double-gate transistor. In this case, when the display device 10 is operating normally, the leakage current through the eighth transistor M8 may be interrupted or reduced.

[0111] Hereinafter, a method for testing a test display panel 100 according to an exemplary embodiment of the present disclosure will be described with reference to Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9A , Figure 9B and Figure 10 a method for testing a test display panel 100 according to an exemplary embodiment of the present disclosure will be described with reference to

[0112] Figure 3 is a waveform diagram showing signals measured in a pixel PX according to an exemplary embodiment in Figure 2 a pixel PX. Figure 4 is a diagram for describing the operation of a pixel PX in response to Figure 3 a signal of a pixel PX. The pixel PX may be any one selected from the pixel PX shown in Figure 1A a pixel PX. Figure 3 and Figure 4 show a test method for determining whether the first transistor M1 to the fourth transistor M4 provided in the pixel PX are defective.

[0113] Referring to Figure 1A , Figure 3 and Figure 4 , at a reference time point T0, the test of the display panel 100 may be started.

[0114] A first power supply voltage VDD may be applied to a first power line PL1. In addition, a test voltage VTEST having a conduction voltage level may be applied to an initialization power line PL3. In other words, an initialization voltage VINT having a voltage level equal to the voltage level of the test voltage VTEST (i.e., the conduction voltage level) may be measured. Here, the conduction voltage level may correspond to a voltage level for turning on a transistor (e.g., Figure 4 any one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8). The cut-off voltage level may correspond to a voltage level for turning off a transistor (e.g., Figure 4The voltage level at which any one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 is turned off.

[0115] Thereafter, a start signal (or scan start signal) having a conduction voltage level can be applied to the scan driver 400 described with reference to Figure 1A In response thereto, the scan driver 400 can sequentially output scan signals having a conduction voltage level to the scan lines SL1 to SLn. An emission start signal having a cut-off voltage level can be applied to the scan driver 400.

[0116] In this case, at the first time point T1, the level of the second scan signal GI[N] can change from the cut-off voltage level to the conduction voltage level in response to the start signal (or scan start signal). During at least a part of the first period P1, the level of the second scan signal GI[N] can be maintained at the conduction voltage level. Here, the width of the first period P1 (and the second period P2) can correspond to the first horizontal period (i.e., the time allotted to driving one pixel bar). Each frame period can include a horizontal period.

[0117] During the first period P1, the level of each of the first scan signal GW[N] and the third scan signal GB[N] can be maintained at the cut-off voltage level, and the level of the emission control signal EM[N] can also be maintained at the cut-off voltage level.

[0118] In this case, as Figure 4 shown, the fourth transistor M4 can be turned on in response to the second scan signal GI[N] having a conduction voltage level, and the test voltage VTEST applied to the initialization power line PL3 can be transmitted to the third node N3. The storage capacitor CST can store the test voltage VTEST. The first transistor M1 can be turned on in response to the test voltage VTEST.

[0119] The second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can remain turned off.

[0120] Referring again to Figure 3 , at the second time point T2, the first scan signal GW[N] can change from the cut-off voltage level to the conduction voltage level. During the second period P2, the level of the first scan signal GW[N] can be maintained at the conduction voltage level.

[0121] The level of the second scan signal GI[N] can change to the cut-off voltage level before the second time point T2 and be maintained at the cut-off voltage level during the second period P2.

[0122] In this case, as Figure 4 shown, the second transistor M2 and the third transistor M3 can be turned on in response to a first scan signal GW[N] having a turn-on voltage level. The third node N3 can be electrically connected to the data line DL through the first transistor M1 to the third transistor M3. Therefore, a test voltage VTEST can be supplied to the data line DL, and a sense voltage VSEN corresponding to the test voltage VTEST can be measured.

[0123] Although the sense voltage VSEN may have a partially distorted shape, for example, due to the charge / discharge characteristics of the storage capacitor CST and signal transmission delay, the sense voltage VSEN can have a pulse shape corresponding to the first scan signal GW[N].

[0124] Thereafter, in this test method, it can be determined whether the pixel PX (or the pixel circuit) is defective based on the voltage level of the sense voltage VSEN.

[0125] For example, this test method can include: comparing the sense voltage VSEN with a preset reference voltage VREF; and when the sense voltage VSEN is equal to or less than the reference voltage VREF, determining that a failure has occurred in at least one of the first transistor M1 to the fourth transistor M4.

[0126] As referred to Figure 3 and Figure 4 described, the method for testing the display panel 100 can include: applying a start signal (or a scan start signal) having a turn-on voltage level to the scan driver 400 (i.e., sequentially applying scan signals to the scan lines SL1 to SLn) in a state where a test voltage VTEST having a turn-on voltage level has been applied to the initialization power line PL3; and measuring the sense voltage VSEN on the data line DL to determine whether the first transistor M1 to the fourth transistor M4 in the pixel PX are defective.

[0127] Figure 5 is a waveform diagram showing signals measured in the pixel PX according to an exemplary embodiment in Figure 2 the. Figure 6 is a diagram for describing the operation of the pixel PX in response to Figure 5 the signal of. Figure 5 and Figure 6 show a test method for determining whether the fifth transistor M5 provided in the pixel PX is defective. The test method described with reference to Figure 5 and Figure 6 can be performed after (or before) the test operations described with reference to Figure 3 and Figure 4 described.

[0128] Referring toFigure 1A , Figure 5 and Figure 6 , at the reference time point T0, the test of the display panel 100 can be started.

[0129] A first power supply voltage VDD can be applied to the first power line PL1. In addition, a test voltage VTEST having a cut-off voltage level can be applied to the initialization power line PL3. In other words, the initialization voltage VINT having the same voltage level as the voltage level of the test voltage VTEST (i.e., the cut-off voltage level) can be measured.

[0130] Thereafter, a start signal (or a scan start signal) having a conduction voltage level and a emission start signal having a conduction voltage level can be simultaneously applied to the scan driver 400 described with reference to Figure 1A . In response thereto, the scan driver 400 can sequentially output scan signals having a conduction voltage level to the scan lines SL1 to SLn, and can also sequentially output emission control signals having a conduction voltage level to the emission control lines EL1 to ELn.

[0131] In this case, at the first time point T1, the level of the second scan signal GI[N] can change from the cut-off voltage level to the conduction voltage level in response to the start signal (or the scan start signal). During at least a part of the first period P1, the level of the second scan signal GI[N] can be maintained at the conduction voltage level.

[0132] During the first period P1, the level of each of the first scan signal GW[N] and the third scan signal GB[N] can be maintained at the cut-off voltage level, and the level of the emission control signal EM[N] can also be maintained at the cut-off voltage level.

[0133] In this case, as shown in Figure 6 , the fourth transistor M4 can be turned on in response to the second scan signal GI[N] having a conduction voltage level, and the test voltage VTEST applied to the initialization power line PL3 (i.e., a voltage having a cut-off voltage level) can be transmitted to the third node N3. The storage capacitor CST can store the test voltage VTEST. The first transistor M1 can be turned off in response to the test voltage VTEST having a cut-off voltage level.

[0134] The second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can remain turned off.

[0135] Referring again to Figure 5, at the second time point T2, the first scan signal GW[N] can transition from a cut-off voltage level to a conduction voltage level. During the second period P2, the first scan signal GW[N] can be maintained at the conduction voltage level. Similarly, the emission control signal EM[N] can transition from a cut-off voltage level to a conduction voltage level. During the second period P2, the emission control signal EM[N] can be maintained at the conduction voltage level. The pulse width of the emission control signal EM[N] can be greater than the pulse width of the first scan signal GW[N], but the present disclosure is not limited thereto.

[0136] The level of the second scan signal GI[N] can be changed to a cut-off voltage level before the second time point T2 and maintained at the cut-off voltage level during the second period P2.

[0137] In this case, as Figure 6 shown, the second transistor M2 and the third transistor M3 can be turned on in response to the first scan signal GW[N] having a conduction voltage level, and the fifth transistor M5 and the sixth transistor M6 can be turned on in response to the emission control signal EM[N] having a conduction voltage level. The first power line PL1 can be electrically connected to the data line DL through the fifth transistor M5 and the second transistor M2. Therefore, the first power supply voltage VDD applied to the first power line PL1 can be supplied to the data line DL, and the sense voltage VSEN corresponding to the first power supply voltage VDD can be measured.

[0138] Thereafter, in this test method, it can be determined whether the pixel PX (or the pixel circuit) is defective based on the voltage level of the sense voltage VSEN.

[0139] For example, this test method can include: comparing the sense voltage VSEN with a preset reference voltage VREF; and when the sense voltage VSEN is equal to or less than the reference voltage VREF, determining that a failure has occurred on the fifth transistor M5.

[0140] As referred to Figure 5 and Figure 6 described, the method of testing the display panel 100 can include: in a state where a test voltage VTEST having a cut-off voltage level has been applied to the initialization power line PL3, applying a start signal (or a scan start signal) having a conduction voltage level and an emission start signal having a conduction voltage level to the scan driver 400 (i.e., sequentially applying scan signals to the scan lines SL1 to SLn, and at the same time, sequentially applying emission control signals to the emission control lines EL1 to ELn); and measuring the sense voltage VSEN on the data line DL to determine whether the fifth transistor M5 in the pixel PX is defective.

[0141] Figure 7A andFigure 7B is a waveform diagram showing signals measured in a pixel PX according to an exemplary embodiment. Figure 2 Figure 8 is a diagram for describing operations of the pixel PX in response to Figure 7A the signal. Figure 7A , Figure 7B and Figure 8 show a test method for determining whether a sixth transistor M6 provided in the pixel PX is defective. The test method to be described with reference to Figure 7A , Figure 7B and Figure 8 can be executed after (or before) the test operations to be described with reference to Figure 3 , Figure 4 , Figure 5 and Figure 6 .

[0142] With reference to Figure 1A , Figure 7A and Figure 8 , at a reference time point T0, the test of the display panel 100 can be started.

[0143] A first power supply voltage VDD can be applied to a first power line PL1. A second power supply voltage VSS can be applied to a second power line PL2. The second power supply voltage VSS can have a voltage level lower than that of the first power supply voltage VDD.

[0144] In addition, a test voltage VTEST having a turn-on voltage level can be applied to an initialization power line PL3. In other words, an initialization voltage VINT having a voltage level the same as that of the test voltage VTEST (i.e., the turn-on voltage level) can be measured.

[0145] Thereafter, a start signal (or a scan start signal) having a turn-on voltage level and a emission start signal having a turn-on voltage level can be simultaneously applied to the scan driver 400 to be described with reference to Figure 1A . In response thereto, the scan driver 400 can sequentially output scan signals having a turn-on voltage level to scan lines SL1 to SLn, and can also sequentially output emission control signals having a turn-on voltage level to emission control lines EL1 to ELn. In addition, gate signals having a turn-on voltage level can be sequentially provided to test lines TL1 to TLn. For example, since the test lines TL1 to TLn are respectively connected to the scan lines SL1 to SLn, the gate signals can be sequentially provided to the test lines TL1 to TLn. Different from this, as shown in Figure 1B and Figure 7B , the gate signals having a turn-on voltage level (e.g., Figure 1B "GT" in Figure 7Bare commonly provided to the test lines TL1 to TLn.

[0146] In this case, at the first time point T1, the level of the second scan signal GI[N] can change from the cut-off voltage level to the on-voltage level in response to the start signal (or scan start signal). During at least a part of the first period P1, the level of the second scan signal GI[N] can be maintained at the on-voltage level.

[0147] During the first period P1, the level of each of the first scan signal GW[N] and the third scan signal GB[N] can be maintained at the cut-off voltage level, and the level of the emission control signal EM[N] can also be maintained at the cut-off voltage level.

[0148] In this case, as Figure 8 shown, the fourth transistor M4 can be turned on in response to the second scan signal GI[N] having the on-voltage level, and the test voltage VTEST (i.e., the voltage having the on-voltage level) applied to the initialization power line PL3 can be transmitted to the third node N3. The storage capacitor CST can store the test voltage VTEST. The first transistor M1 can be turned on in response to the test voltage VTEST having the on-voltage level.

[0149] The second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can remain off. The eighth transistor M8 can be in the off state, but is not limited thereto. For example, the eighth transistor M8 can remain on.

[0150] Referring again to Figure 7A , at the second time point T2, the first scan signal GW[N] can transition from the cut-off voltage level to the on-voltage level. During the second period P2, the first scan signal GW[N] can be maintained at the on-voltage level. Similarly, the emission control signal EM[N] can transition from the cut-off voltage level to the on-voltage level. During the second period P2, the emission control signal EM[N] can be maintained at the on-voltage level. In addition, the gate signal GT[N] can transition from the cut-off voltage level to the on-voltage level. During the second period P2, the gate signal GT[N] can be maintained at the on-voltage level.

[0151] The level of the second scan signal GI[N] can change to the cut-off voltage level before the second time point T2 and be maintained at the cut-off voltage level during the second period P2.

[0152] In this case, as Figure 8As shown, the second transistor M2 and the third transistor M3 can be turned on in response to a first scan signal GW[N] having a turn-on voltage level, and the fifth transistor M5 and the sixth transistor M6 can be turned on in response to an emission control signal EM[N] having a turn-on voltage level. The first power line PL1 can be electrically connected to the second power line PL2 through the fifth transistor M5, the first transistor M1, the sixth transistor M6, and the eighth transistor M8.

[0153] A current flow path can be formed between the first power line PL1 and the second power line PL2. The voltage can be distributed according to the respective on-resistances of the fifth transistor M5, the first transistor M1, the sixth transistor M6, and the eighth transistor M8.

[0154] The node voltage of the first node N1 can be proportional to the on-resistance of each of the first transistor M1, the sixth transistor M6, and the eighth transistor M8, and can be inversely proportional to the on-resistance of the fifth transistor M5.

[0155] The first node N1 can be electrically connected to the data line DL through the turned-on second transistor M2. The node voltage of the first node N1 can be provided to the data line DL, and a sense voltage VSEN corresponding to the node voltage of the first node N1 can be measured.

[0156] Thereafter, in this test method, it can be determined whether the pixel PX (or the pixel circuit) is defective based on the voltage level of the sense voltage VSEN.

[0157] For example, this test method can include: comparing the sense voltage VSEN with a preset reference voltage VREF; and when the sense voltage VSEN is equal to or less than the reference voltage VREF, determining that a failure has occurred on the sixth transistor M6.

[0158] As referred to Figure 7A 、 Figure 7B and Figure 8 As described, the method for testing the display panel 100 can include: with a test voltage VTEST having a cut-off voltage level applied to the initialization power line PL3, applying a start signal (or a scan start signal) having a turn-on voltage level and an emission start signal having a turn-on voltage level to the scan driver 400, and simultaneously providing a gate signal GT[N] having a turn-on voltage level to the test line TL (i.e., the eighth transistor M8); and then measuring the sense voltage VSEN on the data line DL to determine whether the sixth transistor M6 in the pixel PX is defective.

[0159] Although Figure 7A it is shown that the waveform of the gate signal GT[N] is the same as the waveform of the first scan signal GW[N], the present disclosure is not limited thereto. For example, as Figure 7BAs shown, during the period in which it is determined whether the sixth transistor M6 is defective, the gate signal GT[N] can be maintained at the on voltage level. In addition, the gate signal GT[N] (i.e., Figure 1B "GT" in Figure 1B ) can be commonly applied to the test lines TL1 to TLn shown in

[0160] Figure 9A and Figure 9B are waveform diagrams showing signals measured in the pixel PX according to an exemplary embodiment in Figure 2 . Figure 10 is a diagram for describing the operation of the pixel PX in response to the signal in Figure 9A . Figure 9A , Figure 9B and Figure 10 show a test method for determining whether the seventh transistor M7 provided in the pixel PX is defective. The test method described with reference to Figure 9A , Figure 9B and Figure 10 can be performed after (or before) the test operations described with reference to Figure 3 , Figure 4 , Figure 5 and Figure 6 .

[0161] With reference to Figure 1A , Figure 9A and Figure 10 , at the reference time point T0, the test of the display panel 100 can be started.

[0162] A first power supply voltage VDD can be applied to the first power line PL1. A test voltage VTEST having an on voltage level can be applied to the second power line PL2. The initialization power line PL3 can be kept floating (in other words, no separate voltage is applied thereto).

[0163] Thereafter, a start signal (or a scan start signal) having an on voltage level can be applied to the scan driver 400 described with reference to Figure 1A . Here, the start signal can include two pulses (for example, two pulses generated at intervals of one horizontal period).

[0164] In response thereto, the scan driver 400 can sequentially output scan signals each having two pulses with an on voltage level to the scan lines SL1 to SLn. As described with reference to Figure 7A , gate signals having an on voltage level can be sequentially provided to the test lines TL1 to TLn. As shown in Figure 1B and Figure 9B , gate signals having an on voltage level can be simultaneously provided to the test lines TL1 to TLn (i.e., Figure 1B"GT" in or Figure 9B "GT[N]" in).

[0165] An emission start signal having a cut-off voltage level may be provided to the scan driver 400.

[0166] In this case, at the first time point T1, the level of the second scan signal GI[N] may change from the cut-off voltage level to the on-voltage level in response to the start signal (or scan start signal). During at least a part of the first period P1, the level of the second scan signal GI[N] may be maintained at the on-voltage level. Similarly, the level of the third scan signal GB[N] may change from the cut-off voltage level to the on-voltage level. During at least a part of the first period P1, the level of the third scan signal GB[N] may be maintained at the on-voltage level. In addition, the level of the gate signal GT[N] may change from the cut-off voltage level to the on-voltage level. During at least a part of the first period P1, the gate signal GT[N] may be maintained at the on-voltage level.

[0167] During the first period P1, the first scan signal GW[N] may be maintained at the cut-off voltage level.

[0168] In this case, as Figure 10 shown, the fourth transistor M4 may turn on in response to the second scan signal GI[N] having an on-voltage level. The seventh transistor M7 may turn on in response to the third scan signal GB[N] having an on-voltage level. The eighth transistor M8 may remain on in response to the gate signal GT[N] having an on-voltage level. In this case, the test voltage VTEST applied to the second power line PL2 (i.e., a voltage having an on-voltage level) may be transmitted to the third node N3. The storage capacitor CST may store the test voltage VTEST. The first transistor M1 may turn on in response to the test voltage VTEST having an on-voltage level.

[0169] The second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 may remain off.

[0170] Referring again to Figure 9B , at the second time point T2, the first scan signal GW[N] may make a transition from the cut-off voltage level to the on-voltage level. During the second period P2, the first scan signal GW[N] may be maintained at the on-voltage level.

[0171] The level of each of the second scan signal GI[N] and the third scan signal GB[N] may change to the cut-off voltage level before the second time point T2 and be maintained at the cut-off voltage level during the second period P2. As Figure 9AAs shown, before the second time point T2, the gate signal GT[N] can transition from an on voltage level to an off voltage level, but the present disclosure is not limited thereto. For example, as Figure 1B and Figure 9B shown, the gate signal commonly applied to the test lines TL1 to TLn (i.e., Figure 1B "GT" in Figure 9B or

[0172] "GT[N]" in Figure 10 can be maintained at the on voltage level.

[0173] In this case, as

[0174] shown, the second transistor M2 and the third transistor M3 can be turned on in response to the first scan signal GW[N] having an on voltage level, and the third node N3 can be electrically connected to the data line DL through the first transistor M1 to the third transistor M3. Therefore, the test voltage VTEST can be provided to the data line DL, and the sense voltage VSEN corresponding to the test voltage VTEST can be measured.

[0175] Thereafter, in this test method, it can be determined whether the pixel PX (or the pixel circuit) is defective based on the voltage level of the sense voltage VSEN. Figure 9A For example, this test method can include: comparing the sense voltage VSEN with a preset reference voltage VREF; and when the sense voltage VSEN is equal to or less than the reference voltage VREF, determining that a failure has occurred on the seventh transistor M7. Figure 9B and Figure 10 As described with reference to

[0176] Figure 11A and Figure 11B , the method for testing the display panel 100 can include: applying a test voltage VTEST having an on voltage level to the second power line PL2 and turning on the eighth transistor M8, and then applying a scan start signal having two pulses with an on voltage level (and an emission start signal with an off voltage level) to the scan driver 400; and measuring the sense voltage VSEN on the data line DL to determine whether the seventh transistor M7 in the pixel PX is defective. Figure 2 Figures Figure 11A and Figure 11B are diagrams showing examples of the pixel PX of Figure 2 .

[0177] Referring to Figure 11A, the base layer (or substrate) SUB may include a pixel region PXA. The pixel region PXA may include an emission region A_LD, a first circuit region A_PXC1, and a second circuit region A_PXC2. The pixel region PXA may further include a peripheral region A_PER.

[0178] The emission region A_LD, the first circuit region A_PXC1, the second circuit region A_PXC2, and the peripheral region A_PER may be separated from each other by a first reference line L_REF1 extending in a first direction DR1 and a second reference line L_REF2 extending in a second direction DR2. The first reference line L_REF1 may be parallel to the data line DL, and the second reference line L_REF2 may be parallel to the scan line SL.

[0179] Relative to the emission region A_LD, the first circuit region A_PXC1 may be disposed in the first direction DR1, and the second circuit region A_PXC2 may be disposed in the second direction DR2. The peripheral region A_PER may be a region in the pixel region PXA other than the emission region A_LD, the first circuit region A_PXC1, and the second circuit region A_PXC2, and may be disposed adjacent to the first circuit region A_PXC1 and the second circuit region A_PXC2.

[0180] Referring to Figure 2 the light-emitting element LD described may be disposed in the emission region A_LD of the base layer SUB.

[0181] A pixel circuit PXC1 may be disposed in the first circuit region A_PXC1 of the base layer SUB. Here, the pixel circuit PXC1 may supply a driving current to the light-emitting element LD and include at least one transistor connected to the scan line SL and the data line DL. For example, the pixel circuit PXC1 may include the first transistor M1 to the seventh transistor M7 referred to Figure 2 in the description, and a storage capacitor (CST; see Figure 2 ).

[0182] A test circuit PXC2 may be disposed in the second circuit region A_PXC2 of the base layer SUB. The test circuit PXC2 may include an auxiliary transistor connected in parallel to the light-emitting element LD. For example, the test circuit PXC2 may include the eighth transistor M8 referred to Figure 2 in the description.

[0183] In an embodiment, the light-emitting element LD may be manufactured separately from the pixel circuit PXC1 and the test circuit PXC2. For example, the light-emitting element LD may be manufactured in the form of a chip and then bonded or mounted on the base layer SUB on which the pixel circuit PXC1 and the test circuit PXC2 are formed.

[0184] During the process of bonding the light-emitting element LD to the base layer SUB, high temperature and / or high pressure may be generated, and the transistors in the pixel circuit PXC1 may be damaged by the high temperature and / or high pressure. In an exemplary embodiment, since the pixel circuit PXC1 is provided in the first circuit region A_PXC1 separated from the emission region A_LD, the pixel circuit PXC1 can be prevented or suppressed from being damaged during the process of bonding the light-emitting element LD.

[0185] Before mounting the light-emitting element LD on the base layer SUB, since the pixel circuit PXC1 and the test circuit PXC2 have been formed on the base layer SUB, the base layer SUB (e.g., the electrode to which the light-emitting element LD is to be bonded) may remain exposed to the outside. In addition, the operation of mounting the light-emitting element LD can be performed using equipment different from that used for forming the pixel circuit PXC1 and the test circuit PXC2. Therefore, it is necessary to transfer the base layer SUB on which the pixel circuit PXC1 and the test circuit PXC2 are formed. As a result, the electrode may be exposed to the outside for a long time, and static electricity is likely to be generated on the electrode. In the case where static electricity is absorbed, the eighth transistor M8 connected between the electrode and the second power line (PL2; see Figure 2 ) may be damaged. Since the test circuit PXC2 is provided in the second circuit region A_PXC2 separated from the first circuit region A_PXC1, the damage to the eighth transistor M8 can be prevented or suppressed from affecting the pixel circuit PXC1 (e.g., causing damage to the pixel circuit PXC1), so that the pixel circuit PXC1 can be protected from static electricity.

[0186] In an exemplary embodiment, the test circuit PXC2 can be connected to the pixel circuit PXC1 through the first bridging pattern CP1. The first bridging pattern CP1 can extend from the first circuit region A_PXC1 to the second circuit region A_PXC2 via the peripheral region A_PER. However, this is only for illustrative purposes, and the present disclosure is not limited thereto.

[0187] Referring to Figure 11B , the base layer SUB may include a pixel region PXA. The pixel region PXA may include an emission region A_LD, a first circuit region A_PXC1, and a second circuit region A_PXC2.

[0188] The emission region A_LD, the first circuit region A_PXC1, and the second circuit region A_PXC2 may be separated from each other by a first reference line L_REF1_1 and a second reference line L_REF2_1 that extend in the second direction DR2 and are parallel to each other.

[0189] The first circuit region A_PXC1 may be disposed at an upper position with respect to the emission region A_LD, and the second circuit region A_PXC2 may be disposed at a lower position. In other words, the emission region A_LD may be disposed between the first circuit region A_PXC1 and the second circuit region A_PXC2. The first circuit region A_PXC1 and the second circuit region A_PXC2 may be separated from each other by the emission region A_LD.

[0190] Figure 12 is an example layout showing Figure 11A of the pixel PX. Figure 12 shows the pixel PX, focusing on the pixel circuit (PXC1; see Figure 11A ) and the test circuit (PXC2; see Figure 11A ).

[0191] Referring to Figure 12 , the pixel PX may include a semiconductor layer ACT, a first conductive layer GAT1, a second conductive layer GAT2, a third conductive layer SD1, a fourth conductive layer SD2, and a fifth conductive layer (or electrode layer) SD3. The semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer SD1, the fourth conductive layer SD2, and the fifth conductive layer (or electrode layer) SD3 may be formed on different corresponding layers through different corresponding processes. This will be described later with reference to Figure 15 .

[0192] The semiconductor layer ACT may be an active layer forming the channels of the transistors M1 to M8. The semiconductor layer ACT may include a source region and a drain region that are in contact with a first transistor electrode (e.g., source electrode) and a second transistor electrode (e.g., drain electrode) of each of the transistors M1 to M8, respectively. The region between the source region and the drain region may be a channel region.

[0193] In an exemplary embodiment, the semiconductor layer ACT may include a silicon semiconductor (or polycrystalline silicon semiconductor). The channel region formed of a semiconductor pattern may be an undoped semiconductor pattern, which is an intrinsic semiconductor. Each of the source region and the drain region may be a semiconductor pattern doped with an impurity. A P-type impurity may be used as the impurity, but the present disclosure is not limited thereto.

[0194] The semiconductor layer ACT may include a first semiconductor pattern ACT1 and a second semiconductor pattern ACT2. The semiconductor layer ACT will be described in detail with reference to Figure 13 .

[0195] Figure 13 is a plan view showing Figure 12 an example of the semiconductor layer ACT included in the pixel PX.

[0196] Referring toFigure 13 The first semiconductor pattern ACT1 and the second semiconductor pattern ACT2 may be disposed at positions spaced apart from each other. The first semiconductor pattern ACT1 may be disposed in the first circuit region A_PXC1, and the second semiconductor pattern ACT2 may be disposed in the second circuit region A_PXC2.

[0197] The first semiconductor pattern ACT1 may include a first vertical portion (or first sub-semiconductor pattern) ACT_S1, a horizontal portion (or second sub-semiconductor pattern) ACT_S2, a second vertical portion (or third sub-semiconductor pattern) ACT_S3, and a curved portion ACT_S4. The first vertical portion ACT_S1, the horizontal portion ACT_S2, the second vertical portion ACT_S3, and the curved portion ACT_S4 may be joined to each other and integrally formed with each other.

[0198] The first vertical portion ACT_S1 may extend in the first direction DR1 and be disposed adjacent to one side of the first circuit region A_PXC1. The first vertical portion ACT_S1 may form the channels of the second transistor M2 and the fifth transistor M5. As Figure 13 shown, with respect to the horizontal portion ACT_S2, the upper portion of the first vertical portion ACT_S1 may form the channel of the second transistor M2, and the lower portion of the first vertical portion ACT_S1 may form the channel of the fifth transistor M5.

[0199] The horizontal portion ACT_S2 may extend from the middle portion of the first vertical portion ACT_S1 in the second direction DR2 and have a curved shape. The horizontal portion ACT_S2 may form the channel of the first transistor M1. Due to the curved shape of the horizontal portion ACT_S2, the channel capacity of the first transistor M1 can be increased.

[0200] The second vertical portion ACT_S3 may extend in the first direction DR1 and be disposed adjacent to the other side of the first circuit region A_PXC1. With respect to the horizontal portion ACT_S2, the upper portion of the second vertical portion ACT_S3 may form the channel of the third transistor M3, and the lower portion of the second vertical portion ACT_S3 may form the channels of the sixth transistor M6 and the seventh transistor M7.

[0201] The curved portion ACT_S4 may extend from the upper end of the second vertical portion ACT_S3, have a curved shape, and form the channel of the fourth transistor M4.

[0202] In an exemplary embodiment, the third transistor M3 may include a first sub-transistor M3-1 and a second sub-transistor M3-2. The first semiconductor pattern ACT1 may include the channel regions of the first sub-transistor M3-1 and the second sub-transistor M3-2. In other words, the two channel regions are connected in series with each other. Similarly, the fourth transistor M4 may include a first sub-transistor M4-1 and a second sub-transistor M4-2. The first semiconductor pattern ACT1 may include the channel regions of the first sub-transistor M4-1 and the second sub-transistor M4-2. In other words, the two channel regions are connected in series with each other. The third transistor M3 and the fourth transistor M4, each implemented as a double-gate transistor, may prevent or reduce leakage of current (e.g., the driving current flowing from the first transistor M1 to the sixth transistor M6).

[0203] The second semiconductor pattern ACT2 may extend in the first direction DR1 and form the channel of the eighth transistor M8. The eighth transistor M8 may include a first sub-transistor M8-1 and a second sub-transistor M8-2. The second semiconductor pattern ACT2 may include the channel regions of the first sub-transistor M8-1 and the second sub-transistor M8-2. In other words, the two channel regions are connected in series with each other. The eighth transistor M8, implemented as a double-gate transistor, may prevent or reduce leakage of current (e.g., the driving current supplied to the light-emitting element (LD; see Figure 12 ).

[0204] Referring again to Figure 12 , the first conductive layer GAT1 may include a first scan line SL1, a second scan line SL2, a third scan line SL3, an emission control line EL, a test line TL, and a first electrode (or first capacitor electrode) ET1_C.

[0205] The second scan line SL2 may extend in the second direction DR2 and be disposed in the uppermost portion of the pixel region PXA. The second scan line SL2 may overlap with the first semiconductor pattern ACT1 (or the bent portion ACT_S4 of the first semiconductor pattern ACT1; see Figure 13 ) and may form the gate electrode of the fourth transistor M4 or be connected to the gate electrode of the fourth transistor M4. The second scan line SL2 may be substantially the same as the second scan line SLi-1 described with reference to Figure 2 .

[0206] The first scan line SL1 may extend in the second direction DR2 and be disposed between the second scan line SL2 and the first electrode ET1_C. The first scan line SL1 may be associated with the first vertical portion ACT_S1 of the first semiconductor pattern ACT1 (see Figure 13) overlap and may form the gate electrode of the second transistor M2 or be connected to the gate electrode of the second transistor M2. In addition, the first scan line SL1 may overlap with the second vertical portion ACT_S3 of the first semiconductor pattern ACT1 (see Figure 13 ) overlap and may form the gate electrode of the third transistor M3 or be connected to the gate electrode of the third transistor M3. The first scan line SL1 may be substantially the same as the first scan line SLi described with reference to Figure 2 .

[0207] The first electrode ET1_C may have a predetermined surface area, be disposed in an approximate central portion of the first circuit region A_PXC1, and overlap with the horizontal portion ACT_S2 of the first semiconductor pattern ACT1. The first electrode ET1_C may form the gate electrode of the first transistor M1.

[0208] The emission control line EL may extend in the second direction DR2 and be disposed on the lower side of the first electrode ET1_C. The emission control line EL may overlap with each of the first vertical portion ACT_S1 and the second vertical portion ACT_S3 of the first semiconductor pattern ACT1, and may form each of the gate electrodes of the fifth transistor M5 and the sixth transistor M6 or be connected to each of the gate electrodes of the fifth transistor M5 and the sixth transistor M6.

[0209] The third scan line SL3 may extend in the second direction DR2 and be disposed in the lowermost portion of the first circuit region A_PXC1. The third scan line SL3 may overlap with the second vertical portion ACT_S3 of the first semiconductor pattern ACT1, and may form the gate electrode of the seventh transistor M7 or be connected to the gate electrode of the seventh transistor M7.

[0210] The test line TL may be disposed in the second circuit region A_PXC2 and overlap with the second semiconductor pattern ACT2, and may form the gate electrode of the eighth transistor M8 or be connected to the gate electrode of the eighth transistor M8.

[0211] The first conductive layer GAT1 may include one or more metals selected from the following: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer GAT1 may have a single-layer or multi-layer structure. For example, the first conductive layer GAT1 may have a single-layer structure including molybdenum (Mo).

[0212] The second conductive layer GAT2 may include the third power line PL3, the second electrode (or the second capacitor electrode) ET2_C, and the protection pattern BRP0.

[0213] The third power line PL3 may extend in the second direction DR2 and is arranged to be adjacent to each of the upper side and the lower side of the first circuit region A_PXC1.

[0214] In a plan view, the protection pattern BRP0 may be arranged between the second scan line SL2 and the first scan line SL1 and may partially overlap with the second vertical portion ACT_S3 of the first semiconductor pattern ACT1.

[0215] The second electrode ET2_C may overlap with the first electrode ET1_C and together with the first electrode ET1_C form the reference Figure 2 described storage capacitor CST. The surface area of the second electrode ET2_C may be larger than the surface area of the first electrode ET1_C such that the second electrode ET2_C may cover the first electrode ET1_C.

[0216] The second conductive layer GAT2 may include one or more metals selected from the following: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer GAT2 may have a single-layer or multi-layer structure. For example, the second conductive layer GAT2 may have a single-layer structure including molybdenum (Mo).

[0217] The third conductive layer SD1 may include a data line DL, a first sub-power line PL_S1, and first to fifth conductive patterns BRP1 to BRP5 (or first to fifth connection patterns BRP1 to BRP5).

[0218] The data line DL may extend in the first direction DR1 and overlap with the upper end of the first vertical portion ACT_S1 of the first semiconductor pattern ACT1. The data line DL may contact the upper end of the first vertical portion ACT_S1 of the first semiconductor pattern ACT1 through a contact hole CNT1 exposing the upper end of the first vertical portion ACT_S1 of the first semiconductor pattern ACT1 and may form the first electrode of the second transistor M2 or be coupled to the first electrode of the second transistor M2.

[0219] The first sub-power line PL_S1 may extend in the first direction DR1 and is arranged between the data line DL and the first electrode ET1_C in a plan view. The first sub-power line PL_S1 may be coupled to the first power line PL1 described later herein. The first power supply voltage (VDD; see Figure 2 ) may be applied to the first sub-power line PL_S1. The first sub-power line PL_S1 may overlap with the second electrode ET2_C and is coupled to the second electrode ET2_C through a contact hole exposing the second electrode ET2_C.

[0220] The first conductive pattern BRP1 may overlap with the first end of the bent portion ACT_S4 of the first electrode ET1_C and the first semiconductor pattern ACT1. The first conductive pattern BRP1 may contact the first end of the bent portion ACT_S4 of the first semiconductor pattern ACT1 through a contact hole exposing the first end of the bent portion ACT_S4 of the first semiconductor pattern ACT1, and may be coupled to or form the first electrodes of the third transistor M3 (or the first sub-transistor M3-1 of the third transistor M3) and the fourth transistor M4 (or the first sub-transistor M4-1 of the fourth transistor M4).

[0221] The second conductive pattern BRP2 may overlap with the third power line PL3 and the second end of the bent portion ACT_S4 of the first semiconductor pattern ACT1. The second conductive pattern BRP2 may be coupled to the third power line PL3 through a contact hole exposing the third power line PL3. In addition, the second conductive pattern BRP2 may contact the second end of the bent portion ACT_S4 of the first semiconductor pattern ACT1 through a contact hole exposing the second end of the bent portion ACT_S4 of the first semiconductor pattern ACT1, and may be coupled to or form the second electrode of the fourth transistor M4 (or the second sub-transistor M4-2 of the fourth transistor M4). The second conductive pattern BRP2 may couple the fourth transistor M4 and the third power line PL3 to each other.

[0222] The third conductive pattern BRP3 may overlap with the second vertical portion ACT_S3 of the first semiconductor pattern ACT1 and contact the second vertical portion ACT_S3 of the first semiconductor pattern ACT1 through a contact hole exposing a part of the second vertical portion ACT_S3 of the first semiconductor pattern ACT1. The third conductive pattern BRP3 may form or be coupled to each of the second electrodes of the sixth transistor M6 and the first electrodes of the seventh transistor M7.

[0223] The fourth conductive pattern BRP4 may overlap with the first end of the second semiconductor pattern ACT2 and contact the first end of the second semiconductor pattern ACT2 through a contact hole exposing the first end of the second semiconductor pattern ACT2. The fourth conductive pattern BRP4 may be coupled to or form the first electrode of the eighth transistor M8.

[0224] Similarly, the fifth conductive pattern BRP5 may overlap with the second end of the second semiconductor pattern ACT2 and contact the second end of the second semiconductor pattern ACT2 through a contact hole exposing the second end of the second semiconductor pattern ACT2. The fifth conductive pattern BRP5 may be coupled to the second electrode of the eighth transistor M8 or form the second electrode of the eighth transistor M8.

[0225] The third conductive layer SD1 may include one or more metals selected from the following: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer SD1 may have a single-layer or multi-layer structure. For example, the third conductive layer SD1 may have a multi-layer structure of Ti / Al / Ti.

[0226] The fourth conductive layer SD2 may include a first bridging pattern (or connection line) CP1, a second bridging pattern CP2, a first emission capacitor electrode E1_CLD, and a first power line PL1.

[0227] The first bridging pattern CP1 may overlap with the third conductive pattern BRP3 and be coupled to the third conductive pattern BRP3 through a contact hole exposing the third conductive pattern BRP3.

[0228] A part of the first bridging pattern CP1 may extend in the second direction DR2, and another part thereof may extend in the first direction DR1. The first bridging pattern CP1 may extend across the peripheral area A_PER and overlap with the fourth conductive pattern BRP4. The first bridging pattern CP1 may be coupled to the fourth conductive pattern BRP4 through a contact hole exposing the fourth conductive pattern BRP4. The first bridging pattern CP1 may extend in the first direction DR1 and be coupled to the first emission capacitor electrode E1_CLD. The first bridging pattern CP1 may include a portion having a relatively large width (or line width) at a position before the point where the first bridging pattern CP1 is coupled to the first emission capacitor electrode E1_CLD, and may be coupled to the anode electrode AE, which will be described later in this document, through this portion having a large width.

[0229] The first emission capacitor electrode E1_CLD may have a predetermined surface area and be integrally formed with the first bridging pattern CP1. For example, the first bridging pattern CP1 may have an increased line width at a portion where it overlaps with the cathode electrode CE (or the second power line PL2), and the first emission capacitor electrode E1_CLD may be formed.

[0230] The second bridging pattern CP2 may overlap with the fifth conductive pattern BRP5 and be coupled to the fifth conductive pattern BRP5 through a contact hole CNT2 exposing the fifth conductive pattern BRP5.

[0231] The first power line PL1 may extend in the second direction DR2 and cover most of the first circuit region A_PXC1 and the peripheral region A_PER. The first power line PL1 may overlap with the first sub-power line PL_S1 and be coupled to the first sub-power line PL_S1 through a contact hole exposing the first sub-power line PL_S1. The first power line PL1 may be coupled to the first sub-power line PL_S1 extending in the first direction DR1 to form an overall mesh structure. The first power line PL1 may reduce the first power supply voltage (VDD; see Figure 2 )’s decline.

[0232] The fourth conductive layer SD2 may include one or more metals selected from the following: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The fourth conductive layer SD2 may have a single layer or a multi-layer structure. For example, the fourth conductive layer SD2 may have a multi-layer structure of Ti / Al / Ti.

[0233] The fifth conductive layer SD3 may include an anode electrode AE (or a first pixel electrode), a cathode electrode CE (or a second pixel electrode), and a second power line PL2.

[0234] Will refer to Figure 14 The fifth conductive layer SD3 is described in detail.

[0235] Figure 14 is a diagram showing a method according to an exemplary embodiment Figure 12 A plan view of a conductive layer included in a pixel PX. Figure 14 , the fourth conductive layer SD2, the fifth conductive layer SD3 and the light emitting element LD are shown.

[0236] The anode electrode AE may overlap a portion (i.e., a portion with an increased width) of the first bridge pattern CP1 in the emission region A_LD and be coupled to the first bridge pattern CP1 through a contact hole (or through hole) CNT3 exposing the portion of the first bridge pattern CP1. In this case, the anode electrode AE may be coupled to the first electrode of the sixth transistor M6, the first electrode of the seventh transistor M7, and the first electrode of the eighth transistor M8 through the first bridge pattern CP1.

[0237] The cathode electrode CE may be disposed at a position spaced apart from the anode electrode AE in the emission region A_LD and overlap the first emission capacitor electrode E1_CLD. The cathode electrode CE may form a light emitting element (LD; see Figure 2)'s second emission capacitor electrode, and together with the first emission capacitor electrode E1_CLD forms an emission capacitor (CLD; see Figure 2 ).

[0238] In addition, the cathode electrode CE can extend in the second direction DR2 and overlap with the second bridging pattern CP2 in the second circuit region A_PXC2. The cathode electrode CE can be connected to the second bridging pattern CP2 through a contact hole CNT4 that exposes the second bridging pattern CP2. In this case, the cathode electrode CE can be connected to the second electrode of the eighth transistor M8 through the second bridging pattern CP2.

[0239] In addition to the emission region A_LD, the second power line PL2 can cover the first circuit region A_PXC1, the second circuit region A_PXC2, and the peripheral region A_PER. The second power line PL2 can be formed integrally with the cathode electrode CE. The second power line PL2 can include an opening OP located in the emission region A_LD. The anode electrode AE can be disposed in the opening OP and spaced apart from the second power line PL2 by a predetermined distance. Although it will be described below, the second power line PL2 can be disposed in the entire region of the base layer (SUB; see Figure 11A ) except for the opening OP in the emission region A_LD.

[0240] The light-emitting element LD can be disposed in the emission region A_LD. A part of the light-emitting element LD can be connected to the anode electrode AE, and another part of the light-emitting element LD can be connected to the cathode electrode CE.

[0241] The fifth conductive layer SD3 can include one or more metals selected from the following: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fifth conductive layer SD3 can have a single-layer or multi-layer structure. For example, the fifth conductive layer SD3 can have a multi-layer structure of Ti / Al / Ti.

[0242] Figure 15 is a cross-sectional view showing an example of the pixel PX taken along the Figure 12 section lines I-I' and II-II'.

[0243] Refer to Figure 12 , Figure 13 , Figure 14 and Figure 15, the pixel PX may include a pixel circuit layer PCL and a light-emitting element layer LDL stacked on a base layer SUB. The pixel circuit layer PCL may include a buffer layer BFL, a semiconductor layer ACT, a first insulating layer GI1 (or a first gate insulating layer), a first conductive layer GAT1, a second insulating layer GI2 (or a second gate insulating layer), a second conductive layer GAT2, a third insulating layer ILD (or an intermediate insulating layer), a third conductive layer SD1, a first via layer VIA1 (or a fourth insulating layer), a fourth conductive layer SD2, and a second via layer VIA2 (or a fifth insulating layer). The light-emitting element layer LDL may include a fifth conductive layer SD3, a third via layer VIA3 (or a sixth insulating layer), and a light-emitting element LD.

[0244] The buffer layer BFL, the semiconductor layer ACT, the first insulating layer GI1, the first conductive layer GAT1, the second insulating layer GI2, the second conductive layer GAT2, the third insulating layer ILD, the third conductive layer SD1, the first via layer VIA1, the fourth conductive layer SD2, the second via layer VIA2, the fifth conductive layer SD3, and the third via layer VIA3 may be sequentially stacked on the base layer SUB. Since the semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer SD1, the fourth conductive layer SD2, and the fifth conductive layer SD3 have been described with reference to Figure 12 , Figure 13 and Figure 14 , the repeated description thereof will be omitted.

[0245] The buffer layer BFL may be disposed on the entire surface of the base layer SUB. The buffer layer BFL may prevent or inhibit the diffusion of impurity ions, prevent or inhibit the penetration of water or external air, and perform a surface flattening function. The buffer layer BFL may include an inorganic insulating material. For example, the buffer layer BFL may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON). For example, the buffer layer BFL may be a bilayer structure including a silicon oxide layer having an approximate thickness and a silicon nitride layer having an approximate thickness. Depending on the type of the base layer SUB or the processing conditions, the buffer layer BFL may be omitted.

[0246] The semiconductor layer ACT may be disposed on the buffer layer BFL. The semiconductor layer ACT may be disposed between the buffer layer BFL and the first insulating layer GI1. The semiconductor layer ACT may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. The semiconductor layer ACT may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. For example, the semiconductor layer ACT may include a polysilicon layer having a thickness in the approximate to range. The channel region of the semiconductor layer ACT may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer ACT may be a semiconductor pattern doped with a predetermined impurity.

[0247] As described with reference to Figure 12 and Figure 13 , the semiconductor layer ACT may include a first semiconductor pattern ACT1 disposed in the first circuit region A_PXC1 and a second semiconductor pattern ACT2 disposed in the second circuit region A_PXC2. The first semiconductor pattern ACT1 may include the channel regions of each of the sixth transistor M6 and the seventh transistor M7. The second semiconductor pattern ACT2 may include the channel region of the eighth transistor M8 (or the first sub-transistor M8-1 and the second sub-transistor M8-2 of the eighth transistor M8).

[0248] The first insulating layer GI1 may be disposed on the semiconductor layer ACT and the buffer layer BFL (or the base layer SUB). The first insulating layer GI1 may be disposed on substantially the entire surface of the base layer SUB. The first insulating layer GI1 may be a gate insulating layer having a gate insulating function.

[0249] The first insulating layer GI1 may include an inorganic insulating material such as a silicon compound or a metal oxide. For example, the first insulating layer GI1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. The first insulating layer GI1 may have a single-layer structure or a multi-layer structure including stacked layers formed of different materials. For example, the first insulating layer GI1 may have a single-layer structure having a thickness in the to range and including silicon oxide.

[0250] The first conductive layer GAT1 may be disposed on the first insulating layer GI1. The first conductive layer GAT1 may include an emission control line EL, a third scan line SL3, and a test line TL. The emission control line EL may overlap with the channel region of the sixth transistor M6 and form a gate electrode of the sixth transistor M6. The third scan line SL3 may overlap with the channel region of the seventh transistor M7 and form a gate electrode of the seventh transistor M7. The test line TL may overlap with the channel region of the eighth transistor M8 and form a gate electrode of the eighth transistor M8.

[0251] In addition, in the case where the eighth transistor M8 is implemented as a double-gate transistor, the two gate electrodes may be spaced apart from each other and overlap with the second semiconductor pattern ACT2.

[0252] As described with reference to Figure 12 the first conductive layer GAT1 may have a single-layer structure including molybdenum and have an approximate thickness.

[0253] The second insulating layer GI2 may be disposed on the first insulating layer GI1 and the first conductive layer GAT1. The second insulating layer GI2 may be disposed on the entire surface of the base layer SUB.

[0254] The second insulating layer GI2 may include an inorganic insulating material such as a silicon compound or a metal oxide in a manner similar to that of the first insulating layer GI1. For example, the second insulating layer GI2 may have a single-layer structure having a thickness in the range of to and including silicon nitride.

[0255] The second conductive layer GAT2 may be disposed on the second insulating layer GI2. The second conductive layer GAT2 may include a third power line PL3.

[0256] As described with reference to Figure 12 the second conductive layer GAT2 may have a single-layer structure including molybdenum and have an approximate thickness.

[0257] The third insulating layer ILD may be disposed on the second insulating layer GI2 and the second conductive layer GAT2. The third insulating layer ILD may be disposed on substantially the entire surface of the base layer SUB.

[0258] The third insulating layer ILD may include an inorganic insulating material such as a silicon compound or a metal oxide. For example, the third insulating layer ILD may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. The third insulating layer ILD may have a single-layer structure or a multi-layer structure including stacked layers formed of different materials. For example, the third insulating layer ILD may have a multi-layer structure formed by stacking a silicon nitride layer and a silicon oxide layer, wherein each of the silicon nitride layer and the silicon oxide layer has a thickness of.

[0259] The third conductive layer SD1 may be disposed on the third insulating layer ILD. The third conductive layer SD1 may include a second conductive pattern BRP2 to a fifth conductive pattern BRP5.

[0260] The third conductive pattern BRP3 may be connected to a part of the first semiconductor pattern ACT1 through a contact hole penetrating the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD, and form a first transistor electrode ET1 of each of the sixth transistor M6 and the seventh transistor M7.

[0261] The second conductive pattern BRP2 may be connected to the third power line PL3 through a contact hole penetrating the third insulating layer ILD, connected to a part of the first semiconductor pattern ACT1 through a contact hole penetrating the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD, and form a second transistor electrode ET2 of the seventh transistor M7.

[0262] The fourth conductive pattern BRP4 may be connected to a part of the second semiconductor pattern ACT2 through a contact hole penetrating the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD, and form a first transistor electrode ET1 of the eighth transistor M8.

[0263] Similarly, the fifth conductive pattern BRP5 may be connected to a part of the second semiconductor pattern ACT2 through a contact hole penetrating the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD, and form a second transistor electrode ET2 of the eighth transistor M8.

[0264] As described with reference to Figure 12 the third conductive layer SD1 may have a multi-layer structure including Ti / Al / Ti and have an approximate thickness of.

[0265] The first via layer VIA1 may be disposed on the third insulating layer ILD and the third conductive layer SD1. The first via layer VIA1 may be disposed on substantially the entire surface of the base layer SUB.

[0266] The first via layer VIA1 may include an organic insulating material such as a polyacrylate-based resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester resin, a polyphenylene ether-based resin, a polyphenylene sulfide-based resin, or benzocyclobutene (BCB). The first via layer VIA1 may have a single-layer structure or a multi-layer structure including stacked layers formed of different materials. For example, the first via layer VIA1 may include a polyimide-based resin and have a thickness in the approximate range of to .

[0267] The fourth conductive layer SD2 may be disposed on the first via layer VIA1. The fourth conductive layer SD2 may include a first power line PL1, a first bridging pattern CP1, and a second bridging pattern CP2.

[0268] The first bridging pattern CP1 may extend through the first circuit region A_PXC1, the emission region A_LD, and the second circuit region A_PXC2 and be coupled to each of the third conductive pattern BRP3 and the fourth conductive pattern BRP4 through contact holes passing through the first via layer VIA1.

[0269] The second bridging pattern CP2 may be coupled to the fifth conductive pattern BRP5 through a contact hole of the first via layer VIA1 passing through the second circuit region A_PXC2.

[0270] As illustrated with reference to Figure 12 , the fourth conductive layer SD2 may have a multi-layer structure including Ti / Al / Ti and have a thickness of approximately .

[0271] The second via layer VIA2 may be disposed on the first via layer VIA1 and the fourth conductive layer SD2. The second via layer VIA2 may be disposed on substantially the entire surface of the base layer SUB. The second via layer VIA2 may include a polyimide-based resin in a manner similar to that of the first via layer VIA1 and have a thickness of approximately .

[0272] The light-emitting element layer LDL may be disposed on the second via layer VIA2. The light-emitting element layer LDL may include a fifth conductive layer SD3, a third via layer VIA3 (or pixel defining layer), and a light-emitting element LD.

[0273] The fifth conductive layer SD3 may be disposed on the second via layer VIA2 and include an anode electrode AE and a cathode electrode CE of the light-emitting element LD and a second power line PL2. The anode electrode AE, the cathode electrode CE, and the second power line PL2 may be disposed on the same layer through the same process. In addition, as illustrated with reference to Figure 12 and Figure 14As described, the cathode electrode CE can be integrally formed with the second power line PL2.

[0274] The anode electrode AE can be coupled to the first bridging pattern CP1 through a contact hole (or via hole) passing through the second via layer VIA2 in the emission region A_LD.

[0275] In an embodiment, each of the anode electrode AE and the cathode electrode CE (and the second power line PL2) can have a multilayer structure. For example, each of the anode electrode AE and the cathode electrode CE can include an opaque electrode layer having a multilayer structure in a manner similar to that of the fourth conductive layer SD2, the multilayer structure having a thickness and including Ti / Al / Ti, and each of the anode electrode AE and the cathode electrode CE can further include a transparent electrode layer ITO, the transparent electrode layer ITO having a thickness and disposed on the opaque electrode layer to cover the opaque electrode layer. The transparent electrode layer ITO can cover the anode electrode AE and the cathode electrode CE (and the second power line PL2), thereby preventing or suppressing damage to the anode electrode AE and the cathode electrode CE (and the second power line PL2).

[0276] The cathode electrode CE or the second power line PL2 can partially overlap with the first bridging pattern CP1, such that an emission capacitor (CLD; see Figure 12 ) described with reference to Figure 2 can be formed.

[0277] The third via layer VIA3 can be disposed on the second via layer VIA2, include a polyimide-based resin in a manner similar to that of the first via layer VIA1, and have an approximate thickness.

[0278] The third via layer VIA3 can expose the anode electrode AE and the cathode electrode CE. The third via layer VIA3 can separate adjacent pixels from each other and define a pixel region (or emission region A_LD) on which a light-emitting element (LD; see Figure 14 ) is formed or mounted.

[0279] The light-emitting element LD can be disposed on the anode electrode AE and the cathode electrode CE.

[0280] The light-emitting element LD can be a light-emitting element having a micron size. The light-emitting element LD can include a first semiconductor layer S1, an intermediate layer M, and a second semiconductor layer S2 stacked in sequence. The anode electrode AE can be coupled to the first semiconductor layer S1 of the light-emitting element LD through a first contact electrode CTE1. The cathode electrode CE can be coupled to the second semiconductor layer S2 through a second contact electrode CTE2. The first semiconductor layer S1 can be a P-type semiconductor layer. The second semiconductor layer S2 can be an N-type semiconductor layer. The intermediate layer M can be a region where electrons and holes recombine.

[0281] As shown Figure 15 in, the anode electrode AE and the cathode electrode CE of the light-emitting element LD may be provided in the same layer on the pixel circuit layer PCL. In other words, before the light-emitting element LD is supplied or provided, the anode electrode AE and the cathode electrode CE are formed. Therefore, the test and fault detection operations for the first transistor M1 to the seventh transistor M7 (specifically, the sixth transistor M6 and the seventh transistor M7) can be performed by referring to Figure 2 the eighth transistor M8 described.

[0282] As a reference, in the case of a pixel in which the light-emitting element is provided on the anode electrode AE and the cathode electrode CE is formed on the light-emitting element, after the light-emitting element is provided, some transistors (for example, Figure 2 the sixth transistor M6 and the seventh transistor M7 shown in) to be connected to the cathode electrode CE (and the second power line PL2) can be tested. In this case, since the failure of some transistors may be detected after the light-emitting element is provided, the production cost may increase.

[0283] The display device 10 (or the display panel 100 and the pixel PX) according to an embodiment of the present disclosure may include the anode electrode AE and the cathode electrode CE formed in the same layer, and the eighth transistor M8 electrically connected to the anode electrode AE and the cathode electrode CE. Therefore, before the light-emitting element LD is provided, all tests of the pixel PX (or the pixel circuit included in the pixel circuit layer PCL) can be performed.

[0284] Figure 16A , Figure 16B , Figure 16C and Figure 16D show the layout of the pixel PX included in the Figure 1B display device 10 according to an exemplary embodiment. Figure 16A shows the unit pixel PX_G (i.e., the pixel including sub-pixels) corresponding to the Figure 12 pixel PX. Figure 16B shows Figure 16A the fourth conductive layer SD2 included in. Figure 16C shows Figure 16A the fifth conductive layer SD3 included in.

[0285] Referring to Figure 1B and Figure 16A , the base layer (or substrate) SUB may include the pixel region PXA. The pixel region PXA may include the emission region A_LD, the first circuit region A_PXC1, and the second circuit region A_PXC2. The pixel region PXA may further include the peripheral region A_PER.

[0286] The emission region A_LD, the first circuit region A_PXC1, the second circuit region A_PXC2, and the peripheral region A_PER can be separated from each other by a first reference line L_REF1 extending in a first direction DR1 and a second reference line L_REF2 extending in a second direction DR2. The first reference line L_REF1 can be parallel to the data lines DL1, DL2, and DL3, and the second reference line L_REF2 can be parallel to the scan line SL.

[0287] With respect to the emission region A_LD, the first circuit region A_PXC1 can be disposed in a region adjacent to the emission region A_LD in the first direction DR1, and the second circuit region A_PXC2 can be disposed in a region adjacent to the emission region A_LD in the second direction DR2.

[0288] As Figure 16D shown, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be disposed in the emission region A_LD of the base layer SUB. The first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 (or the first sub-pixel circuit to the third sub-pixel circuit) can be sequentially disposed in the first circuit region A_PXC1 of the base layer SUB along the second direction DR2. The test circuit PXC2 can be disposed in the second circuit region A_PXC2.

[0289] Each of the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 is substantially equivalent to or similar to the pixel circuit PXC1 described with reference to Figure 12 , Figure 13 , Figure 14 and Figure 15 ; thus, the repeated description thereof will be omitted.

[0290] Each of the data lines DL1, DL2, and DL3 can extend in the first direction DR1 and can be substantially equivalent to the data line DL described with reference to Figure 12 . In response to the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3, the data lines DL1, DL2, and DL3 can be repeatedly disposed along the second direction DR2. The first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 can be separated from each other by the data lines DL1, DL2, and DL3.

[0291] With reference to Figure 16A and Figure 16B, the fourth conductive layer SD2 may include a first sub-bridging pattern CP1_1 (or a first sub-connection line), a second sub-bridging pattern CP1_2, a third sub-bridging pattern CP1_3, a first emission capacitor CLD1 (or a first emission capacitor electrode), a second emission capacitor CLD2 (or a second emission capacitor electrode), a third emission capacitor CLD3 (or a third emission capacitor electrode), and a first power line PL1.

[0292] The first emission capacitor CLD1, the second emission capacitor CLD2, and the third emission capacitor CLD3 may be formed or disposed in a region overlapping with a second power line PL2 in the emission region A_LD.

[0293] The first sub-bridging pattern CP1_1 of the first pixel circuit PXC1_1 may extend in a first direction DR1 and be coupled to the first emission capacitor CLD1 in the emission region A_LD. The first sub-bridging pattern CP1_1 of the first pixel circuit PXC1_1 may be integrally formed with the electrode of the first emission capacitor CLD1. The first sub-bridging pattern CP1_1 may extend from the first pixel circuit PXC1_1 to the second circuit region A_PXC2 via the second pixel circuit PXC1_2 (or a second sub-pixel circuit region), the third pixel circuit PXC1_3 (or a third sub-pixel circuit region), and the peripheral region A_PER, and may be coupled to a first electrode of a first auxiliary transistor M8_1 in the test circuit PXC2. Here, the first auxiliary transistor M8_1 may be substantially equivalent to the eighth transistor M8 described with reference to Figure 12 description.

[0294] Similarly, the second sub-bridging pattern CP1_2 of the second pixel circuit PXC1_2 may extend in the first direction DR1 and be coupled to the second emission capacitor CLD2 in the emission region A_LD. The second sub-bridging pattern CP1_2 may be integrally formed with the electrode of the second emission capacitor CLD2. In addition, the second sub-bridging pattern CP1_2 may extend to the second circuit region A_PXC2 in a manner similar to that of the first sub-bridging pattern CP1_1 and be coupled to a first electrode of a second auxiliary transistor M8_2 in the test circuit PXC2.

[0295] The third sub-bridging pattern CP1_3 of the third pixel circuit PXC1_3 may extend in the first direction DR1 and be coupled to the third emission capacitor CLD3 in the emission region A_LD. The third sub-bridging pattern CP1_3 may be integrally formed with the electrode of the third emission capacitor CLD3. In addition, the third sub-bridging pattern CP1_3 may extend to the second circuit region A_PXC2 in a manner similar to that of the first sub-bridging pattern CP1_1 and be coupled to a first electrode of a third auxiliary transistor M8_3 in the test circuit PXC2.

[0296] The first power line PL1 may extend in the second direction DR2 and be disposed in the entire regions of the first circuit region A_PXC1, the peripheral region A_PER, and the second circuit region A_PXC2 within a range where the first power line PL1 does not overlap with the first sub-bridging pattern CP1_1, the second sub-bridging pattern CP1_2, and the third sub-bridging pattern CP1_3. The first power line PL1 may include a hole HOL, wherein the first via layer VIA1 is exposed from the peripheral region A_PER through the hole HOL.

[0297] Referring Figure 16A and Figure 16C , the fifth conductive layer SD3 may include a second power line PL2, a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3.

[0298] The second power line PL2 may be disposed on the entire surface of the pixel region PXA except for the first opening OP1 and the second opening OP2 formed in the emission region A_LD. The first opening OP1 may be formed adjacent to the first circuit region A_PXC1 in the emission region A_LD. The second opening OP2 may be formed in the emission region A_LD at a position spaced apart from the first opening OP1 in the first direction DR1. The size of the second opening OP2 may be equal to the size of the first opening OP1; however, the present disclosure is not limited thereto.

[0299] The second power line PL2 may be coupled to the second bridging pattern CP2 through a contact hole (or via hole) exposing the second bridging pattern CP2 in the second circuit region A_PXC2 and may be coupled to the second electrode of the eighth transistor M8 through the second bridging pattern CP2.

[0300] The second anode electrode AE2 may be disposed in the first opening OP1 and spaced apart from the second power line PL2. The first anode electrode AE1 and the third anode electrode AE3 may each be disposed in the second opening OP2 and spaced apart from the second power line PL2.

[0301] The first light-emitting element LD1 may be disposed to partially overlap with the first anode electrode AE1 and the first emission capacitor CLD1. The second light-emitting element LD2 may be disposed to partially overlap with the second anode electrode AE2 and the second emission capacitor CLD2. The third light-emitting element LD3 may be disposed to partially overlap with the third anode electrode AE3 and the third emission capacitor CLD3. Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 is substantially equivalent to or similar to the light-emitting element LD described with reference to Figure 14 and Figure 15 ; thus, repeated description thereof will be omitted.

[0302] In an exemplary embodiment, each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may emit light having a different single color. For example, the first light-emitting element LD1 may emit light having a first color (e.g., green), the second light-emitting element LD2 may emit light having a second color (e.g., red), and the third light-emitting element LD3 may emit light having a third color (e.g., blue).

[0303] The first pixel circuit PXC1_1, the first light-emitting element LD1, and the first auxiliary transistor M8_1 may form a first pixel (or first sub-pixel). The second pixel circuit PXC1_2, the second light-emitting element LD2, and the second auxiliary transistor M8_2 may form a second pixel (or second sub-pixel). The third pixel circuit PXC1_3, the third light-emitting element LD3, and the third auxiliary transistor M8_3 may form a third pixel (or third sub-pixel). The unit pixel PX_G may include the first pixel to the third pixel that emit light having different colors.

[0304] As described with reference to Figure 16A , Figure 16B , Figure 16C and Figure 16D , in a case where the unit pixel PX_G includes a plurality of pixels, the light-emitting elements LD1, LD2, and LD3 of the pixels may also be arranged in the emission region A_LD. The pixel circuits PXC1_1, PXC1_2, and PXC1_3 of the pixels may also be provided in a first circuit region A_PXC1 separated from the emission region A_LD. The test circuit PXC2 may also be provided in a second circuit region A_PXC2 separated from the emission region A_LD and the first circuit region A_PXC1.

[0305] Therefore, even when high temperature and / or high voltage are generated during the process of bonding the light-emitting elements LD1, LD2, and LD3 to the base layer SUB, damage to the transistors in the pixel circuits PXC1_1, PXC1_2, and PXC1_3 due to the high temperature and / or high voltage can be prevented or suppressed. In addition, damage to the pixel circuits PXC1_1, PXC1_2, and PXC1_3 caused by damage to the eighth transistor M8 due to static electricity absorbed through the anode electrodes AE1, AE2, and AE3 can be prevented or suppressed.

[0306] Figure 17 is a plan view showing the pixel PX included in the Figure 1B display device 10 according to an exemplary embodiment. Figure 17 The pixel PX is schematically shown, focusing on the connection relationship between the test circuit PXC2 of the unit pixel PX_G described with reference to Figure 16A and the pixel electrodes (i.e., the cathode electrode and the anode electrode).

[0307] Reference Figure 16A and Figure 17 , each of the unit pixels PX_G11, PX_G12, PX_G21, and PX_G22 is substantially equivalent to or similar to the unit pixel PX_G described in the reference Figure 16A ; therefore, repeated description thereof will be omitted.

[0308] A first sub-test line TL_V extending in the first direction DR1 may be provided on the base layer SUB. The first sub-test line TL_V may include the third conductive layer (SD1; see Figure ) described in the reference and is formed in the same layer as the data line (DL; see ​ ) by the same process as the data line (DL; see ​ ). ​ )

[0309] The first unit pixel PX_G11 provided on the first row and the first column and the first two unit pixel PX_G12 provided on the first row and the second column may be substantially symmetric to each other with respect to the first sub-test line TL_V.

[0310] The arrangement of the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 and the anode electrodes AE1, AE2, and AE3 of the first two unit pixel PX_G12 may be substantially equivalent to the arrangement of the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 and the anode electrodes AE1, AE2, and AE3 of the first unit pixel PX_G11.

[0311] The test circuit PXC2 of the first unit pixel PX_G11 may be provided in the region between the anode electrodes AE1, AE2, and AE3 of the first unit pixel PX_G11 (or the emission region where the anode electrodes AE1, AE2, and AE3 are provided) and the first sub-test line TL_V. The test circuit PXC2 of the first two unit pixel PX_G12 may be provided in the region between the anode electrodes AE1, AE2, and AE3 of the first two unit pixel PX_G12 and the first sub-test line TL_V. The test circuit PXC2 of the first two unit pixel PX_G12 may be adjacent to the test circuit PXC2 of the first unit pixel PX_G11. In other words, the test circuit PXC2 of the first unit pixel PX_G11 and the test circuit PXC2 of the first two unit pixel PX_G12 may be provided in the region between the first reference line L_REF1 and the seventh reference line L_REF7.

[0312] In the region between the first reference line L_REF1 and the seventh reference line L_REF7, a second sub-test line TL_H may be provided. The second sub-test line TL_H may be substantially equivalent to or similar to the test line TL described with reference to ​ The second sub-test line TL_H may extend in the second direction DR2, overlap with the first sub-test line TL_V, and be coupled to the first sub-test line TL_V through a contact hole (not shown). In this case, a test signal applied from an external device to the first sub-test line TL_V may be transmitted to the second sub-test line TL_H. Further, the second sub-test line TL_H may be coupled to the test circuits PXC2 of the first unit pixel PX_G11 and the second unit pixel PX_G12, and may form or be coupled to the gate electrode of the eighth transistor M8 in the test circuit PXC2.

[0313] In the first unit pixel PX_G11, as described with reference to ​ and ​ , the sub-bridging patterns CP1_1, CP1_2, and CP1_3 may be provided to straddle the peripheral region ( ​ and ​ "A_PER" in), and may be coupled to the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 (and / or the anode electrodes AE1, AE2, and AE3) and the test circuit PXC2.

[0314] In the second unit pixel PX_G21, the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 may be disposed in the first direction DR1 (or upper position) with respect to the anode electrodes AE1, AE2, and AE3. In other words, the second unit pixel PX_G21 may be substantially symmetric to the first unit pixel PX_G11 in the vertical direction.

[0315] The arrangement of the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 and the anode electrodes AE1, AE2, and AE3 of the second unit pixel PX_G21 may be substantially equivalent to the arrangement of the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 and the anode electrodes AE1, AE2, and AE3 of the first unit pixel PX_G11.

[0316] However, the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the first unit pixel PX_G11 may be disposed at a lower position with respect to the anodes AE1, AE2, and AE3 of the first unit pixel PX_G11 (or the emission region in which the anodes AE1, AE2, and AE3 are provided). The first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the second unit pixel PX_G21 may be disposed at an upper position with respect to the anodes AE1, AE2, and AE3 of the second unit pixel PX_G21. The first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the second unit pixel PX_G21 may be adjacent to the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the first unit pixel PX_G11. In other words, the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the first unit pixel PX_G11 and the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the second unit pixel PX_G21 may be disposed in a region between the second reference line L_REF2 and the fourth reference line L_REF4.

[0317] The first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 of the second unit pixel PX_G22 may be disposed at an upper position with respect to the anodes AE1, AE2, and AE3 of the second unit pixel PX_G22 (or the emission region in which the anodes AE1, AE2, and AE3 are provided). The test circuit PXC2 of the second unit pixel PX_G22 may be disposed on the left side of the anodes AE1, AE2, and AE3 of the second unit pixel PX_G22. In other words, the second unit pixel PX_G22 may have a structure obtained by rotating the first unit pixel PX_G11 180 degrees in a plan view.

[0318] The second unit pixel PX_G22 may share the first circuit region in which the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 are provided with the first unit pixel PX_G12, and may share the second circuit region in which the test circuit PXC2 is provided with the second unit pixel PX_G21.

[0319] As referred to ​As described, some of the unit pixels PX_G11, PX_G12, PX_G21, and PX_G22 (e.g., unit pixels included in the same column) may include pixel circuits PXC1_1, PXC1_2, and PXC1_3 that are disposed in different directions with respect to the corresponding anode electrodes AE1, AE2, and AE3 (or emission regions), and may share the corresponding first circuit regions in which the pixel circuits PXC1_1, PXC1_2, and PXC1_3 are disposed.

[0320] Similarly, some of the unit pixels PX_G11, PX_G12, PX_G21, and PX_G22 (e.g., unit pixels included in the same row) may include corresponding test circuits PXC2 that are disposed in different directions with respect to the corresponding anode electrodes AE1, AE2, and AE3 (or emission regions), and may share the corresponding second circuit regions in which the test circuits PXC2 are disposed.

[0321] ​ is a plan view of a pixel PX included in a ​ display device 10 according to an exemplary embodiment. ​ is a diagram corresponding to ​ the diagram of.

[0322] Referring to ​ and ​ , except for the first sub-bridging pattern CP1_1, the second sub-bridging pattern CP1_2, and the third sub-bridging pattern CP1_3, ​ the unit pixels PX_G11, PX_G12, PX_G21, and PX_G22 of ​ may be substantially equivalent to or similar to the unit pixels PX_G11, PX_G12, PX_G21, and PX_G22 of

[0323] In the first unit pixel PX_G11, the first sub-bridging pattern CP1_1 may extend from the first pixel circuit PXC1_1 in a first direction DR1, be coupled to a first anode electrode AE1 (or form the first anode electrode AE1) disposed in a second opening OP2, extend in a second direction DR2 via an emission region, and may be coupled to the test circuit PXC2. In other words, the first sub-bridging pattern CP1_1 may extend across or pass through the emission region in which the anode electrodes AE1, AE2, and AE3 are disposed, rather than extending through the peripheral region.

[0324] In this case, the test circuit PXC2 may be coupled to the first anode electrode AE1 through a path independent of the connection path of the first pixel circuit PXC1_1, such that the first pixel circuit PXC1_1 may be protected from static electricity through the first anode electrode AE1.

[0325] Similarly, the second sub-bridging pattern CP1_2 and the third sub-bridging pattern CP1_3 can be coupled to the test circuit PXC2 across or via the emission region.

[0326] In the first two-unit pixel PX_G12, the second one-unit pixel PX_G21, and the second two-unit pixel PX_G22, the arrangements of the first sub-bridging pattern CP1_1, the second sub-bridging pattern CP1_2, and the third sub-bridging pattern CP1_3 are similar to the arrangements of the first sub-bridging pattern CP1_1, the second sub-bridging pattern CP1_2, and the third sub-bridging pattern CP1_3 in the first one-unit pixel PX_G11 (i.e., the arrangement scheme in which the first sub-bridging pattern CP1_1, the second sub-bridging pattern CP1_2, and the third sub-bridging pattern CP1_3 extend across the emission region); thus, the repeated description thereof will be omitted.

[0327] As described with reference to ​ the sub-bridging patterns CP1_1, CP1_2, and CP1_3 connecting the positive electrodes AE1, AE2, and AE3 to the test circuit PXC2 can be arranged to cross or pass through the emission region instead of extending through the peripheral region.

[0328] ​ FIG. is a diagram showing a display device 10_1 according to an exemplary embodiment of the present disclosure.

[0329] Referring to ​ , the display device 10_1 may include a display panel 100, a timing controller 200, a data driver 300, a scan driver 410, and an emission driver 420. Except for the scan driver 410 and the emission driver 420, the display device 10_1 may be substantially equivalent to or similar to the display device 10 described with reference to ​ Therefore, the repeated description thereof will be omitted.

[0330] The display panel 100 may include a display area DA on which an image is displayed and a non-display area NDA excluding the display area DA. The non-display area NDA may be provided on one side of the display area DA or formed to surround the display area DA, but is not limited thereto.

[0331] The display panel 100 may include signal lines and pixels PX. The signal lines may include data lines DL1 to DLm, scan lines SL1 to SLn, emission control lines EL1 to ELn, and test lines TL1 to TLk (where k is a positive integer). The pixels PX, the data lines DL1 to DLm, the scan lines SL1 to SLn, and the emission control lines EL1 to ELn may be substantially equivalent to or similar to those described with reference to ​The described pixel PX, data lines DL1 to DLm, scan lines SL1 to SLn, and emission control lines EL1 to ELn. Therefore, a repeated description thereof will be omitted.

[0332] The test lines TL1 to TLk may extend in a first direction DR1 and be repeatedly provided along a second direction DR2. Each of the test lines TL1 to TLk may be coupled to the pixel PX (or the unit pixel described with reference ​ to) included in two columns. The test lines TL1 to TLk may be electrically coupled to each other and receive a gate signal GT from an external device (e.g., a test device for performing a test on the display panel 100).

[0333] The timing controller 200 may generate a scan control signal SCS and an emission control signal ECS based on control signals provided from an external device (e.g., a graphics processor). The scan control signal SCS may be a signal for controlling the operation of the scan driver 410 and include a start signal (or a scan start signal), a clock signal (or a scan clock signal), etc. The emission control signal ECS may be a signal for controlling the operation of the emission driver 420 and include a start signal (or an emission start signal), a clock signal (or an emission clock signal), etc.

[0334] The scan driver 410 may generate a scan signal based on the scan control signal SCS and provide the scan signal to the scan lines SL1 to SLn.

[0335] In an embodiment, the scan driver 410 may be disposed in the display area DA of the display panel 100. For example, the scan driver 410 may be disposed between pixel columns adjacent to one side (e.g., the left side) of the display panel 100 and formed together with the pixel circuit of the pixel PX.

[0336] The emission driver 420 may generate an emission control signal based on the emission control signal ECS and provide the generated emission control signal to the emission control lines EL1 to ELn.

[0337] In an embodiment, the emission driver 420 may be disposed in the display area DA of the display panel 100. For example, the emission driver 420 may be disposed between pixel columns adjacent to the other side (e.g., the right side) of the display panel 100 and formed together with the pixel circuit of the pixel PX.

[0338] Reference will be made to ​ for a more detailed description of the scan driver 410 and the emission driver 420.

[0339] ​ is a plan view showing an example of the display device 10_1 of ​ . ​Schematically shows a display device 10_1, which focuses on the unit pixels described with reference to ​ Description of the unit pixels.

[0340] With reference to ​ And ​ The display device 10_1 may include unit pixels PX_G11 to PX_G16, PX_G21 to PX_G26, and PX_G31 to PX_G36. Each of the unit pixels PX_G11 to PX_G16, PX_G21 to PX_G26, and PX_G31 to PX_G36 may include a light-emitting element LDS, a pixel circuit PXA1, and a test circuit (or an eighth transistor M8) disposed in separate regions from each other. Here, the light-emitting element LDS may include the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 described with reference to ​ Description of the unit pixels. The pixel circuit PXA1 may include the first pixel circuit PXC1_1, the second pixel circuit PXC1_2, and the third pixel circuit PXC1_3 described with reference to ​ Description of the unit pixels.

[0341] Each of the unit pixels PX_G11 to PX_G16, PX_G21 to PX_G26, and PX_G31 to PX_G36 may be the same as the unit pixel PX_G described with reference to ​ And ​ Description of the unit pixels, and any one of the unit pixels PX_G11, PX_G12, PX_G21, and PX_G22 described with reference to ​ Description of the unit pixels; therefore, repeated description thereof will be omitted.

[0342] The display device 10_1 may include clock signal lines CLK1 and CLK2 and emission clock signal lines CLK_E1 and CLK_E2. The clock signal lines CLK1 and CLK2 may extend in a first direction DR1 and be disposed between adjacent unit pixels. For example, the clock signal lines CLK1 and CLK2 may be disposed between the first and second unit pixels PX_G12 and the first and third unit pixels PX_G13 (or in the peripheral region between the first and second unit pixels PX_G12 and the first and third unit pixels PX_G13). The clock signal lines CLK1 and CLK2 may transmit clock signals.

[0343] The scan driver 410 may be disposed between adjacent unit pixels. For example, in response to the clock signal lines CLK1 and CLK2, the scan driver 410 may be disposed between the first and second unit pixels PX_G12 and the first and third unit pixels PX_G13 (or in the peripheral region between the first and second unit pixels PX_G12 and the first and third unit pixels PX_G13).

[0344] The scan driver 410 may include scan stages ST_S1, ST_S2, and ST_S3. Each of the scan stages ST_S1, ST_S2, and ST_S3 may generate a scan signal corresponding to an output signal (or a carry signal or a start signal) of a previous stage using clock signals transmitted through clock signal lines CLK1 and CLK2.

[0345] The first scan stage ST_S1 may be disposed in a peripheral area between the light-emitting elements LDS of the first two-unit pixel PX_G12 and the light-emitting elements LDS of the first three-unit pixel PX_G13. An input terminal IN of the first scan stage ST_S1 may be coupled to the (i-1)-th scan line SLi-1 (or a previous scan line). An output terminal OUT of the first scan stage ST_S1 may be coupled to the i-th scan line SLi.

[0346] Similarly, the second scan stage ST_S2 may be disposed in a peripheral area between the light-emitting elements LDS of the second two-unit pixel PX_G22 and the light-emitting elements LDS of the second three-unit pixel PX_G23. The third scan stage ST_S3 may be disposed in a peripheral area between the light-emitting elements LDS of the third two-unit pixel PX_G32 and the light-emitting elements LDS of the third three-unit pixel PX_G33. The connection relationships between the second scan stage ST_S2 and the third scan stage ST_S3 and the scan lines SLi, SLi+1, SLi+2, and SLi+3 may be substantially the same as or similar to the connection relationship between the first scan stage ST_S1 and the scan lines SLi-1, SLi, and SLi+1; thus, a repeated description thereof will be omitted.

[0347] The emission driver 420 may include emission stages ST_E1, ST_E2, and ST_E3. Each of the emission stages ST_E1, ST_E2, and ST_E3 may generate an emission signal corresponding to an output signal (or an emission carry signal or an emission start signal) of a previous emission stage using emission clock signals transmitted through emission clock signal lines CLK_E1 and CLK_E2.

[0348] The first emission stage ST_E1 may be disposed in a peripheral area between the light-emitting elements LDS of the first four-unit pixel PX_G14 and the light-emitting elements LDS of the first five-unit pixel PX_G15. The first emission stage ST_E1 may receive a previous emission control signal through the (i-1)-th emission control line ELi-1 and output the emission control signal to the i-th emission control line ELi.

[0349] Similarly, the second emission stage ST_E2 can be disposed in the peripheral region between the light-emitting elements LDS of the second four-unit pixel PX_G24 and the light-emitting elements LDS of the second five-unit pixel PX_G25. The third emission stage ST_E3 can be disposed in the peripheral region between the light-emitting elements LDS of the third four-unit pixel PX_G34 and the light-emitting elements LDS of the third five-unit pixel PX_G35.

[0350] As referred to ​ and ​ As described, the scan driver 410 and the emission driver 420 can be disposed in the display area DA of the display panel 100. Since the test circuits of two unit pixels among the unit pixels PX_G11 to PX_G16, PX_G21 to PX_G26, and PX_G31 to PX_G36 are disposed adjacent to each other in a peripheral region, the scan driver 410 and the emission driver 420 can be disposed in a part of the peripheral region other than the part where the test circuits are disposed. Accordingly, the non-display area NDA formed around the periphery of the display area DA of the display device 10_1 can be reduced, and thus the ineffective space of the display device 10_1 can be reduced.

[0351] In the display panel and the method of testing a display panel according to an exemplary embodiment of the present disclosure, a transistor is provided that is connected in parallel with the light-emitting element, such that a defect test can be performed on the entire pixel circuit.

[0352] In addition, the auxiliary transistor is disposed in a separate region spaced apart from the region in which the light-emitting element and the pixel circuit configured to provide a driving current to the light-emitting element are disposed. Accordingly, damage to the auxiliary transistor and the pixel circuit during the process of mounting the light-emitting element can be prevented or suppressed.

[0353] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A display panel, comprising a substrate having a plurality of pixels, the pixels including: a light-emitting element disposed on the substrate in an emission region within the pixel; a pixel circuit disposed on the substrate in a first circuit region within the pixel, the pixel circuit including a sub-pixel circuit, the sub-pixel circuit including a first transistor to control a driving current flowing from a first power line through the light-emitting element to a second power line; and a test circuit disposed on the substrate in a second circuit region within the pixel, the test circuit including an auxiliary transistor connected in parallel to the light-emitting element, wherein a first electrode of one of the auxiliary transistors is electrically connected to one electrode of the first transistor, and a second electrode of the other auxiliary transistor is electrically connected to the second power line, and wherein, in a plan view of the pixel, the first circuit region and the second circuit region are disposed adjacent to the emission region and separated from each other by the emission region, wherein the first circuit region includes a first semiconductor pattern that forms a channel region of the first transistor, and wherein the second circuit region includes a second semiconductor pattern that forms a channel region of each of the auxiliary transistors.

2. The display panel according to claim 1, further comprising a scan line and a data line disposed on the substrate, Among them, the pixel being defined by the scan line and the data line, and wherein the sub-pixel circuit includes at least one transistor connected to the scan line and the data line.

3. The display panel according to claim 2, wherein, The pixel circuit is disposed in a first direction with respect to the light-emitting element, and wherein the test circuit is disposed in a second direction with respect to the light-emitting element, the second direction being perpendicular to the first direction.

4. The display panel according to claim 3, wherein, The pixel further has a peripheral region, and the pixel further includes a connection line extending from the first circuit region to the second circuit region in the peripheral region, and wherein the auxiliary transistors are respectively connected to the light-emitting element through the connection line.

5. The display panel according to claim 4, further comprising an emission capacitor formed by the connection line extending to the emission region and overlapping with a cathode electrode of the light-emitting element, Among them, a width of a portion of the connection line overlapping with the cathode electrode being greater than a width of a portion of the connection line not overlapping with the cathode electrode.

6. The display panel according to claim 5, wherein, The light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the first light-emitting element is configured to emit light having a first color, the second light-emitting element is configured to emit light having a second color, and the third light-emitting element is configured to emit light having a third color.

7. The display panel according to claim 6, wherein, The cathode electrode of the light-emitting element is connected to the second power line, wherein the second power line is disposed on an entire surface of the substrate and includes an opening formed in the emission region, and wherein an anode electrode of the light-emitting element is disposed in the opening.

8. The display panel according to claim 7, wherein, The second power line includes a first opening and a second opening formed in the emission region, the first opening and the second opening being spaced apart from each other with respect to the negative electrode, and wherein at least one of the first light-emitting element, the second light-emitting element, and the third light-emitting element is disposed in the first opening, and the remaining light-emitting elements among the first light-emitting element, the second light-emitting element, and the third light-emitting element are disposed in the second opening.

9. The display panel according to claim 2, wherein, The sub-pixel circuit includes: The first transistor includes a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; A second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode connected to a first scan line among the scan lines; A third transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode connected to the first scan line; A fourth transistor includes a first electrode connected to a third power line, a second electrode connected to the third node, and a gate electrode connected to a second scan line among the scan lines; A fifth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode connected to an emission control line; A sixth transistor includes a first electrode connected to the second node, a second electrode connected to a fourth node, and a gate electrode connected to the emission control line; A seventh transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode connected to a third scan line among the scan lines; and A storage capacitor connected between the first power line and the third node, and wherein the positive electrode of the light-emitting element is connected to the fourth node.

10. The display panel according to claim 9, further comprising: A pixel circuit layer disposed on the substrate; And A light-emitting element layer disposed on the pixel circuit layer, wherein the pixel circuit layer includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the auxiliary transistor, and the storage capacitor, and wherein the light-emitting element layer includes the light-emitting element, and the positive electrode and the negative electrode of the light-emitting element are disposed on the same layer.

11. The display panel according to claim 10, wherein, The light-emitting element includes a first semiconductor layer, an intermediate layer, and a second semiconductor layer stacked in sequence, wherein the positive electrode is connected to the first semiconductor layer through a first contact electrode, and wherein the negative electrode is connected to the second semiconductor layer through a second contact electrode.

12. The display panel according to claim 10, wherein, The pixel circuit layer includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked in sequence on the substrate, wherein the semiconductor pattern of each of the auxiliary transistors is disposed between the substrate and the first insulating layer, Among them, the gate electrode of each of the auxiliary transistors is disposed between the first insulating layer and the second insulating layer, Among them, the third power line is disposed between the second insulating layer and the third insulating layer, Among them, the first electrode and the second electrode of each of the auxiliary transistors are disposed between the third insulating layer and the fourth insulating layer, and Among them, the first power line is disposed between the fourth insulating layer and the fifth insulating layer.

13. The display panel according to claim 12, wherein, The first electrode of the sixth transistor is connected to the anode electrode of the light-emitting element through a bridging pattern interposed between the fourth insulating layer and the fifth insulating layer, and Among them, the cathode electrode of the light-emitting element is integrally formed with the second power line, and the second power line is disposed on the same layer as the layer where the cathode electrode is disposed.

14. The display panel according to claim 13, wherein, The bridging pattern partially overlaps with the second power line, and Among them, the second power line, the fifth insulating layer, and the bridging pattern form an emission capacitor.

15. The display panel according to claim 1, wherein, The light-emitting element is disposed between the electrical node and the second power line, and The test circuit is disposed between the electrical node and the second power line.

16. The display panel according to claim 1, wherein, Both the light-emitting element and the test circuit are directly connected to the second power line.

17. The display panel according to claim 1, wherein, The first electrode of one of the auxiliary transistors among the auxiliary transistors is electrically connected to the anode electrode of the light-emitting element, and the second electrode of the other auxiliary transistor among the auxiliary transistors is electrically connected to the cathode electrode of the light-emitting element.

18. A display panel, comprising: A substrate including an emission region, a first circuit region, and a second circuit region, wherein the second circuit region is disposed separately from the emission region; A light-emitting element disposed in the emission region; A first pixel circuit disposed in the first circuit region and including at least a first transistor, the first pixel circuit configured to control a driving current flowing from the first power line through the light-emitting element and the first transistor to the second power line in response to a scan signal provided through a scan line and a data signal provided through a data line; and A test circuit disposed in the second circuit region and including two serially-connected auxiliary transistors, the two serially-connected auxiliary transistors being connected in parallel to the light-emitting element, Wherein, the first electrode of the two serially-connected auxiliary transistors is electrically connected to one electrode of the first transistor, and the second electrode of the two serially-connected auxiliary transistors is electrically connected to the second power line, Wherein, the first circuit region and the second circuit region are separated from each other by the emission region, Wherein, the first circuit region includes a first semiconductor pattern, and the first semiconductor pattern forms a channel region of the first transistor, and Wherein, the second circuit region includes a second semiconductor pattern, and the second semiconductor pattern forms a channel region of each of the two serially-connected auxiliary transistors.

19. The display panel according to claim 18, wherein, The substrate includes a pixel region defined by the scan line and the data line, and Among them, the pixel region includes the emission region, the first circuit region, and the second circuit region.

20. The display panel according to claim 19, wherein, The emission region is disposed between the first circuit region and the second circuit region.

21. The display panel according to claim 18, wherein, The first electrodes of the two serially-connected auxiliary transistors are electrically connected to the anodes of the light-emitting elements, and the second electrodes of the two serially-connected auxiliary transistors are electrically connected to the cathodes of the light-emitting elements.

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