Semiconductor packaging method and semiconductor packaging structure

Abstract

The present application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method includes: mounting a lead frame and a plurality of chips to be packaged on a carrier, and the plurality of chips to be packaged are located in a hollow area of ​​the lead frame; an encapsulation layer is covered on the chip to be packaged, the lead frame and the exposed carrier, and filled in the hollow area of ​​the lead frame to form an encapsulation structure; a first rewiring structure electrically connected to the front of the chip to be packaged and the first side of the lead frame is formed on the first surface of the encapsulation structure, and a second rewiring structure electrically connected to the back of the chip to be packaged and the second side of the lead frame is formed on the second surface of the encapsulation structure. The semiconductor packaging structure is manufactured by the semiconductor packaging method. The semiconductor packaging structure of the present application realizes double-sided interconnection packaging of the chip through the lead frame and double-sided rewiring interconnection process, improves the thinness of the product, and can enhance the electrical reliability of the product.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and a semiconductor packaging structure. Background Art

[0002] like Figure 1 As shown, in the prior art, a lead frame 30' and a wiring layer 40' are often used to realize the double-sided interconnection packaging of two chips 10'. The specific structure is: the back of the two chips 10' is attached to the upper surface of the lead frame 30' through a conductive adhesive 20' to realize the back electrical connection, and the wiring layer 40' is connected to the front of the chip 10' through a copper column 50', wherein the copper column needs to be implanted by ultrasonic bonding. The cost of this process is extremely high, but the efficiency is extremely low. In addition, the lead frame 30' is arranged on the back of the chip 10', resulting in a thicker thickness of the packaged product, which will be limited when applied to wearable equipment or other scenarios with high requirements for product thickness. Summary of the invention

[0003] One aspect of the present application provides a semiconductor packaging method, which includes:

[0004] S1: Mounting a lead frame and a plurality of chips to be packaged on a carrier, with the front of the chips to be packaged facing the carrier, the lead frame being provided with a hollow area, the hollow area penetrating the lead frame along a thickness direction, and the plurality of chips to be packaged being located in the hollow area;

[0005] S2: Covering the chip to be packaged, the lead frame and the exposed carrier with an encapsulation layer, and filling the hollow area of ​​the lead frame to form an encapsulation structure, wherein the encapsulation structure includes a first surface and a second surface arranged opposite to the first surface, and the front side of the chip to be packaged and the first side of the lead frame are exposed on the first surface;

[0006] S3: A first rewiring structure is formed on the first surface of the encapsulation structure, the first rewiring structure is electrically connected to the front surface of the chip to be packaged and the first surface of the lead frame, and a second rewiring structure is formed on the second surface of the encapsulation structure, the second rewiring structure is electrically connected to the back surface of the chip to be packaged and the second surface of the lead frame arranged opposite to the first surface.

[0007] Optionally, the lead frame includes a connecting portion, which divides the hollow area into multiple areas, and the chips to be packaged located in different hollow areas are electrically connected through the connecting portion.

[0008] Optionally, the lead frame further includes a frame body, and the frame body is provided with the hollow area penetrating the frame body along the thickness direction; two ends of the connecting portion are respectively connected to two opposite sides of the frame body.

[0009] Optionally, the lead frame further includes a plurality of edge portions isolated from each other, one end of the edge portion is connected to the frame body, and the other end extends toward the hollow area; each of the hollow areas is provided with a plurality of edge portions isolated from each other.

[0010] Optionally, the thickness of the lead frame is greater than the thickness of the chip to be packaged, and before step S3, the method further includes thinning the first surface of the encapsulation structure until the first surface of the lead frame is exposed.

[0011] Optionally, before step S3, the following steps are included:

[0012] A plurality of openings are formed on the second surface of the encapsulation structure, wherein the openings are located directly above the chip to be packaged to expose the back side of the chip to be packaged;

[0013] In step S3, the second rewiring structure formed on the second surface of the encapsulation structure includes a conductive protrusion formed in the opening, and the conductive protrusion is electrically connected to the back surface of the chip to be packaged.

[0014] Optionally, the lead frame includes a first portion and a second portion from the first surface to the second surface of the encapsulation structure along a thickness direction, and a width of the first portion is greater than a width of the second portion.

[0015] A second aspect of the present application provides a semiconductor package structure, comprising:

[0016] An encapsulation structure, comprising a first surface and a second surface opposite to each other, the encapsulation structure comprising a lead frame and a plurality of chips and an encapsulation layer for encapsulating the lead frame and the plurality of chips, the lead frame being provided with a hollow region, the hollow region penetrating the lead frame in a thickness direction, the plurality of chips being located in the hollow region, the encapsulation layer being filled in the hollow region of the lead frame, the encapsulation structure comprising a first surface and a second surface arranged opposite to the first surface, the front surface of the chip and the first surface of the lead frame being exposed on the first surface;

[0017] A first rewiring structure, wherein the first rewiring structure is formed on a first surface of the encapsulation structure, and the first rewiring structure is electrically connected to the front surface of the chip and the first surface of the lead frame;

[0018] A second rewiring structure is formed on the second surface of the encapsulation structure, and the second rewiring structure is electrically connected to the back surface of the chip and a second surface arranged opposite to the first surface.

[0019] Optionally, the lead frame includes a connecting portion, which divides the hollow area into multiple areas, and the chips to be packaged located in different hollow areas are electrically connected through the connecting portion.

[0020] Optionally, the lead frame also includes a plurality of edge portions isolated from each other, wherein the edge portions are arranged along the inner periphery of the encapsulation structure, one end of the edge portion is exposed from the surface of the encapsulation structure, and the other end extends to the hollow area; each of the hollow areas is provided with a plurality of edge portions isolated from each other.

[0021] Optionally, a second surface of the encapsulation structure is provided with a plurality of openings, the openings are arranged corresponding to the chip, and the second rewiring structure includes conductive protrusions, the conductive protrusions are formed in the openings and are electrically connected to the back side of the chip.

[0022] Optionally, the lead frame includes a first portion and a second portion from the first surface to the second surface of the encapsulation structure along a thickness direction, and a width of the first portion is greater than a width of the second portion.

[0023] The semiconductor packaging method and semiconductor packaging structure provided in the embodiments of the present application realize double-sided interconnection packaging of the chip through a lead frame and a double-sided rewiring interconnection process, thereby improving the thinness of the product and enhancing the electrical reliability of the product.

[0024] Specifically, a hollow area is provided in the lead frame, the hollow area penetrates the lead frame in the thickness direction, and a plurality of chips to be packaged are located in the hollow area, that is, the chips to be packaged are embedded in the lead frame, thereby greatly reducing the thickness of the product and achieving lightweight and thinness in the thickness of the product.

[0025] Compared with the prior art, which requires copper pillars to interconnect the two sides of the chip, the technical solution in the present application directly realizes the double-sided interconnection of the chip through the lead frame, and no longer requires copper pillars, thereby increasing the interconnection area, realizing multi-layer wiring process, increasing the freedom of product design, and enhancing the electrical reliability of the product; at the same time, saving production costs and improving overall production efficiency. It should be noted that in the prior art, if multiple copper pillars are set, not only is the positioning process complicated during the production process, but also because multiple independent copper pillars need to be set, the positioning error will be accumulated; in the present application, since the lead frame is integrally formed, each part of the lead frame is fixed on the carrier board after one positioning, so that it is encapsulated in the encapsulation structure, which greatly saves production costs and improves overall production efficiency.

[0026] By arranging a plurality of chips to be packaged in the hollow region of the lead frame and encapsulating the chips to be packaged and the lead frame together, the use of conductive adhesive to fix the chips is avoided, thereby improving the introduction efficiency.

[0027] Compared with the lead frame in the prior art, the lead frame structure of the semiconductor packaging structure of the present application no longer requires the lead frame portion located below the chip, so it can be applicable to chips with larger areas and can accommodate more chips, and has excellent applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a cross-sectional view of a semiconductor packaging structure in the prior art.

[0029] Figure 2 It is a flow chart of the semiconductor packaging method proposed according to the first embodiment of the present application.

[0030] Figure 3 It is a schematic diagram of the front structure of the lead frame proposed in Example 1 of the present application.

[0031] Figure 4 It is a schematic diagram of the front structure of the lead frame proposed in Example 1 of the present application.

[0032] Figure 5(a)-Figure 5(n) It is a process flow chart of the semiconductor packaging method proposed in Example 1 of the present application.

[0033] Figure 6 It is a structural schematic diagram of the semiconductor packaging structure proposed in Example 1 of the present application.

[0034] FIG. 7( a ) is a schematic diagram of the front connection of the semiconductor package structure proposed in Embodiment 1 of the present application.

[0035] FIG. 7( b ) is a schematic diagram of the backside connection of the semiconductor package structure proposed in Embodiment 1 of the present application.

[0036] Figure 8 It is a structural schematic diagram of another implementation of the semiconductor packaging structure proposed in Example 1 of the present application.

[0037] Figure 9(a)-Figure 9(g) It is a process flow chart of the semiconductor packaging method in Example 2 of the present application.

[0038] Fig.10 It is a structural schematic diagram of a semiconductor packaging structure proposed in Example 2 of the present application. DETAILED DESCRIPTION

[0039] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0040] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0041] Example 1

[0042] The present embodiment provides a semiconductor packaging method and a semiconductor packaging structure.

[0043] Figure 2FIG. 1 is a flow chart of the semiconductor packaging method proposed in this embodiment. Figure 2 As shown, the semiconductor packaging method includes the following steps:

[0044] Step 100: Mounting a lead frame and a plurality of chips to be packaged on a carrier, with the front of the chips to be packaged facing the carrier, the lead frame being provided with a hollow area, the hollow area penetrating the lead frame along a thickness direction, and the plurality of chips to be packaged being located in the hollow area;

[0045] Step 200: Covering the chip to be packaged, the lead frame and the exposed carrier with an encapsulation layer, and filling the hollow area of ​​the lead frame to form an encapsulation structure, wherein the encapsulation structure includes a first surface and a second surface arranged opposite to each other, and the front side of the chip to be packaged and the first side of the lead frame are exposed on the first surface;

[0046] Step 300: Form a first rewiring structure on the first surface of the encapsulation structure, the first rewiring structure is electrically connected to the front surface of the chip to be packaged and the first surface of the lead frame, and form a second rewiring structure on the second surface of the encapsulation structure, the second rewiring structure is electrically connected to the back surface of the chip to be packaged and the second surface of the lead frame arranged opposite to the first surface.

[0047] The semiconductor packaging method of this embodiment improves the thinness of the product and can enhance the electrical reliability of the product.

[0048] Specifically, a hollow area is provided in the lead frame, the hollow area penetrates the lead frame in the thickness direction, and a plurality of chips to be packaged are located in the hollow area, that is, the chips to be packaged are embedded in the lead frame, thereby greatly reducing the thickness of the product and achieving lightweight and thinness in the thickness of the product.

[0049] Compared with the prior art, it is necessary to set copper pillars to realize the positive double-sided interconnection of the chip. The technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, and no copper pillars are needed, thereby increasing the interconnection area, realizing multi-layer wiring process, increasing the freedom of product design, and enhancing the electrical reliability of the product; at the same time, it saves production costs and improves overall production efficiency. It should be noted that in the prior art, if multiple copper pillars are set, not only is the positioning process complicated during the production process, but also because multiple independent copper pillars need to be set, the positioning error will be accumulated; in the present application, since the lead frame is integrally formed, each part of the lead frame is fixed on the carrier board after one positioning, so that it is encapsulated in the encapsulation structure, which greatly saves production costs and improves overall production efficiency.

[0050] By arranging a plurality of chips to be packaged in the hollow region of the lead frame and encapsulating the chips to be packaged and the lead frame together, the use of conductive adhesive to fix the chips is avoided, thereby improving the introduction efficiency.

[0051] Compared with the lead frame in the prior art, the lead frame structure of the semiconductor packaging structure of this embodiment is suitable for chips with larger areas and can accommodate more chips, because the lead frame part structure located below the chip is no longer required, and has excellent applicability.

[0052] The specific structure of the lead frame 20 in this embodiment is as follows Figure 3 and Figure 4 As shown, each final semiconductor packaging structure after packaging and cutting corresponds to a lead frame 20 , and a plurality of interconnected lead frames 20 arranged in an array constitute a lead frame 2 , and the lead frame 2 may also consist of only one lead frame 20 .

[0053] Each lead frame 20 includes a frame body 22, and a hollow region 21 is provided in the frame body 22 and penetrates the frame body 22 along the thickness direction T. The number of the hollow regions 21 of the lead frame 20 may be one or more.

[0054] The lead frame 20 also includes a connecting portion 24, both ends of which are respectively connected to the opposite sides of the frame body 22, and the connecting portion 24 separates the hollow area 21 into multiple areas, that is, adjacent hollow areas 21 are separated by the connecting portion 24, and adjacent hollow areas 21 in the same lead frame 20 are separated by the connecting portion 24.

[0055] Specifically, in this embodiment, if Figure 4 As shown, each lead frame 20 divides the hollow area into two by the connecting portion 24 , that is, each lead frame 20 is provided with two hollow areas 21 , and the two hollow areas 21 are separated by the connecting portion 24 .

[0056] The connecting portion 24 includes a first portion 241, a middle portion 242, and a second portion 243 connected in sequence, wherein the first portion 241 and the middle portion 242 form a first angle α, and the second portion 243 and the middle portion 242 form a second angle β, wherein the first portion 241 and the second portion 243 are respectively connected to opposite sides of the frame 22. In this way, by setting the specific structure of the connecting portion 24, a larger connection area can be achieved through the first portion 241 and the second portion 243. Preferably, the first angle α and the second angle β are both equal to 90 degrees, and the first portion 241 and the second portion 243 are parallel to each other, so that the structure of the connecting portion 24 is more stable. Preferably, one end of the first portion 241 away from the connecting portion 24 and one end of the second portion 243 away from the connecting portion 24 are both located on the same side of the connecting portion 24, so that the structure of the connecting portion 24 is more compact.

[0057] The lead frame 20 also includes a plurality of mutually isolated edge portions 23, one end of the edge portion 23 is connected to the frame body 22, and the other end extends to the hollow area 21; each hollow area 21 is provided with a plurality of mutually isolated edge portions 23. Specifically, the edge portion 23 includes a main body 231 and a support portion 232, and the support portion 232 is connected between the frame body 22 and the main body 231. The number of the support portions 232 can be one or more. When the number of the support portions 232 is more than one, the plurality of support portions 232 are arranged at intervals. The shape of the main body 231 can be square, strip or L-shaped. Preferably, the edge portion 23 of the L-shaped main body 231 is arranged at a corner of the hollow area 21 away from the connecting portion 24.

[0058] Furthermore, the chips to be packaged located in different hollow regions are electrically connected through the connecting portion, so that the front side of one chip to be packaged is electrically connected to the back side of another chip to be packaged; or, the front side of one chip to be packaged is electrically connected to the front side of another chip to be packaged; or, the back side of one chip to be packaged is electrically connected to the back side of another chip to be packaged.

[0059] Each lead frame 20 includes a first surface 20 a and a second surface 20 b that are oppositely disposed along the thickness direction T. A plurality of first electrical connection points are disposed on the first surface 20 a , and a plurality of second electrical connection points are disposed on the second surface 20 b .

[0060] Specifically, Figure 5(a)-Figure 5(n) As shown, the semiconductor packaging method of this embodiment includes:

[0061] In step 100, as shown in FIG5(a), the chip 11 to be packaged and the lead frame 20 are mounted on the carrier 3 through the adhesive layer, with the back of the chip 11 to be packaged facing upward and the front facing the carrier 3. The chip 11 to be packaged includes a front side 11a with a pad, and a back side 11b arranged relative to the front side 11a, and the back side 11b is provided with a metal layer 111, so that the front side 11a and the back side 11b of the chip 11 to be packaged have electrical leads. The lead frame 20 is provided with a hollow area 21, and the hollow area 21 penetrates the lead frame 20 along the thickness direction T, and multiple chips 11 to be packaged are located in the hollow area 21.

[0062] In this embodiment, the thickness of the lead frame 20 is greater than the thickness of the chip 11 to be packaged, so as to protect the chip 11 to be packaged.

[0063] The adhesive layer is used to bond the chip 11 to be packaged and the lead frame 20. The adhesive layer can be made of an easily peelable material so that in subsequent processes, the carrier 3 and the chip 11 to be packaged and the lead frame 20 can be peeled apart. For example, a thermal separation material that can lose its viscosity by heating can be used.

[0064] In other embodiments, the adhesive layer may adopt a two-layer structure, a thermal separation material layer and a chip attachment layer. The thermal separation material layer is attached to the carrier 3 and loses its viscosity when heated, and can be peeled off from the carrier 3, while the chip attachment layer adopts a viscous material layer and can be used to attach the chip to be packaged 11. After the chip to be packaged 11 is peeled off from the carrier 3, the chip attachment layer thereon can be removed by chemical cleaning. In one embodiment, the adhesive layer can be formed on the carrier 3 by lamination, printing, etc.

[0065] There are multiple chips 11 to be packaged. The number of chips 11 to be packaged can be adjusted according to design requirements and is not limited here.

[0066] As mentioned above, since the lead frame 20 is integrally formed, that is, the frame body, connecting portion 24, and edge portion 23 of the lead frame are integrally formed, the frame body, connecting portion 24, and edge portion 23 of the lead frame are positioned and fixed on the carrier at one time, thereby greatly saving production costs and improving overall production efficiency.

[0067] In step 200, as shown in FIG. 5( b), the encapsulation layer 14 is covered on the entire carrier 3, that is, on the chip 11 to be packaged, the lead frame 20 and the exposed carrier 3, and is filled in the hollow area 21 of the lead frame 20, and the chip 11 to be packaged and the lead frame 20 are plastic-encapsulated to form an encapsulation structure 10. The encapsulation structure 10 is a flat structure, and after the carrier 3 is peeled off, rewiring and packaging can continue to be performed on the flat structure.

[0068] The encapsulation structure 10 includes a first surface 10a and a second surface 10b that are arranged opposite to each other. The second surface 10b of the encapsulation structure 10 is arranged opposite to the carrier 3, is substantially flat, and is parallel to the surface of the carrier 3. The first surface 10a of the encapsulation structure 10 exposes the protection layer 30 on the front side of the chip 11 to be packaged, and the first surface 20a of the lead frame 20.

[0069] In one embodiment, the encapsulation layer 14 may be formed by laminating an epoxy resin film or a molding film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0070] Optionally, before entering step 300 , the packaging method further includes mounting a first support plate 41 on the second surface 10 b of the encapsulation structure 10 .

[0071] The first support plate 41 is mounted on at least a portion of the second surface 10b of the encapsulation structure 10. As shown in FIG5(c), in one embodiment, the first support plate 41 is mounted on the second surface 10b of the encapsulation structure 10, and the first support plate 41 covers the entire area of ​​the second surface 10b of the encapsulation structure 10.

[0072] The material strength of the first support plate 41 is greater than the material strength of the encapsulation layer, so that the support plate can effectively improve and ensure the mechanical strength of the encapsulation structure during the encapsulation process, effectively suppress the adverse effects caused by the deformation of each structure, thereby improving the product encapsulation effect. In other embodiments, the support plate can also be formed on the second surface 10b of the encapsulation structure 10 by spraying, printing, coating, etc.

[0073] Next, before entering step 300, as shown in FIG5(d), the packaging method further includes peeling off the carrier 3 to expose the first surface 10a of the packaging structure 10. The first surface 10a of the packaging structure 10 exposes the front side of the chip 11 to be packaged and the first side 20a of the lead frame 20.

[0074] Since the adhesive layer between the carrier 3, the chip to be packaged and the lead frame 20 is a thermal separation film, the adhesive layer can be heated to reduce viscosity after being heated, thereby peeling off the carrier 3. The method of peeling off the carrier 3 by heating the adhesive layer can minimize the damage to the chip to be packaged 11 during the peeling process. In other embodiments, the carrier 3 can also be directly peeled off mechanically.

[0075] After the carrier 3 is peeled off, the first surface 10a of the encapsulation structure 10 facing the carrier 3, the front surface of the chip 11 to be packaged, and the first surface 20a of the lead frame 20 are exposed. After the carrier 3 is peeled off, the first encapsulation structure 10 including the chip 11 to be packaged, the lead frame 20, and the encapsulation layer 14 encapsulating the chip 11 to be packaged and the lead frame 20 is obtained. On the formed encapsulation structure 10, rewiring can be performed according to actual conditions, so that the chip 11 to be packaged is electrically connected to the outside world.

[0076] It should be noted that the step of mounting the first support plate 41 may also be performed after the carrier plate 3 is peeled off.

[0077] Next, before entering step 300, as shown in FIG5(e), a protective layer 30 is formed on the first surface 10a of the encapsulation structure 10. Then, as shown in FIG5(f), a protective layer opening 31 is formed on the protective layer 30 at a position corresponding to the pad on the front surface of the chip 11 to be packaged and at a position corresponding to the first electrical connection point on the first surface 20a of the lead frame 20.

[0078] In this embodiment, since the lead frame 20 and the chip to be packaged 11 are arranged on the same horizontal plane, when the protective layer 30 is punched to form the protective layer opening 31, the protective layer 30 is a transparent film layer. In addition to using the transparency of the protective layer 30 for positioning, the lead frame 20 can also be used to assist in positioning, thereby improving the positioning accuracy of the laser drilling.

[0079] In step 300, as shown in FIG. 5(g), a first rewiring structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the first rewiring structure 50 is electrically connected to the pad on the front side of the chip 11 to be packaged, and is electrically connected to the first electrical connection point on the first side 20a of the lead frame 20. The first rewiring structure 50 includes at least one first rewiring layer 51. In the present embodiment, the first rewiring structure 50 includes one first rewiring layer 51, but is not limited thereto, and may also include multiple first rewiring layers 51 according to design requirements, that is, repeated rewiring is performed on the front side of the chip to be packaged, for example, more rewiring structures may be formed in the same manner, and may be adjusted according to design requirements.

[0080] Since the protective layer opening 31 has been formed on the protective layer 30 , when forming the first rewiring layer 51 , at least the protective layer opening 31 can be directly seen, so that the first rewiring structure 50 can be aligned more accurately when being formed.

[0081] When forming the first rewiring structure 50, a conductive medium can be simultaneously filled in the protective layer opening 31 of the protective layer 30 to form a conductive column 52, that is, the first rewiring layer 51 and the conductive column 52 are formed in the same conductive layer forming process. The conductive column 52 forms a vertical connection structure in the protective layer opening 31, and the pads on the front side 11a of the chip 11 to be packaged are electrically led out through the conductive column 52 and the first rewiring layer 51.

[0082] Next, as shown in FIG5(h), a dielectric layer 60 is formed, and the dielectric layer 60 is formed on the first redistribution structure 50 and the first surface 10a of the exposed encapsulation structure 10. The dielectric layer 60 can be formed by a molding film, or the dielectric layer 60 can be formed by lamination or printing. The dielectric layer 60 can be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound.

[0083] As shown in Fig. 5(i), after forming the dielectric layer 60, the packaging method further includes peeling off the first support plate 41. The first support plate 41 can be peeled off directly mechanically or by other methods, which is not limited in the present application and can be set according to the specific application environment.

[0084] Optionally, after peeling off the first support plate 41 , the packaging method further includes attaching a second support plate 42 to a side of the dielectric layer 60 away from the first surface 10 a of the encapsulation structure 10 .

[0085] The second support plate 42 is mounted on at least a portion of the side of the dielectric layer 60 away from the encapsulation structure 10. As shown in FIG5(j), in one embodiment, the second support plate 42 is mounted on the dielectric layer 60, and the second support plate 42 is mounted on the entire side of the dielectric layer 60 away from the encapsulation structure 10.

[0086] The material strength of the second support plate 42 is greater than the material strength of the dielectric layer 60, so that the support plate can effectively improve and ensure the mechanical strength of the packaging structure during the packaging process, effectively suppress the adverse effects caused by the deformation of each structure, thereby improving the packaging effect of the product. In other embodiments, the support plate can also be formed on the dielectric layer 60 by spraying, printing, coating, etc.

[0087] It should be noted that the step of mounting the second support plate 42 may also be performed before peeling off the first support plate 41 .

[0088] Optionally, as shown in FIG. 5( k ), before forming the second redistribution structure 70 on the second surface 10 b of the encapsulation structure 10, the packaging method further comprises grinding the second surface 10 b of the encapsulation structure 10 to reduce the thickness of the encapsulation structure 10. Preferably, the thickness is reduced to expose the second surface 20 b of the lead frame 20.

[0089] In the thinned encapsulation structure 10 , since the thickness of the lead frame 20 is greater than the thickness of the chip 11 to be packaged, an encapsulation layer 14 of a certain thickness will remain on the back of the chip 11 to protect the chip 11 to be packaged.

[0090] It should be noted that, during packaging, due to the consideration of the process of the chip production stage, the received chip to be packaged may be an ultra-thin chip. In order to ensure that the chip is not damaged, the chip cannot be further thinned by grinding and other processes. At the same time, when the chip 11 is an ultra-thin chip, the lead frame 20 cannot be ground to the same thickness as the chip 11, because if the lead frame 20 is ground too thin, there is a risk of breakage. Therefore, it is necessary to retain a certain thickness of the encapsulation layer 14 on the back of the chip and realize the connection between the back of the chip 11 and the second rewiring structure 70 by drilling. Through the above settings, the present application can be applied to the overall packaging of ultra-thin multi-chips. The ultra-thin multi-chip refers to a chip with a thickness of less than 200 microns.

[0091] Next, as shown in FIG5(l), a plurality of openings 15 are formed on the second surface 10b of the encapsulation structure 10, and the openings 15 are arranged corresponding to the chip to be packaged 11 to expose the back side of the chip to be packaged 11. That is, holes are opened on the encapsulation layer 14 located on the back side of the chip to be packaged 11 to form the openings 15.

[0092] 5(m), a second rewiring structure 70 is formed on the second surface 10b of the encapsulation structure 10. The second rewiring structure 70 is electrically connected to the metal layer 111 on the back of the chip 11 to be packaged and the second electrical connection point on the second surface 20b of the lead frame 20.

[0093] It should be noted that the thickness of the rewiring structure (the second rewiring structure 70) is much smaller than that of the prior art (such as Figure 1 The thickness of the lead frame 30' is generally 15um-45um, and the thickness of the lead frame 30' is generally 150um-450um. Therefore, the rewiring structure not only realizes the wiring function, but also improves the thinness of the product.

[0094] In this embodiment, since the lead frame 20 is electrically connected to the first rewiring structure 50 and the second rewiring structure 70, double-sided interconnection of the front and back sides of the chip 11 to be packaged is achieved, that is, the first rewiring structure 50 located on the first surface 10a of the encapsulation structure 10 and the second rewiring structure 70 located on the second surface 10b of the encapsulation structure 10 are connected through the lead frame 20.

[0095] In this way, the electrical lead-out of the front side 11a and the back side 11b of the chip to be packaged 11, as well as the electrical connection of the electronic components (different multiple chips to be packaged 11) inside the semiconductor packaging structure 1 are realized through the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70. Compared with the prior art in which electrical connection is completed through leads, the semiconductor packaging structure of this embodiment requires less space, especially space in the thickness direction; and, since the electrical connection does not need to be finally concentrated on the pin lead-out of the lead frame, the layout of the rewiring structure is more free and flexible.

[0096] Specifically, the electrical lead-out of the front side 11a of the chip to be packaged 11 is achieved through the electrical connection of the solder pad on the front side 11a of the chip to be packaged 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70 in sequence; the electrical lead-out of the back side 11b of the chip to be packaged 11 is achieved by direct electrical connection with the second rewiring structure 70; the interconnection of different chips to be packaged 11, that is, the interconnection of the same side or the interconnection of different sides, such as the interconnection of the front side of one chip to be packaged 11 and the back side of another chip to be packaged 11, can be achieved through the electrical connection of the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70.

[0097] The second rewiring structure may include at least one second rewiring layer and a pin layer, wherein the pin layer is located on a side of the second rewiring layer away from the encapsulation structure. Alternatively, the second rewiring structure includes only one pin layer according to design requirements. The number of layers of the second rewiring layer may be one layer, or may be adjusted according to design requirements, or may be multiple layers, i.e., repeated rewiring is performed on the back side of the chip to be packaged, such as forming more rewiring structures in the same manner, which may be adjusted according to design requirements.

[0098] The semiconductor package structure 1 is electrically connected to the outside through the pin layer, and the next step of installation is performed through the pin layer.

[0099] The material of the pin layer is tin, but is not limited to tin, and may also be a nickel-gold alloy, or other metals.

[0100] In this embodiment, referring again to FIG. 5( m ), the second redistribution structure 70 includes a pin layer 71 .

[0101] When forming the second rewiring structure 70, a conductive medium can be simultaneously filled in the opening 15 of the encapsulation layer 14 to form a conductive protrusion 72, that is, the pin layer 71 and the conductive protrusion 72 are formed in the same conductive layer forming process. The conductive protrusion 72 forms a vertical connection structure in the opening 15, and the pad on the back side 11b of the chip 11 to be packaged is electrically led out through the conductive protrusion 72 and the pin layer 71.

[0102] Next, the second support plate 42 is peeled off, as shown in Fig. 5(n). The second support plate 42 can be peeled off directly mechanically or by other methods, which are not limited in the present application and can be set according to the specific application environment.

[0103] Optionally, before or after peeling off the second support plate 42 , the process further includes a step of cutting off the frame of the lead frame 20 by laser or mechanical cutting, and the illustration of this step is omitted.

[0104] It should also be noted that if multiple semiconductor packaging structures are packaged together, after the packaging is completed, the entire packaging structure is cut into multiple semiconductor packaging structures by laser or mechanical cutting. The structure diagram of the formed semiconductor packaging structure 1 is shown in FIG. Figure 6 shown.

[0105] like Figure 6 FIG. 2 is a schematic diagram of a semiconductor packaging structure 1 obtained by using the semiconductor packaging method according to the present embodiment. The semiconductor packaging structure 1 includes: an encapsulation structure 10 , a first rewiring structure 50 and a second rewiring structure 70 .

[0106] The encapsulation structure 10 includes a first surface 10a and a second surface 10b relative to each other. The encapsulation structure 10 includes a lead frame 20 and multiple chips 11 and an encapsulation layer 14 for encapsulating the lead frame 20 and the multiple chips 11. The lead frame 20 is provided with a hollow area, and the hollow area penetrates the lead frame 20 along the thickness direction T. The multiple chips 11 are located in the hollow area, and the encapsulation layer 14 is filled in the hollow area of ​​the lead frame 20.

[0107] The number of chips 11 is multiple. The number of chips 11 can be adjusted according to design requirements and is not limited here. In this embodiment, the number of chips 11 is two. The number of hollow areas 21 of the lead frame 20 can be one or more. In this embodiment, the number of hollow areas 21 provided in each lead frame 20 is two, but it is not limited thereto, and the number of hollow areas 21 can be other numbers according to design requirements.

[0108] According to design requirements, the multiple chips 11 may be placed in different hollow areas 21 , or the multiple chips 11 may be placed in the same hollow area 21 .

[0109] The lead frame 20 further includes a connecting portion 24 , which divides the hollow region into a plurality of regions. The chips 11 respectively located in different hollow regions are electrically connected via the connecting portion 24 .

[0110] Specifically, in this embodiment, each lead frame 20 divides the hollow area into two by the connecting portion 24, that is, each lead frame 20 is provided with two hollow areas 21, and the two hollow areas 21 are separated by the connecting portion 24. The two chips 11 are respectively located in two different hollow areas.

[0111] The chip 11 includes a front side with a pad and a back side opposite to the front side, and a metal layer 111 is provided on the back side, so that electrical leads are provided on both the front side and the back side of the chip 11. The first side 20a of the lead frame 20 is exposed on the first surface 10a.

[0112] The first rewiring structure 50 is formed on the first surface 10 a of the encapsulation structure 10 corresponding to the front side of the chip 11 , and is electrically connected to the pad on the front side of the chip 11 and to the first electrical connection point on the first side 20 a of the lead frame 20 .

[0113] The first rewiring structure 50 includes at least one first rewiring layer 51. In the present embodiment, the first rewiring structure 50 includes one first rewiring layer 51, but is not limited thereto, and may also include multiple first rewiring layers 51 according to design requirements, that is, repeated rewiring is performed on the front side of the chip, for example, more rewiring structures may be formed in the same manner, and may be adjusted according to design requirements.

[0114] A protective layer 30 is provided on the front of the encapsulation structure 10, and the protective layer 30 is located between the first redistribution structure 50 and the encapsulation structure 10. A protective layer opening 31 is provided on the protective layer 30, and a conductive column 52 formed by filling a conductive medium is provided in the protective layer opening 31. The first redistribution layer 51 and the conductive column 52 can be formed in the same conductive layer forming process.

[0115] The second rewiring structure 70 is formed on the second surface 10b of the encapsulation structure 10 corresponding to the back side of the chip 11. The second rewiring structure 70 is electrically connected to the metal layer 111 on the back side of the chip 11 and the second electrical connection point on the second side 20b of the lead frame 20. The second rewiring structure 70 includes at least one second rewiring layer 71.

[0116] In this embodiment, since the lead frame 20 is electrically connected to the first rewiring structure 50 and the second rewiring structure 70, double-sided interconnection of the front and back sides of the chip 11 is achieved, that is, the first rewiring structure 50 located on the first surface 10a of the encapsulation structure 10 and the second rewiring structure 70 located on the second surface 10b of the encapsulation structure 10 are connected through the lead frame 20.

[0117] In this way, the electrical lead-out of the front and back sides of the chip 11 and the electrical connection of the electronic components (different multiple chips 11) inside the semiconductor packaging structure 1 are realized through the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70. Compared with the prior art in which electrical connections are completed through leads, the semiconductor packaging structure of this embodiment requires less space, especially space in the thickness direction; and since the electrical connections do not need to be finally concentrated on the pins of the lead frame, the layout of the rewiring structure is more free and flexible.

[0118] Specifically, the electrical lead-out of the front side of the chip 11 is achieved through the electrical connection of the solder pad on the front side of the chip 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70 in sequence; the electrical lead-out of the back side of the chip 11 is achieved by direct electrical connection with the second rewiring structure 70; the interconnection of different chips 11, that is, the interconnection on the same side or the interconnection on different sides, such as the interconnection between the front side of one chip 11 and the back side of another chip 11, can be achieved through the electrical connection of the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70.

[0119] The second rewiring structure may include at least one second rewiring layer and a pin layer, and the pin layer is located on the side of the second rewiring layer away from the encapsulation structure. Alternatively, the second rewiring structure includes only one pin layer according to design requirements. The number of layers of the second rewiring layer can be one layer, or it can be adjusted according to design requirements, or it can be multiple layers, that is, repeated rewiring is performed on the front side of the chip, for example, more rewiring structures can be formed in the same way, which can be adjusted according to design requirements. When the second rewiring structure includes at least one second rewiring layer and a pin layer, the orthographic projection of the pin layer is located within the orthographic projection of the second rewiring layer. That is, the spacing between adjacent pin layers is greater than the spacing between adjacent second rewiring layers corresponding to the adjacent pin layers, so that the final semiconductor package product is not easy to short-circuit when soldered using tin or other materials, thereby improving the electrical performance of the product.

[0120] The semiconductor package structure 1 is electrically connected to the outside through the pin layer, and the next step of installation is performed through the pin layer.

[0121] The material of the pin layer is tin, but is not limited to tin, and may also be a nickel-gold alloy, or other metals.

[0122] In this embodiment, the second redistribution structure 70 includes a pin layer 71 .

[0123] The thickness of the lead frame 20 is greater than that of the chip 11 , and the second surface 20 b of the lead frame 20 is exposed from the second surface 10 b of the encapsulation structure 10 , that is, the thickness of the encapsulation structure 10 is equal to the thickness of the lead frame 20 , thereby achieving the thinnest semiconductor package structure 1 .

[0124] Since the thickness of the lead frame 20 is greater than the thickness of the chip 11 , a certain thickness of the encapsulation layer 14 will remain on the back side of the chip 11 to protect the chip 11 .

[0125] As described above, during packaging, due to the consideration of the process of the chip production stage, the received chip to be packaged may be an ultra-thin chip. In order to ensure that the chip is not damaged, the chip cannot be further thinned by grinding and other processes. At the same time, when the chip 11 is an ultra-thin chip, the lead frame 20 cannot be ground to the same thickness as the chip 11, because if the lead frame 20 is ground too thin, there is a risk of breakage. Therefore, it is necessary to retain a certain thickness of the encapsulation layer 14 on the back of the chip and realize the connection between the back of the chip 11 and the second rewiring structure 70 by drilling. Through the above settings, the present application can be applied to the overall packaging of ultra-thin multi-chips. The ultra-thin multi-chip refers to a chip with a thickness of less than 200 microns.

[0126] The second surface 10b of the encapsulation structure 10 is provided with an opening 15, which is arranged corresponding to the chip 11 to expose the back side of the chip 11. That is, the opening 15 is formed by opening a hole in the encapsulation layer 14 located on the back side of the chip 11. The second rewiring structure 70 further includes a conductive protrusion 72, which is formed by filling a conductive medium in the opening 15, and the conductive protrusion 72 is electrically connected to the back side of the chip 11. The pin layer 71 and the conductive protrusion 72 can be formed in the same conductive layer forming process.

[0127] The encapsulation structure 10 also includes a dielectric layer 60, which is formed on the first rewiring structure 50 and the exposed first surface 10a of the encapsulation structure 10. The dielectric layer 60 can be formed by a molding film, or the dielectric layer 60 can be formed by lamination or printing. The dielectric layer 60 can be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound. When the front side of the chip is repeatedly rewired, more dielectric layers can be formed in the same way, which can be adjusted according to design requirements.

[0128] As shown in Fig. 7(a) and Fig. 7(b), the connection portion 24 of the lead frame 20 includes a first portion 241, a middle portion 242 and a second portion 243 which are connected in sequence, the first portion 241 and the middle portion 242 form a first angle α, and the second portion 243 and the middle portion 242 form a second angle β. In this way, by setting the specific structure of the connection portion 24, a larger connection area can be achieved through the first portion 241 and the second portion 243. Preferably, the first angle α and the second angle β are both equal to 90 degrees, and the first portion 241 and the second portion 243 are parallel to each other, so that the structure of the connection portion 24 is more stable. Preferably, one end of the first portion 241 away from the connection portion 24 and one end of the second portion 243 away from the connection portion 24 are both located on the same side of the connection portion 24, so that the structure of the connection portion 24 is more compact.

[0129] The lead frame 20 also includes a plurality of mutually isolated edge portions 23, one end of the edge portion 23 is exposed on the surface of the encapsulation structure 10, and the other end extends to the hollow area 21; each hollow area 21 is provided with a plurality of mutually isolated edge portions 23. Specifically, the edge portion 23 includes a main body 231 and a support portion 232, one end of the support portion away from the main body 231 is exposed on the surface of the encapsulation structure 10, and the other end is connected to the main body 231. The number of support portions 232 can be one or more. When the number of support portions 232 is more than one, the plurality of support portions 232 are arranged at intervals. The shape of the main body 231 can be square, strip or L-shaped. Preferably, the edge portion 23 of the L-shaped main body 231 is arranged at a corner of the hollow area 21 away from the connecting portion 24.

[0130] As mentioned above, since the lead frame 20 is integrally formed and positioned and encapsulated in the encapsulation structure 10 , the production cost is greatly saved and the overall production efficiency is improved.

[0131] Further, in order to illustrate the connection relationship between the front of the chip 11 and the lead frame 20, and the connection relationship between the back of the chip 11 and the lead frame 20, a schematic diagram of the front connection and a schematic diagram of the back connection of the semiconductor package structure in FIG. 7 (a) and FIG. 7 (b) are provided. In the figure, only a schematic connection is made for the rewiring structure to illustrate the connection relationship. It can be seen that the lead frame 20 is electrically connected to the first rewiring structure 50 and the second rewiring structure 70 to realize the interconnection of the front and back of the chip 11, and it can also realize the double-sided interconnection of different chips 11 (the front of one chip 11 and the back of another chip 11) through the electrical connection of the first rewiring structure 50, the connecting portion 24 of the lead frame 20, and the second rewiring structure 70.

[0132] Specifically, the lead frame 20 in FIG. 7(a) and FIG. 7(b) includes two upper and lower hollow regions 21 in the vertical direction, and a chip 11 is placed in each hollow region 21. In FIG. 7(a), the front surface of the chip 11 in the upper hollow region 21 is electrically connected to the connection portion 24 and one of the edge portions 23 of the upper hollow region 21 through the first rewiring structure 50; the front surface of the chip 11 in the lower hollow region 21 is electrically connected to the two edge portions 23 of the lower hollow region 21 through the first rewiring structure 50. In FIG. 7(b), the back surface of the chip 11 in the upper hollow region 21 is electrically connected to the other two edge portions 23 of the upper hollow region 21 through the second rewiring structure 70; the back surface of the chip 11 in the lower hollow region 21 is electrically connected to the connection portion 24 through the second rewiring structure 70. That is, the front surface of the chip 11 located in the upper hollow area 21 is electrically connected to the back surface of the chip 11 located in the lower hollow area 21 through the first rewiring structure 50 , the connecting portion 24 of the lead frame 20 , and the second rewiring structure 70 in sequence.

[0133] In another embodiment, Figure 8 As shown, the lead frame 20 includes a first portion 27 and a second portion 28 along the thickness direction T from the first surface to the second surface of the encapsulation structure 10, and the width w21 of the first portion 27 is greater than the width w22 of the second portion 28, that is, the lead frame 20 with a structure of a step-shaped cross section is formed. In this way, the relatively wide contact surface of the first portion 27 can be beneficial to provide a relatively large area of ​​support for the first rewiring structure 50 when the first rewiring structure 50 is formed above the lead frame 20; moreover, the step-shaped structure can enhance the bonding force between the lead frame 20 and the encapsulation layer, enhance the strength of the pin layer 80 of the semiconductor package structure on the PCB board, and thus enhance the board-level reliability of the product.

[0134] The semiconductor packaging structure of this embodiment improves the thinness of the product by providing an integral structure, thereby enhancing the electrical reliability of the product.

[0135] Specifically, a hollow area is provided in the lead frame, the hollow area penetrates the lead frame in the thickness direction, and multiple chips are located in the hollow area, that is, the chips are embedded in the lead frame, thereby greatly reducing the thickness of the product and achieving lightweight and thin product.

[0136] Compared with the prior art, it is necessary to set copper pillars to realize the positive double-sided interconnection of the chip. The technical solution in this embodiment directly realizes the double-sided interconnection of the chip through the lead frame, and no copper pillars are needed, thereby increasing the interconnection area, realizing multi-layer wiring process, increasing the freedom of product design, and enhancing the electrical reliability of the product; at the same time, it saves production costs and improves overall production efficiency. It should be noted that in the prior art, if multiple copper pillars are set, not only is the positioning process complicated during the production process, but also because multiple independent copper pillars need to be set, the positioning error will be accumulated; in the present application, since the lead frame is integrally formed, each part of the lead frame is fixed on the carrier board after one positioning, so that it is encapsulated in the encapsulation structure, which greatly saves production costs and improves overall production efficiency.

[0137] By arranging a plurality of chips in the hollow area of ​​the lead frame and encapsulating the chips and the lead frame together, the use of conductive adhesive to fix the chips is avoided, thereby improving the introduction efficiency.

[0138] Compared with the lead frame in the prior art, the lead frame structure of the semiconductor packaging structure of this embodiment is suitable for chips with larger areas and can accommodate more chips, because the lead frame part structure located below the chip is no longer required, and has excellent applicability.

[0139] Example 2

[0140] The contents of the semiconductor packaging method of this embodiment are basically the same as the semiconductor packaging method in Example 1, except that, in the semiconductor packaging method of this embodiment, the step of forming the protective layer 12 is placed before mounting the chip 11 to be packaged and the lead frame 20 on the carrier 3, and the first redistribution structure 50 directly forms the first surface 10a of the encapsulation structure 10.

[0141] Specifically, before step 100, as shown in FIG9(a), a protective layer 12 is formed on the front side of the chip to be packaged 11. The chip to be packaged 11 includes a front side 11a provided with a bonding pad, and a back side 11b arranged relative to the front side 11a, and the back side 11b is provided with a metal layer 111, so that both the front side 11a and the back side 11b of the chip to be packaged 11 have electrical leads.

[0142] As shown in Figure 9(b), protective layer openings 121 are formed on the protective layer 12 at positions corresponding to the soldering pads on the front side 11a of the chip 11 to be packaged, and each protective layer opening 121 is at least corresponding to the soldering pads of the chip 11 to be packaged or the circuits led out from the soldering pads, so that the soldering pads on the front side of the chip 11 to be packaged or the circuits led out from the soldering pads are exposed from the protective layer openings 121.

[0143] In step 100, as shown in FIG9(c), the chip to be packaged 11 with the protective layer 12 formed on the front side and the lead frame 20 are mounted on the carrier 3 through the adhesive layer, with the back side of the chip to be packaged 11 facing upward and the front side facing the carrier 3. The lead frame 20 is provided with a hollow area 21, which penetrates the lead frame 20 along the thickness direction T, and a plurality of chips to be packaged 11 are located in the hollow area 21.

[0144] In step 200, as shown in FIG. 9( d ), the encapsulation layer 14 is covered on the entire carrier 3, that is, on the chip 11 to be packaged, the lead frame 20 and the exposed carrier 3, and is filled in the hollow area 21 of the carrier 3, and the chip 11 to be packaged and the lead frame 20 are plastic-encapsulated to form an encapsulation structure 10. The encapsulation structure 10 is a flat structure, and after the carrier 3 is peeled off, rewiring and packaging can continue to be performed on the flat structure.

[0145] After the carrier 3 is peeled off, as shown in FIG9(e), the surface of the protective layer 12 is exposed. At this time, the chip attachment layer in the adhesive layer still exists on the surface of the protective layer 12. When removed by chemical means, the protective layer 12 can still protect the surface of the chip to be packaged 11 from being damaged. After the adhesive layer is completely removed, if the encapsulation material has been infiltrated before, the surface can be made flat by chemical cleaning or grinding, which is beneficial for the subsequent wiring. If there is no protective layer 12, the surface of the chip to be packaged 11 cannot be treated by chemical means or grinding to avoid damaging the circuit on the front of the chip to be packaged 11.

[0146] In step 300, as shown in FIG. 9(f), a first rewiring structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the first rewiring structure 50 is electrically connected to the pad on the front side of the chip 11 to be packaged, and is electrically connected to the first electrical connection point on the first side 20a of the lead frame 20. The first rewiring structure 50 includes at least one first rewiring layer 51. In the present embodiment, the first rewiring structure 50 includes one first rewiring layer 51, but is not limited thereto, and may also include multiple first rewiring layers 51 according to design requirements, that is, repeated rewiring is performed on the front side of the chip to be packaged, for example, more rewiring structures may be formed in the same manner, and may be adjusted according to design requirements.

[0147] Since the protective layer opening 121 has been formed on the protective layer 12 , when forming the first rewiring layer 51 , at least the protective layer opening 121 can be directly seen, so that the first rewiring structure 50 can be aligned more accurately when being formed.

[0148] When forming the first rewiring structure 50, a conductive medium can be simultaneously filled in the protective layer opening 121 of the chip to be packaged 11 to form a conductive column 52, that is, the first rewiring layer 51 and the conductive column 52 are formed in the same conductive layer forming process. The conductive column 52 forms a vertical connection structure in the protective layer opening 121, and the pads on the front side 11a of the chip to be packaged 11 are electrically led out through the conductive column 52 and the first rewiring layer 51.

[0149] Next, as shown in FIG. 9( g ), a dielectric layer 60 is formed on the first redistribution structure 50 and the first surface 10 a of the exposed encapsulation structure 10. The dielectric layer 60 may be formed by a molding film, or by lamination or printing. The dielectric layer 60 may be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound.

[0150] like Fig.10 As shown, the present embodiment also provides a semiconductor structure 1 manufactured by the semiconductor packaging method. The overall structure of the semiconductor structure 1 of the present embodiment is basically the same as that of the embodiment 1, except that the protective layer 12 is provided on the front of the chip 11, the orthographic projection of the protective layer 12 is the same as the orthographic projection of the chip 11, and the side of the protective layer 12 away from the chip 11 is flush with the first surface 10a of the encapsulation structure 10. That is, in the packaging process, the protective layer is formed on the front of the chip 11 before the chip 11 is mounted on the carrier, so that after the carrier is peeled off, when the residual adhesive layer is removed by chemical means, the protective layer 12 can also protect the surface of the chip 11 from being damaged. After the adhesive layer is completely removed, if the encapsulation material has been infiltrated before, the surface can be made flat by chemical cleaning or grinding, which is beneficial to the subsequent wiring; if there is no protective layer 12, the surface of the chip 11 cannot be treated by chemical means or grinding to avoid damaging the circuit on the front of the chip 11.

[0151] In the present application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0152] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor packaging method, characterized in that: It includes: S1: Mounting a lead frame and a plurality of chips to be packaged on a carrier, with the front of the chips to be packaged facing the carrier, the lead frame being provided with a hollow area, the hollow area penetrating the lead frame along the thickness direction, and the plurality of chips to be packaged being located in the hollow area; the lead frame comprising a connecting portion, and adjacent hollow areas are separated by the connecting portion; S2: Covering the chip to be packaged, the lead frame and the exposed carrier with an encapsulation layer, and filling the hollow area of ​​the lead frame to form an encapsulation structure, wherein the encapsulation structure includes a first surface and a second surface arranged opposite to the first surface, and the front side of the chip to be packaged and the first side of the lead frame are exposed on the first surface; S3: forming a first rewiring structure on the first surface of the encapsulation structure, the first rewiring structure being electrically connected to the front surface of the chip to be packaged and the first surface of the lead frame, and forming a second rewiring structure on the second surface of the encapsulation structure, the second rewiring structure being electrically connected to the back surface of the chip to be packaged and the second surface of the lead frame opposite to the first surface; Among the chips to be packaged in two adjacent hollow areas, the front side of one chip to be packaged is electrically connected to the connecting portion through the first rewiring structure, and the back side of the other chip to be packaged is electrically connected to the connecting portion through the second rewiring structure.

2. The semiconductor packaging method according to claim 1, wherein: The lead frame further comprises a frame body, wherein the frame body is provided with the hollow area penetrating the frame body along the thickness direction; and two ends of the connecting portion are respectively connected to two opposite sides of the frame body.

3. The semiconductor packaging method according to claim 2, wherein: The lead frame further includes a plurality of edge portions isolated from each other, one end of the edge portion is connected to the frame body, and the other end extends to the hollow area; each of the hollow areas is provided with a plurality of edge portions isolated from each other.

4. The semiconductor packaging method according to claim 1, wherein: The thickness of the lead frame is greater than the thickness of the chip to be packaged. Before step S3, the method further includes thinning the first surface of the encapsulation structure until the first surface of the lead frame is exposed.

5. The semiconductor packaging method according to claim 1, wherein: Before step S3, the method includes: A plurality of openings are formed on the second surface of the encapsulation structure, wherein the openings are located directly above the chip to be packaged to expose the back side of the chip to be packaged; In step S3, the second rewiring structure formed on the second surface of the encapsulation structure includes a conductive protrusion formed in the opening, and the conductive protrusion is electrically connected to the back surface of the chip to be packaged.

6. The semiconductor packaging method according to claim 1, wherein: The lead frame includes a first portion and a second portion along a thickness direction from the first surface to the second surface of the encapsulation structure, and the width of the first portion is greater than the width of the second portion.

7. A semiconductor packaging structure, characterized in that: It includes: An encapsulation structure, comprising a first surface and a second surface opposite to each other, the encapsulation structure comprising a lead frame and a plurality of chips and an encapsulation layer for encapsulating the lead frame and the plurality of chips, the lead frame being provided with a hollow region, the hollow region penetrating the lead frame in a thickness direction, the plurality of chips being located in the hollow region, the encapsulation layer being filled in the hollow region of the lead frame, the encapsulation structure comprising a first surface and a second surface arranged opposite to the first surface, the front surface of the chip and the first surface of the lead frame being exposed on the first surface; the lead frame comprising a connecting portion, the connecting portion spacing the hollow region into a plurality of regions; A first rewiring structure, wherein the first rewiring structure is formed on a first surface of the encapsulation structure, and the first rewiring structure is electrically connected to the front surface of the chip and the first surface of the lead frame; A second rewiring structure, wherein the second rewiring structure is formed on the second surface of the encapsulation structure, and the second rewiring structure is electrically connected to the back side of the chip and the second side arranged opposite to the first side; among the chips in two adjacent hollow areas, the front side of one of the chips is electrically connected to the connecting portion through the first rewiring structure, and the back side of the other chip is electrically connected to the connecting portion through the second rewiring structure.

8. The semiconductor package structure according to claim 7, wherein: The lead frame also includes a plurality of mutually isolated edge portions, wherein the edge portions are arranged along the inner periphery of the encapsulation structure, one end of the edge portion is exposed from the surface of the encapsulation structure, and the other end extends to the hollow area; each of the hollow areas is provided with a plurality of mutually isolated edge portions.

9. The semiconductor package structure according to claim 7, wherein: A plurality of openings are formed on the second surface of the encapsulation structure, and the openings are arranged corresponding to the chip. The second rewiring structure includes conductive protrusions, and the conductive protrusions are formed in the openings and electrically connected to the back side of the chip.

10. The semiconductor package structure according to claim 7, wherein: The lead frame includes a first portion and a second portion along a thickness direction from the first surface to the second surface of the encapsulation structure, and the width of the first portion is greater than the width of the second portion.

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