Method for forming capacitor, semiconductor device and fine pattern, and semiconductor device

Abstract

The present invention provides a method for forming a capacitor, a method for forming a semiconductor device, a method for forming a fine pattern, and a semiconductor device, wherein the semiconductor device includes: a transistor on a semiconductor substrate including a first region and a second region, and having a gate structure and an impurity region; a first interlayer insulating film covering the transistor and having a contact plug electrically connected to the impurity region; a capacitor including a lower electrode on the first interlayer insulating film in the second region and electrically connected to the contact plug, a dielectric film covering a surface of the lower electrode, and an upper electrode on the dielectric film; and a support layer contacting an upper side surface of the lower electrode to support the lower electrode and extending to the first region, wherein the support layer has a step between the first region and the second region.

Description

Technical Field

[0001] The present inventive concept relates to a method of forming a capacitor, a method of forming a semiconductor device, a method of forming a fine pattern, and a semiconductor device, and more particularly, to a method of forming a capacitor exhibiting excellent performance, a method of forming a semiconductor device, a method of forming a fine pattern, and a semiconductor device. Background Art

[0002] In order to obtain excellent performance of memory devices, it is necessary to improve the performance of data storage devices. In particular, for DRAMs that store data in capacitors, the performance of the capacitors affects the performance of the memory devices. Summary of the Invention

[0003] The present inventive concept provides a method of forming a capacitor exhibiting excellent performance.

[0004] The inventive concept provides a method of forming a semiconductor device exhibiting excellent performance.

[0005] The present inventive concept provides a method of forming a fine pattern.

[0006] The inventive concept provides a semiconductor device exhibiting excellent performance.

[0007] According to one aspect of the present inventive concept, a method for forming a capacitor is provided, the method comprising: forming a mold layer and a support material layer on a semiconductor substrate including a first region and a second region; forming a mask pattern for patterning the mold layer and the support material layer in the first region and the second region; forming a recessed pattern exposing an upper surface of the semiconductor substrate by using the mask pattern; forming a protective film for lining a surface of the mask pattern and an inner surface of the recessed pattern; removing a portion of the protective film to expose at least the upper surface of the mask pattern; removing the mask pattern by a dry cleaning method; removing a remaining portion of the protective film; forming a lower electrode in the recessed pattern; removing the mold layer; forming a dielectric film on a surface of the lower electrode; and forming an upper electrode on the dielectric film.

[0008] According to another aspect of the present invention, a method for forming a semiconductor device may be provided, the method comprising: forming a transistor in the second region of a semiconductor substrate comprising a first region and a second region, the transistor comprising a gate structure and an impurity region; forming an interlayer insulating film on the semiconductor substrate, the interlayer insulating film covering the transistor and having a contact plug electrically connected to the impurity region; forming a mold layer and a support material layer on the interlayer insulating film; forming a mask pattern for patterning the mold layer and the support material layer in the first region and the second region; forming a recessed pattern for exposing the upper surface of the semiconductor substrate by using the mask pattern; forming a protective film for lining the inner surface of the recessed pattern; removing the mask pattern by a dry cleaning method after forming the protective film; removing the protective film after removing the mask pattern; forming a lower electrode in the recessed pattern; selectively removing the mold layer; forming a dielectric film on a surface of the lower electrode; and forming an upper electrode on the dielectric film.

[0009] According to another aspect of the present invention, a method for forming a fine pattern may be provided, the method comprising: sequentially forming a first material film and a second material film on a semiconductor substrate including a first region and a second region; forming a mask pattern having a first pattern density in the first region and a second pattern density in the second region, wherein the second pattern density may be greater than the first pattern density; forming a recessed pattern by using the mask pattern, wherein the recessed pattern exposes an upper surface of the semiconductor substrate; forming a protective film for lining an inner surface of the recessed pattern; after forming the protective film, removing the mask pattern by a dry cleaning method; after removing the mask pattern, removing the protective film; and forming a conductor in the recessed pattern.

[0010] According to another aspect of the present inventive concept, a semiconductor device may be provided, comprising: a transistor on a semiconductor substrate, the transistor having a gate structure and an impurity region, the semiconductor substrate comprising a first region and a second region; a first interlayer insulating film covering the transistor and having a contact plug electrically connected to the impurity region; a capacitor comprising a lower electrode on the first interlayer insulating film in the second region and electrically connected to the contact plug, a dielectric film covering a surface of the lower electrode, and an upper electrode on the dielectric film; and a support layer contacting an upper side surface of the lower electrode to support the lower electrode and extending to the first region, wherein the support layer has a step between the first region and the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a top view of a schematic configuration of an integrated circuit device according to an example embodiment;

[0013] Figure 2 is a block diagram of an integrated circuit device including a DRAM device;

[0014] Figure 3 is a top view of a schematic configuration of an integrated circuit device according to another example embodiment;

[0015] Figure 4 is a top view of a layout of a semiconductor device according to an example embodiment;

[0016] Figure 5 It is along Figure 4 A sectional view taken along line AA';

[0017] Figure 6 yes Figure 5 A partial enlarged view of part VI;

[0018] Figure 7 shows in detail a portion VI according to another example embodiment;

[0019] Figure 8 shows in detail a portion VI according to another example embodiment;

[0020] Figures 9A to 9L are cross-sectional views sequentially illustrating a method of forming a semiconductor device according to an example embodiment, along Figure 4 The cross-sectional view taken along the line AA' corresponds to:

[0021] Figure 10 is a graph showing the measurement results of the capacitances of capacitors in the experimental example and the comparative example. DETAILED DESCRIPTION

[0022] Embodiments of the present inventive concept will now be described more fully with reference to the accompanying drawings. Throughout the drawings, like reference numerals denote like elements, and redundant descriptions thereof will be omitted.

[0023] Figure 1 is a top view of a schematic configuration of an integrated circuit device 10 according to an example embodiment.

[0024] Integrated circuit device 10 may include substrate 12 including a first region 22, a second region 24 surrounding first region 22, and an interface region 26 between first region 22 and second region 24. For example, interface region 26 may surround first region 22, and second region 24 may surround interface region 26.

[0025] The substrate 12 may include, for example, a semiconductor element such as Is or Ge, or at least one compound semiconductor selected from SiGe, SiC, GaAs, InAs, and InP. The substrate 12 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

[0026] In some embodiments, the first region 22 may include a memory cell region of the integrated circuit device 10. In some embodiments, the first region 22 may include a memory cell region of a dynamic random access memory (DRAM). The first region 22 may include a unit memory cell including a transistor and a capacitor, or a unit memory cell including a switching device and a variable resistor.

[0027] The second region 24 may include a core region or a peripheral circuit region (hereinafter referred to as “peripheral circuit region”). A peripheral circuit for driving the memory cells in the first region 22 may be provided in the second region 24.

[0028] A plurality of conductive lines provided to enable electrical connection between the first region 22 and the second region 24 and an insulating structure for insulation between the first region 22 and the second region 24 may be disposed in the interface region 26 .

[0029] Figure 2 is a block diagram of a configuration of an integrated circuit device including a DRAM device.

[0030] Reference Figure 2 In the integrated circuit device 10, the first region 22 may include a memory cell region of a DRAM device, and the second region 24 may include a peripheral circuit region of the DRAM device. The first region 22 may include a memory cell array 22A. A plurality of memory cells for storing data may be arranged in rows and columns in the memory cell array 22A. Each memory cell may include a cell capacitor and an access transistor. The gate of the access transistor may be connected to a corresponding word line among a plurality of word lines arranged in the row direction. One of the source and drain of the access transistor may be connected to a bit line or a complementary bit line arranged in the column direction, and the other may be connected to a cell capacitor.

[0031] The second region 24 may include a row decoder 52 , a sense amplifier 54 , a column decoder 56 , a self-refresh control circuit 58 , a command decoder 60 , a mode register set / extended mode register set (MRS / EMRS) circuit 62 , an address buffer 64 , and a data input / output circuit 66 .

[0032] The sense amplifier 54 can sense and amplify data of memory cells in the memory cell array 22A and store the data in the memory cells. The sense amplifier 54 can be implemented by a cross-coupled amplifier connected between a bit line and a complementary bit line included in the memory cell array 22A.

[0033] Data DQ input through the data input / output circuit 66 can be written to the memory cell array 22A based on the address signal ADD, and data DQ read from the memory cell array 22A based on the address signal ADD can be output to the outside through the data input / output circuit 66. In order to allocate memory cells to write or read data, the address signal ADD can be input to the address buffer 64. The address buffer 64 can temporarily store the address signal ADD input from the outside.

[0034] The row decoder 52 can decode the row address of the address signal ADD output from the address buffer 64 to allocate a word line connected to a memory cell to which data is input or output. For example, in a data write or read mode, the row decoder 52 can decode the row address output from the address buffer 64 to enable the corresponding word line. In addition, in a self-refresh mode, the row decoder 52 can decode the row address generated by an address counter (not shown) to enable the corresponding word line.

[0035] The column decoder 56 can decode the column address of the address signal ADD output from the address buffer 64 to allocate a bit line connected to a memory cell to which data is input or output. The memory cell array 22A can output data from the memory cell allocated by the row address and the column address, or can write data to the memory cell.

[0036] The command decoder 60 may receive a command signal CMD applied from the outside and may internally generate a decoded command signal (eg, a self refresh entry command or a self refresh exit command) by decoding the signal.

[0037] The MRS / EMRS circuit 62 may set an internal mode register in response to the address signal ADD and the MRS / EMRS command to assign an operation mode of the integrated circuit device 10 .

[0038] Although not in Figure 2 Although not shown in FIG. 1 , the integrated circuit device 10 may further include: a clock circuit for generating a clock signal; and a power supply circuit for generating or distributing an internal voltage by receiving a power supply voltage applied from the outside.

[0039] In response to a command output from the command decoder 60, the self-refresh control circuit 58 can control the self-refresh operation of the integrated circuit device 10. Although not shown, the command decoder 60 may include an address counter, a timer, and a core voltage generator. In response to a self-refresh entry command output from the command decoder 60, the address counter can generate a row address to allocate a row address subject to self-refresh and apply the row address to the row decoder 52. The address counter can interrupt the counting operation in response to a self-refresh exit command output from the command decoder 60.

[0040] Figure 3 is a top view of a schematic configuration of an integrated circuit device 70 according to another example embodiment. Figure 1 and Figure 3 1 and 2. In the present invention, like reference numerals denote like elements, and detailed descriptions thereof are omitted.

[0041] Reference Figure 3 , the integrated circuit device 70 may include a plurality of first regions 22. Each first region 22 may be surrounded by a second region 24 with an interface region 26 therebetween. In the integrated circuit device 70, each first region 22 may be a memory cell array area MCA of a DRAM device, and the second region 24 may include a peripheral circuit region of the DRAM device.

[0042] In the first region 22, the memory cell array region MCA may include a reference Figure 2 Memory cell array 22A is depicted. Each first region 22 may be surrounded by an interface region 26 .

[0043] The second region 24 may include a sub-wordline driver block SWD, a sense amplifier block S / A, and a junction block CJT. In the second region 24, multiple sub-wordline driver blocks SWD may be arranged along the wordlines of the memory cell array area MCA, and multiple sense amplifier blocks S / A may be arranged along the bitlines. Multiple bitline sense amplifiers may be arranged in the sense amplifier blocks S / A. The junction block CJT may be located at the intersection of the sub-wordline driver block SWD and the sense amplifier block S / A. Ground drivers and power drivers for driving the bitline sense amplifiers may be alternately arranged in the junction block CJT.

[0044] Although not in Figure 3 Although not shown in FIG, a peripheral circuit such as an inverter chain or an input / output circuit may be further provided in the second region 24.

[0045] Figure 4 is a top view of a layout of a semiconductor device 1 according to an example embodiment. Figure 5 It is along Figure 4 A cross-sectional view taken along line AA'.

[0046] Reference Figure 4 and Figure 5 The semiconductor substrate 100 may include a first region R1 and a second region R2. For example, the first region R1 may include a peripheral circuit region, and the second region R2 may include a cell region.

[0047] In some embodiments, peripheral circuits including row and column decoders, page buffers, and input / output circuits may be disposed on the semiconductor substrate 100 in the first region R1. In some embodiments, the peripheral circuits may include CMOS transistors, resistors, and capacitors electrically connected to the memory cell array.

[0048] In some embodiments, a memory cell array including a plurality of memory cells may be disposed on the semiconductor substrate 100 in the second region R2. The memory cell array may include a plurality of memory cells and a plurality of word lines WL and bit lines BL electrically connected to the memory cells. In some embodiments, each memory cell may include a capacitor 150, which includes a lower electrode 151, an upper electrode 155, and a dielectric film 153 therebetween. For example, the dielectric film 153 may contact the upper and side surfaces of the lower electrode 151, or the dielectric film 153 may contact the upper, lower, and side surfaces of the upper electrode 153. Furthermore, since the support layer 157 horizontally connects the lower electrode 151 of the memory cell, the lower electrode 151 may be prevented from collapsing. The upper surface of the support layer 157 may contact the lower surface of the dielectric film 153, and the side surfaces of the support layer 157 may contact the side surfaces of the upper portion of the lower electrode 151. In some embodiments, the support layer 157 may surround the upper portion of the lower electrode 151.

[0049] In detail, a device isolation layer 101 defining active regions ACT may be formed on the semiconductor substrate 100 in the second region R2. Each active region ACT may have a bar shape, and a major axis of each active region ACT may be disposed in a direction inclined with respect to the word line WL and the bit line BL.

[0050] The word line WL may be provided across the active area ACT. In some embodiments, the word line WL may be formed by providing a gate insulating film GI in a recessed region recessed to a certain depth from the surface of the active area ACT. In addition, the upper surface of the word line WL may be located at a lower level than the upper surface of the active area ACT, and the recessed region where the word line WL is formed may be filled with a cap layer 104 including an insulating material.

[0051] A plurality of impurity regions 103, such as source and drain regions, may be formed in the active region ACT on both sides of the word line WL. The impurity regions 103 may form a plurality of MOS transistors with the word line WL. For example, each of the plurality of MOS transistors may include an impurity region 103 and a gate structure including a gate insulating film GI, the word line WL, and a cap layer 104.

[0052] Bit lines BL may be arranged on the semiconductor substrate 100 in the second region R2, crossing the word lines WL. Each bit line BL may include a conductive line 106, a capping layer 107, and a spacer 108. A first interlayer insulating film 110 may be between the bit lines BL and the semiconductor substrate 100. Bit line contact plugs DC electrically connecting the impurity regions 103 to the bit lines BL may be formed in the first interlayer insulating film 110.

[0053] The first interlayer insulating film 110 may include a high-density plasma (HDP) oxide film, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), O3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), polysilazane, or a combination thereof. Alternatively, the first interlayer insulating film 110 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0054] In addition, the device isolation layer 101 may define a peripheral active region in the semiconductor substrate 100 in the first region R1. A peripheral gate electrode structure PG may be provided across the peripheral active region, and peripheral source and drain regions 105 may be formed in the peripheral active region on both sides of the peripheral gate electrode structure PG. The peripheral gate electrode structure PG may include a gate insulating layer 111, a gate electrode 112, a gate cap layer 113, and spacers 114.

[0055] The second interlayer insulating film 120 may cover the bit lines BL of the second region R2 and the peripheral gate electrode structure PG of the first region R1. The second interlayer insulating film 120 may include an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, polysilazane, or a combination thereof. Alternatively, the second interlayer insulating film 120 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0056] A plurality of contact plugs BC electrically connecting the data storage element (i.e., capacitor 150) to the impurity region 103 may be formed in the second interlayer insulating film 120 of the second region R2. In some embodiments, the contact plugs BC may be disposed in the active region ACT on both sides of each bit line BL. Furthermore, when viewed from above, the contact plugs BC may be arranged in the form of a continuous regular triangle, a honeycomb, or a zigzag shape.

[0057] Furthermore, the contact plug BC may be formed by forming a contact hole exposing the impurity region 103 in the second interlayer insulating film 120, depositing a conductive layer for burying the contact hole, and planarizing and node-isolating the conductive layer. The contact plug BC may include any one of an impurity-doped polysilicon layer, a metal layer, a conductive metal nitride layer, and a metal silicide layer, or a combination thereof.

[0058] In some embodiments, a plurality of contact pads CP may be formed on the contact plugs BC, respectively. The contact pads CP may be two-dimensionally arranged on the second interlayer insulating film 120 of the second region R2. The contact pads CP may increase the contact area between the lower electrode 151 of the capacitor 150 formed thereon and each contact plug BC. The top surface of the contact pad CP may contact the bottom surface of the corresponding lower electrode 151, and the bottom surface of the contact pad CP may contact the top surface of the corresponding contact plug BC. The contact pads CP may have a shape in which two adjacent contact pads CP extend in opposite directions with respect to each bit line BL therebetween.

[0059] The third interlayer insulating film 130 may be formed between the contact pads CP. The third interlayer insulating film 130 may be formed on the top surface of the second interlayer insulating film 120. The top surface of the third interlayer insulating film 130 may be coplanar with the top surface of the contact pads CP, and the bottom surface of the third interlayer insulating film 130 may be coplanar with the bottom surface of the contact pads CP. The third interlayer insulating film 130 may include an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, polysilazane, or a combination thereof. Alternatively, the third interlayer insulating film 130 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0060] The lower electrode 151 of the capacitor 150 may be formed on each contact pad CP. In some embodiments, the lower electrodes 151 may be arranged in the form of continuous regular triangles, honeycombs, or zigzags when viewed in a top plan view.

[0061] The lower electrode 151 may be supported by a support layer 157. The lower electrode 151 may have a high aspect ratio of about 10 to 40, and when the support layer 157 is omitted, the lower electrode 151 may fall sideways and collapse, or may contact an adjacent lower electrode 151. Therefore, in order to prevent the collapse of the lower electrode 151, the support layer 157 is provided, thereby preventing the lower electrode 151 from falling sideways or collapsing.

[0062] The support layer 157 may have a step ST between the first and second regions R1 and R2. The “step” may mean that there is a level difference between the upper surfaces of the support layer 157 in the first and second regions R1 and R2, which will be described in detail below.

[0063] The dielectric film 153 may be conformally formed on the surface of the lower electrode 151. For example, the dielectric film 153 may be formed on the upper surface and side surfaces of the lower electrode 151 and the support layer 157. The upper electrode 155 may be formed on the dielectric film 153. After the capacitor 150 is formed in the second region R2, an embedded insulating film 160 covering the first region R1 and the second region R2 may be formed.

[0064] Figure 6 yes Figure 5 A magnified partial view of region VI.

[0065] Reference Figure 6 The support layer 157 may have a step ST between the first region R1 and the second region R2. The support layer 157 may include a first sublayer 157a, a second sublayer 157b, and a third sublayer 157c.

[0066] The first sublayer 157a is not particularly limited and may include a material having sufficient etching selectivity relative to a mask pattern provided to form a pattern on the support layer 157. For example, the first sublayer 157a may include silicon nitride, silicon carbide, silicon carbon nitride (SiCN), or a combination thereof. The second sublayer 157b may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In particular, the second sublayer 157b may be doped with at least one element such as boron (B), carbon (C), and aluminum (Al). The third sublayer 157c may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. For example, in one example, the second sublayer 157b may include a boron-doped silicon nitride layer, and the first sublayer 157a may include a silicon carbon nitride (SiCN) layer.

[0067] The upper surface of the supporting layer 157 has a first level L1 in the second region R2 and a second level L2 in the first region R1. The second level L2 may be higher than the first level L1, and the height difference H1 therebetween may be about 2 nm to about 20 nm or about 3 nm to about 10 nm. The portion of the upper surface of the supporting layer 157 having the first level L1 and the portion of the upper surface of the supporting layer 157 having the second level L2 may be connected by a vertical sidewall of the supporting layer 157. The vertical sidewall of the supporting layer 157 may be at the boundary between the first region R1 and the second region R2.

[0068] In some embodiments, the second sublayer 157b and the third sublayer 157c may have a substantially constant thickness throughout the first region R1 and the second region R2. As used herein, thickness may refer to a thickness or height measured in a direction perpendicular to the top surface of the substrate 100. In this case, the level difference and thickness difference of the support layer 157 between the first region R1 and the second region R2 may be generated by the level difference and thickness difference of the first sublayer 157a. The step of the support layer 157 between the first region R1 and the second region R2 may be substantially the same as the step of the first sublayer 157a between the first region R1 and the second region R2.

[0069] In some embodiments, the first level L1 may be Figure 5 The level of the upper end of the lower electrode 151 is substantially the same. In some embodiments, the upper surface of the support layer 157 in the second region R2 can be on substantially the same plane (coplanar) as the upper surface of the lower electrode 151. As used herein, when referring to orientation, layout, position, shape, size, quantity or other metrics, terms such as "same", "equal", "flat" or "coplanar" do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity or other metrics, but are intended to cover almost the same orientation, layout, position, shape, size, quantity or other metrics within an acceptable variation that may occur, for example, due to a manufacturing process. The term "substantially" can be used here to emphasize this meaning unless the context or other statements indicate otherwise. For example, items described as "substantially the same", "substantially equal" or "substantially flat" can be exactly the same, equal or flat, or can be the same, equal or flat within an acceptable variation that may occur, for example, due to a manufacturing process.

[0070] Figure 7 Region VI according to another embodiment is shown in detail. In addition to further providing a lower support layer 158, Figure 7 The implementation method and Figure 6 Therefore, the following description focuses on the differences.

[0071] Reference Figure 7 , when the lower support layer 158 is further provided, the lower electrode 151 can be well supported. Figure 7 Two support layers 157 and 158 are shown, but more support layers may be provided.

[0072] The lower supporting layer 158 may include silicon nitride, silicon carbide, silicon carbonitride (SiCN), or a combination thereof.

[0073] Figure 8 Region VI according to another embodiment is shown in detail.

[0074] Reference Figure 8 , the step ST between the first region R1 and the second region R2 may be a step ST having a gradually changing level around the boundary between the first region R1 and the second region R2. Figure 8 As shown, the support layer 157 may have an upper surface level that gradually changes within a certain horizontal length TZ around a boundary between the first region R1 and the second region R2.

[0075] As described in detail below, since when the recessed pattern is formed by using the mask pattern (190m) (see Figure 9D ) occurs, a step ST is generated between the first region R1 and the second region R2. Therefore, although the step ST can be generated between the first region R1 and the second region R2 as a steep step (for example, Figure 6 and Figure 7 ), but when the load effect is gradually manifested, the step ST may be manifested in the form of a gradual level change.

[0076] Figures 9A to 9L are cross-sectional views sequentially illustrating a method of forming a semiconductor device according to an example embodiment, along Figure 4 The cross-sectional view taken along line AA' in FIG.

[0077] Reference Figure 9A , a semiconductor substrate 100 including a first region R1 and a second region R2 can be provided. Figure 5 The semiconductor substrate 100 is described in detail, and thus a description thereof is omitted.

[0078] An active area ACT can be defined by forming a device isolation layer 101 in a semiconductor substrate 100. A gate insulating film GI and word lines WL can be formed after forming a recess extending across the active area ACT. A cap layer 104 comprising an insulating material can be formed over the word lines WL. Furthermore, impurity regions 103 can be formed by implanting impurities into the active area ACT on both sides of each word line WL. The impurity regions 103 can function as source or drain regions. The word lines WL and the source and drain regions can constitute a transistor device.

[0079] Reference Figure 9B The first interlayer insulating film 110 may be formed to completely cover the active area ACT. The first interlayer insulating film 110 may be provided with a bit line contact plug DC, which may be later electrically connected to the bit line BL. The first interlayer insulating film 110 may include silicon oxide. Each bit line BL may include a conductive line 106, a capping layer 107, and a spacer 108.

[0080] In addition, a peripheral gate electrode structure PG may be formed in the first region R1, and a transistor for a peripheral circuit region may be provided by forming impurity regions 105 on both sides of the peripheral gate electrode structure PG. The peripheral gate electrode structure PG may include a gate insulating layer 111, a gate electrode 112, a gate capping layer 113, and a spacer 114.

[0081] After the bit line BL is formed to be electrically connected to the bit line contact plug DC, the second interlayer insulating film 120 may be formed to cover the bit line BL. A contact plug BC may be provided in the second interlayer insulating film 120. The contact plug BC may penetrate the first interlayer insulating film 110 and the second interlayer insulating film 120 to be electrically connected to the impurity region 103.

[0082] Each of the contact plug BC and the bit line contact plug DC may independently include doped polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof.

[0083] exist Figure 9B Although the bit line contact plug DC connected to the bit line BL is not seen, when a person skilled in the art intercepts the bit line contact plug DC connected to the bit line BL, Figure 9B In another suitable cross section different from the cross section of FIG. 1 , a bit line contact plug connected to the bit line BL can be seen.

[0084] Next, a third interlayer insulating film 130 may be formed to cover the second interlayer insulating film 120. A contact pad CP may be provided in the third interlayer insulating film 130. The contact pad CP may be in contact with the contact plug BC. Figure 9B , the contact pad CP not shown as being in contact with the contact plug BC may be a contact pad electrically connected to the contact plug BC farther from the cross section in the viewing direction.

[0085] Reference Figure 9C , a mold layer 140 and a support material layer 157a can be formed on the third interlayer insulating film 130. The mold layer 140 may include, for example, silicon oxide and may be formed, for example, by chemical vapor deposition (CVD). For example, the mold layer 140 may include a borophosphosilicate glass (BPSG) film or an undoped silicate glass (USG) film. The thickness of the mold layer 140 may be defined by the distance from the lower surface of the mold layer 140 to its upper surface and may be determined by considering the height of the capacitor lower electrode to be formed. For example, the thickness of the mold layer 140 may be approximately 200 nm to approximately 4000 nm.

[0086] The support material layer 157a may include a material having sufficient etching selectivity with respect to the mold layer 140. Also, the support material layer 157a may include a material having a relatively low etching rate in an etching atmosphere for removing the mold layer 140 in a subsequent process (e.g., in an etchant stripping process using ammonium fluoride (NH4F), hydrofluoric acid (HF), and water).

[0087] In some embodiments, the support material layer 157a may include silicon nitride, silicon carbonitride, silicon oxide, silicon germanium (SiGe), tantalum oxide, titanium oxide, or a combination thereof, but the constituent material of the support material layer 157a is not limited thereto.

[0088] In some embodiments, the support material layer 157a may have a multi-film structure. For example, the support material layer 157a may have a multi-film structure in which at least two films selected from silicon nitride films, silicon carbonitride films, tantalum oxide films, and titanium oxide films are sequentially stacked.

[0089] The support material layer 157 a may have a thickness of, for example, about 100 nm to about 1000 nm.

[0090] Reference Figure 9D A mask pattern 190m may be formed on the support material layer 157a. In some embodiments, the mask pattern 190m may be a hard mask pattern. In some embodiments, the mask pattern 190m may include polysilicon, silicon nitride, silicon oxide, silicon oxynitride, a spin-on hard mask (SOH), an amorphous carbon layer (ACL), or a combination thereof.

[0091] Mask pattern 190m can be obtained by forming a layer of mask pattern material film and then applying a photolithography method thereto. Specifically, a layer of mask pattern material film is formed and a photoresist pattern is formed thereon by photolithography. Then, the mask pattern material film is patterned using the photoresist pattern as an etching mask, thereby forming mask pattern 190m. After obtaining mask pattern 190m, the photoresist pattern can be removed by a method such as ashing.

[0092] The mask pattern 190m may have a higher pattern density in the second region R2 than in the first region R1. For example, the pattern density of the mask pattern 190m in the second region R2 may be greater than the pattern density of the mask pattern 190m in the first region R1. Figure 9D , a plurality of recessed patterns RM are shown to be formed in the mask pattern 190m of the second region R2. Figure 9D , the recessed pattern RM formed in a portion of the second region R2 close to the first region R1 but not visible in the cross section is indicated by a dotted line.

[0093] Reference Figure 9E , a recess pattern RS can be formed at a location where a lower electrode is to be formed by patterning the support material layer 157a and the mold layer 140 using the mask pattern 190m as an etching mask. The recess pattern RS can expose each contact pad CP. When the contact pad CP is not formed, the recess pattern RS can expose the contact plug BC at a location corresponding to the lower electrode.

[0094] The recess pattern RS may be formed by anisotropic etching. The anisotropic etching may be performed by a method such as HDP etching, reactive ion etching, sputter etching, or reactive ion beam etching. However, the present invention is not limited thereto.

[0095] The width of each recessed pattern RS may be constant according to its height, or may increase as it moves away from the semiconductor substrate 100. For example, the width of the recessed pattern RS may be substantially the same along its entire length, or may increase toward the upper portion of the recessed pattern RS. For example, the width of the pattern of the mold layer 140 may be constant along its entire length, or may decrease as it moves away from the semiconductor substrate 100.

[0096] By partially removing the upper portion of the mask pattern 190m due to the anisotropic etching for forming the recess pattern RS, a recess pattern having Figure 9E The mask pattern 190 is shaped as shown. Figure 9E As shown, it can be seen that the height or amount of the mask pattern 190 remaining in the first region R1 is greater than the height or amount of the mask pattern 190 remaining in the second region R2.

[0097] Although the present inventive concept is not intended to be limited to a particular theory, the height difference of the mask pattern 190 depending on the area may be based on a loading effect. In detail, in the first region R1 where the pattern density is relatively low, Figure 9D The mask pattern 190m exhibits a relatively two-dimensional removal, however, in the second region R2 where the pattern density is relatively high, Figure 9D The mask pattern 190m exhibits relatively three-dimensional removal. Therefore, the removal rate of the mask pattern 190m in the second region R2 may be faster than the removal rate of the mask pattern 190m in the first region R1. As a result, the thickness of the mask pattern 190 in the first region R1 may be greater than the thickness of the mask pattern 190 in the second region R2.

[0098] like Figure 9E As shown, the mask pattern 190 may have an upper surface with a relatively sharp change in height around the boundary between the first region R1 and the second region R2. However, when the loading effect occurs more gradually between the first region R1 and the second region R2, the upper surface of the mask pattern 190 may change with a gentler slope over a longer distance in the horizontal direction.

[0099] For subsequent processes, the mask pattern 190 can be selectively removed by etching. However, since the thickness of the mask pattern 190 in the first region R1 is greater than the thickness of the mask pattern 190 in the second region R2, the remaining portion of the mask pattern 190 in the first region R1 can continue to be removed for a certain period of time even after the removal of the mask pattern 190 in the second region R2 is completed. For example, the removal of the mask pattern 190 in the second region R2 can be completed earlier than the removal of the mask pattern 190 in the first region R1. While the remaining portion of the mask pattern 190 in the first region R1 is removed for a certain period of time, the support layer 157 in the second region R2 can be partially removed.

[0100] When the mask pattern 190 is removed by dry etching according to the related art, since the etching selectivity of the remaining mask pattern 190 in the first region R1 relative to the supporting layer 157 in the second region R2 is relatively low, the supporting layer 157 in the second region R2 may be substantially etched and removed. Since the upper end portion of the lower electrode of the resulting capacitor is substantially at the same level as the upper surface of the supporting layer 157 of the cell region (corresponding to the second region R2), the substantial removal of the supporting layer 157 results in a significant reduction in the height of the capacitor, which results in a reduction in the capacitance of the formed capacitor.

[0101] In the present embodiment, the mask pattern 190 is removed by using dry cleaning instead of dry etching according to the related art. When dry cleaning is used, since the etching selectivity of the remaining mask pattern 190 in the first region R1 with respect to the support layer 157 in the second region R2 is quite high, the loss of the support layer 157 in the second region R2 due to dry cleaning is negligible.

[0102] However, when dry cleaning is used, it is observed that the mold layer 140 is damaged. Therefore, in order to prevent damage to the mold layer 140, a protective film may be formed in the recessed pattern RS. Figure 9F describe.

[0103] Reference Figure 9F , a protection film 170 for lining the inner surface of the recess pattern RS may be formed. In some embodiments, the protection film 170 may be formed not only on the inner surface of the recess pattern RS but also on the exposed surface of the mask pattern 190.

[0104] The protective film 170 may include a material that survives dry cleaning without being removed. For example, the protective film 170 may include a metal nitride, such as titanium nitride (TiN) or tungsten nitride (WN), but the inventive concept is not limited thereto.

[0105] The protective film 170 may be formed by using a method such as CVD or atomic layer deposition (ALD), but the inventive concept is not limited thereto. When the ALD method is used, the protective film 170 may be relatively conformally formed on the inner surface of the recess pattern RS.

[0106] The protective film 170 may have a thickness of, for example, about 0.7 nm to about 5 nm. If the thickness of the protective film 170 is too small, the function of protecting the inner surface of the recessed pattern RS may be poor. On the other hand, if the thickness of the protective film 170 is too large, the manufacturing time may be prolonged and the possibility of particle contamination may increase.

[0107] Reference Figure 9G , at least a portion of the mask pattern 190 may be exposed by partially removing the protection film 170 .

[0108] In some embodiments, the protection film 170 may be partially removed by etch-back and / or chemical mechanical polishing (CMP).

[0109] When the protective film 170 is etched back in the second region R2, as shown in FIG. Figure 9G As shown, the upper surface of the mask pattern 190 may be exposed while lining the inner surface of the recess pattern RS.

[0110] When the protection film 170 is etched back in the first region R1, most of the protection film 170 is etched and removed, and only a portion of the protection film 170 may remain on the sidewall of the mask pattern 190.

[0111] Reference Figure 9H , the mask pattern 190 may be removed by dry cleaning.

[0112] Dry cleaning may be performed by using plasma gas including radicals of a substance such as fluorine without applying a bias voltage. Therefore, in dry cleaning, the mask pattern 190 may be removed isotropically. In some embodiments, in dry cleaning, the plasma gas may not include ions of the substance.

[0113] The plasma gas including radicals of the species may be supplied to the mask pattern 190 after being generated by a remote method, but the present invention is not limited thereto. In some embodiments, the fluorine radicals in the plasma gas may remove the mask pattern 190 by dry cleaning by reacting with silicon in the polysilicon forming the mask pattern 190 as follows.

[0114] Si+4F→SiF4

[0115] For example, C 3 F 8 , C 2 F 6 , or CF 4 may be used as a supply source of fluorine, but the present inventive concept is not limited thereto.

[0116] In some embodiments, when dry cleaning is used, the etch selectivity of the remaining mask pattern 190 in the first region R1 with respect to the supporting layer 157 in the second region R2 may be about 500:1 to about 1000:1 or about 700:1 to about 900:1.

[0117] In detail, as mentioned above Figure 9E As described above, since the thickness of the mask pattern 190 in the first region R1 is greater than the thickness of the mask pattern 190 in the second region R2, the mask pattern 190 remaining in the first region R1 may continue to be removed for a certain period of time even after the mask pattern 190 is completely removed in the second region R2. While the mask pattern 190 remaining in the first region R1 is removed for the certain period of time, the support layer 157 may be partially removed in the second region R2.

[0118] In this state, with respect to the same period, the amount of the remaining mask pattern 190 removed in the first region R1 and the amount of the supporting layer 157 removed in the second region R2 by dry cleaning may be about 500:1 to about 1000:1 or about 700:1 to about 900:1.

[0119] In some embodiments, while the remaining mask pattern 190 in the first region R1 is removed for the certain period of time, the height of the support layer 157 lost due to dry cleaning in the second region R2 may be about 2 nm to about 20 nm or about 3 nm to about 10 nm.

[0120] For example, while the remaining mask pattern 190 in the first region R1 is removed for a certain period of time, the support layer 157 is lost in the second region R2 due to dry cleaning, and the step ST (see FIG. Figure 5 ) is generated between the first region R1 and the second region R2. Therefore, the size of the step between the first region R1 and the second region R2 can be substantially the same as or at least proportional to the height of the support layer 157 lost due to dry cleaning. In some embodiments, the size of the step between the first region R1 and the second region R2 can be about 2 nm to about 20 nm or about 3 nm to about 10 nm.

[0121] When the size of the step between the first region R1 and the second region R2 is within a specific range, for example, less than or equal to 20 nm, less than or equal to 10 nm, less than or equal to 8 nm, less than or equal to 6 nm, less than or equal to 5 nm, or less than or equal to 3 nm, the amount of loss of the support layer 157 during the removal of the remaining mask pattern 190 in the first region R1 is relatively small, which is conducive to forming a capacitor with high capacitance. For example, when the size of the step between the first region R1 and the second region R2 is too large, it may be difficult to form a capacitor with high capacitance.

[0122] As in Figure 9E As described in the description of , when the loading effect further gradually occurs between the first region R1 and the second region R2, and thus the upper surface of the mask pattern 190 changes with a gentler slope over a longer distance in the horizontal direction, the upper surface of the support layer 157 obtained by dry cleaning can have a gently changing step. For example, after forming the recessed pattern RS, the thickness of the mask pattern 190 in the first region R1 is greater than the thickness of the mask pattern 190 in the second region R2, and the thickness of the mask pattern 190 gradually changes therebetween, and this gradual change can be similarly transferred to the upper surface of the support layer 157. As a result, as Figure 8 As shown, a support layer 157 can be obtained having an upper surface level that gradually changes within a certain horizontal length TZ.

[0123] Reference Figure 9I , the protective film 170 can be removed by wet stripping.

[0124] The protective film 170 can be removed by using a wet etchant such as a sulfuric acid peroxide mixture (SPM), a hydrochloric acid peroxide mixture (HPM), an ammonium peroxide mixture (APM), or fluorine. SPM can be a mixture of sulfuric acid and an aqueous hydrogen peroxide solution. HPM can be a mixture of hydrochloric acid and an aqueous hydrogen peroxide solution. APM can be a mixture of ammonium hydroxide and an aqueous hydrogen peroxide solution. Fluorine can be diluted with deionized water and mixed with a surfactant. However, the present invention is not limited thereto.

[0125] Reference Figure 9J , a lower electrode 151 can be formed.

[0126] The lower electrode 151, which is a conductor, may completely fill the interior of the recessed pattern RS. The lower electrode 151 may include cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium silicon nitride (TiSiN), tungsten nitride (WN), platinum oxide (PtO), ruthenium oxide (RuOx), iridium oxide (IrOx), SRO (SrRuO3), BSRO ((Ba, Sr)RuO3), CRO (CaRuO3), LSCO ((La, Sr)CoO3), or a combination thereof. However, the material of the lower electrode 151 is not limited to the above materials.

[0127] The lower electrode 151 may be formed by a method such as CVD, metal organic CVD (MOCVD), or atomic layer deposition (ALD). The material for forming the lower electrode 151 may be formed on the upper surface of the support layer 157 between the recessed patterns RS, which may be removed by using an etch-back process or CMP. The material for forming the lower electrode 151 may be located only inside the recessed pattern RS.

[0128] Reference Figure 9K , the mold layer 140 is removed, and a dielectric film 153 may be formed on surfaces of the lower electrode 151 and the support layer 157 .

[0129] The mold layer 140 may be removed by a wet method through the plurality of holes formed in the support layer 157. For example, the mold layer 140 may be removed by a lift-off process using an etchant such as fluorine. After removing the mold layer 140, the lower electrode 151 may be supported by the support layer 157.

[0130] The dielectric film 153 may be conformally formed on the surface of the lower electrode 151 exposed by removing the mold layer 140. In this state, the dielectric film 153 may be formed on the exposed surface of the support layer 157. The dielectric film 153 may not be formed on a portion of the surface of the lower electrode 151 that contacts the support layer 157.

[0131] The dielectric film 153 may include a nitride, an oxide, a metal oxide, or a combination thereof. For example, the dielectric film 153 may have a single film or multi-film structure including silicon nitride, silicon oxide, a metal oxide (such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2), a dielectric material having a perovskite structure (such as STO (SrTiO3), BST ((Ba, Sr)TiO3), BaTiO3, PZT, or PLZT), or a combination thereof. Detailed examples of the multi-film structure may include a zirconium oxide film / aluminum oxide film / zirconium oxide film (ZAZ) structure or a zirconium oxide film / aluminum oxide film / tantalum oxide film (ZAT) structure.

[0132] In some embodiments, the dielectric film 153 may have a thickness of about 5 nm to about 15 nm, but embodiments are not limited thereto. The dielectric film 153 may be formed by CVD, physical vapor deposition (PVD), or ALD processes.

[0133] Reference Figure 9L , an upper electrode 155 may be formed on the dielectric film 153. For example, the upper electrode 155 may be formed above and between the lower electrodes 151. The upper electrode 155 may include Co, Ti, Ni, W, Mo, Pt, Ru, Ir, TiN, TaN, TiAlN, TaAlN, TiSiN, WN, PtO, RuOx, IrOx, SrRuO3, (Ba, Sr)RuO3, CaRuO3, (La, Sr)CoO3, or a combination thereof. However, the material used to form the upper electrode 155 is not limited to the above materials.

[0134] The upper electrode 155 may be formed by a CVD, MOCVD, PVD, or ALD process.

[0135] The lower electrode 151 , the dielectric film 153 , and the upper electrode 155 may constitute a capacitor 150 .

[0136] A fourth interlayer insulating film 160, also referred to as an embedded insulating film 160, may be further formed on the upper electrode 155 as needed. The fourth interlayer insulating film 160 may include an HDP oxide film, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or a combination thereof. Alternatively, the fourth interlayer insulating film 160 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0137] A memory device having excellent capacitor performance can be provided by using the method according to the above embodiments.

[0138] In the following description, the configuration and effects of the present invention are described with the help of detailed experimental examples and comparative examples. However, these experimental examples are only used to clearly understand the present invention and do not limit the scope of the present invention.

[0139] <Comparative Example>

[0140] A capacitor was formed by a method according to the related art and its capacitance was measured. The method of forming a capacitor according to the comparative example includes:

[0141] (1) forming a mold layer and a support layer;

[0142] (2) forming a mask pattern;

[0143] (3) forming a recessed pattern on the mold layer and the support layer;

[0144] (4) removing the mask pattern by dry etching;

[0145] (5) forming a lower electrode;

[0146] (6) removing the mold layer and forming a dielectric film; and

[0147] (7) Forming the upper electrode.

[0148] <Experimental Example>

[0149] According to an embodiment of the present invention, a capacitor is formed and its capacitance is measured. The method of forming a capacitor according to the experimental example is performed by sequentially performing the following steps:

[0150] (1) forming a mold layer and a support layer;

[0151] (2) forming a mask pattern;

[0152] (3) forming a recessed pattern on the mold layer and the support layer;

[0153] (4) forming a protective film;

[0154] (5) partially removing the protective film by etching back to expose the mask pattern;

[0155] (6) removing the mask pattern by dry cleaning;

[0156] (7) Remove the protective film;

[0157] (8) forming a lower electrode;

[0158] (9) removing the mold layer and forming a dielectric film; and

[0159] (10) Forming the upper electrode.

[0160] Regarding the capacitors of the experimental example and the comparative example, the height, the loss of the support layer, the height variation of the capacitor depending on the position in the wafer, and the support layer step height were measured and summarized in Table 1.

[0161] [Table 1]

[0162] Comparison Examples Experimental Example Capacitor height 1080nm 1150nm Loss of support layer 80nm 10nm Capacitor height variation (across the wafer) About 18nm About 10nm Support layer step height 30nm or smaller 5nm or smaller

[0163] As shown in Table 1, the capacitors according to the exemplary embodiments can have a greater height and less support layer loss than the capacitors according to the comparative examples. Furthermore, it was found that variations in capacitor height across the wafer were reduced, thereby improving process stability and reliability. Furthermore, it can be seen that the step height of the support layer was significantly reduced.

[0164] Figure 10 This graph shows the measurement results of capacitance Cs relative to breakdown voltage BV for capacitors according to the experimental example ("dry cleaning") and the comparative example ("dry etching"). Statistical calculations of capacitance Cs for each capacitor show that capacitance Cs for the experimental example increases by approximately 0.4 fF compared to the comparative example.

[0165] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

[0166] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0033739 filed on March 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method of forming a capacitor, the method comprising: forming a mold layer and a support material layer on a semiconductor substrate including a first region and a second region; forming a mask pattern for patterning the mold layer and the support material layer in the second region; forming a recess pattern in the second region by using the mask pattern, the recess pattern exposing the upper surface of the semiconductor substrate through the mold layer and the support material layer; forming a protective film for lining a surface of the mask pattern and an inner surface of the recessed pattern; removing a portion of the protective film to expose at least an upper surface of the mask pattern; removing the mask pattern by a dry cleaning method; removing the remaining portion of the protective film; forming a lower electrode in the recessed pattern; removing the mold layer; forming a dielectric film on a surface of the lower electrode; as well as forming an upper electrode on the dielectric film, A pattern density of the mask pattern in the second region is higher than a pattern density of the mask pattern in the first region. 2 . The method according to claim 1 , wherein the dry cleaning method comprises a plasma cleaning method without applying a bias voltage. 3 . The method of claim 2 , wherein the mask pattern comprises silicon (Si), and wherein the plasma cleaning method uses a plasma gas comprising fluorine radicals. The method according to claim 1 , wherein removing the portion of the protective film is performed by etching back. The method according to claim 1 , wherein removing the portion of the protective film is performed by chemical mechanical polishing. The method according to claim 1 , wherein removing the remaining portion of the protective film is performed by wet etching.

7. The method according to claim 1, wherein the semiconductor substrate includes at least one transistor, and wherein the lower electrode is electrically connected to the at least one transistor. 8 . The method of claim 1 , wherein after forming the recess pattern, a remaining thickness of the mask pattern in the first region is greater than a remaining thickness of the mask pattern in the second region. 9 . The method of claim 8 , wherein, when the mask pattern is removed by the dry cleaning method, removal of the mask pattern in the second region is completed earlier than removal of the mask pattern in the first region. 10 . The method according to claim 9 , wherein in the dry cleaning method, an etching selectivity of the support material layer with respect to the mask pattern is at least 500:

1. 11 . The method according to claim 9 , wherein after the removal of the mask pattern in the second region is completed, a portion of the support material layer in the second region is removed until the removal of the mask pattern in the first region is completed. 12 . The method according to claim 11 , wherein when the removal of the mask pattern in the first region is completed, a level difference between an upper surface of the support material layer in the first region and an upper surface of the support material layer in the second region is within 2 nm to 20 nm.

13. The method according to claim 1, wherein the protective film is formed by atomic layer deposition, and The protective film has a thickness of 0.7 nm to 5 nm.

14. A method of forming a semiconductor device, the method comprising: forming a transistor in the second region of the semiconductor substrate including the first region and the second region, the transistor including a gate structure and an impurity region; forming an interlayer insulating film on the semiconductor substrate, the interlayer insulating film covering the transistor and having a contact plug electrically connected to the impurity region; forming a mold layer and a support material layer on the interlayer insulating film; forming a mask pattern for patterning the mold layer and the support material layer in the first region and the second region; forming a recess pattern in the second region through the mold layer and the support material layer for exposing the upper surface of the semiconductor substrate by using the mask pattern; forming a protective film for lining the inner surface of the recessed pattern; After forming the protective film, removing the mask pattern by a dry cleaning method; After removing the mask pattern, removing the protective film; forming a lower electrode in the recessed pattern; selectively removing the mold layer; forming a dielectric film on a surface of the lower electrode; as well as forming an upper electrode on the dielectric film, A pattern density of the mask pattern in the second region is higher than a pattern density of the mask pattern in the first region.

15. The method according to claim 14, wherein forming the protective film comprises: forming the protective film for lining the surface of the mask pattern and the inner surface of the recessed pattern; as well as A portion of the protection film is removed to expose an upper surface of the mask pattern.

16. The method of claim 14, wherein when removing the mask pattern, no bias voltage is applied to perform the dry cleaning method.

17. The method of claim 16, wherein the dry cleaning method is performed using a plasma gas including radicals of species.

18. The method of claim 17, wherein the plasma gas does not include ions of a species.

19. A method for forming a fine pattern, the method comprising: sequentially forming a first material film and a second material film on a semiconductor substrate including a first region and a second region; forming a mask pattern having a first pattern density in the first region and a second pattern density in the second region, wherein the second pattern density is greater than the first pattern density; forming a recess pattern in the second region by using the mask pattern, wherein the recess pattern exposes an upper surface of the semiconductor substrate; forming a protective film for lining the inner surface of the recessed pattern; After forming the protective film, removing the mask pattern by a dry cleaning method; After removing the mask pattern, removing the protective film; as well as forming a conductor in the recessed pattern, A pattern density of the mask pattern in the second region is higher than a pattern density of the mask pattern in the first region.

20. A semiconductor device comprising: A transistor on a semiconductor substrate, the transistor having a gate structure and an impurity region, the semiconductor substrate including a first region and a second region; a first interlayer insulating film covering the transistor and having a contact plug electrically connected to the impurity region; a capacitor including a lower electrode on the first interlayer insulating film in the second region and electrically connected to the contact plug, a dielectric film covering a surface of the lower electrode, and an upper electrode on the dielectric film; as well as a support layer contacting an upper side surface of the lower electrode to support the lower electrode and extending to the first region, The supporting layer has a step between the first region and the second region. 21 . The semiconductor device according to claim 20 , wherein the step gradually changes around a boundary between the first region and the second region.

22. The semiconductor device according to claim 20, wherein the support layer comprises: a boron-doped silicon nitride layer; as well as A silicon carbonitride (SiCN) layer is deposited on the boron-doped silicon nitride layer. 23 . The semiconductor device according to claim 22 , wherein the step is formed by a difference in thickness of the silicon carbon nitride (SiCN) layer between the first region and the second region. 24 . The semiconductor device according to claim 22 , wherein a thickness difference of the step is substantially the same as a thickness difference of the silicon carbon nitride (SiCN) layer between the first region and the second region.

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