Computer architecture system for high-speed graph traversal

Abstract

A computer architecture system for graph traversal provides a processor for traversing graph data in a bottom-up order based on vertex degrees. This ordered order reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph can be allocated among different memory structures in a memory hierarchy to provide faster access to vertex data associated with vertices with higher degrees, thereby reducing data access time. The adjacency data can also be encoded to provide higher compression in the memory of vertex data with high vertex degrees.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Nonprovisional 15 / 901,376, filed February 21, 2018, which is incorporated herein by reference. Background Art

[0003] The present invention relates generally to computer architecture systems, and in particular to an architecture that provides increased speed when traversing graph data.

[0004] A graph is a data structure that describes a set of vertices (nodes) interconnected by edges to form a network. Graphs provide useful models of many real-world structures, such as a model of relationships between web pages (where vertices describe web pages and edges describe links between web pages) or a model of relationships between individuals in a social network (where vertices describe individuals and edges describe their friends or interests). Graphs are also used in the fields of neural networks and bioinformatics.

[0005] Computers are often required to process graph data through "graph traversal" operations, in which each vertex of the graph is visited and data is collected to, for example, produce a minimum spanning tree, or to otherwise characterize the graph or the relationships among the vertices.

[0006] The vertices of a graph can be characterized in terms of their "degree", which indicates how many edges are connected to the vertex. A "scale-free graph" is a class of graphs in which the distribution of vertex degrees follows a power law distribution. Typically, such scale-free graphs have a small number of vertices with a large number of connections, and many more vertices with very few connections (long vertices). During graph traversal, such scale-free graphs generate a large number of redundant edge checks (investigations into visited vertices). These edge checks require inefficient and irregular accesses to the memory that holds the graph data.

[0007] By using a hybrid traversal strategy, it is possible to achieve an improvement in graph traversal efficiency, which adopts a "bottom-up" traversal after a "top-down" traversal. In an example top-down traversal (in this case, a breadth-first search), a conventional CPU- or GPU-based system executes a program to check the graph data from the starting vertex outward to find its neighbors (edges leading to other vertices) that establish a frontier. The vertices in the frontier are marked as visited, and then the edges starting from these vertices are investigated in turn to establish a new frontier. When the frontier reaches a critical size after multiple iterations, the search strategy is converted to a "bottom-up" traversal. In this mode, the computer checks the remaining unvisited vertices to check whether they have a connection to the existing border. If there is a connection to the existing border, the vertex is marked as visited and added to the border, and the strategy immediately stops searching for other edges of the vertex, thereby greatly saving processing time.

[0008] Both the top-down and bottom-up search strategies can be performed using multiple parallel processors; however, the "top-down" traversal requires an atomic update to the boundary. The bottom-up strategy, which investigates each vertex separately, does not require this atomic update.

[0009] For example, a description of this hybrid search strategy is found in distributed memory breadth-first search revisited: Enabling Bottom-Up Search, in Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International. IEEE, pp. 1618-1627 (reference Beamer), by Scott Beamer, Aydin Buluc, Krste Asanovic, and David Patterson, which is incorporated herein by reference.

[0010] Even with such a hybrid search strategy, graph data structures can quickly grow large, making graph traversal slow. Currently, Facebook's social networking site is described by a graph with over 1 billion vertices and over 1 trillion edges. Summary of the invention

[0011] The present invention provides an improved computer architecture system that exploits knowledge of vertex degrees when implementing graph traversals. First, in the bottom-up traversal portion, the architecture sorts vertex data according to vertex degrees. As will be discussed in this application, the inventors have determined that this sorting can greatly reduce fruitless edge checks. Second, during access to vertex data, access time is reduced by loading data with the greatest access frequency into the fastest memory in the memory hierarchy. In this regard, the inventors have determined that high-index vertex data is accessed more frequently. Third, when compressing data to achieve larger data storage in fast memory, the storage footprint can be reduced by associating vertex data for high-degree vertices with shorter codewords to improve the representation of that data in smaller, faster storage structures.

[0012] Specifically, in one embodiment, the present invention provides a computer architecture system for graph traversal, the computer architecture system having a memory and a processor, the memory storing an adjacency list describing the vertices of the graph and the connections of the vertices to other vertices through edges, the processor communicating with the memory system, and operating in a bottom-up mode from an unvisited vertex toward the boundary by checking the unvisited vertex using the adjacency list to find the connection to the vertex of the boundary of the visited vertex and moving to the next vertex when the connection to the vertex of the boundary is found. The architecture operates to explore the unchecked vertices in a bottom-up direction in the order of vertex degree, the vertex degree being the number of edges connected to the vertex.

[0013] It is therefore a feature of at least one embodiment of the invention to increase the rate of graph traversal by sorting the traversals by vertex degrees in a bottom-up search. Experimental-based predictions indicate that a graph traversal rate of 45.8 billion edges per second can be achieved using this architecture.

[0014] The adjacency list may be arranged in memory according to vertex degree.

[0015] Therefore, a feature of at least one embodiment of the present invention is to simplify the traversal by vertex degree by pre-sorting the adjacency list before graph traversal. The pre-sorting can be done at high speed in a streaming manner.

[0016] The memory may provide a memory hierarchy starting with smaller, high access speed memory circuits and progressing toward larger, lower access speed memory circuits, and the adjacency list may be organized to place vertices of the adjacency list so that higher vertex degrees are toward the beginning of the memory hierarchy relative to vertices with lower vertex degrees in the adjacency list.

[0017] It is thus a feature of at least one embodiment of the invention to exploit the inventors' empirical determination that higher-degree vertices have more frequent memory accesses by distributing the information for those high-degree vertices in a memory structure with lower access latency.

[0018] The memory hierarchy may include off-chip hybrid memory cube memory as well as on-chip memory on the same integrated circuit as the processor.

[0019] It is thus a feature of at least one embodiment of the invention to greatly increase the ability to store frequently accessed graph data in on-chip memory during graph traversal.

[0020] The computer architecture system may also include a decompressor circuit located between the processor and the memory, which decompresses the adjacency list according to a codebook, the codebook converting codewords representing the adjacency list in the memory into adjacency data, and wherein smaller codewords are associated with adjacency data associated with vertices having higher vertex degrees.

[0021] It is therefore a feature of at least one embodiment of the invention to provide greater compression to frequently accessed vertex information, thereby enabling larger representation of the information in the fastest memory structures.

[0022] The memory decompressor may employ a decompression method known as Exp-Golomb coding.

[0023] It is thus a feature of at least one embodiment of the invention to employ an encoding system that minimizes the additional memory requirements of a decoder.

[0024] The computer architecture system may also operate in a top-down mode from the boundary to unvisited vertices by checking boundary vertices and edges of boundary vertices using an adjacency list to find connections to unvisited vertices, and may include a mode switch that switches the processor system between the first mode and the second mode based on a parameter based on the progress of traversing the graph.

[0025] It is thus a feature of at least one embodiment of the invention to provide the advantages of a hybrid graph traversal (both top-down graph traversal and bottom-up graph traversal) for improved performance.

[0026] The computer architecture system may include a counter updated by the processor during a traversal of the graph, and wherein the mode switch reads the counter to switch the processor system between a first mode and a second mode based on the counter value.

[0027] It is thus a feature of at least one embodiment of the invention to provide runtime optimization of top-down processing or bottom-up processing based on dynamically acquired data.

[0028] The counter may indicate the size of the border.

[0029] It is thus a feature of at least one embodiment of the invention to measure the quality of a traversal, the quality of the traversal being indicative of the likely efficiency in either the top-down mode or the bottom-up mode.

[0030] The processor provides different processing circuits for the first mode and the second mode.

[0031] It is thus a feature of at least one embodiment of the invention to provide a processor optimized for both top-down and bottom-up operations.

[0032] The different processing circuits may employ multiple parallel processors to provide atomic writes to memory for a first processor but not provide atomic writes to memory for a second processor.

[0033] It is thus a feature of at least one embodiment of the invention to allow parallel processing of graph traversal problems.

[0034] Different processing circuits may have independent pipelines.

[0035] It is thus a feature of at least one embodiment of the invention to allow optimization of pipelines for both top-down and bottom-up processing.

[0036] The processor may be an FPGA.

[0037] It is thus a feature of at least one embodiment of the invention to allow efficient implementation of special purpose processors.

[0038] The adjacency list may be arranged in memory by vertex degree.

[0039] It is thus a feature of at least one embodiment of the invention to pre-sort the adjacency list for higher speed processing.

[0040] The computer architecture system may include a sorting processor that executes a stored program and receives an unsorted adjacency list and sorts the list according to vertex degree, the unsorted adjacency list describing the vertices of a graph and the connections of the vertices to other vertices through edges.

[0041] It is thus a feature of at least one embodiment of the invention to provide offline sequencing to simplify the architecture.

[0042] The sorting processor may generate a mapping table indicating a mapping from vertex indices identifying vertices in the unsorted adjacency list to vertex indices in the vertex table.

[0043] It is thus a feature of at least one embodiment of the invention to easily convert traversal information into the original graph.

[0044] These particular objects and advantages may apply to only some of the embodiments falling within the claims, thus not limiting the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a block diagram showing the architecture of the present invention of a general purpose CPU or GPU communicating with a graph traversal processor having a dedicated top-down processor and a bottom-up processor communicating with a memory hierarchy including on-chip memory, hybrid memory cube memory, and other mass storage memory, Figure 1 Also shown is an expanded view of a switching mechanism for switching between a top-down processor and a bottom-up processor;

[0046] Figure 2 is an expanded diagram of a top-down processor and a bottom-up processor having a plurality of parallel processing elements that communicate atomically with a pipeline for the top-down processor and non-atomically with a pipeline for the bottom-up processor;

[0047] Figure 3 yes Figure 1 The operation block diagram of the processor system includes an offline part for sorting graph vertex information and an online part for performing traversal. Figure 3 Also included are diagrams showing graph representations of top-down graph traversal and bottom-up graph traversal;

[0048] Figure 4 is a data flow diagram illustrating conversion of sorted vertex data through a codebook and distribution thereof among various memory systems of a memory hierarchy;

[0049] Figure 5 is a simplified graph of a scale-free network;

[0050] Figure 6 This invention is applicable to Figure 5 a plot of the power-law distribution of the scale of the network; and

[0051] Figure 7 It is a graph of high-degree vertices and low-degree vertices during the bottom-up connection of vertices to edges that provides an intuitive framework for the speed gains of the present invention. DETAILED DESCRIPTION

[0052] Hardware Overview

[0053] Now refer to Figure 1, the computer system 10 may provide a general purpose processor 12, for example, a von Neumann type architecture that may use out-of-order and speculative execution to execute a general purpose instruction set or a so-called graphics processor unit (GPU) that provides multiple parallel operating cores. The general purpose processor 12 may communicate with a hierarchical memory 14 including, for example, an on-chip buffer memory 16, an external memory 18 such as SRAM and DRAM and / or so-called flash memory, and a disk storage device 20. The general purpose processor 12 may execute a program 22 stored in the memory 14, the operation of which will be described below.

[0054] The general purpose processor 12 may communicate with a dedicated graph traversal processor 24, for example, via a shared data bus. As will be discussed in more detail below, the graph traversal processor 24 may include a dedicated top-down processor 26a and a dedicated bottom-up processor 26b. The graph traversal processor 24 may provide an optimized pipeline architecture for the types of top-down graph traversal and bottom-up graph traversal described below. It is contemplated that the dedicated graph traversal processor 24 will be an application specific integrated circuit, and in one embodiment, may be implemented using a field programmable gate array (FPGA) that executes a firmware program.

[0055] The graph traversal processor 24 may also communicate directly or through the general purpose processor 12 with a memory hierarchy 28 including on-chip memory 30 , high bandwidth off-chip memory 31 , and disk memory 20 , where the on-chip memory 30 is constructed on the same integrated circuit substrate as the processor 26 .

[0056] In one embodiment, the high-bandwidth off-chip memory 31 may be a hybrid memory cube (HMC) memory constructed according to the specifications of the Hybrid Memory Cube Consortium, a joint collaboration between Micron and Samsung and a number of other manufacturers, where components are commercially available from Micron under the trade name HMC Gen2 (HMC-15G-SR). The device typically provides extremely high bandwidth (amount of data transferred per second): two full-duplex communication links (memory channels) are provided, each link including eight gigabits per second, fifteen gigabits per second, and providing a total bandwidth of thirty gigabits per second. Other HMC components can support up to four links, each with sixteen gigabits per second, thirty gigabits per second, and an aggregate bandwidth of 240 gigabits per second. As will be described below, the general processor 12 can communicate with the on-chip memory 30 and the off-chip memory 31 to load data into these memories related to the description of the graph to be traversed, and read data from the memories related to the results of the graph traversal.

[0057] On-chip memory 30 may store data structures for graph traversal including a "visited" bitmap 32. The visited bitmap 32 (only a portion of which may be stored in on-chip memory 30) provides an array of bits equal to the number of vertices of the graph being traversed, which may be set or reset to indicate whether those vertices have been visited.

[0058] The on-chip memory 30 may also include a boundary bitmap 33 describing a subset of the graph's visited vertices (again, only a portion of which may be stored in the on-chip memory 30), the subset describing the boundaries of vertices that may be connected to other unvisited vertices. Typically, during a top-down traversal, vertices whose edges have been explored are removed from the boundary bitmap 33.

[0059] On-chip memory 30 may also store a portion of an adjacency table 34 that describes, for each vertex, the edges connected to other vertices. Adjacency table 34 will be discussed in more detail below.

[0060] Since the on-chip memory 30 cannot hold the entire visited bitmap 32 , boundary bitmap 33 or adjacency table 34 , the on-chip portion of the structure is supplemented by the corresponding visited bitmap 32 ′, boundary bitmap 33 ′ and adjacency table 34 ′ in the off-chip memory 31 .

[0061] Still refer to Figure 1 , the graph traversal processor 24 may include a processor controller 36 that may alternately activate one or the other of the top-down processor 26a and the bottom-up processor 26b during the graph traversal. Typically, the graph traversal begins with a particular graph vertex using the top-down processor 26a, then switches to the bottom-up processor 26b, and then typically switches back to the top-down processor 26a to complete the final steps of the graph traversal process.

[0062] Processor controller 36 is controlled by threshold comparator 38 which analyses the values ​​of counters 40 and 42 which communicate with top-down processor 26a and bottom-up processor 26b, respectively, to gather statistical information about the graph traversal, as will be discussed below.

[0063] In general, each of the top-down processor 26a and the bottom-up processor 26b may communicate with the on-chip memory 30 and the off-chip memory 31 either directly as indicated by arrows 44 or through a decompressor 46, the operation of which will be discussed in more detail below. These decompressors 46 are shown separately, but may in fact share components.

[0064] Now refer to Figure 2, each of the top-down processor 26a and the bottom-up processor 26b can include multiple independently operating processing units 47a and 47b, which can work in parallel on shared data in respective pipelines 48a and 48 to simultaneously process different vertices of the graph for high-speed operation. Typically, the processing unit 47a will write to the pipeline 48a atomically to prevent competition conditions regarding marking the vertex as visited. The atomic write can be implemented by a locking system 50 of a type known in the art. In contrast, as will be discussed below, the processing unit 47b that implements the bottom-up processor 26b does not need to be atomically locked.

[0065] Hardware Operation

[0066] Now temporarily refer to Figure 5 and Figure 6 , a simplified graph 52 that can be traversed by the present invention may provide a set of vertices 54 interconnected by edges 56. In general, the graph 52 may be described by an adjacency list 34 that lists each vertex 54 by a unique vertex index and describes the direct connections of the vertex to other vertices. Each vertex may also include additional information that may be accessed during graph traversal by separate indexing operations not discussed herein.

[0067] During a graph traversal, a starting vertex 54 is selected, followed by graph edges 56, until every vertex in the graph has been visited. During the traversal, data related to the vertices 54 or their connections may be collected. Graph traversal is a basic operation of the processing of FIG52, and may be used, for example, to develop a simplified depiction of a graph (e.g., a minimum spanning tree) that orders or identifies connections in, for example, a social network.

[0068] In many important graph applications, the graph 52 will approximate a so-called scale-free graph, in which a small number of vertices 54 (shown here as cross-hatched) have a large number of edges 56, much larger than most of the remaining vertices 54. The number of edges 56 will be referred to as the vertex "degree", and in a scale-free graph, the number of edges in a set of vertices 54 of the graph 52 is typically a power-law distribution 58. As will be discussed below, the present invention uses vertex degree to control the order of vertex traversal in a bottom-up traversal to improve the efficiency of the traversal, and further uses vertex degree to locate vertex data (primarily adjacency lists 34) in a memory hierarchy and compress the data.

[0069] Now refer to Figure 1 and Figure 3, the graph traversal execution may begin as indicated by processing block 60, where the adjacency list 34 is sorted according to vertex degree so that the vertex 54 associated with the highest degree is located, for example, at the beginning of the adjacency list 34. A typical adjacency table 34 may, for example, provide a vertex index table 62 having one array element in an array for each vertex index (vertices 0 to 7 are shown here), where the vertex index is a unique number associated with each vertex 54 that is typically encoded in the address of the array element. The value in the array element for each vertex 54 provides a pointer 64 from the parent vertex 54 of the vertex index table 62 to the beginning of a range 66 in a corresponding adjacency array 68. The values ​​in the adjacency array 68 within the range 66 for that parent vertex 54 describe each edge leading out of the parent vertex 54 according to the index number of the vertex 54 connected to the parent vertex 54 by those edges leading out of the parent vertex 54. The end of the range 66 is described by the beginning of the next range for the next parent vertex 54 in the vertex index table 62.

[0070] The degree of a given vertex 54 is easily determined from the adjacency list 34 by the length of the range 66. Figure 3 , vertex (0) has a degree of (3), indicating that the parent vertex (0) is connected to three other vertices 54. Typically, the vertices 54 are arranged in the vertex index table 62 and the adjacency list 34 in an arbitrary order relative to their degrees, but the vertices 54 are sorted into an order according to degree, such that the highest degree vertex 54 is first in these data structures, using, for example, a general purpose processor 12. Preferably, the sorting may be strictly based on vertex degree; however, it will be appreciated from the following description that if such sorting is generally observed, such as by an ordered arrangement of high vertex degree, medium vertex degree, and low vertex degree, or a statistical trend of vertex degrees, the present invention yields less benefit.

[0071] In the depicted example, the unsorted adjacency list 34 shown will be sorted by degree so that vertex (0) (degree 3) is first, followed by vertices (2) and (3) both of degree 2, and finally vertex (1) of degree 1. In the sorting process, the order of the vertices in the vertex index table 62 will change accordingly, and the mapping table 23 ( Figure 1 62) to map the new order to the original vertex numbers so that the order of the original vertices can be reestablished. The values ​​stored in each array element of the adjacency array 68 can be updated to reference the new index value of the sorted vertex index table 62. Generally, the visited bitmap 32 and the boundary bitmap 33 can be similarly sorted to facilitate the positioning of the data for efficient access.

[0072] Now refer to Figure 4, the inventors have determined that, as indicated by the depicted asymptotically decreasing curve 69, higher degree vertices statistically experience a greater number of memory accesses than lower degree vertices 54 during graph traversal. Therefore, the vertex data in the sorted adjacency list 34 can be divided into memory hierarchies 28 ( Figure 1 20 . In the example shown in FIG. 20 , the sizes of the bins 70 a to 70 c will be equal to the sizes of the different memory structures in the memory hierarchy 28, where, for example, the first bin 70 a holds the data of the adjacency list 34 associated with the vertex 54 having the highest vertex degree, and the first bin 70 a will match the size of and be associated with the on-chip memory 30. Similarly, the size of the bin 70 b holding the data of the adjacency list 34 associated with the vertex 54 having the lower vertex degree will match the size of the off-chip memory, and finally the bin 70 c will hold the data of the adjacency list 34 associated with the long tail of the vertices 54 having the lowest vertex degree, and will be of a size sufficient to be stored and will be stored in the disk storage device 20. In this way, the data of the vertices 54 having the higher vertex degree that are most frequently memory accessed will be held in a faster memory structure that provides improved access speed.

[0073] The allocation of data for vertex 54 may be accomplished, for example, directly from adjacency list 34 to memory hierarchy 28, or alternatively, the data may be first compressed using code table 72 to produce an encoded codeword 76, which is then allocated to memory hierarchy 28 along arrow 77. In this process, the vertex data of bins 70a to 70c may be subjected to different compression mechanisms to provide greater compression for the data in bin 70a to allow greater storage in a small storage area of ​​on-chip memory 30. Similarly, the data in bin 70b may be subjected to greater compression than the data in bin 70c to allow economical use of off-chip memory 31. This variation in net compression may be performed by appropriate construction of codebook 72 that maps adjacency list 34 to codewords 76, allocating shorter codewords 76 (within the codeword range) to more frequently accessed data. Typically, the length of codeword 76 is set shorter for vertex data of vertices of higher degrees. The encoding process may utilize a variety of known compression techniques including Huffman coding. In one embodiment, the encoding process may be Exp-Golomb encoding as described, for example, in Solomon Golomb, Run-length encodings (Corresp.), IEEE Transactions on Information Theory 12, 3 (1966), 399-401.

[0074] Reference again Figure 3The compression process is illustrated by process block 74, and loading the codeword into memory is indicated by process block 78. These steps may be performed "offline" relative to processor 24, or may be performed by dedicated hardware incorporated into processor 24 as mentioned below.

[0075] Once the vertex data is properly sorted, compressed, and loaded into the processor 24, the processor controller 36 may be particularly utilized as indicated by processing block 80. By enabling the top-down processor 26a (e.g. Figure 1 ) to activate the processor 24. In this process, starting at the seed vertex 54' specified by the user in the configuration data of the processor 24, the processor 24 will query the adjacency table 34 and identify those vertices 54 that are connected to each edge of the seed vertex 54' to define the boundary 82. The processor 24 will then sequentially move through the vertices 54 of the boundary (e.g., as shown by the numbers 1, 2, and 3) to identify other vertices 54 that are connected to the vertex 54 of the boundary 82, thereby establishing a new boundary (not shown) in the outward expansion of the boundary 82 as shown by arrow 85. In this process, the bitmap 32 (as shown) has been accessed. Figure 1 The bit array (shown) tracks these visited vertices, and the boundary bitmap 33 tracks those vertices within the boundary 82 and updates accordingly. In general, vertices 54 whose edges have been investigated can be removed from the boundary bitmap 33 but still remain visited and therefore remain in the visited bitmap 32.

[0076] The simplified algorithm for top-down traversal follows these steps:

[0077] For each boundary of vertices;

[0078] For each vertex in the boundary;

[0079] If the vertex connected by the edge is not visited;

[0080] Then mark the vertex as visited;

[0081] Move the marked vertices to the boundary and collect other data;

[0082] Next edge;

[0083] Next vertex;

[0084] The next frontier.

[0085] It should be understood that multiple processing units 47 of the top-down processor 26a can operate in parallel to investigate different vertices 54 of the boundary 82, but when they find an unvisited vertex 54, they must atomically mark it as read, so there is no writing to a given "child" vertex by multiple processing units 47. Figure 1The pipelining technique of communication (as shown) obtains access to the necessary data for this traversal.

[0086] As boundary 82 expands, the efficiency of the search process decreases due to the increased likelihood that multiple given vertices 54 in boundary 82 will be connected to a common vertex, such as vertex 54". In these cases, subsequent "checks" of other edges 56 for common vertex 54" will waste processor resources, resulting in unnecessary accesses to adjacency table 34 in memory hierarchy 28 for that edge and unnecessary consumption of processor power.

[0087] To address the reduced efficiency caused by the redundancy of edge checking, after each boundary 82 is completed (all included vertices 54 are scanned), as indicated by decision block 88, a decision can be made as to whether it is more efficient to begin bottom-up processing using bottom-up processor 26b.

[0088] The decision as indicated by decision block 81 as to whether to start bottom-up processing takes into account counters 40 and 42 which may be updated simultaneously. Counter 40 keeps track of the number of edges (m) that need to be checked in the current frontier. f ) and the number of unexplored edges (m u ), while counter 42 keeps track of the size of the border in the vertex (n f ). These counters 40 and 42 can be updated in hardware during the traversal process, eliminating the need to scan the boundary bitmap 33 or the adjacency table 34.

[0089] Specifically, (m f ) and (n f ) is calculated by accumulating the degree and number of each vertex 54 as it is added to the boundary 82. The remaining value m u It is calculated by subtracting the sum of all degrees of all visited vertices from the total number of edges.

[0090] The threshold determination indicated by decision block 81 as to when to switch between top-down processing or bottom-up processing can employ the techniques described in the Beamer paper referenced above and incorporated by reference. Preliminary experiments indicate that thresholds α=15 and β=20 can be used. In this process, threshold comparator 38 looks at counters 40 and 42 and controls top-down processor 26a (in which case it is deactivated) and bottom-up processor 26b (in which case it is activated). The same decision block 81 can also check at the end of each boundary 82 to see if all vertices 54 have been visited, and if all vertices 54 have been visited, the program terminates.

[0091] Assuming the traversal is not complete, if the decision at decision block 81 is to no longer use top-down processing, then as indicated by processing block 84, the bottom-up processor 26b (eg, Figure 1 In the bottom-up processing, the vertices 54 of the boundary 82 are no longer sorted, but instead, the processing is performed in an ordered traversal of the unvisited vertices 54 in order according to the vertex degree, which is facilitated by the sorting of the adjacency list 34. That is, the bottom-up processor 26b starts from the highest degree unvisited vertex.

[0092] At each unvisited vertex 54, the edges are checked to see if they are connected to the boundary 82 (i.e., if they are connected to a vertex 54 already in the boundary 82). If such a connection exists, the unvisited vertex 54 is marked as visited, and no further edges to that vertex 54 need to be checked. This ability to quickly check edges is a significant benefit of the bottom-up approach.

[0093] The simplified algorithm for the bottom traversal follows these steps:

[0094] For each unvisited vertex;

[0095] For each edge;

[0096] If the edge connects to a vertex in the boundary;

[0097] Then mark the unvisited vertex as visited;

[0098] Add this vertex to the boundary

[0099] Jump out;

[0100] Next side;

[0101] Next vertex;

[0102] In this case, the border 82 continues to grow without removing the vertex 54 because the vertex 54 that was added was not explored by all other edges, which would allow the vertex 54 to be removed from the border 82, for example. It should be understood that checking the unvisited vertex 54 can be performed in parallel by the processing unit 47b, and because no other processing unit 47b will process the unvisited vertex 54, the processing unit 47b does not need to atomically write to the bitmap associated with the unvisited array. Once each unvisited vertex is visited, some vertices 54 that are still not connected to the border 82 (and therefore marked as visited) will remain. The process will then loop through the unvisited vertices 54 again, in the expectation that as the border 82 expands, some of these unvisited vertices will now be connected to the border 82.

[0103] Temporary reference Figure 7, can obtain the intuitive understanding of the benefit of bottom-up traversal of vertex 54 using degree sorting by considering high vertex 54a and low degree vertex 54b that each have half of the edges connected to border 82. The visit to any one of vertex 54a or 54b presents an equal chance that any given edge 56 is connected to border 82 and terminates to view these edges. In this respect, the two vertices 54a and 54b are equally attractive in terms of avoiding the probability of quickly getting the "jump out" state that terminates to view this vertex. However, when being added to border 82, high vertex 54a greatly increases the rate at which other vertices 54 will be connected to border 82, because compared with low degree vertex 54b, high vertex 54a presents a large number of edges that are not connected to the border, presenting more opportunities for remaining vertex 54b. As a result, by starting from high vertex 54a, the unconnected edges of border 82 increase faster, thereby increasing the chance of rapid termination of future vertices compared with the reverse order. This in turn reduces the need for repeated loops through unvisited vertices.

[0104] Refer again Figure 3 As described above, after each unvisited vertex 54 has been viewed, there will be some unvisited vertices that are not yet connected to the current boundary, and the bottom-up sorting will be repeated after passing through decision block 86, which again tests whether the traversal is complete and whether it is desired to resume top-down processing according to process block 80. In addition, decision block 86 relies on the evaluation of threshold comparators 38 for 40 and 42 and the activation of processor 26 by processor controller 36.

[0105] Assuming that the graph traversal is not complete, the processing of FIG. 52 continues to move between the processing of processing block 80 and the processing of processing block 84 according to the comparison of the value of counter 40 with the value of counter 42 by threshold comparator 38 .

[0106] Although the above discussion regards the execution of processing blocks 60, 74 and 78 as being performed off-line by a separate general purpose processor 12, it will be appreciated that these steps may also be incorporated into the processor 24 by providing dedicated sorting and compression circuitry that performs the initial scan of the necessary adjacency table 34 to provide the above-described sorting and compression.

[0107] Certain terms are used herein for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions referenced in the accompanying drawings. Terms such as "front," "rear," "back," "bottom," and "side" describe the orientation of portions of a component in a consistent but arbitrary reference system, which orientation becomes clear by reference to the text and associated drawings describing the component in question. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning. Similarly, the terms "first," "second," and other such numerical terms referring to a structure do not imply a sequence or order unless the context clearly indicates otherwise.

[0108] When introducing the elements or features of the present disclosure and exemplary embodiments, the articles "a", "an", "the" and "said" are intended to mean that there are one or more such elements or features. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements or features in addition to those specifically noted. It should also be understood that unless specifically identified as an execution order, the method steps, processing and operations described herein should not be interpreted as having to be performed in the specific order discussed or illustrated. It should also be understood that additional or alternative steps may be adopted.

[0109] References to "microprocessor" and "processor" or "the microprocessor" and "the processor" may be understood to include one or more microprocessors that may communicate in one or more independent and / or distributed environments, and thus may be configured to communicate with other processors via wired or wireless communications, wherein such one or more processors may be configured to operate on one or more processor-controlled devices, which may be similar or different devices. In addition, unless otherwise specified, references to memory may include one or more processor-readable and accessible memory elements and / or components, which may be located within a processor-controlled device, external to a processor-controlled device, and may be accessed via a wired network or a wireless network.

[0110] In particular, the present invention is not intended to be limited to the embodiments and drawings included herein, and the claims should be understood to include modifications of these embodiments within the scope of the appended claims, including combinations of parts of the embodiments and elements of different embodiments. The entire contents of all publications described herein, including patent publications and non-patent publications, are incorporated herein by reference.

Claims

1. A computer architecture system for graph traversal, comprising: a memory storing an adjacency list describing the vertices of the graph and the connections of the vertices to other vertices through edges; as well as a processor in communication with the memory and operating in a bottom-up mode from unvisited vertices toward the boundary by checking unvisited vertices using the adjacency list to find a connection to any vertex of a boundary of visited vertices and moving to the next vertex when a connection to a vertex of the boundary is found; wherein the unvisited vertices are examined in the bottom-up direction in order of vertex degree, the vertex degree being the number of edges connected to the vertex, and wherein the adjacency list is arranged in the memory according to vertex degree, and wherein the memory provides a memory hierarchy starting with smaller, high access speed memory circuits and progressing toward larger, lower access speed memory circuits, and wherein the adjacency list is organized to place vertices with higher vertex degrees in the adjacency list toward the beginning of the memory hierarchy relative to vertices with lower vertex degrees in the adjacency list.

2. The computer architecture system according to claim 1, wherein: The memory hierarchy includes off-chip hybrid memory cube memory and on-chip memory on the same integrated circuit as the processor.

3. The computer architecture system of claim 1 , further comprising a decompressor circuit located between the processor and the memory, the decompressor circuit decompressing the adjacency list according to a codebook, the codebook converting a codeword representing the adjacency list in the memory into the adjacency list, and wherein, Smaller codewords are associated with data in the adjacency list for vertices with higher vertex degrees.

4. The computer architecture system according to claim 3, wherein: The decompressor circuit uses Exp-Golomb coded decompression.

5. The computer architecture system according to claim 1, wherein: The processor also operates in a top-down mode from the boundary to the unvisited vertices by checking the edges of the boundary vertices using the adjacency list to find connections to unvisited vertices; and The computer architecture system also includes a mode switch that switches the processor between the top-down mode and the bottom-up mode based on a parameter describing a progress of traversing the graph.

6. The computer architecture system of claim 5, further comprising a counter updated by the processor during a traversal of the graph, and wherein, The mode switch reads the counter to switch the processor between the top-down mode and the bottom-up mode based on a counter value.

7. The computer architecture system according to claim 6, wherein: The counter indicates the size of the border.

8. The computer architecture system according to claim 5, wherein: The processor provides different processing circuits for the top-down mode and the bottom-up mode.

9. The computer architecture system according to claim 8, wherein: The different processing circuits employ multiple parallel processors.

10. The computer architecture system according to claim 8, wherein: The different processing circuits have independent pipelines.

11. The computer architecture system according to claim 5, wherein: The processor is an FPGA.

12. The computer architecture system according to claim 5, wherein: The memory hierarchy includes off-chip hybrid memory cube memory and on-chip memory on the same integrated circuit as the processor.

13. The computer architecture system according to claim 5, wherein: Also included is a decompressor circuit located between the processor and the memory, which decompresses the adjacency list according to a codebook, which converts codewords representing the adjacency list in the memory into the adjacency list, and wherein smaller codewords are associated with data for vertices with higher vertex degrees in the adjacency list.

14. The computer architecture system according to claim 13, wherein: The decompressor circuit uses Exp-Golomb coded decompression.

15. The computer architecture system according to claim 1 includes a sorting processor, which executes a stored program and receives an unsorted adjacency list and sorts the unsorted adjacency list according to vertex degree, wherein the unsorted adjacency list describes the vertices of the graph and the connections of the vertices to other vertices through edges.

16. The computer architecture system according to claim 15, wherein: The sorting processor generates a mapping table indicating mappings from vertices in the unsorted adjacency list to vertices in the adjacency list.

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