Method for forming semiconductor recess

Abstract

The present application relates to a method for forming a semiconductor recess. Methods, apparatus, and systems related to forming a recess in a semiconductor structure are described. An exemplary method includes etching the semiconductor structure using a high temperature acid and water dilution. The method also includes etching the semiconductor structure using a room temperature acid and water and a surface modification chemical wet etching.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods, and more particularly to the formation of semiconductor recesses. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), and flash memory, among others. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and may be used in a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Volatile memory cells (e.g., DRAM cells) require power to maintain their stored data state (e.g., via a refresh process), in contrast to non-volatile memory cells (e.g., flash memory cells) that maintain their storage state without power. However, various volatile memory cells (e.g., DRAM cells) may operate (e.g., program, read, erase, etc.) faster than various non-volatile memory cells (e.g., flash memory cells). Summary of the invention

[0003] The present disclosure provides a method comprising etching a semiconductor structure using a high temperature acid and water dilution etching, and etching a semiconductor structure using a room temperature acid and water and a surface modification chemical wet etching.

[0004] The present disclosure provides a method comprising patterning a semiconductor structure using a high temperature acid and water dilution to remove nitride protrusions on a capacitor structure, patterning the semiconductor structure using a room temperature acid and water and a surface modification chemical dilution, and patterning the semiconductor structure using a reduction stripping to reduce the resistance of the semiconductor structure and remove the surface modification chemical.

[0005] The present disclosure provides a method comprising etching a semiconductor structure using a high temperature dilution of about 2000 parts deionized water to about 1 part hydrofluoric acid, etching the semiconductor structure using a room temperature wet etch of about 300 parts deionized water to about 1 part hydrofluoric acid and a surface modification chemical, and performing a reduction stripping to reduce the resistance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A -D illustrates a cross-sectional view of a portion of a memory device in different examples of a semiconductor manufacturing sequence for forming a semiconductor recess according to various examples of the present disclosure.

[0007] Figure 2-4 A flow chart of an exemplary method for forming a semiconductor recess according to various examples of the present disclosure is shown.

[0008] Figure 5 is a functional block diagram of a system for implementing an exemplary semiconductor manufacturing process according to various embodiments of the present disclosure.

[0009] Figure 6 A functional block diagram of a computing system including at least one memory array having a structure formed according to one or more examples of the present disclosure is shown.

[0010] Figure 7 A cross-sectional view of a portion of an exemplary semiconductor structure of a memory device according to various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0011] Various types of semiconductor structures on memory devices (e.g., semiconductor structures including volatile or non-volatile memory cells) may include linear trenches and / or circular, square, elliptical, etc. shaped chambers that may be formed in semiconductor materials to create openings on the semiconductor materials for subsequent semiconductor processing steps. Various materials may be deposited using chemical vapor deposition (CVD), plasma deposition, etc., and patterned using photolithography techniques, doped and etched using steam, wet etching processes, and / or dry etching processes to form semiconductor structures on substrates. Such openings may contain or be associated with various materials that facilitate data access, storage, and / or processing or various support structures on the memory device. For example, capacitor materials may be deposited into these openings to store and access data.

[0012] To increase the capacitance of a cell of a memory device, the surface area of ​​the capacitor material formed into the columns can be increased by increasing the height of the columns of capacitor material within the openings using various photolithography and dry etching techniques. The surface area of ​​the capacitor material can also be increased by reducing the width of the columns of capacitor material within the openings. However, due to possible clearance margins and smaller spacing, increasing the height of the capacitor columns can increase the risk of protrusions or wider protruding features on the capacitor pillars, which can mask other materials within the capacitor pillars and can reduce the openings available for the capacitor material.

[0013] To alleviate this problem, a method of etching a protrusion using a wet etch is further described below. For example, a protrusion may be generated at the silicon layer of a capacitor pillar. A wet etch comprising a dilution of acid and water can be used to selectively etch the silicon dielectric protrusion without affecting other materials within the capacitor pillar. The capacitor pillar can include layers of silicon, metal, nitride and / or oxide materials. The dilution can be a high temperature combination of water and acid. Etching can result in straighter capacitor pillars and increased space within the opening to deposit the capacitor material.

[0014] The present disclosure includes methods, apparatus, and systems related to forming semiconductor recesses. Examples of the methods described herein include etching a semiconductor structure using a high temperature acid and water dilution. The exemplary methods also include etching the semiconductor structure using a room temperature process that uses acid and water and a silane-based surface modification chemical to selectively etch a silicon dielectric protrusion without affecting other materials within the capacitor pillar.

[0015] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part of the present disclosure, and one or more examples of how to practice the present disclosure are shown in the accompanying drawings by way of illustration. These examples are described in sufficient detail so that those skilled in the art can practice the examples of the present disclosure, and it should be understood that other examples can be utilized and process, electrical and / or structural changes can be made without departing from the scope of the present disclosure. As used herein, "multiple" something can refer to one or more such things. For example, multiple capacitors can refer to at least one capacitor.

[0016] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the figure and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, the reference numeral 118 may refer to Figure 1B 18, and similar or identical components may be referenced Figure 1C 118 in. In some cases, multiple similar but functionally and / or structurally distinguishable elements or components in the same figure or in different figures may be sequentially referenced by the same element number (eg, 101-1, 101-2).

[0017] Figure 1AA cross-sectional view 100-1 of a portion of an exemplary memory device in another example of a semiconductor manufacturing sequence for forming a semiconductor recess according to multiple examples of the present disclosure is shown. The exemplary memory device 100-1 can include a plurality of capacitor pillars 101-1, 101-2 (hereinafter collectively referred to as capacitor pillars 101), each of which can be composed of a first silicon-based material 118 (shown as having been formed in an underlying substrate material 120), a metal material 116, and / or a second silicon-based material 114. The substrate material 120 can be formed of various undoped or doped dielectric materials on which the memory device material can be manufactured. Examples of the substrate material 120 can include silicon-based oxides, among other possibilities.

[0018] In a number of examples, the first silicon-based material 118 may be a silicon oxide (SiO2) material. In some examples, the first silicon-based material 118 may be formed of polysilicon, among other possibilities. The first silicon-based material 118 may also be formed of a semiconductor material. The first silicon-based material 118 may be initially formed (e.g., deposited) within the underlying substrate material 120 by dry etching through a photolithographic pattern. For example, the first silicon-based material 118 may be formed from the bottom of the underlying substrate material 120 to a height of 50-60 nm above the underlying substrate material 120. In some examples, the first silicon-based material 118 may be a silicon-based material different from the substrate material 120. In other examples, the first silicon-based material 118 may be a combination of silicon-based material layers (as examples, two layers of silicon-based material, three layers of silicon-based material, etc.).

[0019] As shown, the metal material 116 can be formed (e.g., deposited) on a surface of the first silicon-based material 118 opposite to the underlying substrate material 120. For example, the metal material 116 can be formed on top of the first silicon-based material 118 to a specific height of about 24-30 nm above the underlying substrate material 120, or dry-etched through the photolithographic pattern to form the metal material 116 on top of the material 118. In one example, the metal material 116 can be formed of tungsten (W). In another example, the metal material 116 can be formed of other transition metals, such as rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), titanium (Ti), zirconium (Zr), chromium (Cr), ruthenium (Ru), and palladium (Pd), among other possibilities. The metal material 116 can be oxidized.

[0020] Similar to the first silicon-based material 118, the silicon-based material 114 can be formed on the surface of the metal material 116 opposite to the first silicon-based material 118. In other words, the second silicon-based material 114 can be formed (e.g., deposited) on the upper surface of the metal material 116. In one example, the second silicon-based material 114 can be doped with nitride to form a silicate nitride (SiNx) material. In another example, the second silicon-based material 114 can be doped with oxide and nitride to form silicon in oxynitride (SiON) material. In multiple examples, the second silicon-based material 114 can be formed of a dielectric material.

[0021] A dry etching process may be used to etch through portions of the second silicon-based material 114, the metal material 116, and / or the first silicon-based material 118 to form openings 103 within the previously listed materials (as shown between the plurality of pillars 101-1 and 101-2, hereinafter collectively referred to as the plurality of pillars 101). As shown, each of the plurality of pillars 101 may include a first silicon-based material 118 formed in an underlying substrate material 120, a metal material 116, and a second silicon-based material 114. The openings 103 may be used as columns of capacitor material. The openings 103 may extend from the top of the surface of the second silicon-based material 114 to the surface of the underlying substrate material 120.

[0022] In at least one example, the width or diameter of the opening 103 between the plurality of pillars 101-1 and 101-2 can be in the range of about 200-600 angstroms (or 20 to 60 nm), and the height of the opening 103 can be in the range of about 200-600 angstroms (or 20 to 60 nm), about 8,000-15,000 angstroms (800-1,500 nm), and can result in an aspect ratio (AR) of height to width in the range of about 25:1 to about 50:1 as etching continues through the second silicon-based material 114 and approaches the substrate material 120. As the height of the plurality of pillars 101 increases, bending and / or tilting of the plurality of pillars 101 may occur.

[0023] The dry etching process used to form the plurality of pillars 101 passes through the first silicon-based material 118, the metal material 116, and the second silicon-based material 114. The dry etching through the different materials can result in a protrusion in the second silicon-based material 114. The protrusion 115 can be a wider protruding feature formed on the second silicon-based material 114. In one example, the protrusion 115 can be on one pillar (101-1 or 101-2), but not on the other pillar (101-2 or 101-1, respectively). The protrusion 115 can mask features of other materials within the plurality of pillars 101. The protrusion 115 can protrude into the opening 103, reducing the space and / or volume of the capacitor material.

[0024] Figure 1BA cross-sectional view 100 - 2 illustrates a portion of an exemplary memory device in an example of a semiconductor manufacturing sequence for forming a semiconductor recess according to various examples of the present disclosure. Figure 1B Shown in the completed combination Figure 1A The structure of a portion of an exemplary memory device at a particular stage following the exemplary manufacturing sequence described.

[0025] A wet etching process sequence may be used to remove protrusions on the plurality of pillars 101 (eg, Figure 1A The wet etching process sequence can form a depression by removing the protrusion. That is, the depression of the protrusion 115 can be formed at the opening (such as Figure 1A The wet etching process sequence may include etching the semiconductor structure using a high temperature acid and water dilution, followed by etching the semiconductor structure using a room temperature acid and water wet etch and a silane-based surface modification chemical. The surface modification chemical may consist of hexamethyldisilazane (HMDS).

[0026] As mentioned above, there can be two groups of etching: wet / steam etching at high temperatures and wet / steam etching at room temperature using silane-based surface modification chemicals HMDS processing. Wet etching can remove material by immersing the material in a chemical solution that reacts with the selected film to form soluble byproducts. Steam etching can use reactive gaseous molecules in the gas phase to dissolve the material. It can utilize steam instead of liquid etchants to remove material.

[0027] The wet etching sequence can result in straighter openings and increased space for capacitor material. The high temperature etching process can selectively target the silicon-based material layer 114 of the plurality of pillars 101 (represented by a single capacitor pillar 101) where the protrusions have been formed without targeting the metal material 116 or other silicon-based material 118. The first wet etching dilution can use a high temperature dilution to etch the silicon-based material 114. The second wet etching can be a room temperature wet etching that makes the plurality of pillars 101 hydrophobic.

[0028] Figure 1C A cross-sectional view 100 - 3 of a portion of an exemplary memory device in an example of a semiconductor manufacturing sequence for forming a semiconductor recess according to various examples of the present disclosure is shown. Figure 1C Shown in the completed combination Figure 1A and 1B The structure of a portion of an exemplary memory device at a particular stage following an exemplary fabrication sequence is described.

[0029] In the formation of Figure 1BAfter the recess, a nitride material 112 may be formed on the first silicon-based material 118, the metal material 116, and the second silicon-based material 114. The nitride material 112 may be a spacer nitride. The nitride material 112 may be used to protect the material below the nitride material 112 (the first silicon-based material 118, the metal material 116, and the second silicon-based material 114) during a subsequent processing sequence. The nitride material 112 may be selected for dielectric or resistive properties. For example, one or more dielectric and / or resistor nitrides may be selected from boron nitride (BN), silicon nitride (SiNx, Si3N4), aluminum nitride (AlN), gallium nitride (GN), tantalum nitride (TaN, Ta2N), titanium nitride (TiN, Ti2N), and tungsten nitride (WN, W2N, WN2), among other possibilities, to form the nitride material 112. The nitride material may be formed of the same material as the first silicon-based material 118. The nitride material may be formed of the same material as the second silicon-based material 114.

[0030] Nitride material 112 may be formed over the etched plurality of pillars 101. Nitride material 112 may be formed over the material pillars 101. Nitride material 112 may take the shape of the underlying plurality of pillars 101. That is, the etched plurality of pillars 101 have a straight profile that nitride material 112 may assume.

[0031] Figure 1D A cross-sectional view 100 - 4 illustrates a portion of an exemplary memory device in an example of a semiconductor manufacturing sequence for forming a semiconductor recess according to various examples of the present disclosure. Figure 1D Shown in the completed combination Figure 1A , 1B 1C and the structure of a portion of an exemplary memory device at a particular stage following the exemplary manufacturing sequence described in FIG. 1C.

[0032] The straighter profile of the plurality of pillars 101 can improve the subsequent dry etching margin. With the protrusions still intact, the dry etching may not be able to approach the corners of the top of the nitride material 112, where the plurality of pillars 101 can connect to the top of the substrate material 120. Removing the protrusions can increase the dry etching margin and provide a straighter columnar profile. The dry etching 121 can approach areas of the plurality of pillars 101 that were previously inaccessible, such as the entire top of the nitride material 112.

[0033] Figure 2 A flow chart of an exemplary method 222 for forming a semiconductor recess according to various examples of the present disclosure is shown. The method 222 is to generate Figure 1BThat is, the method 222 of forming a recess in a semiconductor structure details the formation of a recess by removing a protrusion from a plurality of pillars (eg, pillar 101).

[0034] At block 224, method 222 may include etching the semiconductor structure using a high temperature acid and water dilution. The high temperature dilution may include a ratio of about 2000 parts water to about 1 part acid (2000:1). The acid may be hydrofluoric acid. The water may be deionized water. The dilution may have an elevated temperature in the range of 60 to 75 degrees Celsius. The high temperature dilution may be used during a wet etching process. The high temperature dilution may be used to selectively etch the silicon protrusions without affecting other materials within the capacitor pillars. That is, the high temperature dilution may etch the underlying capping nitride material and silicon-based material without affecting other silicon-based or metal materials within the capacitor pillars.

[0035] At frame 226, method 222 may include etching the semiconductor structure using room temperature wet etching of acid and water and surface modification chemicals. That is, the room temperature wet etching may consist of acid, water and surface modification chemicals. The room temperature wet etching may include a ratio of about 300 parts water to about 1 part acid (300:1). The acid may be hydrofluoric acid. The water may be deionized water. The room temperature may be 20 to 25 degrees Celsius. The room temperature wet etching may be the second step in the wet etching sequence and may occur after the high temperature etching. Frame 226 may occur after frame 224. That is, after the high temperature dilution has been applied, the room temperature wet etching may be applied to the plurality of pillars. The room temperature wet etching may include surface modification chemicals. The surface modification chemicals may prevent the semiconductor structure from tipping over during the etching process and may make the surface of the semiconductor structure hydrophobic. That is, after the room temperature wet etching, the material within the capacitor pillar may be hydrophobic.

[0036] Figure 3 370 is a flow chart of an exemplary method 370 for forming a semiconductor recess according to multiple examples of the present disclosure. Unless explicitly stated, the elements of the methods described herein are not limited to a specific order or sequence. In addition, the various method embodiments or elements thereof described herein can be performed at the same or substantially the same time point.

[0037] At block 328, method 370 may include patterning the semiconductor structure using a high temperature acid and water dilution to smooth the nitride protrusions on the capacitor structure. That is, the high temperature acid and water dilution may be used to form a pattern of nitride protrusions on the capacitor pillars. The high temperature dilution may etch underlying overlying nitride materials and silicon-based materials without affecting other silicon-based or metal materials within the capacitor pillars. That is, the high temperature dilution may be used to selectively etch silicon protrusions without affecting other materials within the capacitor pillars.

[0038] At block 330, method 370 may include patterning the semiconductor structure using room temperature acid and water and a surface modification chemical dilution. Room temperature wet etching may be used to pattern the semiconductor structure after patterning the semiconductor structure with a high temperature dilution. That is, the capacitor pillars may be etched using a high temperature dilution and then etched using a room temperature wet etch. The room temperature wet etch may be used to render the surface of the semiconductor structure hydrophobic. That is, after the room temperature wet etch, the material within the capacitor pillars may be hydrophobic.

[0039] At box 332, method 370 may include patterning the semiconductor structure using reductive stripping to reduce the resistance of the semiconductor structure and remove the surface modification chemical. The room temperature wet etching mentioned in conjunction with box 332 can make the capacitor pillar hydrophobic. Reductive stripping can be used to remove the surface modification chemical after the wet etching process is completed. The steps at box 332 of method 370 can occur after the steps at box 330 of method 370. That is, reductive stripping can be applied to the capacitor pillar after the room temperature etching has been applied. The surface modification chemical can be used to prevent the semiconductor structure from tipping over during the wet etching sequence and make the surface of the semiconductor structure hydrophobic. Reductive stripping can be used to remove the hydrophobic effect of the surface modification chemical. Reductive stripping can also be used to reduce the semiconductor resistance and reduce the oxidized metal to the element metal. In one example, the reductive stripping can be formed by oxygen and hydrogen (O2 / H2). In another example, the reductive stripping can be formed by oxygen and ammonia (O2 / NH3). In some examples, the reductive stripping can be formed by pure hydrogen (H2).

[0040] Figure 4 A flow chart of an exemplary method 450 for forming a semiconductor recess according to multiple examples of the present disclosure is shown. Unless explicitly stated, the elements of the methods described herein are not limited to a specific order or sequence. In addition, the various method embodiments or elements thereof described herein can be performed at the same or substantially the same time point.

[0041] At block 434, method 450 may include etching the semiconductor structure using a high temperature dilution of about 2000 parts deionized water to about 1 part hydrofluoric acid. The dilution may have an elevated temperature in the range of 60 to 75 degrees Celsius. The high temperature dilution may be used as a wet etch. The high temperature dilution may be used to selectively etch the silicon protrusion without affecting other materials within the capacitor pillar. That is, the high temperature dilution may etch the underlying capping nitride material and silicon-based material without affecting other silicon-based or metal materials within the capacitor pillar.

[0042] At block 436, method 450 may include etching the semiconductor structure using a room temperature wet etch of about 300 parts deionized water to about 1 part hydrofluoric acid and a surface modification chemical. That is, the room temperature wet etch may consist of hydrofluoric acid, deionized water, and a surface modification chemical. The etching may use a room temperature in the range of 20 to 25 degrees Celsius. The room temperature wet etch may include a surface modification chemical. The surface modification chemical may prevent the semiconductor structure from tipping over during the etching process and make the surface of the semiconductor structure hydrophobic.

[0043] At block 438, method 450 may include reducing the resistance of the semiconductor structure using reduction stripping. The room temperature wet etching of block 436 may make the capacitor pillars hydrophobic. Reduction stripping may be used to remove the surface modification chemicals after the etching process is completed. That is, reduction stripping may be used to remove the hydrophobic effect of the surface modification chemicals. Reduction stripping may also be used to reduce the resistance of the semiconductor and reduce the oxidized metal material to the elemental metal material. The metal material may be oxidized by a dry etching process used to form the plurality of pillars.

[0044] Figure 5 is a functional block diagram of a system 560 for implementing an exemplary semiconductor manufacturing process according to various embodiments of the present disclosure. The system 560 may include a processing device 561. The processing device 561 may be configured to be capable of forming a semiconductor recess.

[0045] The processing equipment 561 can include a semiconductor processing chamber 562 to enclose a component configured to form a semiconductor recess. The chamber 562 can also enclose a carrier 563 to hold a batch of semiconductor wafers 564 (e.g., substrate material 120). The processing equipment 561 can include and / or be associated with a tool including, for example, a pump 565 unit and a purge 566 unit, which are configured to introduce and remove a reducing agent. The processing equipment 561 can also include a temperature control unit 567, which is configured to maintain the chamber 562 at an appropriate temperature as described herein.

[0046] System 560 may also include controller 568. Controller 568 may include or be associated with circuitry and / or programming for implementing, for example, the formation of a semiconductor recess. Adjustment of such deposition and cleaning operations by controller 568 may control the thickness of the materials (first silicon-based material, metal, second silicon-based material) described herein.

[0047] In various embodiments, the controller 568 may be configured to use hardware as a control circuit. For example, such a control circuit may be an application specific integrated circuit (ASIC) having logic for controlling the manufacturing steps through the associated deposition and cleaning processes to form a semiconductor recess.

[0048] Figure 6 6 is a functional block diagram of a computing system 680 including at least one memory array having an architecture formed according to one or more examples of the present disclosure. System 644 may be, for example, a solid state drive (SSD).

[0049] exist Figure 6 In the example shown, the system 644 includes a memory interface 646, a plurality of memory devices 640-1 ... 640-N, and a controller 648 that can be selectively coupled to the memory interface 646 and the memory devices 640-1 ... 640-N. The memory interface 646 can be used to transfer information between the system 644 and another device (such as a host 642). The host 642 can include a processor (not shown). As used herein, a "processor" can be a plurality of processors, such as a parallel processing system, a plurality of coprocessors, etc. An exemplary host can include or be implemented in a laptop computer, a personal computer, a digital camera, a digital recording device and playback device, a mobile phone, a PDA, a memory card reader, an interface hub, etc. Such a host 602 can be associated with manufacturing operations performed on a semiconductor device and / or an SSD using, for example, processing.

[0050] In a number of examples, the host 642 can be associated with (e.g., include or be coupled to) a host interface 643. The host interface 643 can allow for input of scaled preferences (e.g., in digitally and / or structurally defined gradients) to define, for example, a final structure or intermediate structure of a memory device to be implemented by a processing device (e.g., as shown at 640) and / or a critical dimension (CD) of a memory cell array formed thereon (e.g., as shown at 654). The scaled preferences can be set at the host interface 643 via input of a plurality of preferences stored by the host 642, input of preferences from another storage system (not shown), and / or input of preferences by a user (e.g., a human operator).

[0051] The memory interface 646 may be in the form of a standardized physical interface. For example, when the system 644 is used for information (e.g., data) storage in the computing system 680, the memory interface 646 may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, in addition to other physical connectors and / or interfaces. However, in general, the memory interface 606 may provide an interface for passing control, addresses, information, scaled preferences, and / or other signals between a controller 648 of the system 644 and a host 642 (e.g., via a host interface 643).

[0052] The controller 648 may include, for example, firmware and / or control circuitry (e.g., hardware). The controller 648 may be operatively coupled to and / or included on the same physical device (e.g., a die) as the one or more memory devices 640-1 ... 640-N. For example, the controller 648 may be or may include an ASIC as hardware that may be operatively coupled to a circuit (e.g., a printed circuit board) that includes the memory interface 646 and the memory devices 640-1 ... 640-N. Alternatively, the controller 648 may be included on a separate physical device that is communicatively coupled to a physical device (e.g., a die) that includes the one or more memory devices 640-1 ... 640-N.

[0053] The controller 648 can communicate with the memory devices 640-1...640-N to direct operations to read out (e.g., read), program (e.g., write) and / or erase information, as well as other functions and / or operations for managing memory cells. The controller 648 can have circuits that can include multiple integrated circuits and / or discrete components. In multiple examples, the circuits in the controller 648 can include control circuits for controlling access across the memory devices 640-1...640-N and / or circuits for providing a translation layer between the host 642 and the system 644.

[0054] For example, the memory devices 640-1 ... 640-N may include a plurality of memory arrays 654 (eg, arrays of volatile and / or non-volatile memory cells). For example, the memory devices 640-1 ... 640-N may include an array of memory cells, such as a plurality of memory arrays 654 (eg, arrays of volatile and / or non-volatile memory cells). Figures 1A-1D A portion of an exemplary memory device 670 of the described structure. As will be appreciated, the memory cells in the memory array 654 of the memory devices 640-1 ... 640-N and / or as shown at 776 can be in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash architecture (e.g., NAND, NOR, etc.), a three-dimensional (3D) RAM and / or flash memory cell architecture, or some other memory array architecture including pillars and adjacent trenches.

[0055] The memory devices 640, 776 may be formed on the same die. The memory device (e.g., memory device 640-1) may include one or more memory cell arrays 654 formed on the die. The memory device may include a readout circuit 555 and a control circuit 641 associated with the one or more arrays 654 formed on the die or a portion thereof. The readout circuit 655 may be used to determine (read out) a specific data value (e.g., 0 or 1) stored at a specific memory cell in a row of the array 654. In addition to directing the storage, erasure, etc. of data values ​​in response to commands from the host 642 and / or the host interface 643, the control circuit 641 may be used to direct the readout circuit 655 to read out a specific data value. The command may be sent directly to the control circuit 641 via the memory interface 646 or sent to the control circuit 641 via the controller 648.

[0056] Figure 6 The examples shown in the drawings may include additional circuits that are not shown so as not to obscure the examples of the present disclosure. For example, the memory devices 640, 776 may include address circuits to latch address signals provided on the I / O connectors through the I / O circuits. The address signals may be received and decoded by the row decoders and column decoders to access the memory array 654. It will be understood that the number of address input connectors may depend on the density and / or architecture of the memory devices 640, 776 and / or the memory array 654.

[0057] Figure 7 A cross-sectional view of a portion of an example of a semiconductor structure of a memory device 776 including structures formed according to various embodiments of the present disclosure is shown. Figure 7 The portion of the memory device 776 shown in the figure is shown as including a DRAM memory cell architecture by way of example and not limitation. Another RAM, flash (e.g., NAND or NOR) and / or 3D memory cell architecture may also include pillars and adjacent trenches. Embodiments are not limited thereto. Although the DRAM transistor 790 and capacitor 792 are shown as being arranged in a lateral configuration, embodiments may include transistors 790 and capacitors 692 arranged in a lateral, vertical, or any other configuration.

[0058] Figure 7 The portion of the memory device 776 shown in FIG. 7 can represent two DRAM memory cells in a 1T1C (one transistor one capacitor) configuration or one DRAM memory cell in a 2T2C configuration. The DRAM memory cell can utilize each capacitor 792 formed in the trench 796 to store a specific charge corresponding to a data value. Figure 7The formation of trench 796 as shown can result in the formation of pillars 788 from the etched material on each side of the trench 796. Pillar 788 can be formed (e.g., fabricated) as a layer of doped or undoped semiconductor material deposited on substrate material 798. The semiconductor material can be etched to form pillars 788 and trenches 796. In some embodiments, openings (e.g., circular, square, rectangular, etc. openings, rather than linear trenches) can be etched into the semiconductor material and capacitor material can be deposited in the openings, although this configuration does not affect the concept of passivation material for pillars adjacent to the trenches described herein.

[0059] Furthermore, embodiments of the present disclosure are not limited to forming capacitors in trenches for data storage, nor are they limited to trenches containing capacitor materials. For example, various types of memory devices may include trenches between sidewall structures (e.g., pillars) in which various materials may be positioned to facilitate data access, storage, and / or processing, or in which various materials may be formed for conduction and / or isolation (e.g., conductors, resistors, and / or dielectric materials), among other functions and / or operations.

[0060] In various embodiments, the trench 796 can be etched to a specific depth in the pillar material. The trench 796 can be etched to a depth in the material of the pillar 788 close to the depth of the substrate material 798, such as Figure 7 Alternatively, trench 796 can be etched into the material of pillar 788 to the top of substrate material 798 or into substrate material 798. The depth of trench 796 near the top of substrate material 798 and / or the depth near substrate material 798 is referred to herein as being in the bottom region of the trench.

[0061] As described herein, further deepening (e.g., etching) the trench into the pillar material or substrate material formed according to the embodiments described in Figures 1-5 can increase the surface area of ​​the trench boundary. In one example, increasing the surface area of ​​the trench boundary can increase the capacitance of the capacitor 792 formed in the trench 796 (e.g., by increasing the volume and / or surface area of ​​the capacitor). In this example, the trench 796 can be lined with a dielectric material 794, and the capacitor material can be formed (e.g., deposited) within the trench 796 and on the dielectric material 794 to form the capacitor 792 to a specific (e.g., target) depth.

[0062] Each pillar 788 of pillar material can extend to a specific height above the substrate material 798. In this way, each pillar 788 has a top surface at a specific height. A variety of structural materials can be formed on the top surface of the pillar 788 adjacent to the groove 796 or in association therewith. For example, a specific material 782 can be formed to facilitate data access, storage and / or processing (e.g., a conductor, a resistor and / or a dielectric material). Such a material 782 can be formed on the top surface of the pillar 788 adjacent to the groove 796. A masking material 711 can be formed to protect the underlying material 782 and / or the top surface of the pillar 788 adjacent to the groove 796 from subsequent processing and / or wear encountered when using the memory device 776. A masking material 711 can be formed on the top surface of the pillar 788 adjacent to the groove 796 or in association therewith (e.g., Figure 6 ) other structural materials. In addition to other possible structural materials, the other structural materials may include transistor 790, access line 786 and / or read line 778 and / or read line contact 779. The contact area between the read line contact and the semiconductor material may be an active area 781 of the read line contact. The active area 781 may also be associated with multiple access lines 786. The structural material just described as being formed on the top surface of the column 788 adjacent to the groove 796 and / or associated with the top surface of the column 788 adjacent to the groove 796 is referred to herein as being located in the top area of ​​the column 788 and / or the groove 796.

[0063] In the above detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which is shown by way of illustration one or more examples of how the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the examples of the present disclosure, and it should be understood that other examples may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0064] It should be understood that the terms used herein are used only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" include singular and plural referents unless the context clearly indicates otherwise. Similarly, "multiple", "at least one" and "one or more" (for example, multiple memory arrays can refer to one or more memory arrays), while "multiple" is intended to refer to more than one such thing. In addition, the words "can" and "may" are used throughout this application in a permissive sense (i.e., with the potential, able to), rather than a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to". The terms "coupled" and "coupling" mean physically connected directly or indirectly, and unless otherwise specified, may include wireless connections for accessing and / or moving (transmitting) instructions (e.g., control signals, address signals, etc.) and data, as appropriate to the context.

[0065] Although illustrative examples have been illustrated and described herein, semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicon-based materials, nitride materials, buffer materials, etching chemicals, etching processes, solvents, memory devices, memory cells, sidewalls of openings and / or trenches are included, in addition to various combinations and configurations of other materials and / or components associated with the formation of semiconductor recesses. The examples of the present disclosure are not limited to those combinations explicitly listed herein. Other combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemicals, etching processes, solvents, memory devices, memory cells, sidewalls of openings and / or trenches associated with the formation of semiconductor recesses (other than those disclosed herein) are expressly included within the scope of the present disclosure.

[0066] Although specific examples have been illustrated and described herein, it will be understood by those skilled in the art that the specific examples shown may be replaced by arrangements calculated to obtain the same results. The present disclosure is intended to cover modifications or variations of one or more examples of the present disclosure. It should be understood that the above description is provided in an illustrative rather than a restrictive manner. By reading the above description, the combination of the above examples and other examples not specifically described herein will be clear to those skilled in the art. The scope of one or more examples of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more examples of the present disclosure should be determined with reference to the full scope of the attached claims and the equivalents authorized by these claims.

[0067] In the foregoing detailed description, some features are grouped together in a single example to simplify the disclosure. The disclosed method should not be interpreted as reflecting the intention that the disclosed examples of the disclosure must use more features than the features explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the invention lies in less than all the features of a single disclosed example. Therefore, the attached claims are hereby incorporated into the detailed description, with each claim independently serving as a separate example.

Claims

1. A method for etching a semiconductor structure, comprising: etching the semiconductor structure using a dilution of an acid and water at a first temperature, the first temperature being in a range of 60 to 75 degrees Celsius; as well as The semiconductor structure is etched using a wet etch using acid and water and a surface modification chemical at a second temperature in the range of 20 to 25 degrees Celsius, the surface modification chemical being used to render the surface of the semiconductor structure hydrophobic.

2. The method of claim 1 further comprising etching the semiconductor structure using hydrofluoric acid in the dilution of acid and water at the first temperature.

3. The method of claim 1 further comprising etching the semiconductor structure at the first temperature using a ratio of about 2000 parts water to about 1 part acid in the dilution of acid and water.

4. The method of claim 1 further comprising etching the semiconductor structure at the second temperature in the wet etch of acid and water using a ratio of about 300 parts water to about 1 part acid. 5 . The method of claim 1 , further comprising using deionized water in the dilution of acid and water at the first temperature and in the wet etching of acid and water at the second temperature.

6. A method for etching a semiconductor structure, comprising: patterning the semiconductor structure using a dilution of acid and water at a first temperature to remove nitride bumps on the capacitor structure, the first temperature being in a range of 60 to 75 degrees Celsius; patterning the semiconductor structure at a second temperature using an acid and water and a dilution of a surface modification chemical, the second temperature being in the range of 20 to 25 degrees Celsius, the surface modification chemical being used to render the surface of the semiconductor structure hydrophobic; as well as The semiconductor structure is patterned using reductive stripping to reduce the resistance of the semiconductor structure and remove the surface modification chemical.

7. The method of claim 6, further comprising using the dilution as a wet etch at the first temperature and the second temperature.

8. The method of claim 6, further comprising initiating the second temperature after completing the dilution at the first temperature.

9. The method of claim 6, further comprising shaping the semiconductor structure into a rectilinear profile having an increased area for depositing capacitor material.

10. A method for etching a semiconductor structure, comprising: etching the semiconductor structure using a dilution of about 2000 parts deionized water to about 1 part hydrofluoric acid at a first temperature, the first temperature being in a range of 60 to 75 degrees Celsius; The semiconductor structure is etched using: wet etching with about 300 parts deionized water to about 1 part hydrofluoric acid and a surface modification chemical at a second temperature, the second temperature being in the range of 20 to 25 degrees Celsius, the surface modification chemical being used to render the surface of the semiconductor structure hydrophobic; as well as Reductive stripping is performed to reduce the resistance of the semiconductor structure. 11 . The method of claim 10 , wherein etching the semiconductor structure comprises etching a first aspect ratio semiconductor structure having a silicon layer and a metal layer, the first aspect ratio being in a range of 25:1 to 50:

1.

12. The method of claim 11 further comprising forming a nitride layer over the etched silicon and metal layers. 13 . The method of claim 11 , wherein etching the semiconductor structure comprises etching the first aspect ratio semiconductor structure having a first silicon layer as a semiconductor.

14. The method of claim 11, further comprising etching the semiconductor structure having tungsten as the metal layer.

15. The method of claim 11, wherein etching the semiconductor structure comprises etching the first aspect ratio semiconductor structure having a second silicon layer as a dielectric.

16. The method of claim 11, further comprising selectively etching the silicon layer using the dilution at the first temperature.

17. The method of claim 10, further comprising performing a reductive stripping, wherein the reductive stripping comprises oxygen and hydrogen.

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