Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0034007, filed on March 26, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This invention relates to a semiconductor package. For example, the invention relates to the shape, structure, and layout of reinforcements for effectively controlling the warpage of a semiconductor package substrate. Background Technology

[0003] With the trend towards miniaturization, thinning, and high density in electronic products, printed circuit boards (PCBs) are also becoming smaller and thinner. Furthermore, PCB design has become more complex due to the increasing demands for multifunctionality, high-capacity data transmission and reception beyond the portability of electronic devices, requiring advanced technical expertise. Consequently, the demand for multilayer PCBs on which power circuits, grounding circuits, signal circuits, and other circuits are formed is increasing.

[0004] For example, various semiconductor chips, such as central processing units and power integrated circuits, are mounted on multilayer printed circuit boards. During operation, high temperatures can be generated within these semiconductor chips. If this high-temperature heat is transferred to the semiconductor chips performing storage functions, it can cause malfunctions such as damage to the storage cells.

[0005] As multilayer printed circuit boards (PCBs) become increasingly thinner, warpage can increase. Increased warpage in multilayer PCBs can break ball (e.g., solder ball) contacts, leading to semiconductor chip failure. Summary of the Invention

[0006] One aspect of the present invention is to provide a semiconductor package in which warpage is effectively controlled.

[0007] Another aspect of the present invention is a semiconductor package in which temperature transfer between semiconductor chips is controlled.

[0008] According to some aspects of the present invention, a semiconductor package includes: a first substrate; a second substrate disposed on the first substrate; a first semiconductor chip disposed on the second substrate; and a reinforcement extending from an upper surface of the first substrate to an upper surface of the second substrate, the reinforcement not contacting the first semiconductor chip, wherein a first height from the upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to the uppermost surface of the reinforcement.

[0009] According to some embodiments of the present invention, a semiconductor package includes: a first substrate; a second substrate disposed on the first substrate; a first semiconductor chip disposed on the second substrate; a reinforcement extending from an upper surface of the first substrate to an upper surface of the second substrate, the reinforcement not contacting the first semiconductor chip; and a first air gap located between the reinforcement and a sidewall of the second substrate.

[0010] According to some embodiments of the present invention, a semiconductor package includes: a first substrate; a second substrate disposed on the first substrate; a first semiconductor chip disposed on the second substrate; a second semiconductor chip disposed on the second substrate, the second semiconductor chip being horizontally spaced apart from the first semiconductor chip; a reinforcement extending from an upper surface of the first substrate to an upper surface of the second substrate, the reinforcement not contacting the first semiconductor chip or the second semiconductor chip; a first air gap between the reinforcement and the first semiconductor chip; and a second air gap between the reinforcement and the second semiconductor chip.

[0011] According to some embodiments of the present invention, a semiconductor package includes: a first substrate including a first region and a second region surrounding the periphery of the first region; a second substrate disposed on the first region, the second substrate including a third region and a fourth region surrounding the periphery of the third region; a first semiconductor chip disposed on the third region; a second semiconductor chip disposed on the third region, the second semiconductor chip being horizontally spaced from the first semiconductor chip; and a reinforcement extending along the second region, wherein the reinforcement extends further from an upper surface of the first substrate to an upper surface of the second substrate, and the reinforcement does not contact the first semiconductor chip or the second semiconductor chip.

[0012] According to some embodiments of the present invention, a semiconductor package includes: a first substrate including a first region and a second region surrounding the periphery of the first region; a second substrate disposed on the first region, the second substrate including a third region and a fourth region surrounding the periphery of the third region; a first semiconductor chip disposed on the third region; a second semiconductor chip disposed on the third region, the second semiconductor chip being horizontally spaced from the first semiconductor chip in a first direction; a third semiconductor chip disposed on the third region, the third semiconductor chip being horizontally spaced from the first semiconductor chip in a first direction and horizontally spaced from the second semiconductor chip in a second direction; and a reinforcement extending along the second region, wherein the reinforcement extends further from an upper surface of the first substrate to an upper surface of the second substrate, and the reinforcement further extends between the second semiconductor chip and the third semiconductor chip on the second substrate.

[0013] However, the aspects of the inventive concept are not limited to those set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art from the detailed description of the inventive concept given below. Attached Figure Description

[0014] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0015] Figure 1 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0016] Figure 2 It is along Figure 1 A cross-sectional view taken by line A-A'.

[0017] Figure 3 It is shown Figure 2 A magnified view of region I.

[0018] Figure 4 It is along Figure 1 A cross-sectional view taken by line B-B'.

[0019] Figure 5 It is shown Figure 4 A magnified view of area II.

[0020] Figure 6 It is along Figure 1 A cross-sectional view taken by line C-C'.

[0021] Figure 7This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0022] Figure 8 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0023] Figure 9 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0024] Figure 10 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0025] Figure 11 It is along Figure 10 A cross-sectional view taken by line D-D'.

[0026] Figure 12 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0027] Figure 13 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0028] Figure 14 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0029] Figure 15 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments.

[0030] Figure 16 This is an exemplary cross-sectional view illustrating a semiconductor package according to some embodiments.

[0031] Explanation of icon numbers

[0032] 100: First substrate;

[0033] 100a, 200a: First surface;

[0034] 100b, 200b: Second surface;

[0035] 100u, 300u: Top surface;

[0036] 101: Fifth side;

[0037] 102: Sixth side;

[0038] 110: First connection terminal;

[0039] 200: Second substrate;

[0040] 200s: First sidewall;

[0041] 201: First side;

[0042] 202: Second side;

[0043] 203: Seventh side;

[0044] 204: Eighth side;

[0045] 210: Second connection terminal;

[0046] 220: First bottom filling material;

[0047] 300: First Semiconductor Chip;

[0048] 300s: Second sidewall;

[0049] 301: Third side;

[0050] 302: Fourth side;

[0051] 310: Second semiconductor chip;

[0052] 320: Third semiconductor chip;

[0053] 330: The fourth semiconductor chip;

[0054] 340: The fifth semiconductor chip;

[0055] 341: Third connection terminal;

[0056] 350: The sixth semiconductor chip;

[0057] 351: Second bottom filling material;

[0058] 360: The Seventh Semiconductor Chip;

[0059] 370: The eighth semiconductor chip;

[0060] 380: The ninth semiconductor chip;

[0061] 400: Reinforcing component;

[0062] 400a: Part 1;

[0063] 400b: Part Two;

[0064] 400c: Part Three;

[0065] 400u: top surface;

[0066] 500: Interface film;

[0067] 600: Heatsink;

[0068] AG1: First air gap;

[0069] AG2: Second air gap;

[0070] AG3: Third air gap;

[0071] A-A', B-B', C-C', D-D': lines;

[0072] CR1: First region;

[0073] H1: First altitude;

[0074] H2: Second altitude;

[0075] I, II: Regions;

[0076] P1: First connection path;

[0077] P2: Second connection path;

[0078] P3: Third connection path;

[0079] PR1: Second Region;

[0080] X1: First direction;

[0081] X2: Third-party;

[0082] Y1: Second direction;

[0083] Y2: Fourth direction. Detailed Implementation

[0084] Figure 1 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken by line A-A'. Figure 3 It is shown Figure 2 A magnified view of region I. Figure 4 It is along Figure 1 A cross-sectional view taken by line B-B'. Figure 5 It is shown Figure 4 A magnified view of area II. Figure 6 It is along Figure 1 A cross-sectional view taken by line C-C'.

[0085] See Figure 1A semiconductor package according to some embodiments may include a first substrate 100, a second substrate 200, a first semiconductor chip 300, a second semiconductor chip 310, a third semiconductor chip 320, a fourth semiconductor chip 330, a fifth semiconductor chip 340, and a reinforcing member 400. Although the figures show the first semiconductor chips 300 to the fifth semiconductor chips 340 disposed on the second substrate 200, the invention is not limited to the number of semiconductor chips disposed on the second substrate 200. For example, a semiconductor package according to some embodiments may be configured as a multi-chip package. For example, a semiconductor package according to some embodiments may include two or more semiconductor chips.

[0086] Each of the first semiconductor chips 300 to the fifth semiconductor chips 340 may be a semiconductor chip performing a specific function, such as a bare die formed from a semiconductor wafer. For example, the first semiconductor chip 300 may be a semiconductor chip performing the logic function of a memory device. For example, the second semiconductor chip 310 to the fifth semiconductor chip 340 may be memory chips performing the storage function of a memory device. However, the invention is not limited thereto, and the first semiconductor chip 300 to the fifth semiconductor chip 340 may perform functions different from those described above.

[0087] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. Unless the context otherwise indicates, these terms are used only to distinguish one element, component, region, layer, or segment from another, for example, as a naming convention. Therefore, without departing from the teachings of the invention, a first element, component, region, layer, or segment discussed in one section of the specification may be referred to as a second element, component, region, layer, or segment in another section of the specification or in the claims. Furthermore, in some cases, even if the terms "first," "second," etc., are not used in the specification, they may still be referred to as "first" or "second" in the claims to distinguish different claimed elements from each other.

[0088] First semiconductor chips 300 to fifth semiconductor chips 340 may be disposed on second substrate 200. First semiconductor chips 300 to fifth semiconductor chips 340 may be spaced apart from each other on second substrate 200. For example, on second substrate 200, second semiconductor chip 310 and fourth semiconductor chip 330 may be spaced apart from each other in a first direction X1 and may be disposed on opposite sides of first semiconductor chip 300. Furthermore, on second substrate 200, third semiconductor chip 320 and fifth semiconductor chip 340 may be spaced apart from each other in the first direction X1 and may be disposed on opposite sides of first semiconductor chip 300. For example, second semiconductor chip 310 and third semiconductor chip 320 may be spaced apart from each other in a second direction Y1 and may be disposed on one side of first semiconductor chip 300. Similarly, fourth semiconductor chip 330 and fifth semiconductor chip 340 may be spaced apart from each other in the second direction Y1 and may be disposed on the other side of first semiconductor chip 300. For example, the second semiconductor chip 310, the third semiconductor chip 320, the fourth semiconductor chip 330 and the fifth semiconductor chip 340 may be disposed on the second substrate 200, thereby being spaced apart from the first semiconductor chip 300 in the first direction X1.

[0089] The first substrate 100 may be a packaging substrate, such as a printed circuit board (PCB), a ceramic substrate, or the like. For example, the first substrate 100 may include multiple insulating films and an internal wiring layer. For example, the internal wiring layer may be disposed between two of the multiple insulating films. The second substrate 200 may be an insert substrate and may include, for example, FR4, polyimide, silicon, glass, or the like.

[0090] The first substrate 100 and the second substrate 200 may be interconnected. For example, the first substrate 100 and the second substrate 200 may be electrically connected to each other via a conductive material (e.g., solder balls or wires). The first semiconductor chip 300 to the fifth semiconductor chip 340 may be connected to the second substrate 200. For example, the first semiconductor chip 300, the second semiconductor chip 310, the third semiconductor chip 320, the fourth semiconductor chip 330, and the fifth semiconductor chip 340 may be electrically connected to and / or fixed to the second substrate 200. The first semiconductor chip 300 to the fifth semiconductor chip 340 may be interconnected via the interior of the second substrate 200. For example, the first semiconductor chip 300, the second semiconductor chip 310, the third semiconductor chip 320, the fourth semiconductor chip 330, and the fifth semiconductor chip 340 may be electrically connected to each other, for example, via wires formed within the second substrate 200. Further reference Figure 2 and Figure 3 An example is provided.

[0091] See Figures 1 to 3 A first connection terminal 110 may be disposed on a first surface 100a of the first substrate 100. The first connection terminal 110 may be used to electrically connect a semiconductor package according to some embodiments to an external device or circuit. Although the figures show solder balls as the first connection terminal 110, the invention is not limited thereto.

[0092] The second substrate 200 may be disposed on the second surface 100b of the first substrate 100. The first substrate 100 and the second substrate 200 may be electrically connected to each other via a second connection terminal 210. For example, the second connection terminal 210 may be disposed between the second surface 100b of the first substrate 100 and the first surface 200a of the second substrate 200, and may contact each of the first substrate 100 and the second substrate 200. For example, the second connection terminal 210 may be directly connected to the first substrate 100 and the second substrate 200 without any intervening layer or material. The space between the second connection terminals 210 may be filled with a first underfill material 220. The first underfill material 220 may be filled to enclose each of the second connection terminals 210, thereby protecting the second connection terminals 210.

[0093] It will be understood that when an element is referred to as "connected" or "coupled" to another element or "on" another element, it may be directly connected or coupled to the other element or on the other element, or there may be an intervening element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, or referred to as "contacting" or "in contact with" another element, there is no intervening element (e.g., the elements are in contact). Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "proximately" and "directly adjacent to," etc.).

[0094] First semiconductor chips 300 to fifth semiconductor chips 340 may be disposed on the second surface 200b of the second substrate 200. As described above, the first semiconductor chips 300 to fifth semiconductor chips 340 may be spaced apart from each other. The second substrate 200 and the first semiconductor chip 300 may be electrically connected to each other via a third connection terminal 341. For example, the third connection terminal 341 may be disposed between the second surface 200b of the second substrate 200 and the first semiconductor chip 300, and may contact each of the second substrate 200 and the first semiconductor chip 300. Similarly, the second substrate 200 and the second semiconductor chip 310 may be electrically connected to each other via the third connection terminal 341. For example, the third connection terminal 341 may be disposed between the second surface 200b of the second substrate 200 and the second semiconductor chip 310, and may contact each of the second substrate 200 and the second semiconductor chip 310. The space between the third connection terminals 341 may be filled with a second bottom filler material 351. For example, a second bottom filler material 351 can be filled to cover each of the third connection terminals 341, thereby protecting the third connection terminals 341.

[0095] Similarly, each of the third semiconductor chip 320 to the fifth semiconductor chip 340 can be electrically connected to the second substrate 200 via the third connection terminal 341. For ease of description, a detailed description of the connection relationship between the second substrate 200 and the third semiconductor chip 320 to the fifth semiconductor chip 340 will not be provided.

[0096] According to some embodiments, the first underfill material 220 and the second underfill material 351 may comprise an epoxy resin, benzocyclobutene, or polyimide. However, the invention is not limited thereto. For example, the first underfill material 220 and the second underfill material 351 may also comprise silica filler. In another example, the first underfill material 220 and the second underfill material 351 may comprise an adhesive and a flux. The flux may comprise an oxide film remover. In yet another example, the first underfill material 220 and the second underfill material 351 may comprise silica filler and flux. In yet another example, the first underfill material 220 and the second underfill material 351 may comprise a non-conductive paste.

[0097] According to some embodiments, the first semiconductor chip 300 and the second semiconductor chip 310 can be electrically connected to each other via a second substrate 200. For example, the first semiconductor chip 300 and the second semiconductor chip 310 can be electrically connected to each other via a first connection path P1 formed in the second substrate 200. For example, the first connection path P1 can be a conductor pattern. For example, a third connection terminal 341 on the first semiconductor chip 300 and a third connection terminal 341 on the second semiconductor chip 310 can be electrically connected to each other via the first connection path P1 formed in the second substrate 200. The first semiconductor chip 300 and the second semiconductor chip 310 can transmit and receive electrical signals to each other via the first connection path P1. For ease of description, simplification is provided. Figure 3 The shape of the first connection path P1 shown is not limited to this. For example, depending on the embodiment, the first connection path P1 may also have a more complex shape. Similarly, the first semiconductor chip 300 to the fifth semiconductor chip 340 may be electrically connected to each other via the second substrate 200. Similarly, the first semiconductor chip 300 to the fifth semiconductor chip 340 may transmit and receive electrical signals to each other. For ease of description, Figure 3 Only the connection relationship between the first semiconductor chip 300 and the second semiconductor chip 310 is shown. Although for ease of explanation, Figure 3 Only one first connection path P1 is shown for the electrical connection between the first semiconductor chip 300 and the second semiconductor chip 310, but the invention is not limited thereto. For example, the first semiconductor chip 300 and the second semiconductor chip 310 can be electrically connected to each other through two or more connection paths.

[0098] According to some embodiments, the first semiconductor chip 300 can be electrically connected to an external device or circuit via a first connection terminal 110. For example, a third connection terminal 341 disposed on the first semiconductor chip 300 can be electrically connected to a second connection path P2 formed in the second substrate 200, and the second connection path P2 can be electrically connected to the second connection terminal 210. For example, the second connection path P2 can be a conductor pattern. The second connection terminal 210 can be electrically connected to the first connection terminal 110 via a third connection path P3 formed in the first substrate 100. For example, the third connection path P3 can be a conductor pattern. For example, the first semiconductor chip 300 can receive electrical power and / or electrical signals from an external device or circuit. For example, the electrical power and / or electrical signals supplied to the first connection terminal 110 can be provided to the first semiconductor chip 300 via the third connection path P3, the second connection terminal 210, the second connection path P2, and the third connection terminal 341. However, this is illustrative, and the invention is not limited thereto. Similarly, the second semiconductor chip 310 to the fifth semiconductor chip 340 can be electrically connected to an external device or circuit, for example, to receive and / or transmit electrical power and / or electrical signals.

[0099] See again Figure 1 The first substrate 100 may include a first region CR1 and a second region PR1 surrounding the first region CR1. For example, the first region CR1 may be the central region of the first substrate 100, and the second region PR1 may be the peripheral region of the first substrate 100.

[0100] According to some embodiments, a second substrate 200 may be disposed in a first region CR1 of a first substrate 100. At least a portion of a reinforcement 400 may be disposed in a second region PR1 of the first substrate 100. For example, at least a portion of the reinforcement 400 may extend along the second region PR1 of the first substrate 100. The reinforcement 400 may prevent / reduce warping in the first substrate 100. For example, the reinforcement 400 may be made of one or more materials selected from steel, stainless steel, aluminum, and copper, such as a thermally conductive material. Therefore, the reinforcement 400 may include a metal layer. From a top view, the reinforcement 400 may have a shape including, for example, an annular shape or a closed loop shape. As illustrated in the figures, a portion of the reinforcement 400 may extend diagonally at an angle relative to the top surface of the first substrate 100. The reinforcement may be a thermally conductive layer, for example, to conduct heat between two items to which it is connected. For example, the reinforcement 400 may have one or more of the characteristics described in Table 1 below to reduce / prevent warping of the first substrate 100 and / or the second substrate 200.

[0101] [Table 1]

[0102]

[0103] At least a portion of the reinforcing member 400 may extend from the first substrate 100 to the second substrate 200. For example, the reinforcing member 400 may be disposed on a first region CR1 and a second region PR1 of the first substrate 100. For example, the reinforcing member 400 may extend from the first region CR1 of the first substrate 100 to a portion of the second substrate 200 between a second semiconductor chip 310 and a third semiconductor chip 320 disposed on the second substrate 200. In some embodiments, the reinforcing member 400 may extend from the first region CR1 of the first substrate 100 to a portion between the second semiconductor chip 310 and the third semiconductor chip 320 of the first substrate 100. The reinforcing member 400 may extend from the first region CR1 of the first substrate 100 to a portion between a fourth semiconductor chip 330 and a fifth semiconductor chip 340 of the second substrate 200. The reinforcing member 400 disposed on the second substrate 200 may prevent / reduce warping in the second substrate 200. See also Figure 4 and Figure 5 The shape of the reinforcing member 400 extending from the first substrate 100 to the second substrate 200 is further described.

[0104] See Figure 1 , Figure 4 as well as Figure 5 The reinforcing member 400 may extend from the first substrate 100 to the second substrate 200. An interface film 500 may be further disposed on the second substrate 200 between the reinforcing member 400 and the second substrate 200. For example, the reinforcing member 400 and the second substrate 200 may be connected to each other via the interface film 500.

[0105] According to some embodiments, the interface film 500 may comprise a combination of silicone resin (Si resin) and a first material. The first material may comprise a material with a thermal conductivity of 10 W / (m·K) or greater than 10 W / (m·K). According to some embodiments, the first material may comprise at least one of Al₂O₃, Al, and ZnO. For example, the interface film 500 may comprise a combination of silicone resin and Al₂O₃, but the invention is not limited thereto.

[0106] According to some embodiments, a first height H1 from the upper surface 100u of the first substrate 100 to the upper surface 300u of the first semiconductor chip 300 may be greater than a second height H2 from the upper surface 100u of the first substrate 100 to the uppermost surface 400u of the reinforcing member 400. For example, the upper surface 300u of the first semiconductor chip 300 may protrude from the uppermost surface 400u of the reinforcing member 400. For example, the first height H1 and the second height H2 may be distances in a direction perpendicular to the upper surface 100u of the first substrate 100.

[0107] In a semiconductor package according to some embodiments, heat sinks (e.g., provided on the first semiconductor chip 300 to the fifth semiconductor chip 340) are used. Figure 16 The heat generated by the first semiconductor chip 300 to the fifth semiconductor chip 340 can be released to the outside by a reinforcement 400 (or similar device). If the first height H1 is less than the second height H2, the heat generated by the first semiconductor chip 300 to the fifth semiconductor chip 340 may not be effectively released due to the interference of the reinforcement 400, even when a heat sink is installed. For example, when the first height H1 is less than the second height H2, the heat sink may not contact the semiconductor chips 300, 310, 320, 330, and 340. Therefore, according to some embodiments, by arranging the reinforcement 400 such that the first height H1 is greater than the second height H2, the heat generated by the first semiconductor chip 300 to the fifth semiconductor chip 340 can be effectively released.

[0108] The term “heat-conductive or thermally-conductive” is not only unsuitable for a particular material because it provides incidental thermal conduction, but is intended to refer to materials commonly referred to as good thermal conductors or known to have thermal conductivity, or components having similar thermal conductivity properties to these materials.

[0109] According to some embodiments, the reinforcing member 400 may include a first portion 400a connected to and / or disposed on a first substrate 100, and a second portion 400b connected to and / or disposed on a second substrate 200. Furthermore, the reinforcing member 400 may also include a third portion 400c connecting the first portion 400a and the second portion 400b. The third portion 400c of the reinforcing member 400 may not be in contact with the first sidewall 200s of the second substrate 200. For example, the first sidewall 200s of the second substrate may be exposed to air. Furthermore, the third portion 400c of the reinforcing member 400 may not be in contact with the upper surface 100u of the first substrate 100. For example, free space may exist between the third portion 400c of the reinforcing member 400, the first substrate 100, and the first sidewall 200s of the second substrate 200. For example, a first air gap AG1 may be formed / placed between the third portion 400c of the reinforcing member 400, the first sidewall 200s of the second substrate 200, and the upper surface 100u of the first substrate 100. For example, the first air gap AG1 may be filled with air. In some embodiments, the first air gap AG1 may be filled with a gas. For example, the gas may be nitrogen.

[0110] As mentioned above, the reinforcing member 400 prevents / reduces warping of the first substrate 100 and the second substrate 200. In this case, if the reinforcing member 400 contacts the first sidewall 200s of the second substrate 200, the force preventing / reducing warping of the first substrate 100 and the second substrate 200 can be transmitted to the second substrate 200. For example, when the reinforcing member 400 contacts the first sidewall 200s of the second substrate 200, physical stress in the lateral direction can be transmitted, for example, from the first substrate 100 and / or the second substrate 200 to the second substrate 200. In this situation, deformation can occur in the second substrate 200 due to the physical stress in the lateral direction, and the connection between the first substrate 100 and the second substrate 200 can be broken. Therefore, according to some embodiments of the present invention, by forming / arranging a first air gap AG1 between the reinforcing member 400 and the first sidewall 200s of the second substrate 200, the physical stress transmitted to the second substrate 200 can be reduced.

[0111] According to some embodiments, the reinforcing member 400 does not contact the second sidewall 300s of the first semiconductor chip 300. For example, the second sidewall 300s of the first semiconductor chip 300 may be exposed to air. For example, a free space may exist between the first semiconductor chip 300 and the reinforcing member 400. For example, a second air gap AG2 may be formed / placed between the second portion 400b of the reinforcing member 400 and the second sidewall 300s of the first semiconductor chip 300. For example, the second air gap AG2 may be filled with air or a gas such as nitrogen. Reference will be made below. Figure 6 To provide another interpretation.

[0112] According to some embodiments, the reinforcing member 400 does not contact the second semiconductor chip 310. For example, a free space may exist between the second portion 400b of the reinforcing member 400 and the second semiconductor chip 310. Furthermore, the reinforcing member 400 may not contact the third semiconductor chip 320. For example, a free space may exist between the second portion 400b of the reinforcing member 400 and the third semiconductor chip 320. For example, a third air gap AG3 may be formed / placed between the reinforcing member 400 and the second semiconductor chip 310, and between the reinforcing member 400 and the third semiconductor chip 320. For example, the third air gap AG3 may be filled with air or a gas such as nitrogen.

[0113] For ease of explanation, it is assumed that the first semiconductor chip 300 is a logic chip of the memory device, and that the second semiconductor chip 310 and the third semiconductor chip 320 are memory chips of the memory device. For example, each chip described herein may be a single chip or a stacked chip. As mentioned above, the reinforcing member 400 and the first semiconductor chip 300 may not be in contact with each other. For example, a second air gap AG2 may be formed / placed between the reinforcing member 400 and the first semiconductor chip 300. The reinforcing member 400 and the second semiconductor chip 310 may not be in contact with each other. The reinforcing member 400 and the third semiconductor chip 320 may not be in contact with each other. For example, a third air gap AG3 may be formed / placed between the reinforcing member 400 and the second semiconductor chip 310, and between the reinforcing member 400 and the third semiconductor chip 320.

[0114] When the semiconductor package according to some embodiments is operated, the first semiconductor chip 300 may generate more heat than the second semiconductor chip 310 and the third semiconductor chip 320. If the reinforcement 400 is arranged to contact the first semiconductor chip 300, the second semiconductor chip 310, and the third semiconductor chip 320, for example, if a second air gap AG2 and / or a third air gap AG3 are not formed / placed between the reinforcement 400 and the first semiconductor chip 300, the second semiconductor chip 310, and the third semiconductor chip 320, then the heat generated by the first semiconductor chip 300 can be transferred to the second semiconductor chip 310 and the third semiconductor chip 320. Since memory chips are susceptible to heat, the second semiconductor chip 310 and the third semiconductor chip 320 may malfunction or the memory cells may be damaged. Therefore, by forming / placed a second air gap AG2 and / or a third air gap AG3 between the reinforcement 400 and the first semiconductor chip 300, the second semiconductor chip 310, and the third semiconductor chip 320 according to some embodiments, heat transfer to the high-temperature-sensitive semiconductor chips can be prevented. Furthermore, by forming / arranging a second air gap AG2 and / or a third air gap AG3 between the reinforcing member 400 according to some embodiments and the first semiconductor chip 300, the second semiconductor chip 310 and the third semiconductor chip 320, failures of the semiconductor package according to some embodiments can be prevented / reduced.

[0115] Similarly, each of the fourth semiconductor chip 330 and the fifth semiconductor chip 340 may not be in contact with the reinforcement 400. For example, an air gap may be formed / placed between the reinforcement 400 and the fourth semiconductor chip 330, and between the reinforcement 400 and the fifth semiconductor chip 340.

[0116] Figure 7 This is an exemplary layout diagram used to explain semiconductor packages according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0117] See Figure 7 According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a first semiconductor chip 300 to a fifth semiconductor chip 340, and a reinforcing member 400. The second substrate 200 may be disposed on the first substrate 100. The first semiconductor chip 300 to the fifth semiconductor chip 340 may be disposed on the second substrate 200.

[0118] According to some embodiments, the reinforcing member 400 may extend further from the first substrate 100 to the second substrate 200 along a second direction Y1, for example, to be formed on the first substrate 100 and the second substrate 200. The second direction Y1 may be perpendicular to the first direction X1. The reinforcing member 400 may not contact the first semiconductor chip 300 to the fifth semiconductor chip 340 on the second substrate 200. For example, an air gap may be formed / placed between the reinforcing member 400 and the first semiconductor chip 300 to the fifth semiconductor chip 340. Furthermore, as described above, the air gap may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. The air gap may be filled with air or a gas such as nitrogen. Figure 7 The cross-sectional view taken by line B-B' can be similar to Figure 4 A cross-sectional view. Therefore, no explanation will be provided.

[0119] Figure 8 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0120] See Figure 8 According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a first semiconductor chip 300 to a fifth semiconductor chip 340, and a reinforcing member 400. The second substrate 200 may be disposed on the first substrate 100. The first semiconductor chip 300 to the fifth semiconductor chip 340 may be disposed on the second substrate 200.

[0121] According to some embodiments, the reinforcement 400 may further extend to surround the periphery of the first semiconductor chip 300 to the fifth semiconductor chip 340 on the second substrate 200. For example, the reinforcement 400 may further extend on the second substrate 200 in a first direction X1 and a second direction Y1 (e.g., along the edge of the second substrate 200).

[0122] The reinforcing member 400 may not contact the first to fifth semiconductor chips 300 on the second substrate 200. For example, air gaps may be formed / placed between the reinforcing member 400 and the first to fifth semiconductor chips 300, respectively. Furthermore, as described above, air gaps may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. Figure 8 The cross-sectional view taken by line B-B' can be similar to Figure 4 Therefore, no explanation will be provided.

[0123] Figure 9 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0124] See Figure 9 According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a first semiconductor chip 300, a second semiconductor chip 310, a fourth semiconductor chip 330, and a reinforcing member 400. The second substrate 200 may be disposed on the first substrate 100. The first semiconductor chip 300, the second semiconductor chip 310, and the fourth semiconductor chip 330 may be disposed on the second substrate 200.

[0125] According to some embodiments, the reinforcement 400 may further extend to surround three sides of the second semiconductor chip 310 on the second substrate 200. Similarly, the reinforcement 400 may further extend to surround three sides of the fourth semiconductor chip 330 on the second substrate 200.

[0126] The reinforcing member 400 may not contact the first semiconductor chip 300, the second semiconductor chip 310, and the fourth semiconductor chip 330 on the second substrate 200. For example, air gaps may be formed / placed between the reinforcing member 400 and the first semiconductor chip 300, between the reinforcing member 400 and the second semiconductor chip 310, and between the reinforcing member 400 and the fourth semiconductor chip 330, respectively. Furthermore, as described above, air gaps may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. Figure 9 The cross-sectional view taken by line B-B' can be similar to Figure 4 Therefore, no explanation will be provided.

[0127] Figure 10 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. Figure 11 It is along Figure 10 A cross-sectional view taken by line D-D'. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0128] See Figure 10 and Figure 11 According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a sixth semiconductor chip 350, a seventh semiconductor chip 360, and a reinforcing member 400. The sixth semiconductor chip 350 and the seventh semiconductor chip 360 may be disposed on the second substrate 200. The sixth semiconductor chip 350 and the seventh semiconductor chip 360 may be spaced apart from each other on the second substrate 200 in a second direction Y1.

[0129] According to some embodiments, the reinforcement 400 may extend along a gap formed between a sixth semiconductor chip 350 and a seventh semiconductor chip 360 on the second substrate 200. For example, the reinforcement 400 may extend from the first substrate 100 to the second substrate 200 between the sixth semiconductor chip 350 and the seventh semiconductor chip 360. For example, the reinforcement 400 may extend across the second substrate 200 and be formed on the second substrate 200.

[0130] The reinforcing member 400 may not contact the sixth semiconductor chip 350 and the seventh semiconductor chip 360. For example, air gaps may be formed / placed between the reinforcing member 400 and the sixth semiconductor chip 350, and between the reinforcing member 400 and the seventh semiconductor chip 360, respectively. Furthermore, as... Figure 11 As shown, a first air gap AG1 may be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. For example, free space may exist between the reinforcing member 400 and the first sidewall 200s of the second substrate 200.

[0131] Figure 12 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0132] See Figure 12 According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a sixth semiconductor chip 350, a seventh semiconductor chip 360, an eighth semiconductor chip 370, a ninth semiconductor chip 380, and a reinforcing member 400. The sixth to ninth semiconductor chips 380 may be disposed on the second substrate 200. The sixth and seventh semiconductor chips 350 and 360 may be spaced apart from each other on the second substrate 200 in a second direction Y1. The eighth and ninth semiconductor chips 380 may be spaced apart from each other on the second substrate 200 in the second direction Y1. The sixth and eighth semiconductor chips 370 and 360 may be spaced apart from each other on the second substrate 200 in a first direction X1. The seventh and ninth semiconductor chips 380 may be spaced apart from each other on the second substrate 200 in the first direction X1.

[0133] According to some embodiments, a reinforcing member 400 may extend on the second substrate 200 in a first direction X1 to cross between the sixth semiconductor chip 350 and the seventh semiconductor chip 360, and between the eighth semiconductor chip 370 and the ninth semiconductor chip 380. Additionally, the reinforcing member 400 may further extend in a second direction Y1 to cross between the sixth semiconductor chip 350 and the eighth semiconductor chip 370, and between the seventh semiconductor chip 360 and the ninth semiconductor chip 380. For example, the reinforcing member 400 may cross the second substrate 200 in both the first direction X1 and the second direction Y1 and be formed on the second substrate 200.

[0134] The reinforcing member 400 and the sixth to ninth semiconductor chips 350 may not be in contact with each other on the second substrate 200. For example, air gaps may be formed / placed between the reinforcing member 400 and the sixth semiconductor chip 350, between the reinforcing member 400 and the seventh semiconductor chip 360, between the reinforcing member 400 and the eighth semiconductor chip 370, and between the reinforcing member 400 and the ninth semiconductor chip 380, respectively. Furthermore, as described above, air gaps may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. Figure 12 The cross-sectional view taken by line D-D' can be similar to Figure 11 Therefore, no explanation will be provided.

[0135] Figure 13 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0136] See Figure 13 According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a first semiconductor chip 300, a second semiconductor chip 310, a fourth semiconductor chip 330, and a reinforcing member 400. The first semiconductor chip 300, the second semiconductor chip 310, and the fourth semiconductor chip 330 may be disposed on the second substrate 200.

[0137] According to some embodiments, the second substrate 200 may include a first side 201 extending in a first direction X1 and a second side 202 extending in a second direction Y1. The first semiconductor chip 300 may include a third side 301 extending in a third direction X2 and a fourth side 302 extending in a fourth direction Y2. The first directions X1 to the fourth direction Y2 may be different from each other. For example, the first direction X1, the second direction Y1, the third direction X2, and the fourth direction Y2 may be in the same plane. For example, the third direction X2 and the fourth direction Y2 may be perpendicular to each other. For example, in a plan view, the first semiconductor chip 300 may be disposed obliquely on the second substrate 200 relative to the second substrate 200. Similarly, each of the second semiconductor chip 310 and the fourth semiconductor chip 330 may be disposed obliquely on the second substrate 200 relative to the second substrate 200. For example, in a plan view, the edge lines of the semiconductor chips 300, 310, and 330 may be neither parallel nor perpendicular to the edge lines of the second substrate 200.

[0138] According to some embodiments, the reinforcement 400 may extend beyond the corner of the second substrate 200. For example, the reinforcement 400 may extend from the first substrate 100 to the second substrate 200 along a third direction X2. In another example, the reinforcement 400 may extend from the first substrate 100 to the second substrate 200 along a fourth direction Y2. For example, the edge lines of the reinforcement 400 formed on the second substrate 200 may be parallel to the third direction X2 and the fourth direction Y2, respectively.

[0139] The reinforcing member 400 may not contact the first semiconductor chip 300, the second semiconductor chip 310, and the fourth semiconductor chip 330 on the second substrate 200. For example, air gaps may be formed / placed between the reinforcing member 400 and the first semiconductor chip 300, between the reinforcing member 400 and the second semiconductor chip 310, and between the reinforcing member 400 and the fourth semiconductor chip 330, respectively. Furthermore, as described above, air gaps may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. Figure 13 The cross-sectional view taken by line D-D' can be similar to Figure 11 Therefore, no explanation will be provided.

[0140] Figure 14 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0141] See Figure 14According to some embodiments, a semiconductor package may include a first substrate 100, a second substrate 200, a first semiconductor chip 300 to a fifth semiconductor chip 340, and a reinforcing member 400. The first semiconductor chip 300 to the fifth semiconductor chip 340 may be disposed on the second substrate 200.

[0142] According to some embodiments, the first substrate 100 may include a fifth side 101 extending in a second direction Y1 and a sixth side 102 extending in a first direction X1. The second substrate 200 may include a seventh side 203 extending in a third direction X2 and an eighth side 204 extending in a fourth direction Y2. The first directions X1 to the fourth directions Y2 may be different from each other. For example, the second substrate 200 may be disposed on the first substrate 100 at an angle relative to the first substrate 100. For example, in a plan view, the edge lines of the second substrate 200 may be neither parallel nor perpendicular to the edge lines of the first substrate 100. Although Figure 14 The first semiconductor chip 300 to the fifth semiconductor chip 340 are arranged side by side with the second substrate 200, for example... Figure 14 In this invention, the adjacent sides of the second substrate 200 and semiconductor chips 300, 310, 320, 330 and 340 are parallel to each other, but the invention is not limited thereto.

[0143] According to some embodiments, the reinforcement 400 may extend to at least one corner of the second substrate 200. For example, the reinforcement 400 may extend from the first substrate 100 to the second substrate 200 along a first direction X1. In another example, the reinforcement 400 may extend from the first substrate 100 to the second substrate 200 along a second direction Y1, for example, for forming the reinforcement 400 at a corner of the second substrate 200.

[0144] The reinforcing member 400 may not contact the first to fifth semiconductor chips 300 on the second substrate 200. For example, air gaps may be formed / placed between the reinforcing member 400 and the first semiconductor chip 300, between the reinforcing member 400 and the second semiconductor chip 310, between the reinforcing member 400 and the third semiconductor chip 320, between the reinforcing member 400 and the fourth semiconductor chip 330, and between the reinforcing member 400 and the fifth semiconductor chip 340, respectively. Furthermore, as described above, air gaps may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. Figure 14 The cross-sectional view taken by line D-D' can be similar to Figure 11 Therefore, no explanation will be provided.

[0145] Figure 15 This is an exemplary layout diagram illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0146] use Figure 14 The reinforcement 400 of the described semiconductor package may extend further in a third direction X2. The reinforcement 400 may extend further from the first substrate 100 to the second substrate 200 along the third direction X2. For example, the reinforcement 400 may extend further in a third direction X2 between the second semiconductor chip 310 and the third semiconductor chip 320, for example, to be formed on the second substrate 200. For example, the reinforcement 400 may extend further in a third direction X2 between the fourth semiconductor chip 330 and the fifth semiconductor chip 340, for example, to be formed on the second substrate 200.

[0147] The reinforcing member 400 may not contact the first to fifth semiconductor chips 300 on the second substrate 200. For example, air gaps may be formed / placed between the reinforcing member 400 and the first semiconductor chip 300, between the reinforcing member 400 and the second semiconductor chip 310, between the reinforcing member 400 and the third semiconductor chip 320, between the reinforcing member 400 and the fourth semiconductor chip 330, and between the reinforcing member 400 and the fifth semiconductor chip 340, respectively. Furthermore, as described above, air gaps may also be formed / placed between the reinforcing member 400 and the first sidewall 200s of the second substrate 200. Due to the... Figure 15 The cross-sectional view taken by line D-D' can be similar to Figure 11 And the cross-sectional view taken along line B-B' can be similar to Figure 4 Therefore, its description will not be provided.

[0148] Figure 16 This is an exemplary cross-sectional view illustrating a semiconductor package according to some embodiments. For ease of explanation, repeated or similar descriptions will be omitted or briefly described.

[0149] See Figure 16 According to some embodiments, the semiconductor package may further include a heat sink 600. The heat sink 600 may extend from one side of the reinforcement 400 on the first substrate 100 to the other side, for example, to opposite sides. The heat sink 600 may contact the first semiconductor chip 300. As described above, the second height H2 of the uppermost surface 400u of the reinforcement 400 (e.g., above the top surface of the first substrate 100) may be lower than the first height H1 of the upper surface 300u of the first semiconductor chip 300 (e.g., above the top surface of the first substrate 100). Therefore, interference may not occur between the reinforcement 400 and the heat sink 600. For example, a gap may exist between the uppermost surface 400u of the reinforcement 400 and the lower surface of the heat sink 600 to space the reinforcement 400 and the heat sink 600 apart from each other.

[0150] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to these preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed in this invention are used only in a general and descriptive sense and not for limiting purposes.

[0151] Embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art will understand that the present invention can be implemented in other specific forms without altering the technical concept or essential features of the invention. Furthermore, the above embodiments are merely examples and do not limit the scope of the present invention.

Claims

1. A semiconductor package, comprising: First substrate; A second substrate is disposed on the first substrate; A first semiconductor chip is disposed on the second substrate; A reinforcing member extends from the upper surface of the first substrate to the upper surface of the second substrate, and the reinforcing member does not contact the first semiconductor chip; A second semiconductor chip is disposed on the second substrate, and the second semiconductor chip is spaced apart from the first semiconductor chip in the horizontal direction; as well as An air gap is located between the reinforcing member and the second semiconductor chip. The first height from the upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than the second height from the upper surface of the first substrate to the uppermost surface of the reinforcement. The reinforcement extends further between the first semiconductor chip and the second semiconductor chip, and the reinforcement overlaps with the first semiconductor chip and the second semiconductor chip in the horizontal direction.

2. The semiconductor package according to claim 1, further comprising: The first air gap is located between the reinforcing member and the sidewall of the second substrate.

3. The semiconductor package according to claim 2, further comprising: The second air gap is located between the reinforcing member and the first semiconductor chip.

4. The semiconductor package according to claim 1, further comprising: An interface film is located between the second substrate and the reinforcing member. The interface film comprises a combination of a first material with a thermal conductivity of 10 W / (m·K) or greater than 10 W / (m·K) and a silicone resin.

5. The semiconductor package of claim 1, wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other via the second substrate.

6. The semiconductor package of claim 1, wherein the first substrate further comprises a first region and a second region surrounding the first region, and The second substrate is disposed in the first region, and the reinforcement extends along the second region.

7. The semiconductor package of claim 1, wherein the first substrate includes a first side extending in a first direction and a second side extending in a second direction. The second substrate includes a third side extending upward in a third direction and a fourth side extending in a fourth direction, and The first direction, the second direction, the third direction, and the fourth direction are different from each other in the plan view.

8. The semiconductor package of claim 1, wherein the second substrate includes a first side extending in a first direction and a second side extending in a second direction. The first semiconductor chip includes a third side extending upward in a third direction and a fourth side extending in a fourth direction, and The first direction, the second direction, the third direction, and the fourth direction are different from each other in the plan view.

9. A semiconductor package, comprising: First substrate; A second substrate is disposed on the first substrate; A first semiconductor chip is disposed on the second substrate; A reinforcing member extends from the upper surface of the first substrate to the upper surface of the second substrate, and the reinforcing member does not contact the first semiconductor chip; The first air gap is located between the reinforcing member and the sidewall of the second substrate; A second semiconductor chip is disposed on a second substrate, and the second semiconductor chip is spaced apart from the first semiconductor chip in the horizontal direction. as well as The third air gap is located between the reinforcing member and the second semiconductor chip. The first height from the upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than the second height from the upper surface of the first substrate to the upper surface of the reinforcement. The reinforcement extends further between the first semiconductor chip and the second semiconductor chip, and the reinforcement overlaps with the first semiconductor chip and the second semiconductor chip in the horizontal direction.

10. The semiconductor package according to claim 9, further comprising: The second air gap is located between the reinforcing member and the first semiconductor chip.

11. The semiconductor package according to claim 9, further comprising: An interface film is disposed between the second substrate and the reinforcing member. The interface film comprises a combination of a first material with a thermal conductivity of 10 W / (m·K) or greater than 10 W / (m·K) and a silicone resin.

12. A semiconductor package, comprising: The first substrate includes a first region and a second region surrounding the periphery of the first region; A second substrate is disposed on the first region, the second substrate including a third region and a fourth region surrounding the periphery of the third region; A first semiconductor chip is disposed on the third region; A second semiconductor chip is disposed on the third region, and the second semiconductor chip is spaced apart from the first semiconductor chip in the horizontal direction. as well as The reinforcing member extends along the second region. The reinforcing member extends further from the upper surface of the first substrate to the upper surface of the second substrate, and the reinforcing member does not contact the first semiconductor chip or the second semiconductor chip. The first height from the upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than the second height from the upper surface of the first substrate to the upper surface of the reinforcement. The reinforcement extends further between the first semiconductor chip and the second semiconductor chip, and the reinforcement overlaps with the first semiconductor chip and the second semiconductor chip in the horizontal direction.

13. The semiconductor package of claim 12, wherein the first substrate includes a first side extending in a first direction and a second side extending in a second direction. The second substrate includes a third side extending upward in a third direction and a fourth side extending in a fourth direction, and The first direction, the second direction, the third direction, and the fourth direction are different from each other.

14. The semiconductor package of claim 12, wherein the second substrate includes a first side extending in a first direction and a second side extending in a second direction. The first semiconductor chip includes a third side extending upward in a third direction and a fourth side extending in a fourth direction, and The first direction, the second direction, the third direction, and the fourth direction are different from each other.

15. The semiconductor package of claim 12, wherein the reinforcement extends further along the fourth region.

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