Cascode amplifier biasing

Abstract

A power amplifier circuit includes a first transistor, a second transistor, and a biasing circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connected to a collector of the first transistor, and a collector configured to output a second signal. The biasing circuit is coupled to the first transistor and the second transistor. The biasing circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor that is about twice a DC voltage at the collector of the first transistor. The biasing circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor that is about twice an AC or RF voltage at the collector of the first transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a power amplifier, and more particularly, to a biasing circuit for a power amplifier. BACKGROUND

[0002] A power amplifier is a circuit in a wireless transceiver for amplifying a signal to be transmitted. Generally, an impedance conversion matching circuit can be used at the output of the power amplifier for impedance matching. However, the use of the impedance conversion matching circuit will increase the power consumption of the power amplifier. To avoid high power consumption, the impedance conversion matching circuit can be omitted by using a high voltage supply. However, high breakdown voltage transistors are required. To reduce the voltage withstand of the transistors, a cascode amplifier can be implemented. SUMMARY

[0003] According to an aspect of the disclosure, a power amplifier circuit includes a first transistor, a second transistor, and a biasing circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connected to a collector of the first transistor, and a collector configured to output a second signal. The biasing circuit is coupled to the first transistor and the second transistor. The biasing circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor that is about twice a DC voltage at the collector of the first transistor. The biasing circuit is configured to provide a radio frequency (RF) voltage at the collector of the second transistor that is about twice an RF voltage at the collector of the first transistor.

[0004] According to another aspect of the disclosure, a power amplifier circuit includes a first transistor, a second transistor, and an amplifier. The first transistor is configured in a common emitter arrangement. The second transistor is connected to the first transistor and is configured in a common base arrangement. The amplifier has a first input, a second input, and an output. The first input of the amplifier is connected to a collector of the second transistor. The second input of the amplifier is connected to an emitter of the second transistor. The output of the amplifier is connected to a base of the second transistor. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a schematic diagram illustrating a power amplifier according to some embodiments of the disclosure.

[0006] Figure 2 is a schematic diagram illustrating a power amplifier according to some embodiments of the disclosure.

[0007] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D illustrate simulation results of the power amplifier shown in Figure 2 FIG. 4.

[0008] Common reference numbers are used throughout the drawings and detailed description to indicate the same or similar components. The present disclosure can be understood more readily by reference to the following detailed description taken in connection with the accompanying drawings. DETAILED DESCRIPTION

[0009] While described with particular reference to a portable transceiver, the circuit and method for biasing a gallium arsenide (GaAs) power amplifier (also referred to as GaAs biasing circuit) can be implemented in any GaAs device in which biasing current and voltage is required to be provided. Further, the circuit described below can be fabricated using an integrated bipolar-field effect transistor (BIFET) process that utilizes the lower on voltage of a field effect transistor. Further, in particular embodiments, the transistors described below include bipolar junction transistors (referred to as BJTs) fabricated using a process referred to as a BIFET process or BiHEMT process, which includes heterojunction bipolar junction transistors (referred to as HBTs) and field effect transistors (referred to as FETs) or pseudomorphic high electron mobility transistors (referred to as pHEMTs). In some embodiments, the transistors described below can be fabricated using a process referred to as GaAs, indium phosphide (InP), silicon-germanium (SiGe), gallium nitride (GaN), complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI), or any other suitable process.

[0010] As used herein, reference to a base, emitter, collector, or other component or other circuit component of a transistor that is connected directly to a base, emitter, collector, or other component or other circuit component of another transistor can refer to a connection with another circuit component (e.g., a transistor) disposed therebetween.

[0011] Figure 1 is a schematic diagram illustrating a power amplifier 100 in accordance with some embodiments of the present disclosure. The power amplifier 100 includes biasing circuits 110 and 120, transistors Ql and Q2, input matching element IMN, and output matching element OMN.

[0012] The emitter of transistor Ql is connected to ground (that is, to a ground voltage). The base of transistor Ql is connected to receive a direct current (DC) bias (e.g., a DC current and / or a DC voltage) from bias circuit 120. In some embodiments, bias circuit 120 can include an RF blocking element RL2. In other embodiments, RF blocking element RL2 can be omitted. Bias circuit 120 can be any other bias circuit that can provide a DC bias current and / or a DC bias voltage. The base of transistor Ql is configured to receive a radio frequency (RF) signal from input RFIN. In some embodiments, the base of transistor Ql is connected to input RFIN through input matching element IMN and / or capacitor C3. The collector of transistor Ql is connected to the base of transistor Q2 and to bias circuit 110.

[0013] The emitter of transistor Q2 is connected to the collector of transistor Ql and to bias circuit 110. The base of transistor Q2 is connected to bias circuit 110. The collector of transistor Q2 is connected to bias voltage VDD. In some embodiments, the collector of transistor Q2 is connected to bias voltage VDD through inductor LI. The collector of transistor Q2 is configured to output an amplified RF signal through output RFOUT of power amplifier 100 in accordance with the RF signal received from input RFIN. In some embodiments, the collector of transistor Q2 is connected to output RFOUT through output matching element OMN and / or capacitor C4. In some embodiments, output matching element OMN can be omitted.

[0014] In some embodiments, transistor Ql is connected or configured in a common emitter (CE) arrangement. Transistor Q2 is connected or configured in a common base (CB) arrangement. Transistor Ql and transistor Q2 can be configured or connected to define a cascode amplifier.

[0015] Bias circuit 110 includes amplifier Al; resistors Rl, R2; capacitors Cl, C2; and RF blocking element RLl. Amplifier Al has a first input (+), a second input (-), and an output. In some embodiments, amplifier Al is an operational amplifier or any other suitable differential amplifier. In some embodiments, the voltage V+ at the first input of amplifier Al is substantially the same as the voltage V- at the second input of amplifier Al. The first input of amplifier Al is connected to resistors Rl and R2. The second input of amplifier Al is connected to the collector of transistor Ql and to the emitter of transistor Q2. The output of amplifier Al is connected to RF blocking element RLl. In some embodiments, RF blocking element RLl includes at least one resistor and / or at least one inductor and is connected between the output of amplifier Al and the base of transistor Q2.

[0016] Resistor Rl is connected between the first input of amplifier Al and the collector of transistor Q2. Resistor R2 is connected between the second input of amplifier A2 and ground. In some embodiments, resistor Rl and resistor R2 are connected or configured in series to act as a DC voltage divider. The DC voltage V+ at the first input of amplifier Al is related to the DC voltage V2 at the collector of transistor Q2 according to the ratio between resistor Rl and resistor R2. For example, V2 and V+ are related as follows:

[0017]

[0018] If Rl is equivalent to R2, then the DC voltage V+ at the first input of amplifier Al is substantially half of the DC voltage V2 at the collector of transistor Q2. Since the DC voltage V+ at the first input of amplifier Al is substantially the same as the DC voltage V- at the second input of amplifier Al, and the second input of amplifier Al is connected to the collector of transistor Ql, the DC voltage VI at the collector of transistor Ql is substantially half of the DC voltage V2 at the collector of transistor Q2. In other words, the DC voltage drop across the collector and emitter of transistor Ql (i.e., VI) is substantially the same as the DC voltage drop across the collector and emitter of transistor Q2 (i.e., V2-Vl).

[0019] Capacitor Cl is connected between the base (and RF blocking element) of transistor Q2 and the collector of transistor Q2. Capacitor C2 is connected between the base (and RF blocking element) of transistor Q2 and ground. In some embodiments, the impedance of capacitor C2 is less than the impedance of resistor Rl. In some embodiments, capacitor Cl and capacitor C2 are connected or configured in series to act as a capacitive voltage divider (or RF voltage divider or feedback). The RF voltage (or AC voltage) Vb at the base of transistor Q2 is related to the RF voltage (or AC voltage) V2 at the collector of transistor Q2 according to the ratio between capacitor Cl and capacitor C2. For example, V2 and Vb are related as follows:

[0020]

[0021] If Cl is equivalent to C2, then the RF voltage Vb at the base of transistor Q2 is substantially half of the RF voltage V2 at the collector of transistor Q2. Since the RF voltage Vb at the base of transistor Q2 is substantially the same as the RF voltage VI at the emitter of transistor Q2, the RF voltage drop across the collector and emitter of transistor Ql (i.e., VI) is substantially the same as the RF voltage drop across the collector and emitter of transistor Q2 (i.e., V2-Vl).

[0022] In some embodiments, Figure 1The transistors Ql and Q2 illustrated in the middle can be implemented by using FETs, HEMTs, PHEMTs, MOS, or any other suitable transistors. In those embodiments, the transistor Ql is connected or configured in a common source (CS) arrangement, and the transistor Q2 is connected or configured in a common emitter (CE) arrangement. Since the CE arrangement transistor Q2 has an input capacitor Cin at the gate of the transistor Q2, the capacitor C2 and the input capacitor Cin are arranged in parallel. Therefore, the capacitor Cl should be equivalent to (C2 + Cin) to ensure that the RF voltage Vb at the gate of the transistor Q2 is substantially half of the RF voltage V2 at the emitter of the transistor Q2.

[0023] According to some embodiments of the disclosure, the amplifier Al and the registers Rl and R2 are configured to provide DC feedback for the biasing circuit 110, and the capacitors Cl and C2 are configured to provide RF feedback for the biasing circuit 110. The biasing circuit 110 is configured to allow the RF and DC voltage drops across the collector and base of the transistor Ql to be substantially the same as the RF and DC voltage drops across the collector and base of the transistor Q2, so that both the RF and DC power consumptions of the transistor Q2 are substantially the same as those of the transistor Ql, which in turn will reduce the chip area of the power amplifier 100 and lower the manufacturing cost. In addition, since the biasing circuit 110 is configured to maintain the RF and DC voltage drops across the transistor Ql the same as those across the transistor Q2, the current flowing through the transistor Ql is substantially the same as that flowing through the transistor Q2 regardless of how the DC bias at the base of the transistor Ql changes, which will increase the reliability and stability of the power amplifier 100.

[0024] Figure 2 is a schematic diagram illustrating a power amplifier 200 according to some embodiments of the disclosure. The power amplifier 200 is similar to the power amplifier 100 in Figure 1 , except that the biasing circuit 210 of the power amplifier 200 further includes a transistor Q21, a capacitor C21, resistors R21 and R22.

[0025] The collector of the transistor Q21 is connected to the bias voltage VDD. The base of the transistor Q21 is connected to the output of the amplifier Al. The emitter of the transistor Q21 is connected to the resistor R21 and the capacitor C21. The resistor R21 is connected between the emitter of the transistor Q21 and the base of the transistor Q2. The capacitor C21 is connected between the emitter of the transistor Q21 and the second input of the amplifier Al. The resistor R22 is connected between the second input of the amplifier Al and the emitter of the transistor Q2.

[0026] Figure 3A 、 3B , 3C and 3D illustrate a power amplifier 300 according to some embodiments of the disclosure. Figure 2The simulation results of the power amplifier 200 are shown in FIGS. 1A-1C. In FIG. 1A, Figure 3A In FIG. 2A, the x-axis represents time (nsec), and the y-axis represents the voltage V1 (sum of DC voltage and RF voltage) at the collector of the transistor Q1 with different RF input voltages or power levels at the base of the transistor Q1. In FIG. 2B, Figure 3B In FIG. 2A, the x-axis represents time (nsec), and the y-axis represents the voltage V1 (sum of DC voltage and RF voltage) at the collector of the transistor Q1 with different RF input voltages or power levels at the base of the transistor Q1. In FIG. 2B, Figure 3C In FIG. 2A, the x-axis represents time (nsec), and the y-axis represents the voltage V1 (sum of DC voltage and RF voltage) at the collector of the transistor Q1 with different RF input voltages or power levels at the base of the transistor Q1. In FIG. 2B, Figure 3D In FIG. 2A, the x-axis represents time (nsec), and the y-axis represents the voltage V1 (sum of DC voltage and RF voltage) at the collector of the transistor Q1 with different RF input voltages or power levels at the base of the transistor Q1. In FIG. 2B,

[0027] As shown in FIGS. 1A-1C, Figure 3A , 3B and 3C, the voltage V1 (sum of DC voltage and RF voltage) at the collector of the transistor Q1 is substantially half of the voltage V2 (sum of DC voltage and RF voltage) at the collector of the transistor Q2, and the voltage drop (V1) across the transistor Q1 is substantially the same as the voltage drop (V2-V1) across the transistor Q2, regardless of the change in the RF input voltage or power level at the base of the transistor Q1. In addition, as shown in FIG. 2A, Figure 3D the current Ic1 (sum of DC current and RF current) at the collector of the transistor Q1 is substantially the same as the current Ic2 (sum of DC current and RF current) at the collector of the transistor Q2. Thus, the power dissipation (sum of DC power dissipation and RF power dissipation) of the transistor Q1 is substantially the same as the power dissipation (sum of DC power dissipation and RF power dissipation) of the transistor Q2, which in turn will reduce the chip area of the power amplifier 200 and lower the manufacturing cost.

[0028] As used herein, the singular terms "a," "an," and "the" can encompass multiple references unless the context clearly dictates otherwise.

[0029] In addition, quantities, ratios and other numerical values are sometimes presented in a range format. It is to be understood that such range format is used for convenience and brevity and should be taken as a literal disclosure of each distinct number

[0030] As used herein and unless otherwise defined, the terms "substantially," "generally," "approximately," and "about" are used to describe and account for minor variations in the value. When used in connection with an event or circumstance, the terms can encompass the explicit occurrence of the event or circumstance as well as an event or circumstance that is approximately or nearly the same as the event or circumstance. For example, when used in connection with a numerical value, the terms can encompass a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be considered "essentially" the same or equal if the difference between the two values is less than or equal to ±10% of the average of the values (such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0031] While the disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not intended to limit the disclosure. Those skilled in the art can readily devise numerous alterations, substitutions and equivalents without departing from the true spirit and scope of the disclosure as defined by the appended claims. The drawings are not necessarily to scale. Distinctions between the artistic rendering in the disclosure and actual devices can exist due to variations in manufacturing processes, etc. Other embodiments of the disclosure can exist that are not specifically illustrated. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the claims. Although methods disclosed herein have been described with reference to particular sequences for performing certain operations, it will be understood that these operations can be combined, divided, re-ordered, or generally re-sequenced without departing from the teachings of the disclosure. Accordingly, unless specifically indicated otherwise, the order and grouping of operations is not a limitation of the disclosure.

Claims

1. A power amplifier circuit, comprising: A first transistor having a base configured to receive a first signal; The second transistor has an emitter connected to the collector of the first transistor, and a collector configured to output a second signal; as well as A bias circuit, coupled to the first transistor and the second transistor, The bias circuit is configured to generate a DC voltage at the collector of the second transistor that is approximately twice the DC voltage at the collector of the first transistor. The bias circuit is configured to generate an RF voltage at the collector of the second transistor that is approximately twice the RF voltage at the collector of the first transistor. and The bias circuit includes: A first resistor is connected to the collector of the second transistor; as well as A first capacitor is connected between the first resistor and the base of the second transistor.

2. The power amplifier circuit according to claim 1, wherein the bias circuit further comprises: An amplifier having a first input, a second input, and an output, the output being connected to the base of a second transistor, wherein a first resistor is connected between the collector of the second transistor and the first input of the amplifier, and The output of the amplifier is connected to the first capacitor; as well as A second resistor is connected between the first input of the amplifier and ground.

3. The power amplifier circuit according to claim 2, wherein the first voltage at the first input of the amplifier is substantially the same as the second voltage at the second input of the amplifier.

4. The power amplifier circuit according to claim 1, wherein the bias circuit further comprises: An RF voltage divider, comprising the first capacitor and connected to the base of the second transistor; as well as An RF blocking element is connected to the RF voltage divider.

5. The power amplifier circuit of claim 4, wherein the bias circuit further includes a second capacitor connected between the base of the second transistor and ground. The second capacitor is connected in parallel with the input capacitor of the second transistor; and The impedance of the first resistor is greater than the impedance of the second capacitor.

6. The power amplifier circuit according to claim 1, further comprising a plurality of RF blocking elements respectively connected to the base of the first transistor and the base of the second transistor.

7. The power amplifier circuit of claim 6, further comprising an inductor, wherein the collector of the second transistor is connected to a bias voltage via the inductor, and the inductor is connected to the first capacitor.

8. A power amplifier circuit, comprising: The first transistor is arranged with a common emitter; A second transistor is connected to the first transistor and is arranged with a common base. as well as An amplifier having a first input, a second input, and an output; as well as A first resistor is connected to the collector of the second transistor; as well as A first capacitor is connected between the first resistor and the base of the second transistor. The first input of the amplifier is connected to the collector of the second transistor, the second input of the amplifier is connected to the emitter of the second transistor, and the output of the amplifier is connected to the base of the second transistor.

9. The power amplifier circuit according to claim 8, further comprising: A second resistor is connected between the first input of the amplifier and ground. The first capacitor and the first resistor are connected at the collector of the second transistor.

10. The power amplifier circuit of claim 9, wherein the collector of the second transistor is connected to receive a DC bias voltage via an inductor.

11. The power amplifier circuit of claim 9, further comprising: The second capacitor is connected between the first capacitor and ground.

12. The power amplifier circuit of claim 8, further comprising a first element having at least one resistor and an inductor, and an RF voltage divider including the first capacitor, wherein the first element is connected between the output of the amplifier and the RF voltage divider.

13. The power amplifier circuit according to claim 8, further comprising: A third transistor has a base connected to the output of the amplifier and an emitter connected to the base of the second transistor; A third resistor is connected between the emitter of the third transistor and the base of the second transistor; A third capacitor is connected between the emitter of the third transistor and the second input of the amplifier; as well as A fourth resistor is connected between the second input of the amplifier and the emitter of the second transistor.

14. The power amplifier circuit according to claim 12, wherein... The emitter of the first transistor is connected to ground; and The base of the first transistor is connected to the DC bias circuit and the RF input.

15. The power amplifier circuit of claim 14, further comprising a second element having at least one resistor and an inductor, wherein the second element is connected between the base of the first transistor and the DC bias circuit.

16. The power amplifier circuit of claim 8, wherein the first transistor and the second transistor comprise heterojunction bipolar junction transistors.

17. The power amplifier circuit of claim 8, wherein the DC voltage difference between the collector and the emitter of the second transistor is substantially the same as the DC voltage difference between the collector and the emitter of the first transistor.

18. The power amplifier circuit of claim 8, wherein the DC voltage at the collector of the second transistor is approximately twice the DC voltage at the collector of the first transistor.

19. The power amplifier circuit of claim 8, wherein the RF voltage difference between the collector and emitter of the second transistor is substantially the same as the RF voltage difference between the collector and emitter of the first transistor.

20. The power amplifier circuit of claim 8, wherein the RF voltage at the collector of the second transistor is approximately twice the RF voltage at the collector of the first transistor.

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