Method for forming semiconductor structure and semiconductor structure

Abstract

The embodiment of the present invention relates to a method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate, on which a plurality of discrete sacrificial layers are formed; forming a buffer layer on the sidewall surface of the sacrificial layer, wherein the material of the buffer layer has organic groups and inorganic components; forming a sidewall layer on the surface of the buffer layer, and the buffer layer is located between the sidewall layer and the sacrificial layer; after forming the sidewall layer, removing the sacrificial layer; after removing the sacrificial layer, etching the substrate using the sidewall layer and the buffer layer as masks. The present invention can improve the pattern quality of self-aligned patterns and improve the yield rate of semiconductor production.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Art

[0002] Driven by Moore's Law, semiconductor technology continues to move towards smaller process nodes. With the continuous advancement of semiconductor technology, the functions of devices are becoming increasingly powerful, and the difficulty of semiconductor manufacturing is also increasing day by day. Photolithography technology is the most critical production technology in semiconductor manufacturing. As semiconductor process nodes continue to decrease, existing photolithography technology can no longer meet the needs of semiconductor manufacturing.

[0003] Double-patterning (DP) technology and even multi-patterning technology have become one of the best choices in the industry. Double-patterning technology only requires minor changes to the existing lithography infrastructure to effectively fill the gap in lithography technology for smaller nodes and improve the minimum pitch between adjacent semiconductor patterns. The principle of double-patterning technology is to decompose a set of high-density patterns into two sets of discrete, lower-density patterns, and then prepare them on the wafer. The main double-patterning technologies in the existing technology include: self-aligned double-patterning (SADP), secondary lithography and etching process (LELE: Litho-Eth-Litho-Eth).

[0004] However, the performance of the semiconductor structure formed by the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure and a semiconductor structure, so as to improve the pattern quality of self-aligned patterning and increase the production yield.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a plurality of discrete sacrificial layers are formed; forming a buffer layer on the side wall surface of the sacrificial layer, wherein the material of the buffer layer has organic groups and inorganic components; forming a side wall layer on the surface of the buffer layer, and the buffer layer is located between the side wall layer and the sacrificial layer; removing the sacrificial layer; and etching the substrate using the side wall layer and the buffer layer as masks.

[0007] An embodiment of the present invention also provides a semiconductor structure, comprising: a substrate and a plurality of discrete sacrificial layers located on the substrate; a buffer layer located on the side wall surface of the sacrificial layer, the material of the buffer layer containing organic groups and inorganic components; a side wall layer located on the surface of the buffer layer, and the buffer layer is located between the side wall layer and the sacrificial layer.

[0008] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0009] In the technical solution of the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming a separate sacrificial layer on a substrate and before forming a sidewall layer, a buffer layer is formed on the sidewall surface of the sacrificial layer, and the material of the buffer layer has organic groups and inorganic components, and the organic groups and the sacrificial layer material are compatible, so that the interface between the buffer layer and the sacrificial layer not only has a good bonding effect but also has a small stress at the interface; then a sidewall layer is formed on the surface of the buffer layer, so that the buffer layer is located between the sidewall layer and the sacrificial layer, the inorganic components in the buffer layer are chemically bonded to the sidewall layer, and the stress between the buffer layer and the sidewall layer is relatively small. In addition, since the buffer layer is formed between the sacrificial layer and the sidewall layer, the problem of large interface stress caused by direct contact between the sacrificial layer and the sidewall layer is avoided. Therefore, after removing the sacrificial layer, the problem of tilting or collapsing of the sidewall layer due to stress is avoided, so that the graphic morphology of the sidewall layer can remain unchanged, thereby improving the graphic quality of self-aligned graphics and improving the production yield of semiconductor structures.

[0010] In addition, the heating temperature of the heat treatment is 100° C. to 130° C., such as 110° C., 120° C., and 125° C. In this heating temperature range, the component molecules in the silane coupling agent move more violently, and the chance of molecular collision increases, which is beneficial to the formation of co-condensation polymers, thereby increasing the hydrolysis reaction rate and the condensation reaction rate, and improving the quality of the formed buffer layer.

[0011] In addition, the process parameters of the coating process include: a coating speed of 1000rpm to 1500rpm, and an acceleration of 500 to 1500. Sampling the above coating speed and acceleration is conducive to improving the uniformity of the thickness of the film formed by coating, and correspondingly improving the uniformity of the thickness of the buffer layer formed after the subsequent hydrolysis and condensation reaction, ensuring that the thickness of the buffer layer on the side wall surface of the sacrificial layer is uniform and has a suitable thickness, thereby helping to improve the stress relief effect of the buffer layer, and effectively avoiding the problem that some areas of the side wall of the sacrificial layer are not covered by the buffer layer or the thickness of the covered buffer layer is too thin. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0013] Figures 1 to 4 It is a schematic cross-sectional structure diagram corresponding to each step of a semiconductor structure forming method;

[0014] Figures 5 to 13 A schematic structural diagram corresponding to each step of the semiconductor structure forming method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] As can be seen from the background art, the performance of the existing semiconductor structures needs to be improved.

[0016] Now we analyze it in combination with a method for forming a semiconductor structure. Figures 1 to 4 It is a schematic diagram of the cross-sectional structure corresponding to each step of a semiconductor structure forming method.

[0017] refer to Figure 1 , a substrate 100 is provided, and a plurality of discrete sacrificial layers 101 are formed on the substrate 100 .

[0018] refer to Figure 2 A sidewall film 102 is formed on the top and sidewall of the sacrificial layer 101 and the substrate, and the sidewall film 102 conformally covers the sacrificial layer 101 .

[0019] refer to Figure 3 , etch back the sidewall film 102 (refer to Figure 2 ), the sidewall film 102 located on the top of the sacrificial layer 101 is etched away, and the sidewall film 102 on the substrate 100 is also etched away to form a sidewall layer 103 covering the sidewall of the sacrificial layer 101.

[0020] refer to Figure 4 , remove the sacrificial layer 101 (refer to Figure 3 ).

[0021] Subsequent steps include: using the sidewall layer 103 as a mask, etching the substrate 100 to form a target pattern.

[0022] After removing the sacrificial layer 101, it is found that the sidewall layer 103 will deform, tilt or collapse toward the original position of the sacrificial layer 101, causing the position of the sidewall layer 103 to deviate from the design target. The position of the sidewall layer 103 deviates by an angle of θ. In severe cases, the sidewall layer 103 may collapse. When the substrate 100 is etched using the sidewall layer 103 as a mask, the target pattern formed will no longer meet the process requirements.

[0023] Further analysis revealed that the reasons for the above problems include: the material of the sacrificial layer 101 is usually an organic material such as photoresist, while the material of the sidewall layer 103 is usually an inorganic material such as silicon nitride, and the lattice constants of the sacrificial layer 101 and the sidewall layer 103 are quite different, that is, the lattice structures of the sacrificial layer 101 and the sidewall layer 103 are quite different, so there is a large stress between the sacrificial layer 101 and the sidewall layer 103. When the sacrificial layer 101 is removed, the stress on one side of the sacrificial layer 101 will cause the sidewall layer 103 to deform, tilt or even collapse toward the middle.

[0024] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a plurality of discrete sacrificial layers are formed; forming a buffer layer on the sidewall surface of the sacrificial layer, wherein the material of the buffer layer has organic groups and inorganic components; forming a sidewall layer on the surface of the buffer layer, and the buffer layer is located between the sidewall layer and the sacrificial layer; removing the sacrificial layer; and etching the substrate using the sidewall layer and the buffer layer as masks. Since the buffer layer acts as a stress buffer between the sacrificial layer and the sidewall layer, the problem of deformation and tilting of the sidewall layer due to stress after removing the sacrificial layer is avoided, and the sidewall layer is ensured to always have a good graphic morphology, thereby improving the quality of the graphic formed after etching the substrate and improving the production yield of the semiconductor structure.

[0025] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0026] Figures 5 to 13 A schematic structural diagram corresponding to each step of the semiconductor structure forming method provided in an embodiment of the present invention.

[0027] refer to Figure 5 , providing a substrate, on which a plurality of discrete sacrificial layers 202 are formed.

[0028] The base includes a substrate 200 and a layer to be etched 201 located on the surface of the substrate 200. The substrate 200 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V substrate or a sapphire substrate.

[0029] In this embodiment, the method for forming a semiconductor structure is applied to the back-end of line (BOEL) in a semiconductor process as an example. The layer to be etched 201 includes at least one dielectric layer and an interconnect structure located in the dielectric layer. The layer to be etched 201 may also include: a hard mask layer (not shown) located on the surface of the dielectric layer, and the hard mask layer is subsequently patterned, and the patterned hard mask layer is used as a mask to etch the dielectric layer. The material of the hard mask layer may be a dielectric mask material, a metal mask material, or a metal compound mask material.

[0030] In other embodiments, the method for forming a semiconductor structure may also be applied to a front-end of line (FOEL) process in a semiconductor manufacturing process, and the corresponding layer to be etched may be a gate dielectric layer, a gate layer or a hard mask layer.

[0031] In this embodiment, the sacrificial layer 202 is a photoresist layer. The process steps for forming the sacrificial layer 202 include: forming a photoresist film on the surface of the substrate; exposing and developing the photoresist film to form a patterned photoresist layer, and the patterned photoresist layer is used as the sacrificial layer 202.

[0032] refer to Figure 6 A buffer layer 203 is formed on the side wall surface of the sacrificial layer 202, and the material of the buffer layer 203 contains organic groups and inorganic components.

[0033] In this embodiment, the buffer layer 203 is also formed on the top surface of the sacrificial layer 202 and the substrate surface between adjacent sacrificial layers 202 .

[0034] The buffer layer 203 is a stress buffer layer. Specifically, the organic groups in the material structure of the buffer layer 203 have good compatibility with the sacrificial layer 202, so that the interface between the buffer layer 203 and the sacrificial layer 202 not only has a good bonding effect, but also can reduce the stress at the interface between the buffer layer 203 and the sacrificial layer 202. In addition, the sidewall layer formed subsequently is usually an inorganic material, and the inorganic components in the material of the buffer layer 203 are conducive to making the interface between the buffer layer 203 and the sacrificial layer 202 have a good bonding effect. At the same time, since the buffer layer 203 is formed between the sacrificial layer 202 and the sidewall layer, the problem of high interface stress caused by direct contact between the sacrificial layer 202 and the sidewall layer is avoided.

[0035] Moreover, in this embodiment, the material structure of the buffer layer 203 is a dendrite structure. The buffer layer 203 with a dendrite structure can well disperse and alleviate the stress between the sacrificial layer 202 and the subsequently formed sidewall layer, further improving the problem of stress concentration.

[0036] In other embodiments, the material structure of the buffer layer may also be a chain structure or a star structure.

[0037] The organic group is an organic group having good compatibility with the photoresist material. In this embodiment, the organic group includes an alkane group, an alkene group or a cycloalkene group, wherein the alkane group, the alkene group or the cycloalkene group includes a methyl group, an ethyl group or a phenyl group.

[0038] In this embodiment, the material of the buffer layer 203 is A-SiO x -R, x≤4, where R is an organic group, A-SiO x The organic group R in the buffer layer 203 is combined with the sacrificial layer 202, and the O- in the buffer layer 203 is combined with the sidewall layer formed subsequently.

[0039] The thickness of the buffer layer 203 should not be too thin or too thick. If the thickness of the buffer layer 203 is too thin, the stress buffering effect of the buffer layer 203 is limited; if the thickness of the buffer layer 203 is too thick, it is not conducive to meeting the development trend of miniaturization and microminiaturization of semiconductor structures. In this embodiment, the thickness of the buffer layer 203 is 5 angstroms to 20 angstroms, for example, 8 angstroms, 12 angstroms, 15 angstroms, and 18 angstroms. It should be noted that the thickness of the buffer layer 203 refers to the thickness in the direction parallel to the substrate surface and perpendicular to the side wall of the sacrificial layer 202.

[0040] The buffer layer is formed by a hydrolysis condensation reaction of a coupling agent.

[0041] The process for forming the buffer layer 203 includes: providing a coupling agent, and the coupling agent is in contact with the side wall surface of the sacrificial layer 202 , so that the coupling agent undergoes a hydrolysis condensation reaction on the side wall surface of the sacrificial layer 202 to form the buffer layer 203 .

[0042] The coupling agent is a silane coupling agent, and the structure of the silane coupling agent is A y -Si-R x , x+y=4, after the hydrolysis condensation reaction, the buffer layer 203 formed is A-SiO x -R. The types of the silane coupling agent include VtSi(OMe)3, C2H5Si(OEt)3 or PhSi(OEt)3.

[0043] Specifically, the process steps for forming the buffer layer 203 include the following steps:

[0044] A reaction solution containing a coupling agent is prepared in advance. The solvent used in the reaction solution may be methanol, ethanol or isopropanol, and the reaction solution may also include deionized water. In the prepared reaction solution, the mass percentage of the coupling agent is 0.1% to 2%, for example, 1%, 1.3%, 1.6%, 1.8%.

[0045] The reaction solution containing the coupling agent can be an acidic solution or an alkaline solution. It should be noted that the functional groups of different types of coupling agents may have certain acidity or alkalinity, so the reaction solution also has corresponding acidity and alkalinity conditions.

[0046] Generally, under acidic conditions, the coupling agent hydrolyzes and condenses faster, tending to form a buffer layer 203 with a long chain structure; under alkaline conditions, the coupling agent hydrolyzes and condenses faster, tending to form a buffer layer 203 with a network cross-linked structure. Therefore, the structure of the buffer layer 203 to be formed can be selected according to the requirements of the actual process, and the acidity and alkalinity of the reaction solution can be determined accordingly.

[0047] The reaction solution is subsequently coated onto the top and sidewall surfaces of the sacrificial layer 202 using a coating process. In order to improve the coating effect, the reaction solution may be filtered using a filter membrane before the subsequent coating process. In this embodiment, the filter membrane is a filter membrane composed of a nylon (polyamide) and an ultra-high molecular weight polyethylene (UPE) membrane, and the filter pore diameter in the filter membrane is in the range of 15 nm to 25 nm, such as 18 nm, 20 nm, and 23 nm.

[0048] The reaction solution is coated on the top and sidewall surfaces of the sacrificial layer 202. In this embodiment, the reaction solution is coated on the top and sidewall surfaces of the sacrificial layer 202 and also coated on the substrate surface between adjacent sacrificial layers 202 by a coating process.

[0049] If the acceleration and rotation speed in the coating process are too slow, the uniformity of the thickness of the formed film will be poor and the step coverage will be poor; if the acceleration and rotation speed in the coating process are too fast, the thickness of the formed film will be thin. Therefore, in this embodiment, the process parameters of the coating process include: the coating rotation speed is 1000rpm to 1500rpm, for example, 1200rpm, 1350rpm, 1400rpm, and the acceleration is 500rpm. 2 ~1500rpm 2 , for example 800rpm 2 , 1000rpm 2 , 1300rpm 2 .

[0050] Sampling the above-mentioned coating rotation speed and acceleration is beneficial to improving the uniformity of the film thickness formed by coating, and correspondingly improving the uniformity of the thickness of the buffer layer 203 formed after the subsequent hydrolysis and condensation reaction, ensuring that the thickness of the buffer layer 203 on the side wall surface of the sacrificial layer 202 is uniform and has a suitable thickness, thereby helping to improve the stress relief effect of the buffer layer 203, and effectively avoiding the problem that some areas of the side wall of the sacrificial layer 202 are not covered by the buffer layer 203 or the thickness of the covered buffer layer 203 is too thin.

[0051] In this embodiment, the coating process takes 10 seconds to 20 seconds. In other embodiments, the coating process may also take 10 seconds to 20 seconds according to actual process requirements.

[0052] Next, the sacrificial layer 202 is heated to allow the coupling agent in the reaction solution to undergo a hydrolysis-condensation reaction to form the buffer layer 203 .

[0053] If the heating temperature used in the heat treatment is too low, the component molecules in the coupling agent in the reaction solution move slowly, which is not conducive to the formation of the co-condensation product. In this embodiment, the heating temperature of the heat treatment is 100°C to 130°C, such as 110°C, 120°C, and 125°C. In this heating temperature range, the component molecules in the coupling agent move more violently, and the chance of molecular collision increases, which is conducive to the formation of the co-condensation product, thereby helping to increase the hydrolysis reaction rate and the condensation reaction rate, and improve the quality of the formed buffer layer 203.

[0054] In this embodiment, the heating time of the heating treatment is 10s to 30s, the thickness of the formed buffer layer 203 is moderate, and the damage to the sacrificial layer 202 caused by too long heating time is avoided.

[0055] After the hydrolysis and condensation reaction, a washing step is also performed to remove the coupling agent and reaction by-products that have not undergone the hydrolysis and condensation reaction, and also to remove the solvent, deionized water, etc. in the reaction solution.

[0056] Subsequent process steps include: forming a sidewall layer on the surface of the buffer layer 203, and the buffer layer 203 is located between the sidewall layer and the sacrificial layer 202. The steps of forming the sidewall layer will be described in detail below with reference to the accompanying drawings.

[0057] refer to Figure 7 , a sidewall film 204 is formed on the surface of the buffer layer 203 .

[0058] The sidewall film 204 provides a process basis for subsequent etching to form a sidewall layer. In this embodiment, before forming the sidewall layer, the buffer layer 203 is also located on the top surface of the sacrificial layer 202 and the substrate surface. Accordingly, the sidewall film 204 is formed on the surface of the buffer layer 203 .

[0059] The material of the sidewall film 204 is an inorganic material. In this embodiment, the material of the sidewall film 204 is silicon oxide. In other embodiments, the material of the sidewall film can also be silicon nitride, silicon oxynitride or silicon oxycarbonitride.

[0060] The sidewall film 204 is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0061] The buffer layer 203 plays a role of stress buffering between the sacrificial layer 202 and the side wall film 204. As can be seen from the above analysis, the stress at the interface between the buffer layer 203 and the side wall film 204 and at the interface between the sacrificial layer 202 and the side wall film 204 is small; and the special structure of the buffer layer 203 can also play a role in dispersing stress.

[0062] It should be noted that, in other embodiments, Figure 8 As shown, before forming the sidewall layer, the buffer layer 203 can be etched back to remove the buffer layer 203 located on the top of the sacrificial layer 202 and on the substrate, and retain the buffer layer 203 located on the sidewall surface of the sacrificial layer 202; accordingly, the sidewall film 204 is formed on the top of the sacrificial layer 202, the surface of the buffer layer 203 and the surface of the substrate.

[0063] refer to Fig. 9 , remove the sidewall film 204 and the buffer layer 203 located on the top of the sacrificial layer 202, and remove part of the sidewall film 204 and the buffer layer 203 on the substrate, retain the buffer layer 203 and the sidewall film 204 on the side wall surface of the sacrificial layer 202, and the retained sidewall film 204 serves as the sidewall layer 205.

[0064] The sidewall film 204 and the buffer layer 203 located on the top of the sacrificial layer 202 are etched away using an anisotropic etching process.

[0065] The material of the sidewall layer 205 is an inorganic material, and the details may refer to the above description of the sidewall film 204 .

[0066] like Fig.10 As shown, Fig.10 A schematic diagram showing the chemical bonds between the buffer layer 203 and the sidewall layer 205 and the sacrificial layer 202 is shown, wherein the organic group R in the buffer layer 203 combines with the material of the sacrificial layer 202 to form a chemical bond, and the O-bond in the buffer layer 203 combines with the material in the sidewall layer 205 to form a chemical bond.

[0067] It can be seen from the above analysis that in this embodiment, the stress at the interface between the sidewall layer 205 and the buffer layer 203 is small, and the stress at the interface between the sacrificial layer 202 and the buffer layer 203 is small.

[0068] refer to Fig.11 After forming the sidewall layer 205, the sacrificial layer 202 is removed (refer to Fig. 9 ).

[0069] It should be noted that, in the process of removing the sacrificial layer 202 , due to the influence of process conditions such as etching selectivity, etching ion types, and etching time, the buffer layer 203 may be consumed to a certain extent.

[0070] In this embodiment, the sacrificial layer 202 is a photoresist, and an ashing process (ash) is used to remove the sacrificial layer 202; in other embodiments, a wet resist removal process may also be used to remove the sacrificial layer.

[0071] Since the buffer layer 203 can play the role of stress buffering, it can effectively alleviate and release the stress generated between different interfaces, thereby avoiding the problem of deformation, tilting or collapse of the sidewall layer 205 due to stress after removing the sacrificial layer 202. In this embodiment, after removing the sacrificial layer 202, the sidewall layer 205 still maintains a good graphic shape, thereby improving the production yield of the semiconductor structure.

[0072] In this embodiment, the buffer layer 203 is also located between the sidewall layer 205 and the substrate. Fig.12 and Fig.13 As shown, before forming the sidewall layer 205, the buffer layer 203 located on the top of the sacrificial layer 202 and on the substrate is removed, and before forming the sidewall film 204 (refer to Figure 8 ), remove the sidewall film 204 on the top of the sacrificial layer 202 and the substrate, retain the buffer layer 203 and the sidewall film 204 on the sidewall surface of the sacrificial layer 202, and the retained sidewall film 204 is used as the sidewall layer 205. Accordingly, the sidewall layer 205 is in direct contact with the substrate.

[0073] Subsequent process steps also include: etching the substrate using the sidewall layer 205 and the buffer layer 203 as masks.

[0074] The substrate is etched using a dry etching process. Specifically, in this embodiment, the layer to be etched 201 is etched using a dry etching process until a preset pattern is formed in the layer to be etched 201.

[0075] After etching the substrate, the method further includes removing the spacer layer 205 and the buffer layer 203 .

[0076] In this embodiment, a new self-aligned double patterning process is used to transfer the pattern to the substrate using the sidewall layer 205 and the buffer layer 203. Since the material of the buffer layer 203 contains organic groups and inorganic components, the buffer layer 203 and the sidewall layer 205 and the buffer layer 203 and the sacrificial layer 202 (refer to Fig.10 ) are relatively small, thus solving the problem of damage to the pattern caused by stress, making the sidewall layer 205 and the buffer layer 203 have good morphology. Therefore, the morphology of the pattern formed by etching the substrate in the substrate will also meet the process requirements, thereby improving the semiconductor production yield.

[0077] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, referring to Fig. 9 The semiconductor structure includes: a substrate and a plurality of discrete sacrificial layers 202 located on the substrate; a buffer layer 203 located on the sidewall surface of the sacrificial layer 202, wherein the material of the buffer layer 203 contains organic groups and inorganic components; a sidewall layer 205 located on the surface of the buffer layer 203, wherein the buffer layer 203 is located between the sidewall layer 205 and the sacrificial layer 202.

[0078] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0079] In this embodiment, the base includes a substrate 200 and a layer to be etched 201 located on the substrate 200, and the material of the sacrificial layer 202 is a photoresist material, and the corresponding sacrificial layer 202 is a photoresist layer. For a detailed description of the base and the sacrificial layer 202, reference can be made to the corresponding description of the aforementioned embodiment, which will not be repeated here.

[0080] In this embodiment, the buffer layer 203 is also located between the sidewall layer 205 and the substrate. Fig.12 As shown, the buffer layer 203 may also be located only between the spacer layer 205 and the sacrificial layer 202 , and the spacer layer 205 is also in contact with the surface of the substrate.

[0081] The material of the sidewall layer 205 is an inorganic material, and the corresponding sidewall layer 205 is an inorganic material layer. In this embodiment, the material of the sidewall layer 205 is silicon nitride. In other embodiments, the material of the sidewall layer can also be silicon oxide, silicon oxynitride or silicon oxycarbon nitride.

[0082] In this embodiment, the thickness of the buffer layer 203 is 5 angstroms to 10 angstroms.

[0083] In this embodiment, the buffer layer 203 is formed by a hydrolysis condensation reaction of a coupling agent. In this embodiment, the coupling agent is a silane coupling agent.

[0084] The organic groups in the buffer layer 203 material are combined with the sacrificial layer 202 material, so that the buffer layer 203 and the sacrificial layer 202 are tightly bonded and the stress at the interface between the two is small; and the chemical bonds in the inorganic components in the buffer layer 203 are bonded with the chemical bonds in the side wall layer 205, so that the buffer layer 203 and the side wall layer 205 are tightly bonded and the stress at the interface between the two is small.

[0085] Therefore, in this embodiment, the stress between the side wall layer 205 and the sacrificial layer 202 is small. When the sacrificial layer 202 needs to be removed later, since the stress between the sacrificial layer 202 and the side wall layer 205 and between the sacrificial layer 202 and the buffer layer 203 is small, the side wall layer 205 graphic morphology will not change or tilt due to stress, so that the side wall layer 205 still maintains a good morphology after the sacrificial layer 202 is removed.

[0086] Moreover, in this embodiment, the material structure of the buffer layer 203 can also be a chain structure, a branch structure or a star structure, which is beneficial to further enhance the stress relief and stress release function of the buffer layer 203, thereby being more beneficial to reducing the stress at the interface between the side wall layer 205, the buffer layer 203 and the sacrificial layer 202, and further ensuring that the side wall layer 205 has a good graphic morphology.

[0087] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a plurality of discrete sacrificial layers are formed, wherein the material of the sacrificial layers is an organic material; forming a buffer layer on the side wall surface of the sacrificial layer, wherein the material of the buffer layer has an organic group and an inorganic component, and the organic group and the inorganic component are located in the same layer of material of the buffer layer; Forming a sidewall layer on the surface of the buffer layer, wherein the buffer layer is located between the sidewall layer and the sacrificial layer, and the material of the sidewall layer is an inorganic material; removing the sacrificial layer; The substrate is etched using the sidewall layer and the buffer layer as masks.

2. The forming method according to claim 1, characterized in that: The organic group includes an alkane group, an alkene group or a cycloalkene group.

3. The forming method according to claim 1, characterized in that: The thickness of the buffer layer is 5 angstroms to 20 angstroms.

4. The forming method according to claim 1, characterized in that: The buffer layer is formed by a hydrolysis condensation reaction of a coupling agent.

5. The forming method according to claim 4, characterized in that: The coupling agent includes a silane coupling agent.

6. The forming method according to claim 4, characterized in that: The process steps for forming the buffer layer include: preparing a reaction solution containing the coupling agent; coating the reaction solution to the top and side wall surfaces of the sacrificial layer; and heating the sacrificial layer to allow the coupling agent in the reaction solution to undergo the hydrolysis condensation reaction to form the buffer layer.

7. The forming method according to claim 6, characterized in that: In the prepared reaction solution, the mass percentage of the coupling agent is 0.1% to 2%.

8. The forming method according to claim 6, characterized in that: The reaction solution is coated on the top and sidewall surface of the sacrificial layer by a coating process; the process parameters of the coating process include: a coating speed of 1000 rpm to 1500 rpm, an acceleration of 500 rpm 2 ~1500rpm 2 .

9. The forming method according to claim 6, characterized in that: The process parameters of the heating treatment include: a heating temperature of 100°C to 130°C.

10. The forming method according to claim 1, characterized in that: Before forming the side wall layer, the buffer layer is also formed on the top surface of the sacrificial layer and the surface of the substrate; the process steps for forming the side wall layer include: forming a side wall film on the surface of the buffer layer; removing the side wall film and the buffer layer on the top of the sacrificial layer and removing the side wall film and the buffer layer on the substrate, retaining the buffer layer and the side wall film on the side wall surface of the sacrificial layer, and the retained side wall film serves as the side wall layer.

11. The forming method according to claim 1, characterized in that: Before forming the side wall layer, the formed buffer layer is also located on the top surface of the sacrificial layer and the surface of the substrate; the process steps for forming the side wall layer include: removing the buffer layer located on the top of the sacrificial layer and the substrate, and retaining the buffer layer located on the side wall surface of the sacrificial layer; forming a side wall film on the top of the sacrificial layer, the surface of the buffer layer and the substrate; removing the side wall film located on the top of the sacrificial layer and the substrate, retaining the buffer layer and the side wall film on the side wall surface of the sacrificial layer, and the retained side wall film serves as the side wall layer.

12. A semiconductor structure, characterized in that: include: A substrate and a plurality of separate sacrificial layers located on the substrate, wherein the sacrificial layers are made of organic materials; A buffer layer located on the sidewall surface of the sacrificial layer, wherein the material of the buffer layer contains organic groups and inorganic components, and the organic groups and the inorganic components are located in the same layer of material of the buffer layer; A sidewall layer is located on the surface of the buffer layer, and the buffer layer is located between the sidewall layer and the sacrificial layer. The material of the sidewall layer is an inorganic material.

13. The semiconductor structure according to claim 12, wherein: The buffer layer is also located between the spacer layer and the substrate; or, the spacer layer is also in contact with a partial surface of the substrate.

14. The semiconductor structure according to claim 12, wherein: The thickness of the buffer layer is 5 angstroms to 20 angstroms.

15. The semiconductor structure according to claim 12, wherein: The buffer layer is formed by a hydrolysis condensation reaction of a coupling agent.

16. The semiconductor structure according to claim 15, wherein: The coupling agent includes a silane coupling agent.

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