Capacitor and method for manufacturing same, storage device

Abstract

The present disclosure relates to a capacitor and a manufacturing method thereof, and a storage device. The capacitor manufacturing method includes: providing a substrate and forming a contact layer on the substrate, wherein a surface of the contact layer away from the substrate includes at least one contact area, and a surface of the contact area away from the substrate has at least two-level stepped structures; forming a support layer covering the contact layer; forming corresponding accommodation holes on the support layer to expose each of the contact areas; forming a first electrode, a second electrode, and a dielectric layer separating the first electrode and the second electrode in each of the accommodation holes, wherein the first electrode is in contact with the contact area.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a capacitor and a manufacturing method thereof, and a storage device. Background Art

[0002] A dynamic random access memory (DRAM) cell includes a capacitor for storing charge and a transistor for accessing the capacitor. With the development and advancement of technology, the size of dynamic random access memory is miniaturized. The internal capacitor is continuously reduced in size according to Moore's Law, and the contact resistance between the capacitor contact point and the capacitor electrode is continuously increased. Due to the increase in the contact resistance between the capacitor contact point and the capacitor electrode, the performance of the capacitor is reduced, such as reduced capacitance and increased energy consumption.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to provide a capacitor and a method for manufacturing the same, as well as a storage device, thereby overcoming, at least to a certain extent, the problem of reduced performance of the capacitor due to the increase in contact resistance of capacitor contact points and capacitor electrodes in the related art.

[0005] According to one aspect of the present disclosure, a method for manufacturing a capacitor is provided, the method comprising:

[0006] Providing a substrate, and forming a contact layer on the substrate, wherein the contact layer comprises at least one contact region, and a surface of each contact region away from the substrate has at least two-level stepped structures;

[0007] forming a support layer covering the contact layer;

[0008] Forming corresponding accommodation holes on the support layer to expose the contact areas;

[0009] A first electrode, a second electrode and a dielectric layer separating the first electrode and the second electrode are formed in each of the accommodating holes, and the first electrode is in contact with the contact area.

[0010] According to one embodiment of the present disclosure, forming a contact layer on the substrate includes:

[0011] depositing a contact layer material on the substrate;

[0012] The contact layer material is patterned to form a plurality of contact regions having at least two-level stepped structures on a surface away from the substrate to constitute the contact layer.

[0013] According to an embodiment of the present disclosure, a first electrode, a second electrode, and a dielectric layer separating the first electrode and the second electrode are formed in each of the receiving holes, including:

[0014] Depositing a first electrode material layer, a dielectric material layer, a second electrode material layer, a dielectric material layer and a first electrode material layer in sequence on the inner wall of the containing hole and a side of the supporting layer away from the substrate to form a first intermediate capacitor;

[0015] Thinning an end surface of the first intermediate capacitor away from the substrate until the support layer is exposed to form a first sub-electrode, a first dielectric layer, a fourth sub-electrode, a second dielectric layer and a second sub-electrode;

[0016] Thinning a portion of the fourth sub-electrode and filling the thinned region with insulating material to form a third insulating layer;

[0017] A first electrode material is deposited on end surfaces of the first sub-electrode and the second sub-electrode away from the substrate to form a third sub-electrode to connect the first sub-electrode and the second sub-electrode.

[0018] According to one embodiment of the present disclosure, the capacitor manufacturing method further includes:

[0019] forming a first insulating layer on the surface of the third sub-electrode;

[0020] A fifth sub-electrode is deposited on a side of the first insulating layer away from the substrate, and the fifth sub-electrode is connected to the fourth sub-electrode.

[0021] According to an embodiment of the present disclosure, before depositing the fifth sub-electrode, the method further includes:

[0022] Thinning a preset area of ​​the first sub-electrode, and depositing an insulating material in the thinned area to form a second insulating layer;

[0023] A fifth sub-electrode is deposited on a side of the first insulating layer away from the substrate, and the fifth sub-electrode is connected to the fourth sub-electrode, comprising:

[0024] A fifth sub-electrode is deposited on a side of the first insulating layer away from the substrate, the fifth sub-electrode is connected to the fourth sub-electrode, and a second insulating layer separates the fifth sub-electrode from the first sub-electrode.

[0025] According to an embodiment of the present disclosure, forming a first insulating layer on the surface of the third sub-electrode includes:

[0026] forming a first sub-insulating layer on both sides of the third sub-electrode;

[0027] A second sub-insulating layer is formed on a side of the third sub-electrode away from the substrate, and the first sub-insulating layer and the second sub-insulating layer are connected.

[0028] According to a second aspect of the present disclosure, a capacitor is provided, comprising:

[0029] substrate;

[0030] A contact layer, disposed on the substrate, the contact layer comprising at least one contact area, and a surface of each contact area away from the substrate having at least two-level stepped structures;

[0031] A supporting layer, disposed on the substrate and covering the contact layer, wherein the contact layer is formed with corresponding accommodation holes exposing the contact areas;

[0032] A first electrode is formed in the receiving hole and contacts the stepped structure of the corresponding contact area;

[0033] a second electrode, arranged opposite to the first electrode;

[0034] The dielectric layer is formed between the first electrode and the second electrode.

[0035] According to one embodiment of the present disclosure, the first electrode includes:

[0036] The first sub-electrode is a hollow barrel-shaped structure with an open top and a closed bottom connected to the contact layer;

[0037] A second sub-electrode is disposed inside the first sub-electrode, with a gap between the first sub-electrode and the second sub-electrode;

[0038] The third sub-electrode is disposed on the top of the first sub-electrode and is used to connect the first sub-electrode and the second sub-electrode.

[0039] According to one embodiment of the present disclosure, the dielectric layer includes:

[0040] a first dielectric layer formed on an inner wall of the first sub-electrode;

[0041] The second dielectric layer is formed on the surface of the second sub-electrode, and there is a gap between the first dielectric layer and the second dielectric layer.

[0042] According to one embodiment of the present disclosure, the second electrode includes:

[0043] a fourth sub-electrode, wherein the fourth sub-electrode is disposed in the gap between the first dielectric layer and the second dielectric layer;

[0044] The fifth sub-electrode is connected to the fourth sub-electrode and is disposed on the top of the fourth sub-electrode.

[0045] According to one embodiment of the present disclosure, a first insulating layer is arranged between the fifth sub-electrode and the third sub-electrode; a second insulating layer is arranged between the fifth sub-electrode and the first sub-electrode; and a third insulating layer is arranged between the fourth sub-electrode and the third sub-electrode.

[0046] According to a third aspect of the present disclosure, a storage device is provided, comprising the above-mentioned capacitor.

[0047] The method for manufacturing a capacitor provided by the present disclosure provides a contact area on a contact layer on a substrate, forms at least two steps of a stepped structure on the surface of the contact area away from the substrate, and the first electrode contacts the surface of the contact area away from the substrate. The contact area between the contact area and the first electrode is increased by the at least two steps of the stepped structure, thereby reducing the contact resistance between the first electrode and the contact area, thereby improving the performance of the capacitor. In addition, the method for manufacturing a capacitor provided by the present disclosure does not require wet etching to remove the support layer of the capacitor structure, and the capacitor is also prepared, thereby increasing the stability of the capacitor structure.

[0048] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0050] Figure 1 The present invention provides a flowchart of a first capacitor manufacturing method according to an exemplary embodiment of the present invention.

[0051] Figure 2 The present invention is a flowchart of a second capacitor manufacturing method provided by an exemplary embodiment of the present invention.

[0052] Figure 3 The present invention is a flowchart of a third capacitor manufacturing method provided by an exemplary embodiment of the present invention.

[0053] Figure 4 A schematic structural diagram of a capacitor provided in accordance with an exemplary embodiment of the present disclosure.

[0054] Figures 5 to 20 A process diagram of a capacitor manufacturing process provided for an exemplary embodiment of the present disclosure.

[0055] Fig.21 A schematic structural diagram of a first electrode provided in an exemplary embodiment of the present disclosure.

[0056] Fig. 22 A schematic structural diagram of a dielectric layer provided for an exemplary embodiment of the present disclosure.

[0057] Fig.23 A schematic structural diagram of a second electrode provided in an exemplary embodiment of the present disclosure.

[0058] In the figure:

[0059] 100, substrate; 200, contact layer; 300, supporting layer; 310, first supporting layer; 320, second supporting layer; 330, third supporting layer; 400, first electrode; 410, first sub-electrode; 420, second sub-electrode; 430, third sub-electrode; 500, dielectric layer; 510, first dielectric layer; 520, second dielectric layer; 600, second electrode; 610, fourth sub-electrode; 620, fifth sub-electrode; 710, first insulating layer; 720, second insulating layer; 740, supporting insulating layer; 750, third insulating layer.

[0060] 10. Photoresist; 20. Contact layer material; 40. First electrode material layer; 50. Dielectric material layer; 60. Second electrode material layer; 70. Insulating material. DETAILED DESCRIPTION

[0061] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0062] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0063] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0064] In this exemplary embodiment, a method for manufacturing a capacitor is first provided. Figure 1 As shown, the capacitor manufacturing method includes:

[0065] Step S110, providing a substrate 100, and forming a contact layer 200 on the substrate 100, wherein the contact layer 200 includes at least one contact area, and a surface of each contact area away from the substrate 100 has at least two-level stepped structures;

[0066] Step S120, forming a support layer 300 covering the contact layer 200;

[0067] Step S130, forming corresponding accommodation holes 350 exposing the contact areas on the support layer 300;

[0068] Step S140 , forming a first electrode 400 , a second electrode 600 , and a dielectric layer 500 separating the first electrode 400 and the second electrode 600 in each of the receiving holes 350 , wherein the first electrode 400 contacts the contact area.

[0069] The method for manufacturing a capacitor provided by the embodiment of the present disclosure is to set a contact area on the contact layer 200 on the substrate 100, and form at least two steps of stepped structures on the surface of the contact area away from the substrate 100, and the first electrode 400 is in contact with the surface of the contact area away from the substrate 100, and the contact area and the first electrode 400 are increased by at least two steps of stepped structures, thereby reducing the contact resistance between the first electrode 400 and the contact area, and improving the performance of the capacitor. In addition, the method for manufacturing a capacitor provided by the present disclosure does not require wet etching to remove the support layer 300 of the capacitor structure, thereby increasing the stability of the capacitor structure.

[0070] The following is a detailed description of each step of the capacitor manufacturing method provided by the embodiment of the present disclosure:

[0071] In step S110 , a substrate 100 may be provided, and a contact layer 200 may be formed on the substrate 100 . The surface of the contact layer 200 away from the substrate 100 includes at least one contact region.

[0072] Among them, Figure 2As shown, forming a contact layer 200 on the substrate 100 may include:

[0073] Step S210, depositing the contact layer material 20 on the substrate 100;

[0074] Step S220 , patterning the contact layer material 20 to form a plurality of contact regions having at least two-level stepped structures on a surface away from the substrate 100 to constitute the contact layer 200 .

[0075] The contact layer material 20 may be tungsten, which is formed on the surface of the substrate 100 by chemical vapor deposition. Figure 5 and 6 As shown, after the contact layer 200 is deposited on the substrate 100 by chemical vapor deposition, a photoresist 10 is coated on the side of the contact layer 200 away from the substrate 100, and photolithography is performed to form multiple contact areas in the contact layer 200. The contact area can be cylindrical, and multiple mutually independent cylindrical contact areas are formed by photolithography. Of course, in practical applications, the contact area can also be other structures such as prisms. The embodiments of the present disclosure are not limited to this. The contact area can be the side of the contact point plug away from the substrate, and the support insulating layer 740 is filled between the multiple contact point plugs.

[0076] With the development and progress of technology, the size of dynamic random access memory is miniaturized, and its internal capacitor is continuously reduced in geometric size according to Moore's Law, and the contact resistance between the capacitor contact point and the capacitor electrode is continuously increased. Due to the increase of the contact resistance between the capacitor contact point and the capacitor electrode, the performance of the capacitor is reduced. In order to solve this problem, the disclosed embodiment increases the contact area between the contact layer 200 and the first electrode 400 by setting at least two steps on the contact surface of the contact layer 200 and the first electrode 400, thereby reducing the contact resistance.

[0077] Among them, Figure 7 As shown, a staircase structure can be formed in the contact area by photolithography. For example, to form a two-level staircase structure, a photoresist 10 can be coated on half of the contact area surface, and the other half can be etched to form two levels of stairs. Of course, in practical applications, multiple levels of stairs can also be formed by multiple photolithography, and the present disclosure will not be further illustrated here.

[0078] In step S120, a support layer 300 covering the contact layer 200 may be formed, wherein the support layer 300 may be integrally formed or layered. Figure 8As shown, the support layer 300 includes multiple layers, which are the first support layer 310, the second support layer 320 and the third support layer 330 in the order away from the substrate 100, wherein the second support layer 320 is embedded with a silicon nitride layer 340, and the third support layer 330 is provided with a silicon nitride layer 340 on the side away from the substrate 100. The first support layer 310, the second support layer 320 and the third support layer 330 are functional layers, which are made of dielectric materials, and the silicon nitride layer is a skeleton layer for supporting. Before forming the support layer 300, an insulating material can be filled into the non-contact area of ​​the contact layer 200 so that multiple contact areas are insulated from each other. The support layer 300 can be formed by a chemical vapor deposition method, and the material of the support layer 300 can be boro-phospho-silicate-glass (BPSG) and the like, which is not specifically limited in the embodiments of the present disclosure.

[0079] In step S130 , receiving holes 350 that expose the contact areas may be formed on the support layer 300 in a one-to-one correspondence.

[0080] like Fig. 9 As shown, the number of the accommodation holes 350 is the same as the number of the contact areas and the positions correspond to the contact areas one by one. Of course, in practical applications, the number of the accommodation holes 350 and the contact areas may also be different, and the embodiments of the present disclosure do not specifically limit this. The accommodation holes 350 can be formed by photolithography, and the photoresist 10 is patterned on the side of the support layer 300 away from the substrate 100, and photolithography is performed until the contact areas are exposed.

[0081] In step S140 , a first electrode 400 , a second electrode 600 , and a dielectric layer 500 separating the first electrode 400 and the second electrode 600 may be formed in each of the receiving holes 350 , and the first electrode 400 is in contact with the contact region.

[0082] Among them, Figure 3 As shown, a first electrode 400, a second electrode 600 and a dielectric layer 500 separating the first electrode 400 and the second electrode 600 are formed in each of the receiving holes 350, including:

[0083] Step S310, depositing a first electrode material layer 40, a dielectric material layer 50, a second electrode material layer 60, a dielectric material layer 50 and a first electrode material layer 40 in sequence on the inner wall of the receiving hole 350 and a side of the supporting layer 300 away from the substrate 100 to form a first intermediate capacitor;

[0084] Step S320, thinning the end surface of the first intermediate capacitor away from the substrate 100 until the support layer 300 is exposed, forming a first sub-electrode 410, a first dielectric layer 510, a fourth sub-electrode 610, a second dielectric layer 520 and a second sub-electrode 420;

[0085] Step S330, thinning a portion of the fourth sub-electrode 610, and filling the thinned region with insulating material to form a third insulating layer 750;

[0086] Step S340 , depositing the first electrode 400 material on the end surfaces of the first sub-electrode 410 and the second sub-electrode 420 away from the substrate 100 to form a third sub-electrode 430 to connect the first sub-electrode 410 and the second sub-electrode 420 .

[0087] In step S310, a first electrode material layer 40, a dielectric material layer 50, a second electrode material layer 60, a dielectric material layer 50 and a first electrode material layer 40 may be sequentially deposited on the inner wall of the receiving hole 350 and the side of the supporting layer 300 away from the substrate 100 to form a first intermediate capacitor.

[0088] Among them, Fig.10 As shown, when the first electrode material layer 40, the dielectric material layer 50, the second electrode material layer 60, the dielectric material layer 50 and the first electrode material layer 40 are deposited, the first electrode material layer 40, the dielectric material layer 50, the second electrode material layer 60, the dielectric material layer 50 and the first electrode material layer 40 are sequentially formed on the side of the support layer 300 away from the substrate 100, that is, the electrodes in the plurality of receiving holes 350 are respectively connected to the dielectric layer 500. The first electrode material layer 40, the dielectric material layer 50, the second electrode material layer 60, the dielectric material layer 50 and the first electrode material layer 40 fill the receiving holes 350 into a solid structure.

[0089] In step S320 , the end surface of the first intermediate capacitor away from the substrate 100 may be thinned until the support layer 300 is exposed to form a first sub-electrode 410 , a first dielectric layer 510 , a fourth sub-electrode 610 , a second dielectric layer 520 and a second sub-electrode 420 .

[0090] like Fig.11As shown, the first intermediate capacitor can be thinned by chemical mechanical polishing until the support layer 300 is exposed, so as to separate the first electrode 400 material, the dielectric layer 500 material and the second electrode 600 material in each accommodation hole 350 in the first intermediate capacitor to form a partition layer so as to insulate them from each other. In step S310, the first electrode material layer 40, the dielectric material layer 50, the second electrode material layer 60, the dielectric material layer 50 and the first electrode material layer 40 are sequentially deposited to form a first sub-electrode 410, a first dielectric layer 510, a fourth sub-electrode 610, a second dielectric layer 520 and a second sub-electrode 420, respectively.

[0091] For example, the first sub-electrode 410, the first dielectric layer 510, the fourth sub-electrode 610 and the second dielectric layer 520 are all hollow thin-walled columnar structures, which are nested in the order of the first sub-electrode 410, the first dielectric layer 510, the fourth sub-electrode 610 and the second dielectric layer 520. The second sub-electrode 420 is a solid columnar structure and is arranged inside the second dielectric layer 520.

[0092] In step S330 , a portion of the fourth sub-electrode 610 may be thinned, and the thinned region may be filled with an insulating material 70 to form a third insulating layer 750 .

[0093] like Fig.12 As shown, part of the fourth sub-electrode 610 is thinned, and the part of the fourth sub-electrode 610 can be covered by the photoresist 10, and then photolithography is performed to thin the other part of the fourth sub-electrode 610 by back etching. After the back etching and thinning are completed, as shown in FIG. Fig.13 As shown, an insulating material 70, such as silicon nitride, is deposited in the area outside the definition of the photoresist 10. Fig.14 As shown, after the filling of the insulating material 70 is completed, etching back is performed, and the insulating material 70 in the thinned area of ​​the fourth sub-electrode 610 and the insulating material 70 on both sides of the photoresist 10 are retained during the etching back.

[0094] In step S340, if Figures 15 to 17 As shown, the first electrode 400 material can be deposited on the end surfaces of the first sub-electrode 410 and the second sub-electrode 420 away from the substrate 100 to form a third sub-electrode 430 to connect the first sub-electrode 410 and the second sub-electrode 420. A connection region is set on the end surfaces of the first sub-electrode 410 and the second sub-electrode 420 away from the substrate 100, and the connection region is used to deposit the third sub-electrode 430, and the third sub-electrode 430 is electrically connected to the first sub-electrode 410 and the second sub-electrode 420. The connection region can be defined by the photoresist 10.

[0095] Further, such as Fig.18 As shown, the capacitor manufacturing method further includes: forming a first insulating layer 710 on the surface of the third sub-electrode 430; Fig.19 and20 As shown, a preset area of ​​the first sub-electrode 410 is thinned, and an insulating material is deposited in the thinned area to form a second insulating layer 720, wherein the preset area may be an area on the end of the first sub-electrode 410 away from the substrate 100 that is exposed outside the first insulating layer 710; a fifth sub-electrode 620 is deposited on a side of the first insulating layer 710 away from the substrate 100, the fifth sub-electrode 620 is connected to the fourth sub-electrode 610, the fifth sub-electrode 620 is a common electrode, and is connected to multiple fourth sub-electrodes 610 to supply power to the second electrode 600.

[0096] The first insulating layer 710 is formed on the surface of the third sub-electrode 430, including: forming a first sub-insulating layer on both sides of the third sub-electrode 430, the first sub-insulating layer may be a silicon nitride layer, and in practical applications, the first sub-insulating layer may be formed by the insulating material on both sides of the photoresist 10 in step S330; forming a second sub-insulating layer on the side of the third sub-electrode 430 away from the substrate 100, the first sub-insulating layer and the second sub-insulating layer are connected, and the second sub-insulating layer is first defined by the photoresist 10 and then deposited. The second sub-insulating layer covers the third sub-electrode 430 to insulate the third sub-electrode 430 from the fifth sub-electrode 620, and the material thereof may be silicon nitride.

[0097] It is worth noting that the exemplary embodiment of the present disclosure produces a double-sided capacitor, but in actual applications, the method can also produce capacitors with more sides, such as three-sided capacitors, four-sided capacitors, etc. The embodiments of the present disclosure are not limited to this.

[0098] The method for manufacturing a capacitor provided in an embodiment of the present disclosure is to set a contact area on the contact layer 200 on the substrate 100, and form at least two steps of stepped structures on the surface of the contact area away from the substrate 100, so that the first electrode 400 is in contact with the surface of the contact area away from the substrate 100, and the contact area between the contact area and the first electrode 400 is increased by at least two steps of stepped structures, thereby reducing the contact resistance between the first electrode 400 and the contact area, thereby improving the performance of the capacitor. In addition, the method for manufacturing a capacitor provided in the present disclosure does not require wet etching to remove the support layer 300 of the capacitor structure, and a double-sided capacitor is manufactured, thereby avoiding the need to use wet etching to remove the support layer of the capacitor structure in the related art, and increasing the stability of the capacitor structure.

[0099] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0100] The exemplary embodiment of the present disclosure also provides a capacitor, such as Figure 4 As shown, the capacitor includes: a substrate 100, a contact layer 200, a support layer 300, a first electrode 400, a second electrode 600 and a dielectric layer 500; the contact layer 200 is arranged on the substrate 100, and the surface of the contact layer 200 includes at least one contact area, and the surface of the contact area away from the substrate 100 has at least two-level stepped structures; the support layer 300 is arranged on the substrate 100 and covers the contact layer 200, and the contact layer 200 is formed with corresponding accommodating holes 350 exposing each of the contact areas; the first electrode 400 is formed in the accommodating hole 350 and contacts with the corresponding stepped structure of the contact area away from the substrate 100; the second electrode 600 and the first electrode 400 are arranged opposite to each other; the dielectric layer 500 is formed between the first electrode 400 and the second electrode 600.

[0101] The capacitor provided by the embodiment of the present disclosure is provided with a contact area on the contact layer 200 on the substrate 100, and at least two-level stepped structures are formed on the surface of the contact area away from the substrate 100, and the first electrode 400 is in contact with the surface of the contact area away from the substrate 100. The contact area between the contact area and the first electrode 400 is increased by at least two-level stepped structures, thereby reducing the contact resistance between the first electrode 400 and the contact area, thereby improving the performance of the capacitor. In addition, the capacitor manufacturing method provided by the present disclosure does not need to use wet etching to remove the support layer 300 of the capacitor structure, thereby increasing the stability of the capacitor structure.

[0102] The components of the capacitor provided in the embodiment of the present disclosure are described in detail below:

[0103] like Fig.21 As shown, the first electrode 400 includes a first sub-electrode 410, a second sub-electrode 420 and a third sub-electrode 430. The first sub-electrode 410 is a hollow barrel-shaped structure with an open top, and the other end of the structure is connected to the contact layer 200. The second sub-electrode 420 is arranged in the first sub-electrode 410, and there is a gap between the first sub-electrode 410 and the second sub-electrode 420. The third sub-electrode 430 is arranged on the top of the first sub-electrode 410, and is used to connect the first sub-electrode 410 and the second sub-electrode 420.

[0104] The cross section of the first sub-electrode 410 may be a circular ring, the cross section of the second sub-electrode 420 may be a circle, and the first sub-electrode 410 and the second sub-electrode 420 are coaxially arranged to ensure that the gap between the first sub-electrode 410 and the second sub-electrode 420 is the same along the circumferential direction of the second sub-electrode 420. Of course, in practical applications, the cross section of the first sub-electrode 410 may also be a rectangular ring, and the corresponding cross section of the second sub-electrode 420 may be a rectangle, etc., which is not specifically limited in the embodiments of the present disclosure. The third sub-electrode 430 is located on the side of the first sub-electrode 410 and the second sub-electrode 420 away from the substrate 100 and is electrically connected to the first sub-electrode 410 and the second sub-electrode 420.

[0105] The material of the first electrode 400 may be metal, metal oxide, metal nitride or other conductive material, which is not specifically limited in the present disclosure. For example, in one embodiment, the material of the first electrode 400 may be titanium nitride, titanium or tungsten. Among them, the materials of the first sub-electrode 410, the second sub-electrode 420 and the third sub-electrode 430 may be the same or different, which is not specifically limited in the present disclosure.

[0106] like Fig. 22 As shown, the dielectric layer 500 includes a first dielectric layer 510 and a second dielectric layer 520. The first dielectric layer 510 is formed on the inner wall of the first sub-electrode 410 and is used to separate the first sub-electrode 410 and the second electrode 600. The second dielectric layer 520 is formed on the surface of the second sub-electrode 420. There is a gap between the first dielectric layer 510 and the second dielectric layer 520. The second dielectric layer 520 is used to separate the second sub-electrode 420 and the second electrode 600. The first dielectric layer 510 and the second dielectric layer 520 have uniform thickness. The material of the dielectric layer 500 is one or more of aluminum oxide, silicon oxide, zirconium oxide and silicon nitride.

[0107] like Fig.23 As shown, the second electrode 600 includes a fourth sub-electrode 610 and a fifth sub-electrode 620, and the fourth sub-electrode 610 is disposed in the gap between the first dielectric layer 510 and the second dielectric layer 520. The fifth sub-electrode 620 is connected to the fourth sub-electrode 610 and is disposed on the top of the fourth electrode 610. The fifth sub-electrode 620 is a common electrode, connected to a plurality of fourth sub-electrodes 610, and supplies power to the second electrode 600. A third insulating layer 750 is filled between the third sub-electrode 430 and the fourth sub-electrode 610. For example, in one embodiment, the material of the second electrode 600 may be titanium nitride, titanium, or tungsten.

[0108] In order to further ensure the insulation between the first electrode 400 and the second electrode 600, a first insulating layer 710 is provided between the fifth sub-electrode 620 and the third sub-electrode 430. A second insulating layer 720 is provided between the fifth sub-electrode 620 and the first sub-electrode 410. A first sub-insulating layer is formed on both sides of the third sub-electrode 430, and the first sub-insulating layer may be a silicon nitride layer. A second sub-insulating layer is formed on the side of the third sub-electrode 430 away from the substrate 100, and the first sub-insulating layer and the second sub-insulating layer are connected. The second sub-insulating layer is first defined by the photoresist 10 and then deposited. The second sub-insulating layer covers the third sub-electrode 430 to insulate the third sub-electrode 430 from the fifth sub-electrode 620, and the material thereof may be silicon nitride.

[0109] The substrate 100 includes a substrate and a supporting insulating layer 740; the supporting insulating layer 740 is arranged on the substrate and has an accommodating area, and the contact layer 200 is arranged in the accommodating area. In actual use, the substrate 100 may also include bit lines, word lines, and switching elements distributed in an array. A plurality of active areas are formed in the substrate, and a plurality of word line grooves are formed in the substrate. The grooves penetrate the active areas, and the grooves are filled with dielectrics and wires to form word lines. A barrier layer, a wire layer, and a dielectric layer are covered on the above substrate, and the line width of the bit line is defined by photolithography, and then etching is performed to form the bit line.

[0110] When the accommodation hole 350 is cylindrical, the contact layer 200 may include a plurality of cylindrical contact plugs distributed in an array, and the side of the contact plug away from the substrate 100 is provided with at least two steps, thereby increasing the contact area between the contact layer 200 and the first electrode 400 and reducing the contact resistance. A supporting insulating layer 740, such as silicon nitride, is filled between the plurality of contact plugs to insulate the plurality of contact plugs from each other. Of course, in practical applications, the contact plugs may also be structures such as rectangular columns, and the embodiments of the present disclosure are not limited thereto.

[0111] like Figure 8As shown, the support layer 300 can be integrally formed or layered. For example, the support layer 300 includes multiple layers, which are the first support layer 310, the second support layer 320 and the third support layer 330 in the order away from the substrate 100, wherein the second support layer 320 is embedded with a silicon nitride layer, and the third support layer 330 is provided with a silicon nitride layer on the side away from the substrate 100. The first support layer 310, the second support layer 320 and the third support layer 330 are functional layers made of dielectric materials, and the silicon nitride layer is a skeleton layer for supporting. Before forming the support layer, an insulating material can be filled into the non-contact area of ​​the contact layer 200 so that multiple contact areas are insulated from each other. The support layer 300 can be formed by a chemical vapor deposition method, and the material of the support layer 300 can be boro-phospho-silicate-glass (BPSG) or the like, which is not specifically limited in the embodiments of the present disclosure.

[0112] The exemplary embodiment of the present disclosure also provides a storage device, including the above-mentioned capacitor. The capacitor used in the storage device of the embodiment of the present disclosure has the same structure as the capacitor in the embodiment of the above-mentioned embedded capacitor structure, and therefore has the same beneficial effects, which will not be repeated here. The storage device can be a DRAM (dynamic random access memory) or other storage devices.

[0113] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a capacitor, characterized in that: The capacitor manufacturing method comprises: Providing a substrate, and forming a contact layer on the substrate, wherein the contact layer comprises at least one contact region, and a surface of each contact region away from the substrate has at least two-level stepped structures; forming a support layer covering the contact layer; Forming corresponding accommodation holes on the support layer to expose the contact areas; A first electrode, a second electrode and a dielectric layer separating the first electrode and the second electrode are formed in each of the accommodating holes, and the first electrode is in contact with the contact area.

2. The method for manufacturing a capacitor according to claim 1, wherein: Forming a contact layer on the substrate, comprising: depositing a contact layer material on the substrate; The contact layer material is patterned to form a plurality of contact regions having at least two-level stepped structures on a surface away from the substrate to constitute the contact layer.

3. The method for manufacturing a capacitor according to claim 1, wherein: A first electrode, a second electrode and a dielectric layer separating the first electrode and the second electrode are formed in each of the accommodating holes, comprising: Depositing a first electrode material layer, a dielectric material layer, a second electrode material layer, a dielectric material layer and a first electrode material layer in sequence on the inner wall of the containing hole and a side of the supporting layer away from the substrate to form a first intermediate capacitor; Thinning an end surface of the first intermediate capacitor away from the substrate until the support layer is exposed to form a first sub-electrode, a first dielectric layer, a fourth sub-electrode, a second dielectric layer and a second sub-electrode; Thinning a portion of the fourth sub-electrode and filling the thinned area with insulating material to form a third insulating layer; A first electrode material is deposited on end surfaces of the first sub-electrode and the second sub-electrode away from the substrate to form a third sub-electrode to connect the first sub-electrode and the second sub-electrode.

4. The method for manufacturing a capacitor according to claim 3, wherein: The capacitor manufacturing method further includes: forming a first insulating layer on the surface of the third sub-electrode; A fifth sub-electrode is deposited on a side of the first insulating layer away from the substrate, and the fifth sub-electrode is connected to the fourth sub-electrode.

5. The method for manufacturing a capacitor according to claim 4, wherein: Before depositing the fifth sub-electrode, the method further comprises: Thinning a preset area of ​​the first sub-electrode, and depositing an insulating material in the thinned area to form a second insulating layer; A fifth sub-electrode is deposited on a side of the first insulating layer away from the substrate, and the fifth sub-electrode is connected to the fourth sub-electrode, comprising: A fifth sub-electrode is deposited on a side of the first insulating layer away from the substrate, the fifth sub-electrode is connected to the fourth sub-electrode, and a second insulating layer separates the fifth sub-electrode from the first sub-electrode.

6. The method for manufacturing a capacitor according to claim 4, wherein: Forming a first insulating layer on the surface of the third sub-electrode includes: forming a first sub-insulating layer on both sides of the third sub-electrode; A second sub-insulating layer is formed on a side of the third sub-electrode away from the substrate, and the first sub-insulating layer and the second sub-insulating layer are connected.

7. A capacitor, characterized in that: The capacitor comprises: substrate; A contact layer, disposed on the substrate, the contact layer comprising at least one contact area, and a surface of each contact area away from the substrate having at least two-level stepped structures; A supporting layer, disposed on the substrate and covering the contact layer, wherein the contact layer is formed with corresponding accommodation holes exposing the contact areas; A first electrode is formed in the receiving hole and contacts the stepped structure of the corresponding contact area; a second electrode, arranged opposite to the first electrode; a dielectric layer formed between the first electrode and the second electrode; Wherein, the materials of the first electrode and the second electrode are titanium nitride, titanium or tungsten.

8. The capacitor according to claim 7, wherein: The first electrode comprises: The first sub-electrode is a hollow barrel-shaped structure with an open top and a closed bottom connected to the contact layer; A second sub-electrode is disposed inside the first sub-electrode, with a gap between the first sub-electrode and the second sub-electrode; The third sub-electrode is disposed on the top of the first sub-electrode and is used to connect the first sub-electrode and the second sub-electrode.

9. The capacitor according to claim 8, characterized in that The dielectric layer comprises: a first dielectric layer formed on an inner wall of the first sub-electrode; The second dielectric layer is formed on the surface of the second sub-electrode, and there is a gap between the first dielectric layer and the second dielectric layer.

10. The capacitor according to claim 9, wherein: The second electrode comprises: a fourth sub-electrode, wherein the fourth sub-electrode is disposed in the gap between the first dielectric layer and the second dielectric layer; The fifth sub-electrode is connected to the fourth sub-electrode and is disposed on the top of the fourth sub-electrode.

11. The capacitor according to claim 10, wherein: A first insulating layer is disposed between the fifth sub-electrode and the third sub-electrode; a second insulating layer is disposed between the fifth sub-electrode and the first sub-electrode; and a third insulating layer is disposed between the fourth sub-electrode and the third sub-electrode.

12. A storage device, characterized in that: Comprising a capacitor as described in any one of claims 7-11.

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