Thin film transistor array substrate and display device

Abstract

This invention discloses a thin-film transistor array substrate and a display device. The thin-film transistor array substrate includes a first semiconductor layer and a second semiconductor layer formed of two different semiconductor materials, a first gate electrode and a conductive layer overlapping the first semiconductor layer, a second gate electrode and a third gate electrode overlapping the second semiconductor layer, and an intermediate insulating layer disposed between the second semiconductor layer and the second gate electrode. By optimizing the film layer structure and molding process of the thin-film transistor array substrate, the process time is shortened, manufacturing costs are saved, the film layer thickness is reduced, and the flexible bending performance of the array substrate is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to a display device, and specifically to a thin film transistor array substrate of a display device. Background Art

[0002] With the development of display technology and users' increasing requirements on the appearance, performance and other aspects of display devices, active-matrix organic light emitting diode (AMOLED) flexible displays are becoming more and more widely used. As the performance of displays improves, whether the display devices can maintain low power consumption characteristics has become an increasingly important focus.

[0003] Low-temperature polysilicon (LTPS) thin-film transistors are widely welcomed by the market for their advantages such as high resolution, high brightness, and high aperture ratio. However, the mobility of polysilicon in the active layer of the LTPS process is too large, resulting in high leakage current and high power consumption under low-frequency driving. In order to better develop grayscale, the channel length in the driving thin-film transistor must be made very large, which makes it difficult to achieve high PPI (Pixels Per Inch). At the same time, using low-temperature polysilicon as the active layer also has high hysteresis, which easily leads to the problem of image retention. Metal oxides have emerged as new semiconductor active layer materials. Their advantages are high carrier mobility, low cost, low energy consumption and low heat generation, but their disadvantages are poor stability of TFT threshold voltage and the oxide active layer material is relatively sensitive to the outside world.

[0004] In the prior art, semiconductor layers of different materials are arranged on the same substrate to form a thin film transistor array substrate and a display device, so that the display device can have the advantages of both thin film transistors. For example, the two semiconductor layers are polysilicon material and metal oxide material respectively. The display device made in this way can have high brightness and high resolution while reducing driving power consumption. However, the process is complicated, especially the manufacturing process temperature of low-temperature polysilicon elements is about 600°C, which is difficult to combine with metal oxide semiconductor technology, and the manufacturing cost remains high. At the same time, due to the existence of two different active layers at the same time, the thickness of the array substrate is relatively large, which is difficult to meet the current development trend of thinness and flexibility.

[0005] Therefore, the existing technology has defects and needs to be solved urgently. Summary of the invention

[0006] The present invention aims to provide a thin film transistor array substrate and a display device, so as to optimize the production process, reduce the manufacturing cost, and have a better thickness of the array substrate.

[0007] To achieve the above object, the present invention provides a thin film transistor array substrate, comprising:

[0008] a first semiconductor layer;

[0009] a first gate insulating layer covering the first semiconductor layer;

[0010] A first gate electrode disposed on the first gate insulating layer and overlapping the first semiconductor layer;

[0011] a second gate insulating layer covering the first gate electrode;

[0012] A conductive layer and a second gate electrode disposed on the second gate insulating layer and arranged in the same layer;

[0013] an intermediate insulating layer, covering the conductive layer and the second gate electrode;

[0014] a second semiconductor layer disposed on the intermediate insulating layer, wherein the second semiconductor layer overlaps with the second gate electrode;

[0015] a third gate insulating layer covering the second semiconductor layer,

[0016] a third gate electrode disposed on the third gate insulating layer and overlapping the second semiconductor layer;

[0017] The first semiconductor layer and the second semiconductor layer are semiconductor layers made of different materials, and the intermediate insulating layer includes an oxide insulating layer.

[0018] Particularly, the first semiconductor layer includes polysilicon semiconductor material, and the second semiconductor layer includes oxide semiconductor material.

[0019] Particularly, the intermediate insulating layer is a single oxide insulating layer, and the thickness of the intermediate insulating layer is 1500-4500 Å.

[0020] Particularly, the hydrogen content in the second gate insulating layer is greater than or equal to 20%.

[0021] In particular, the intermediate insulating layer further includes a nitride insulating layer, wherein the nitride insulating layer is located below the oxide insulating layer, and a film thickness of the oxide insulating layer is equal to or less than a film thickness of the nitride insulating layer.

[0022] Particularly, the hydrogen content in the nitride insulating layer is ≥10% and ≤15%, and the hydrogen content in the second gate insulating layer is greater than 15%.

[0023] Particularly, the oxide insulating layer is a dense oxide film layer.

[0024] Particularly, the thickness of the intermediate insulating layer is 2-3 times the thickness of the second gate insulating layer.

[0025] Particularly, a height difference between an upper surface of the first semiconductor layer and a lower surface of the second semiconductor layer is 3500-7500 Å.

[0026] The present invention further provides a display device, comprising a thin film transistor array substrate, wherein the thin film transistor array substrate is any one of the thin film transistor array substrates described above.

[0027] Beneficial effects of the present invention: The present invention performs a hydrogenation process on low-temperature polysilicon semiconductors in advance to avoid the impact of high-temperature treatment on metal oxide semiconductor materials. At the same time, the film layer structure and molding process of the thin-film transistor array substrate are optimized, the process time is shortened, the manufacturing cost is saved, the film layer thickness is reduced, and the flexible bending performance of the array substrate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic structural diagram of a thin film transistor array substrate provided by an embodiment of the present invention.

[0030] Figure 2 A schematic diagram of another structure of a thin film transistor array substrate provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0032] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0035] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0036] See also Figure 1 , is a schematic structural diagram of a first embodiment of a thin film transistor array substrate of the present invention. The present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising: a substrate 100, a first semiconductor layer 101 disposed on the substrate 100, a first gate insulating layer 102 covering the first semiconductor layer 101, a first gate electrode 103 disposed on the first gate insulating layer 102 and overlapping with the first semiconductor layer 101, a second gate insulating layer 104 covering the first gate electrode 103, a conductive layer 105 and a second gate electrode 106 disposed on the second gate insulating layer 104 and arranged in the same layer, an intermediate insulating layer 107 covering the conductive layer 105 and the second gate electrode 106, a second semiconductor layer 108 disposed on the intermediate insulating layer 107, the second semiconductor layer 108 overlapping with the second gate electrode 106; a third gate insulating layer 109 covering the second semiconductor layer 108, and a third gate electrode 110 disposed on the third gate insulating layer 109 and overlapping with the second semiconductor layer 108. The conductive layer 105 overlaps with the first gate electrode 103 , and the conductive layer 105 and the first gate electrode 103 below form the upper and lower electrodes of the storage capacitor in the pixel circuit, and the second gate electrode 106 serves as the lower gate of the oxide thin film transistor, wherein the second gate electrode 106 does not overlap with the first gate electrode 103 .

[0037] The first semiconductor layer 101 and the second semiconductor layer 108 are semiconductor layers of different materials. In this embodiment, the first semiconductor layer 101 preferably includes polycrystalline silicon semiconductor material, such as low temperature polycrystalline silicon (LTPS), and the second semiconductor layer 108 includes oxide semiconductor material, such as indium gallium zinc oxide (IGZO). In other embodiments, the metal oxide semiconductor layer can also be at least one of zinc oxide (ZnO), indium oxide (InO), and gallium oxide (GaO). The first semiconductor layer and the second semiconductor layer form active layers of the first thin film transistor and the second thin film transistor, respectively. The thin film transistor array substrate also includes a fourth gate insulating layer 111 disposed on the third gate electrode 110, and a first source and a drain electrode and a second source and a drain electrode disposed on the fourth gate insulating layer 111. The first source and the drain electrode are connected to the first semiconductor layer, and the second source and the drain electrode are connected to the second semiconductor layer.

[0038] Since there are grain boundaries between polysilicon grains and interface states between polysilicon and the gate insulating layer, the electrical properties of polysilicon thin film transistors are affected. Therefore, in the manufacturing process of low-temperature polysilicon thin film transistors, the polysilicon active layer is often hydrogenated. The hydrogenation treatment is to use hydrogen ions to fill the unbonded bonds of polysilicon atoms to reduce dangling bonds, thereby improving the stability of P-Si, improving electron mobility, conductivity and threshold voltage uniformity, and reducing leakage current (Ioff). However, the hydrogenation treatment needs to be carried out under high temperature conditions, which will cause hydrogen ions (H+) to diffuse in all directions, causing free H+ to act on the active layer of the oxide thin film transistor, robbing oxygen in the metal oxide, resulting in a large number of oxygen defects in the oxide, making the oxide semiconductor layer conductive, and then causing a short circuit between the source and drain of the oxide transistor.

[0039] In order to save process steps in the prior art, the hydrogenation of polysilicon and the heat treatment of the oxide semiconductor layer are often carried out simultaneously. In order to prevent hydrogen ions from affecting the oxide semiconductor material during the high-temperature hydrogenation process, the intermediate insulating layer between the two semiconductor layers is required to have good hydrogen resistance, so that the intermediate insulating layer often needs to be thick enough to achieve the above purpose. This results in the array substrate being thicker and unable to meet the requirements of flexible bending.

[0040] In the embodiment of the present invention, the high-temperature hydrogenation treatment of polysilicon in the thin film transistor array substrate is carried out in advance, that is, the first semiconductor layer 101 is subjected to high-temperature hydrogenation treatment after the second gate insulating layer 104 is formed. At this time, hydrogen ions can only migrate in the direction of the polysilicon semiconductor material below. After complete hydrogenation, the subsequent conductive layer 104, the second gate electrode 106 and the intermediate insulating layer 107 are manufactured. Since the hydrogenation treatment has been completed at this time, the intermediate insulating layer is not required to provide hydrogen ions for hydrogenation, so the intermediate insulating layer 107 can be a single oxide insulating layer, which can reduce the film forming process, simplify the process, and reduce the manufacturing cost. In addition, since the intermediate insulating layer 107 does not need to participate in the high-temperature hydrogenation process, the requirements for its hydrogen barrier will also be reduced, so that the thickness of the single oxide insulating layer has room for further optimization, which is more conducive to achieving flexible bending. Specifically, the thickness of the intermediate insulating layer is preferably 1500-4500A. This thickness range can not only ensure a good hydrogen barrier effect and prevent the oxide semiconductor layer from being conductorized, but also take into account the flexible bending performance of the thin film transistor array substrate.

[0041] The intermediate insulating layer 107 is preferably SiO x The inorganic insulating layer of the material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or a spin coating method, etc.

[0042] In order to ensure sufficient hydrogenation, the hydrogen content of the first gate insulating layer 102 and the second gate insulating layer 104 can be adjusted to provide sufficient hydrogen ions to the first semiconductor layer 101 during the hydrogenation process. The hydrogen content in the film layer can be adjusted by adjusting the process parameters, such as adjusting the film formation rate and the gas ratio. After the film is formed, the H+ concentration in each film layer can be tested by testing the content of SH and NH in the film by spectral analysis (FTIR). In this embodiment, the hydrogen content in the second gate insulating layer 104 is preferably greater than or equal to 20%, and more preferably the hydrogen content in the second gate insulating layer 104 is between 20% and 30%, so as to ensure that sufficient hydrogen ions are provided during the hydrogenation process to achieve complete hydrogenation of polysilicon.

[0043] In other embodiments, the hydrogenation process can also be performed after the metal layer where the conductive layer 105 and the second gate electrode 106 are located is formed. At this time, the metal layer has not been etched yet and can completely cover the second gate insulating layer 104. During the hydrogenation process, the metal layer can also block the upward migration of hydrogen ions, thereby improving the utilization rate of hydrogen ions and the hydrogenation effect. After the hydrogenation is completed, the metal layer is patterned to form a patterned conductive layer 105 and a second gate electrode 106. The conductive layer 105 is arranged in the same layer as the second gate electrode 106 of the second thin film transistor. This simplifies the process flow, reduces the production of a film layer, and is also conducive to the thinning of the overall thickness of the array substrate. Similarly, the intermediate insulating layer produced at this time does not need to participate in the hydrogenation process, which is conducive to further optimization and thinning of the thickness of the intermediate insulating layer 107.

[0044] In other embodiments, in order to shorten the heat treatment time, the process of simultaneously performing the hydrogenation treatment and the heat treatment of the oxide semiconductor can also be used. In this case, in order to optimize the film thickness, the intermediate insulating layer needs to be improved. Figure 2 As shown, the intermediate insulating layer 107 includes an oxide insulating layer 107A and a nitride insulating layer 107B, and the nitride insulating layer 107B is located below the oxide insulating layer 107A.

[0045] In the process of hydrogenating the polysilicon semiconductor layer, there are two main factors that affect the migration of hydrogen ions: first, whether there are substances that block the diffusion of hydrogen and affect the normal diffusion of H; second, the diffusion of hydrogen ions will diffuse from high concentration to low concentration. Therefore, the nitride insulating layer 107B in the intermediate insulating layer 107 described in this embodiment is attached to the second gate insulating layer 104, wherein the nitrogen element can inhibit the migration of hydrogen ions and prevent the diffusion of hydrogen ions toward the direction of the oxide semiconductor, thereby improving the utilization rate of hydrogen ions. At the same time, the nitride insulating layer 107B also contains hydrogen, which can also play a role in supplementing hydrogen ions during the hydrogenation process to ensure the complete hydrogenation of polysilicon. Since the oxide insulating layer 107A in the intermediate insulating layer 107 does not contain hydrogen ions, it can play a good barrier role in the migration of hydrogen ions, and can effectively avoid the influence of hydrogen ions on oxide semiconductor materials, so that the process combination of polysilicon thin film transistors and oxide semiconductor thin film transistors is realized, and the yield of the product is improved.

[0046] In order to control the migration direction of hydrogen ions, in this embodiment, the hydrogen ion content in the nitride insulating layer 107B is further limited to be only slightly lower than the hydrogen ion content in the second gate insulating layer 104, so that the concentration difference of the hydrogen content in the nitride insulating layer 107B and the adjacent second gate insulating layer 104 is much smaller than the concentration difference of the hydrogen content in the second gate insulating layer 104 and the first semiconductor layer 101, so that when the hydrogen ions diffuse, they will migrate in the direction of the first semiconductor layer 101 with a larger concentration difference, which is equivalent to forming a migration blocking switch in the nitride insulating layer, which can play a better role in inhibiting migration. In this embodiment, it is preferred that the hydrogen content in the nitride insulating layer 107B is ≥10% and ≤15%, and the hydrogen content in the second gate insulating layer 104 is greater than 15%. In this way, sufficient hydrogen ion supply can be guaranteed to achieve complete hydrogenation of polysilicon, and the effect of better inhibiting the migration of hydrogen ions to the second semiconductor layer 108 can be achieved.

[0047] In addition, the hydrogen barrier effect can be improved by increasing the density of the film layer. In other embodiments, the oxide insulating layer 107A is a dense oxide film layer. Specifically, the oxide insulating layer 107A is preferably made of SiO x Preparation, by adjusting the stacking speed of the oxide insulating layer, using a coupling agent to modify the film or heat treating the film at 200°C-500°C, a denser oxide insulating layer can be obtained.

[0048] The density of the oxide film layer is usually characterized by the deposition-etching ratio of the oxide film, wherein a higher deposition-etching ratio means a higher density of the film layer. In this embodiment, an oxide film layer with a deposition-etching ratio higher than 3:1 is preferably used as a dense oxide film layer to enable it to have better hydrogen resistance.

[0049] By improving the hydrogen barrier capability of the nitride insulating layer 107B or the oxide insulating layer 107A in the intermediate insulating layer 107, the intermediate insulating layer 107, especially the oxide insulating layer 107A, avoids using a larger thickness to obtain a better hydrogen barrier effect, thereby making it feasible and beneficial to reduce the film thickness of the oxide insulating layer 107A. In this embodiment, the film thickness of the oxide insulating layer 107A is preferably less than or equal to the film thickness of the nitride insulating layer 107B, which can shorten the film deposition or coating time and improve mass production efficiency, and is also beneficial to reducing the thickness of the thin film transistor array substrate.

[0050] In some embodiments, the thickness of the first gate insulating layer 102 and the second gate insulating layer 104 are both 1000-1500A, the thickness of the intermediate insulating layer 107 is 2-3 times the thickness of the second gate insulating layer 104, and it is further preferred that the thickness of the intermediate insulating layer 107 is 1500-4500A. On the other hand, by optimizing the film structure and manufacturing process of the array substrate, the height difference between the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer in the thin film transistor array substrate is preferably 3500-7500A, and it is more preferred that the height difference between the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer is 4500-6500A, which not only takes into account the functional characteristics and flexibility of the thin film transistor array substrate, but also helps to reduce costs and improve production efficiency in terms of process.

[0051] An embodiment of the present invention further provides a display device, wherein the display device comprises a thin film transistor array substrate, and the thin film transistor array substrate is any of the thin film transistor array substrates described above.

[0052] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0053] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thin film transistor array substrate, characterized in that: include: a first semiconductor layer; a first gate insulating layer covering the first semiconductor layer; A first gate electrode disposed on the first gate insulating layer and overlapping the first semiconductor layer; a second gate insulating layer covering the first gate electrode; A conductive layer and a second gate electrode disposed on the second gate insulating layer and arranged in the same layer; an intermediate insulating layer, covering the conductive layer and the second gate electrode; a second semiconductor layer disposed on the intermediate insulating layer, wherein the second semiconductor layer overlaps with the second gate electrode; a third gate insulating layer covering the second semiconductor layer, a third gate electrode disposed on the third gate insulating layer and overlapping the second semiconductor layer; Among them, the first semiconductor layer and the second semiconductor layer are semiconductor layers of different materials, the intermediate insulating layer includes an oxide insulating layer and a nitride insulating layer, the nitride insulating layer is located below the oxide insulating layer, the hydrogen content in the nitride insulating layer is ≥10% and ≤15%, and the hydrogen content in the second gate insulating layer is greater than 15%.

2. The thin film transistor array substrate according to claim 1, wherein: The first semiconductor layer includes a polysilicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material.

3. The thin film transistor array substrate according to claim 2, wherein: The film thickness of the oxide insulating layer is equal to or less than the film thickness of the nitride insulating layer.

4. The thin film transistor array substrate according to claim 1, wherein: The oxide insulating layer is a dense oxide film layer.

5. The thin film transistor array substrate according to claim 1, wherein: The thickness of the intermediate insulating layer is 2-3 times the thickness of the second gate insulating layer.

6. The thin film transistor array substrate according to claim 1, wherein: A height difference between an upper surface of the first semiconductor layer and a lower surface of the second semiconductor layer is 3500-7500 Å.

7. A display device, comprising a thin film transistor array substrate, wherein the thin film transistor array substrate is the thin film transistor array substrate according to any one of claims 1 to 6.

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