A PWM signal selection circuit and motor controller

Abstract

An embodiment of the present invention discloses a PWM signal selection circuit and a motor controller. The PWM signal selection circuit includes a first frequency selection circuit, a second frequency selection circuit, and a logic circuit. The first frequency selection circuit selects PWM signals with a frequency less than or equal to an upper limit in the PWM signal and inputs them into the logic circuit, and the second frequency selection circuit selects PWM signals with a frequency greater than or equal to a lower limit in the PWM signal and inputs them into the logic circuit. The embodiment of the present invention enables the logic circuit to only allow PWM signals within a preset frequency range on the high-voltage side to generate control signals among the PWM signals transmitted from the low-voltage side to the high-voltage side, thereby improving the anti-interference ability of the signal transmission path, suppressing the interference of frequency signals outside the preset frequency range on the control signal, and reducing the interference of single-level control signals such as normally low and normally high in the signal transmission path, so that the control signal can meet the control occasions of high voltage and large current.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of electrical technology, and in particular to a PWM signal selection circuit and a motor controller. Background Art

[0002] With the increase of on-board electronic equipment, the number of electronic controllers is increasing.

[0003] In the field of automotive electronic controllers, low-voltage control signals are needed to control high-voltage actuators. For example, single-level control signals such as normally low and normally high are required. In the low-voltage to high-voltage signal transmission path, the control signal is easily interfered with, causing malfunction at the actuator end. Current signal transmission paths that only reduce emission and conduction coupling interference at the structural design or layout level are no longer sufficient for high-voltage and high-current control scenarios. Summary of the Invention

[0004] Embodiments of the present invention provide a PWM signal selection circuit and a motor controller to improve the anti-interference capability of a signal transmission path and reduce interference of a control signal in the signal transmission path.

[0005] In a first aspect, an embodiment of the present invention provides a PWM signal selection circuit, characterized by comprising: a first frequency selection circuit, a second frequency selection circuit and a logic circuit;

[0006] The first frequency selection circuit includes an input terminal and an output terminal, wherein the input terminal of the first frequency selection circuit is used to input a PWM signal; the first frequency selection circuit is used to select a PWM signal having a frequency less than or equal to an upper limit frequency from the PWM signal and output the signal from the output terminal of the first frequency selection circuit;

[0007] The second frequency selection circuit includes an input terminal and an output terminal, wherein the input terminal of the second frequency selection circuit is used to input a PWM signal; the second frequency selection circuit is used to select a PWM signal having a frequency greater than or equal to a lower limit among the PWM signals and output the signal from the output terminal of the second frequency selection circuit;

[0008] The logic circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the logic circuit is connected to the output terminal of the first frequency selection circuit, and the second input terminal of the logic circuit is connected to the output terminal of the second frequency selection circuit. The logic circuit is used to select a PWM signal within a preset frequency range from the PWM signal and output it from the output terminal of the logic circuit. The preset frequency range is between an upper limit frequency and a lower limit frequency.

[0009] Optionally, the first frequency selection circuit includes a first oscillator, a first trigger, a first resistor and a first capacitor; the second frequency selection circuit includes a second oscillator, a second trigger, a second resistor and a second capacitor;

[0010] A first input terminal of the first oscillator is connected to an input terminal of the first frequency selection circuit, a second input terminal of the first oscillator is connected to a power signal, a third input terminal of the first oscillator is connected to the power signal via a first resistor, and the third input terminal of the first oscillator is grounded via a first capacitor;

[0011] A first input terminal of the second oscillator is connected to an input terminal of the second frequency selection circuit, a second input terminal of the second oscillator is connected to a power signal, a third input terminal of the second oscillator is connected to the power signal via a second resistor, and the third input terminal of the second oscillator is grounded via a second capacitor;

[0012] A first input terminal of the first trigger is connected to the output terminal of the first oscillator, a second input terminal of the first trigger is connected to the first input terminal of the first oscillator, a third input terminal of the first trigger is connected to the fourth input terminal and then connected to a power signal, and an output terminal of the first trigger is connected to the output terminal of the first frequency selection circuit;

[0013] The first input terminal of the second trigger is connected to the fourth input terminal of the first trigger, the second input terminal of the second trigger is connected to the second input terminal of the first trigger, the third input terminal of the second trigger is connected to the fourth input terminal and then connected to the output terminal of the second oscillator, and the output terminal of the second trigger is connected to the output terminal of the second frequency selection circuit.

[0014] Optionally, the upper limit frequency f1 is determined by the first resistor R1 and the first capacitor C1, and f1=1 / (R1*C1).

[0015] Optionally, the lower limit frequency f2 is determined by the second resistor R2 and the second capacitor C2, and f1 = 1 / (R2*C2).

[0016] Optionally, the logic circuit includes a NAND gate; the first input terminal of the NAND gate serves as the first input terminal of the logic circuit, the second input terminal of the NAND gate serves as the second input terminal of the logic circuit, and the output terminal of the NAND gate serves as the output terminal of the logic circuit.

[0017] Optionally, the first trigger and / or the second trigger is a D-type trigger.

[0018] Optionally, the first oscillator and / or the second oscillator is a monostable multivibrator.

[0019] In a second aspect, an embodiment of the present invention further provides a motor controller, characterized in that it includes the PWM signal selection circuit, control module and isolation circuit as described in any one of the first aspects above;

[0020] The control module is used to generate PWM signals;

[0021] The isolation circuit is connected to the control module, and is used to isolate the PWM signal; the isolation circuit is connected to the PWM signal selection circuit, and is used to transmit the isolated PWM signal to the PWM signal selection circuit.

[0022] Optionally, the isolation circuit includes a digital isolator; the input end of the digital isolator is connected to the output end of the control module; the output end of the digital isolator is connected to the input end of the first frequency selection circuit and to the input end of the second frequency selection circuit.

[0023] The PWM signal selection circuit provided by the embodiment of the present invention is configured by providing a first frequency selection circuit, a second frequency selection circuit, and a logic circuit. The first frequency selection circuit selects PWM signals with a frequency less than or equal to an upper limit in the PWM signal and inputs them into the logic circuit, while the second frequency selection circuit selects PWM signals with a frequency greater than or equal to a lower limit in the PWM signal and inputs them into the logic circuit. The embodiment of the present invention enables the logic circuit to only allow PWM signals within a preset frequency range on the high-voltage side to generate control signals among the PWM signals transmitted from the low-voltage side to the high-voltage side. This solves the technical problem that a signal transmission path that only reduces emission and conduction coupling interference at the structural design level or the layout level cannot meet the requirements of high-voltage and high-current control scenarios. It improves the anti-interference capability of the signal transmission path, suppresses the interference of frequency signals outside the preset frequency range on the control signal, and reduces the interference of single-level control signals such as normally low and normally high in the signal transmission path, so that the control signal can meet the requirements of high-voltage and high-current control scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic structural diagram of a PWM signal selection circuit provided by an embodiment of the present invention;

[0025] Figure 2 A schematic structural diagram of another PWM signal selection circuit provided by an embodiment of the present invention;

[0026] Figure 3 A schematic structural diagram of another PWM signal selection circuit provided by an embodiment of the present invention;

[0027] Figure 4 A schematic structural diagram of a motor controller provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0029] The PWM signal selection circuit provided in the embodiment of the present invention can be applied to the motor controller of new energy vehicles. Figure 1 A structural diagram of a PWM signal selection circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the PWM signal selection circuit includes: a first frequency selection circuit 10, a second frequency selection circuit 20 and a logic circuit 30;

[0030] The first frequency selection circuit 10 includes an input terminal and an output terminal. The input terminal of the first frequency selection circuit 10 is used to input a PWM signal. The first frequency selection circuit 10 is used to select a PWM signal with a frequency less than or equal to an upper limit frequency from the PWM signal and output it from the output terminal of the first frequency selection circuit 10.

[0031] The second frequency selection circuit 20 includes an input terminal and an output terminal. The input terminal of the second frequency selection circuit 20 is used to input a PWM signal. The second frequency selection circuit 20 is used to select a PWM signal having a frequency greater than or equal to a lower limit among the PWM signals and output it from the output terminal of the second frequency selection circuit 20.

[0032] The logic circuit 30 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the logic circuit 30 is connected to the output terminal of the first frequency selection circuit 10, and the second input terminal of the logic circuit 30 is connected to the output terminal of the second frequency selection circuit 20. The logic circuit 30 is used to select a PWM signal within a preset frequency range from the PWM signal and output it from the output terminal of the logic circuit 30. The preset frequency range is between an upper limit frequency and a lower limit frequency.

[0033] In this application, the PWM signal selection circuit is set in the signal transmission path from the low voltage side to the high voltage side. More specifically, the PWM signal selection circuit can be set on the high voltage side. The PWM can be a high-frequency PWM signal. Figure 1After the PWM signal emitted from the low-voltage side is converted into a high-voltage PWM signal, it can be divided into two paths. One PWM signal enters the first frequency selection circuit 10 from the input end. The first frequency selection circuit 10 selects PWM signals with a frequency less than or equal to the upper limit from the PWM signal and outputs them from its own output end to the first input end of the logic circuit 30. The other PWM signal enters the second frequency selection circuit 20 from the input end. The second frequency selection circuit 20 selects PWM signals with a frequency greater than or equal to the lower limit from the PWM signal and outputs them from its own output end to the second input end of the logic circuit 30. Furthermore, the logic circuit 30 selects a PWM signal within a preset frequency range from the PWM signal based on its own logical operation and outputs it from its own output end. The preset frequency range is based on the upper and lower frequency limits. The upper and lower frequency limits corresponding to the preset frequency range can be flexibly set according to actual needs. Accordingly, the logic circuit 30 can only allow PWM signals within a preset frequency range as control signals on the high-voltage side of the signal transmission path, thereby improving the anti-interference capability of the signal transmission path, suppressing the interference of frequency signals outside the preset frequency range on the control signal, and reducing the interference of single-level control signals such as normally low and normally high in the signal transmission path, so that the control signal can meet the control needs of high-voltage and high-current applications.

[0034] As a possible implementation of this application, Figure 2 A schematic diagram of another PWM signal selection circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the first frequency selection circuit 10 includes a first oscillator 11, a first trigger 12, a first resistor R1 and a first capacitor C1; the second frequency selection circuit 20 includes a second oscillator 21, a second trigger 22, a second resistor R2 and a second capacitor C2.

[0035] A first input terminal a1 of the first oscillator 11 is connected to an input terminal of the first frequency selection circuit 10, a second input terminal a2 of the first oscillator 11 is connected to a power supply signal VDD, a third input terminal a3 of the first oscillator 11 is connected to the power supply signal VDD via a first resistor R1, and the third input terminal a3 of the first oscillator 11 is grounded via a first capacitor C1;

[0036] A first input terminal c1 of the second oscillator 21 is connected to an input terminal of the second frequency selection circuit 20, a second input terminal c2 of the second oscillator 21 is connected to a power supply signal VDD, a third input terminal c3 of the second oscillator 21 is connected to the power supply signal VDD via a second resistor R2, and the third input terminal c3 of the second oscillator 21 is grounded via a second capacitor C2;

[0037] A first input terminal b1 of the first trigger 12 is connected to the output terminal of the first oscillator 11, a second input terminal b2 of the first trigger 12 is connected to the first input terminal a1 of the first oscillator 11, a third input terminal b3 of the first trigger 12 is connected to the fourth input terminal b4 and then connected to the power supply signal VDD, and an output terminal of the first trigger 12 is connected to the output terminal of the first frequency selection circuit 10;

[0038] The first input terminal d1 of the second trigger 22 is connected to the fourth input terminal b4 of the first trigger 12, the second input terminal d2 of the second trigger 22 is connected to the second input terminal b2 of the first trigger 12, the third input terminal d3 of the second trigger 22 is connected to the fourth input terminal d4 and then connected to the output terminal of the second oscillator 21, and the output terminal of the second trigger 22 is connected to the output terminal of the second frequency selection circuit 20.

[0039] See also Figure 2 After the PWM signal emitted from the low-voltage side is converted into a high-voltage PWM signal, it can be divided into two paths. One PWM signal enters the first oscillator 11 from the first input terminal a1 of the first oscillator 11. After passing through the first oscillator 11, the PWM signal enters the first input terminal b1 of the first trigger 12 from the output terminal of the first oscillator 11. After passing through the first trigger 12, the PWM signal is output from the output terminal of the first trigger 12 to the first input terminal of the logic circuit 30. Accordingly, based on the connection relationship between the first resistor R1 and the first capacitor C1 and the first oscillator 11, the PWM signal passes through the first oscillator 11 and the first trigger 12 in sequence. The first frequency selection circuit 10 suppresses frequency signals greater than the upper limit frequency in the PWM signal, thereby achieving anti-interference selection of PWM signals less than or equal to the upper limit frequency in the PWM signal. Based on the connection relationship between the first resistor R1 and the first capacitor C1 and the first oscillator 11, the upper limit frequency f1 is optionally determined by the first resistor R1 and the first capacitor C1, and f1 = 1 / (R1*C1).

[0040] Another PWM signal enters the second oscillator 21 from the first input terminal c1 of the second oscillator 21. After passing through the second oscillator 21, the PWM signal enters the third input terminal d3 of the second trigger 22 from the output terminal of the second oscillator 21. After passing through the second trigger 22, the PWM signal is output from the output terminal of the second trigger 22 to the second input terminal of the logic circuit 30. Accordingly, based on the connection relationship between the second resistor R2 and the second capacitor C2 and the second oscillator 21, the PWM signal passes through the second oscillator 21 and the second trigger 22 in sequence. The second frequency selection circuit 20 suppresses frequency signals within the PWM signal that are less than the lower limit frequency, thereby achieving anti-interference selection of PWM signals within the PWM signal that are greater than or equal to the lower limit frequency. Optionally, based on the connection relationship between the second resistor R2 and the second capacitor C2 and the second oscillator 21, the lower limit frequency f2 is determined by the second resistor R2 and the second capacitor C2, and f1 = 1 / (R2*C2).

[0041] As another possible implementation of the present application, the logic circuit includes a NAND gate; the first input of the NAND gate serves as the first input of the logic circuit, the second input of the NAND gate serves as the second input of the logic circuit 30, and the output of the NAND gate serves as the output of the logic circuit. Specifically, the NAND gate is a superposition of an AND gate and a NOT gate, having multiple inputs and one output. If all inputs are high, the output is low; if at least one of the inputs is low, the output is high.

[0042] As another possible implementation of the present application, the first trigger and / or the second trigger is a D-type trigger.

[0043] As another possible implementation of the present application, the first oscillator and / or the second oscillator is a monostable multivibrator.

[0044] In order to further explain the working principle of the PWM signal selection circuit of the present application in detail, for example, Figure 3 A schematic diagram of another PWM signal selection circuit provided by an embodiment of the present invention, wherein Figure 3In the example, first oscillator 11 and second oscillator 21 are both monostable multivibrators, such as a 74HC123 retriggerable monostable multivibrator, first flip-flop 12 and second flip-flop 22 are both D-type flip-flops, such as a 74HC74 D-type flip-flop, and logic circuit 30 is a NAND gate. Table 1 is the truth table for a 74HC123 retriggerable monostable multivibrator, and Table 2 is the truth table for a 74HC74 D-type flip-flop with set and reset terminals. ↑ represents a rising edge, ↓ represents a falling edge, H represents a high level, L represents a low level, and X is negligible. In Table 1, RD, A, and B represent the "Input" ports of the 74HC123, and Q and QN represent the "Output" ports of the 74HC123. In Table 2, S, R, CL, and D are all input ports of 74HC74, and Q and Q are all output ports of 74HC74. For the 74HC74 trigger, when the R port and the S port are both high, the Q port follows the D port.

[0045] Table 1

[0046]

[0047] Table 2

[0048]

[0049] See also Figure 3 After the PWM signal from the low-voltage side is converted into a high-voltage PWM signal, it can be divided into two paths. One PWM signal enters the first oscillator 11. According to the connection relationship of the first oscillator 11, the RD of the first oscillator 11 is high, and the A is low. Referring to Table 1, when the RD of the first oscillator 11 is high, and the A is low, and a rising edge occurs at the B port, the Q port outputs a high level for a duration set by the first resistor R1 and the first capacitor C1. After the high level output lasts for a duration (R1*C1), the Q port output changes to a low level. Thus, when the interval time t≤R1*C1 between the rising edges of the B port of the first oscillator 11, the Q port output remains high. With the Q port of the first oscillator 11 maintained at a high level, referring to Table 2, the Q port of the first flip-flop 12 remains high, and the Q NOT port remains low. When the Q NOT port of the first flip-flop 12 remains low, the output of the logic circuit 30 remains constant at a high level. That is to say, the interval time 1 / t of the rising edge of the B port of the first oscillator 11 is ≥ 1 / (R1*C1), and the output of the logic circuit 30 is constantly at a high level. If you want the output of the logic circuit 30 to be a low level, the frequency f of the PWM signal must be less than 1 / (R1*C1). Accordingly, the frequency f of the PWM signal output by the logic circuit 30 is set to be less than 1 / (R1*C1).

[0050] Another PWM signal enters the second oscillator 21. According to the connection relationship of the second oscillator 21, the RD of the second oscillator 21 is high, and A is low. Referring to Table 1, when the RD of the second oscillator 21 is high and A is low, when a rising edge occurs at the B port, the Q port outputs a high level for a duration set by the second resistor R2 and the second capacitor C2. After the high level output lasts for a duration (R2*C2), the Q port output changes to a low level. Thus, when the interval time t≥R2*C2 between rising edges at the B port of the second oscillator 21, the output of the Q port remains low. The Q port of the second oscillator 21 remains low, and referring to Table 2, the Q port of the second flip-flop 22 remains low. When the Q port of the second flip-flop 22 remains low, the output of the logic circuit 30 remains constant high. That is to say, the interval time 1 / t of the rising edge of the B port of the second oscillator 21 is ≤ 1 / (R2*C2), and the output of the logic circuit 30 is constantly at a high level. If the output of the logic circuit 30 is to be a low level, the frequency f of the PWM signal must be greater than 1 / (R2*C2). Accordingly, the frequency f of the PWM signal output by the logic circuit 30 is set to be greater than 1 / (R2*C2).

[0051] As can be seen from this, the output of logic circuit 30 remains constant at a low level only when the frequency of the high-voltage PWM signal is within the preset frequency range. If the control signal frequency is abnormal, the output of logic circuit 30 remains constant at a high level. In other words, logic circuit 30 only allows PWM signals with a frequency range within (1 / (R2*C2), 1 / (R1*C1)) to serve as control signals on the high-voltage side of the signal transmission path. This improves the anti-interference capability of the signal transmission path, suppresses interference with the control signal from frequency signals outside the preset frequency range, and reduces interference from single-level control signals, such as normally low and normally high, in the signal transmission path. This allows the control signal to meet the requirements of high-voltage and high-current control applications. Furthermore, by adjusting first resistor R1, first capacitor C1, second resistor R2, and second capacitor C2, the preset frequency range can be flexibly set.

[0052] An embodiment of the present invention further provides a motor controller, Figure 4 This is a schematic diagram of the structure of a motor controller provided by an embodiment of the present invention, which can be applied to new energy vehicles. Figure 4 As shown, the motor controller includes a PWM signal selection circuit as described in any of the above technical solutions ( Figure 4, the PWM signal selection circuit is marked as 300), the control module 100 and the isolation circuit 200; the control module 100 is used to generate a PWM signal; the isolation circuit 200 is connected to the control module 100, and the isolation circuit 200 is used to isolate the PWM signal; the isolation circuit 200 is connected to the PWM signal selection circuit 300, and the isolation circuit 200 is used to transmit the isolated PWM signal to the PWM signal selection circuit 300.

[0053] As a possible implementation of the present application, the control module can be a low-voltage single-chip microcomputer, and the isolation circuit includes a digital isolator; the input end of the digital isolator is connected to the output end of the control module; the output end of the digital isolator is connected to the input end of the first frequency selection circuit, and to the input end of the second frequency selection circuit.

[0054] In the present application, the control module on the low-voltage side generates and sends a PWM signal to the isolation circuit. The isolation circuit outputs a high-voltage PWM signal to the PWM signal selection circuit. The high-voltage PWM signal is selected by the PWM signal selection circuit for anti-interference performance. The PWM signal selection circuit then outputs a control signal within a preset frequency range to the actuator. In other words, the present application provides a PWM signal selection circuit based on the current signal transmission path that only reduces emission and conduction coupling interference for control signals at the structural design or layout level. The PWM signal selection circuit selects the PWM signal in the signal transmission path for anti-interference performance, and ultimately provides the control signal within the preset frequency range to the actuator, thereby improving the anti-interference capability of the signal transmission path, suppressing interference of frequency signals outside the preset frequency range on the control signal, and reducing interference of single-level control signals such as normally low and normally high in the signal transmission path, thereby improving the stability and reliability of the motor controller operation.

[0055] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A PWM signal selection circuit, characterized in that: include: a first frequency selection circuit, a second frequency selection circuit, and a logic circuit; The first frequency selection circuit includes an input terminal and an output terminal, wherein the input terminal of the first frequency selection circuit is used to input a PWM signal; the first frequency selection circuit is used to select a PWM signal having a frequency less than or equal to an upper limit among the PWM signals and output the signal from the output terminal of the first frequency selection circuit; The second frequency selection circuit includes an input terminal and an output terminal, wherein the input terminal of the second frequency selection circuit is used to input the PWM signal; the second frequency selection circuit is used to select a PWM signal having a frequency greater than or equal to a lower limit among the PWM signals and output the signal from the output terminal of the second frequency selection circuit; The logic circuit includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the logic circuit is connected to the output terminal of the first frequency selection circuit, and the second input terminal of the logic circuit is connected to the output terminal of the second frequency selection circuit; the logic circuit is configured to select the PWM signal within a preset frequency range from the PWM signal and output the selected PWM signal from the output terminal of the logic circuit; wherein the preset frequency range is between the upper frequency limit and the lower frequency limit; The first frequency selection circuit includes a first oscillator, a first trigger, a first resistor and a first capacitor; The second frequency selection circuit includes a second oscillator, a second trigger, a second resistor and a second capacitor; The first input terminal of the first oscillator is connected to the input terminal of the first frequency selection circuit, the second input terminal of the first oscillator is connected to the power signal, the third input terminal of the first oscillator is connected to the power signal through the first resistor, and the third input terminal of the first oscillator is grounded through the first capacitor; a first input terminal of the second oscillator connected to an input terminal of the second frequency selection circuit, a second input terminal of the second oscillator connected to the power signal, a third input terminal of the second oscillator connected to the power signal via the second resistor, and a third input terminal of the second oscillator connected to ground via the second capacitor; A first input terminal of the first trigger is connected to the output terminal of the first oscillator, a second input terminal of the first trigger is connected to the first input terminal of the first oscillator, a third input terminal of the first trigger is connected to a fourth input terminal and then receives the power signal, and an output terminal of the first trigger is connected to the output terminal of the first frequency selection circuit; The first input terminal of the second trigger is connected to the fourth input terminal of the first trigger, the second input terminal of the second trigger is connected to the second input terminal of the first trigger, the third input terminal of the second trigger is connected to the fourth input terminal and then connected to the output terminal of the second oscillator, and the output terminal of the second trigger is connected to the output terminal of the second frequency selection circuit; The PWM signal selection circuit is arranged in a signal transmission path from the low-voltage side to the high-voltage side.

2. The PWM signal selection circuit according to claim 1, wherein: The upper limit frequency f1 is determined by the first resistor R1 and the first capacitor C1, and f1=1 / (R1*C1).

3. The PWM signal selection circuit according to claim 1, wherein: The lower limit frequency f2 is determined by the second resistor R2 and the second capacitor C2, and f2=1 / (R2*C2).

4. The PWM signal selection circuit according to claim 1, wherein: The logic circuit includes a NAND gate; The first input end of the NAND gate serves as the first input end of the logic circuit, the second input end of the NAND gate serves as the second input end of the logic circuit, and the output end of the NAND gate serves as the output end of the logic circuit.

5. The PWM signal selection circuit according to claim 1, wherein: The first trigger and / or the second trigger is a D-type trigger.

6. The PWM signal selection circuit according to claim 1, wherein: The first oscillator and / or the second oscillator is a monostable multivibrator.

7. A motor controller, characterized in that: comprising the PWM signal selection circuit, control module and isolation circuit according to any one of claims 1 to 6; The control module is used to generate the PWM signal; The isolation circuit is connected to the control module, and is used to isolate the PWM signal; the isolation circuit is connected to the PWM signal selection circuit, and is used to transmit the isolated PWM signal to the PWM signal selection circuit.

8. The motor controller according to claim 7, characterized in that: The isolation circuit includes a digital isolator; The input end of the digital isolator is connected to the output end of the control module; the output end of the digital isolator is connected to the input end of the first frequency selection circuit and the input end of the second frequency selection circuit.

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