Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device with good reliability. A semiconductor device including a transistor, the transistor comprising: a first insulator; a second insulator; a first oxide; a second oxide; a third oxide; a first conductor and a second conductor; a third insulator; a third conductor; a fourth insulator; and a fifth insulator. Openings reaching the second oxide are provided in the fourth insulator and the fifth insulator, and a third oxide, a third insulator, and a third conductor are sequentially provided from one side of the inner wall of the opening in a manner of embedding the opening. In the channel length direction of the transistor, at least a part of the fourth insulator in a region where the fourth insulator does not overlap with the second oxide contacts the first insulator. In the channel width direction of the transistor, at least a part of the third oxide in a region where the third oxide does not overlap with the second oxide contacts the first insulator.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Further, one aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that, in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, or storage devices are also one aspect of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Background Art

[0004] As a semiconductor thin film that can be applied to transistors, silicon-based semiconductor materials are well-known. In addition, as other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, it is known that in addition to unit metal oxides such as indium oxide and zinc oxide, there are also multi-metal oxides. Among the multi-metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0005] Through research on IGZO, in oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been discovered (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Non-Patent Documents 4 and 5 disclose that even in an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure, there are minute crystals.

[0006] A transistor using IGZO for the active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays that utilize this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] [Prior Art Documents]

[0008] [Non-Patent Literature]

[0009] [Non-Patent Literature 1] S.Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186

[0010] [Non-Patent Literature 2] S.Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10

[0011] [Non-Patent Literature 3] S.Ito et al., “The Proceedings of AM-FPD’13 Digest of Technical Papers”, 2013, p.151-154

[0012] [Non-Patent Literature 4] S.Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022

[0013] [Non-Patent Literature 5] S.Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p.155-164

[0014] [Non-Patent Literature 6] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7

[0015] [Non-Patent Literature 7] S.Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217

[0016] [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626 - 629 Summary of the Invention

[0017] Technical Problem to be Solved by the Invention

[0018] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Additionally, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high-frequency characteristics. Additionally, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good reliability. Additionally, one of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Additionally, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Additionally, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0019] One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of storing data for a long period. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a fast information writing speed. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a high degree of design freedom. One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device.

[0020] Note that the above description of the purposes does not preclude the existence of other purposes. Furthermore, one embodiment of the present invention does not need to achieve all of the above purposes. Additionally, purposes other than these can be clearly understood from the descriptions in the specification, drawings, claims, etc., and purposes other than the above can be derived from the descriptions in the specification, drawings, claims, etc.

[0021] Means for Solving the Technical Problem

[0022] One aspect of the present invention is a semiconductor device including a transistor. The transistor includes: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a second oxide on the first oxide; a third oxide on the second oxide; a first conductor and a second conductor on the second oxide; a third insulator on the third oxide; a third conductor on the third insulator; a fourth insulator on the first conductor and the second conductor; and a fifth insulator on the fourth insulator. Among them, an opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide is provided so as to cover the inner wall of the opening. The third insulator is provided so as to cover the inner wall of the opening with the third oxide interposed therebetween. The third conductor is provided so as to be embedded in the opening with the third oxide and the third insulator interposed therebetween. In the channel length direction of the transistor, at least a part of the fourth insulator in a region where the fourth insulator does not overlap with the second oxide is in contact with the first insulator. Based on the bottom surface height of the first insulator in the channel width direction of the transistor, the bottom surface height of the third conductor in a region where the third conductor does not overlap with the second oxide is lower than the bottom surface height of the second oxide. In the channel width direction of the transistor, at least a part of the third oxide in a region where the third oxide does not overlap with the second oxide is in contact with the first insulator.

[0023] In the above semiconductor device, preferably, the third oxide has a stacked structure including a first layer and a second layer. The first layer is in contact with the second oxide and the fifth insulator, and the second layer is provided between the first layer and the third insulator. In addition, the crystallinity of the second layer is preferably higher than that of the first layer. In addition, preferably, both the first layer and the second layer contain In, element M (M is Al, Ga, Y, or Sn), and Zn, and the atomic ratio of In in the constituent elements of the second layer is less than the atomic ratio of In in the constituent elements of the first layer.

[0024] In addition, another aspect of the present invention is a semiconductor device including a transistor, where the transistor includes: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a second oxide on the first oxide; a third oxide on the second oxide; a third insulator on the third oxide; a conductor on the third insulator; a fourth insulator in contact with at least a part of the third oxide, at least a part of the top surface of the second oxide, at least a part of the side surface of the second oxide, at least a part of the side surface of the first oxide, at least a part of the side surface of the second insulator, and at least a part of the first insulator; a fifth insulator on the fourth insulator; and a sixth insulator in contact with at least a part of the top surface of the third oxide, at least a part of the top surface of the third insulator, at least a part of the top surface of the conductor, and at least a part of the top surface of the fifth insulator. The second oxide includes a first region, a second region, and a third region located between the first region and the second region. The resistance of the first region and the second region is lower than that of the third region. The conductor is disposed above the third region in a manner overlapping the third region. A part of the third oxide and a part of the third insulator are disposed between the side surface of the conductor and the side surface of the fifth insulator. The fourth insulator has a region in contact with the first region and the second region. In the channel width direction of the transistor, based on the bottom surface height of the first insulator, the bottom surface height of the conductor in the region where the conductor does not overlap with the second oxide is lower than the bottom surface height of the second oxide. In the channel width direction of the transistor, at least a part of the third oxide in the region where the third oxide does not overlap with the second oxide is in contact with the first insulator.

[0025] In the above semiconductor device, the first region and the second region preferably contain phosphorus or boron.

[0026] In addition, in the above semiconductor device, it is preferred that the first region and the second region contain more oxygen defects than the third region.

[0027] In addition, in the above semiconductor device, it is preferred that the fourth insulator has a stacked structure including a third layer and a fourth layer, preferably the third layer is in contact with the first insulator, and preferably the fourth layer is in contact with the fifth insulator. In addition, the third layer preferably contains silicon oxide, and the fourth layer preferably contains aluminum oxide.

[0028] In addition, in the above semiconductor device, preferably, the third oxide has a stacked structure including a first layer and a second layer, the first layer is in contact with the second oxide and the fifth insulator, and the second layer is disposed between the first layer and the third insulator. In addition, it is preferred that both the first layer and the second layer contain In, element M (M is Al, Ga, Y, or Sn), and Zn, and preferably the atomic ratio of In to element M in the second layer is less than the atomic ratio of In to element M in the first layer.

[0029] Advantages of the Invention

[0030] According to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with high-frequency characteristics can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Additionally, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0031] Furthermore, a semiconductor device capable of retaining data for a long period can be provided. Additionally, a semiconductor device with a fast data writing speed can be provided. Additionally, a semiconductor device with a high degree of design freedom can be provided. Additionally, a semiconductor device capable of suppressing power consumption can be provided. Additionally, a novel semiconductor device can be provided.

[0032] Note that the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have all of the above effects. In addition, effects other than these can be clearly understood from the descriptions in the specification, drawings, claims, etc., and effects other than the above can be derived from the descriptions in the specification, drawings, claims, etc.

[0033] Brief Description of the Drawings

[0034] [Fig. 1] is a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0035] Figure 2 is a perspective view of a semiconductor device according to one aspect of the present invention.

[0036] [Fig. 3] is a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0037] [Fig. 4] is a top view and a cross-sectional view showing a manufacturing method of a semiconductor device according to one aspect of the present invention.

[0038] [Fig. 5] is a top view and a cross-sectional view showing a manufacturing method of a semiconductor device according to one aspect of the present invention.

[0039] [Fig. 6] is a top view and a cross-sectional view showing a manufacturing method of a semiconductor device according to one aspect of the present invention.

[0040] [Fig. 7] is a top view and a cross-sectional view showing a manufacturing method of a semiconductor device according to one aspect of the present invention.

[0041] ​[Fig. 8] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0042] [Fig. 9] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0043] [Fig. 10] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0044] [Fig. 11] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0045] [Fig. 12] is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0046] [Fig. 13] is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0047] [Fig. 14] is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0048] [Fig. 15] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0049] [Fig. 16] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0050] [Fig. 17] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0051] [Fig. 18] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0052] [Fig. 19] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0053] [Fig. 20] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0054] [Fig. 21] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0055] [Fig. 22] is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0056] Figure 23 is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0057] ​​Figure 24 is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0058] Figure 25 is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0059] Figure 26 is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0060] [FIG. 27] is a block diagram showing a structural example of a storage device according to one embodiment of the present invention.

[0061] [FIG. 28] is a circuit diagram showing a structural example of a storage device according to one embodiment of the present invention.

[0062] [FIG. 29] is a schematic diagram of a semiconductor device according to one embodiment of the present invention.

[0063] [FIG. 30] is a schematic diagram of a storage device according to one embodiment of the present invention.

[0064] [FIG. 31] is a diagram showing an electronic device according to one embodiment of the present invention.

[0065] Embodiments of the Invention

[0066] Hereinafter, embodiments will be described with reference to the accompanying drawings. However, those of ordinary skill in the art can easily understand the fact that the embodiments can be implemented in multiple different forms, and the ways and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments.

[0067] In the accompanying drawings, for the sake of clear explanation, the sizes, layer thicknesses, or regions are sometimes exaggerated. Therefore, the present invention is not necessarily limited to the above dimensions. In addition, in the accompanying drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or values shown in the drawings. For example, in actual manufacturing processes, sometimes layers or resist masks are unintentionally thinned due to processes such as etching, but are sometimes omitted from the drawings for the sake of easy understanding. In addition, in the accompanying drawings, the same reference numerals are sometimes used commonly between different drawings to represent the same parts or parts having the same functions, and the repeated description thereof is omitted. In addition, when representing parts having the same function, the same hatching is sometimes used without particularly attaching reference numerals.

[0068] ​​In addition, particularly in a top view (also referred to as a plan view) or a perspective view, etc., for the convenience of understanding the invention, sometimes the description of some constituent elements is omitted. In addition, sometimes the description of some hidden lines, etc., is omitted.

[0069] In addition, in this specification, etc., for convenience, ordinal numbers such as first, second, etc. are added, and they do not indicate the process order or the stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third", etc. for explanation. In addition, the ordinal numbers described in this specification, etc., sometimes do not match the ordinal numbers used to specify one aspect of the present invention.

[0070] In this specification, etc., for convenience, words and phrases indicating configuration such as "upper" and "lower" are used to describe the positional relationship of the constituent elements with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the directions describing each constituent element. Therefore, it is not limited to the words and phrases described in this specification, and can be appropriately changed according to the situation.

[0071] For example, in this specification, etc., when it is clearly described that "X is connected to Y", it means the following situations: X is electrically connected to Y; X is functionally connected to Y; X is directly connected to Y. Therefore, it is not limited to the specified connection relationship (for example, the connection relationship shown in the drawings or in the text, etc.), and connection relationships other than those shown in the drawings or in the text are also included in the content disclosed in the drawings or in the text.

[0072] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0073] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., the channel formation region refers to the region where current mainly flows.

[0074] In addition, in the case of using transistors with different polarities or when the current direction changes during the operation of the circuit, etc., the functions of the source and the drain sometimes switch with each other. Therefore, in this specification, etc., sometimes the source and the drain can be interchanged with each other.

[0075] Note that the channel length refers to, for example, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap in the top view of the transistor or in the channel formation region. Additionally, in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length is any value, maximum value, minimum value, or average value in the channel formation region.

[0076] The channel width refers to, for example, the length in the direction of the channel formation region perpendicular to the channel length direction in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap in the top view of the transistor or in the channel formation region. Additionally, in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width is any value, maximum value, minimum value, or average value in the channel formation region.

[0077] In this specification and the like, depending on the structure of the transistor, the actual channel width (hereinafter, also referred to as the "effective channel width") in the region where the channel is formed may be different from the channel width shown in the top view of the transistor (hereinafter, also referred to as the "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, sometimes the effective channel width is greater than the apparent channel width, so its influence cannot be ignored. For example, in a miniaturized transistor where the gate electrode covers the side of the semiconductor, sometimes the proportion of the channel formation region formed on the side of the semiconductor increases. In this case, the effective channel width is greater than the apparent channel width.

[0078] In this case, it is sometimes difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0079] In this specification, when simply described as "channel width", it sometimes refers to the apparent channel width. Or, in this specification, when simply described as "channel width", it sometimes refers to the effective channel width. Note that by analyzing cross-sectional TEM images and the like, values such as the channel length, channel width, effective channel width, and apparent channel width can be determined.

[0080] Note that impurities in a semiconductor refer to elements other than the main component of the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When impurities are included, for example, an increase in the density of defect states of the semiconductor or a decrease in crystallinity may sometimes occur. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, for example, there are Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, water sometimes acts as an impurity. In addition, when the semiconductor is an oxide semiconductor, for example, the generation of oxygen defects may sometimes occur due to the entry of impurities. In addition, when the semiconductor is silicon, as impurities that change the characteristics of the semiconductor, for example, there are oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0081] Note that in this specification and the like, silicon oxynitride refers to a substance in which the oxygen content is greater than the nitrogen content. In addition, silicon nitride oxide refers to a substance in which the nitrogen content is greater than the oxygen content.

[0082] In addition, in this specification and the like, "insulator" can be referred to as "insulating film" or "insulating layer". In addition, "conductor" can be referred to as "conductive film" or "conductive layer". In addition, "semiconductor" can be referred to as "semiconductor film" or "semiconductor layer".

[0083] In this specification and the like, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less. "Substantially parallel" means a state in which the angle formed by two straight lines is -30° or more and 30° or less. In addition, "perpendicular" means a state in which the angle between two straight lines is 80° or more and 100° or less. Therefore, it also includes a state in which the angle is 85° or more and 95° or less. "Substantially perpendicular" means a state in which the angle formed by two straight lines is 60° or more and 120° or less.

[0084] Note that in this specification, a barrier film refers to a film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. When the barrier film has conductivity, it is sometimes referred to as a conductive barrier film.

[0085] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which may also be abbreviated as OS), etc. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing an oxide or an oxide semiconductor.

[0086] Note that in this specification and the like, normally off means that the current per channel width of 1 μm flowing through the transistor when no potential is applied to the gate or a ground potential is applied to the gate is 1×10 -20 A or less at room temperature, 1×10 -18 A or less at 85 °C, or 1×10 -16 A or less at 125 °C.

[0087] (Embodiment 1)

[0088] An example of a semiconductor device including a transistor 200 according to one aspect of the present invention will be described below.

[0089] 〈Structural Example 1 of Semiconductor Device〉

[0090] Figures 1A to 1C are a plan view and a cross-sectional view of a transistor 200 and the periphery of the transistor 200 according to one aspect of the present invention.

[0091] Figure 1A is a plan view of a semiconductor device including a transistor 200. In addition, Figure 1B and Figure 1C are cross-sectional views of the semiconductor device. Here, Figure 1B is a cross-sectional view of the portion shown by the dotted line A1 - A2 along Figure 1A , and is also a cross-sectional view in the channel length direction of the transistor 200. In addition, Figure 1C is a cross-sectional view of the portion shown by the dotted line A3 - A4 along Figure 1A , and is also a cross-sectional view in the channel width direction of the transistor 200. Note that Figure 1A some constituent elements are omitted in the plan view of

[0092] for clarity. Figure 2 is a perspective view of a transistor 200 according to one aspect of the present invention. Note that Figure 2 some constituent elements are omitted in the perspective view of

[0093] One embodiment of the semiconductor device of the present invention includes a transistor 200, an insulator 214 used as an interlayer film, insulators 280, 274, and 281. In addition, the semiconductor device further includes conductors 240 (conductors 240a and 240b) that are electrically connected to the transistor 200 and used as plugs. In addition, insulators 241 (insulators 241a and 241b) are provided in contact with the sides of the conductors 240 used as plugs.

[0094] In addition, an insulator 241 is provided in contact with the side walls of the openings of the insulators 254, 280, 274, and 281, and a first conductor of the conductor 240 is provided in contact with its side, and a second conductor of the conductor 240 is provided inside. Here, the height of the top surface of the conductor 240 may be substantially the same as the height of the top surface of the insulator 281. In addition, a structure in which the first conductor and the second conductor of the conductor 240 are stacked on the transistor 200 is shown, but the present invention is not limited thereto. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a stacked structure, numbers may sometimes be assigned in the order of formation for distinction.

[0095] [Transistor 200]

[0096] As shown in FIG. 1, the transistor 200 includes an insulator 216 provided on a substrate (not shown), a conductor 205 provided so as to be embedded in the insulator 216, an insulator 222 provided on the insulator 216 and the conductor 205, an insulator 224 provided on the insulator 222, oxides 230 (oxides 230a, 230b, and 230c) provided on the insulator 224, an insulator 250 provided on the oxides 230, conductors 260 (conductors 260a and 260b) provided on the insulator 250, conductors 242a and 242b in contact with a part of the top surface of the oxide 230b, and an insulator 254 disposed in contact with a part of the top surface of the insulator 222, the sides of the insulator 224, the sides of the oxide 230a, the sides of the oxide 230b, the sides of the conductor 242a, the top surface of the conductor 242a, the sides of the conductor 242b, and the top surface of the conductor 242b.

[0097] The conductor 260 is used as the gate electrode of the transistor 200, and the conductors 242a and 242b are used as the source electrode or the drain electrode. In the transistor 200, the conductor 260 used as the gate electrode is formed self-alignedly in such a manner as to be embedded in the opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be surely arranged in the region between the conductors 242a and 242b without alignment.

[0098] The conductor 260 preferably includes a conductor 260a and a conductor 260b provided on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom surface and the side surface of the conductor 260b. In addition, as Figure 1B shown, the top surface of the conductor 260 is substantially flush with the top surface of the insulator 250 and the top surface of the oxide 230c. Note that in the transistor 200, the conductor 260 has a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

[0099] The insulators 222, 254, and 274 preferably have a function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules). In addition, the insulators 222, 254, and 274 preferably have a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). For example, the permeability of one or both of hydrogen and oxygen in the insulators 222, 254, and 274 is preferably lower than that of the insulator 224. The permeability of one or both of hydrogen and oxygen in the insulators 222, 254, and 274 is preferably lower than that of the insulator 250. The permeability of one or both of hydrogen and oxygen in the insulators 222, 254, and 274 is preferably lower than that of the insulator 280.

[0100] The oxide 230 preferably includes an oxide 230a provided on the insulator 224, an oxide 230b provided on the oxide 230a, and an oxide 230c provided on the oxide 230b and at least a part of which is in contact with the top surface of the oxide 230b.

[0101] Note that in the transistor 200, three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof, but the present invention is not limited thereto. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided.

[0102] In addition, preferably, in the transistor 200, a metal oxide (hereinafter sometimes referred to as an oxide semiconductor) to be used as a semiconductor is used for the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) including the channel formation region.

[0103] Since the transistor 200 using an oxide semiconductor for the channel formation region has an extremely small leakage current (off-state current) in the non-conducting state, a low-power semiconductor device can be provided. In addition, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 constituting a highly integrated semiconductor device.

[0104] For example, as the oxide 230, a metal oxide such as In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.) is preferably used. In particular, as the element M, aluminum, gallium, yttrium, or tin can be used. In addition, as the oxide 230, In-Ga oxide, In-Zn oxide, or Ga-Zn oxide can also be used.

[0105] In addition, in a transistor using an oxide semiconductor, if impurities and oxygen defects exist in the channel formation region of the oxide semiconductor, the electrical characteristics are likely to vary, and sometimes the reliability is reduced. In addition, when the channel formation region in the oxide semiconductor contains oxygen defects, the transistor tends to have normally-on characteristics. Therefore, it is preferable to reduce the oxygen defects in the channel formation region as much as possible. For example, oxygen can be supplied to the oxide 230 through the insulator 250 or the like to fill the oxygen defects. Thereby, a transistor can be provided in which the electrical characteristics are stable with suppressed electrical characteristic variations and the reliability is improved.

[0106] In addition, when an element included in the conductor 242 (conductor 242a and conductor 242b) provided in contact with the oxide 230 and used as a source electrode or a drain electrode has a function of absorbing oxygen of the oxide 230, a low-resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230. In this case, in the low-resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) entering the oxygen defects are used as donors, and the carrier density increases. In addition, hereinafter, hydrogen entering the oxygen defects is sometimes referred to as V O H.

[0107] In addition, Figure 3A shows Figure 1B an enlarged view of a partial region of the transistor 200 shown. As Figure 3AAs shown, a conductor 242 is provided in contact with the oxide 230, and regions 243 (region 243a and region 243b), which are low-resistance regions, are sometimes formed at the interface between the oxide 230 and the conductor 242 and in its vicinity. The oxide 230 includes a region 234 that serves as a channel formation region of the transistor 200 and a region 231 (region 231a and region 231b) that includes at least a part of the region 243 and serves as a source region or a drain region. Note that in the following drawings, even if the region 243 is not shown in an enlarged view or the like, the same region 243 as described above is sometimes formed.

[0108] In addition, although an example is shown in which the regions 243a and 243b are provided so as to diffuse in the depth direction near the conductor 242 of the oxide 230b, the present invention is not limited thereto. The regions 243a and 243b may be appropriately formed according to the required electrical characteristics of the transistor. In the oxide 230, it is sometimes difficult to clearly observe the boundaries of the respective regions. The concentration of the elements detected in each region is not limited to changing stepwise for each region, but may also change gradually (also referred to as gradation) in each region.

[0109] In addition, as Figure 1B shown, the insulator 254 preferably contacts the top surfaces of the conductors 242a and 242b, the side surfaces of the conductors 242a and 242b other than the side surfaces facing each other, the side surfaces of the oxides 230a and 230b, and a part of the top surface of the insulator 224 and the side surface of the insulator 222. By adopting the above structure, the insulator 280 is separated from the insulator 224, the oxides 230a, and 230b by the insulator 254. Thereby, entry of impurities such as hydrogen into the insulator 224, the oxides 230a, and 230b in the insulator 280 and the like can be suppressed.

[0110] The insulator 274 contacts the top surfaces of each of the conductor 260, the insulator 250, and the oxide 230c. In addition, as Figure 3A shown, in the transistor 200 of one aspect of the present invention, the insulator 274 contacts the insulator 250. By adopting such a structure, entry of impurities such as hydrogen into the insulator 250 in the insulator 281 and the like can be suppressed. Thereby, negative effects on the electrical characteristics of the transistor and the reliability of the transistor can be suppressed.

[0111] In addition, as Figure 3AAs shown, the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 is sometimes lower than the height of each of the top surfaces of the conductors 242a and 242b, based on the bottom surface of the insulator 224. For example, the difference between the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 and the height of each of the top surfaces of the conductors 242a and 242b is 0 nm or more and 30 nm or more and 15 nm or less.

[0112] in addition, Figure 3B Show Figure 1C FIG. 2 is an enlarged view of a portion of the transistor 200 shown in FIG. Figure 1C and Figure 3B As shown, in the channel width direction of the transistor 200, with the bottom surface of the insulator 222 as a reference, the bottom surface height of the conductor 260 in the region where the oxide 260 and the oxide 230b do not overlap is preferably lower than the bottom surface height of the oxide 230b. By adopting a structure in which the conductor 260 used as a gate electrode covers the side and top surfaces of the oxide 230b in the channel formation region through the oxide 230c and the insulator 250, the structure makes it easy for the electric field of the conductor 260 to act on the entire region 234 of the oxide 230b. As a result, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is recorded as T2, and T2 is greater than 0nm and less than 100nm, preferably greater than 3nm and less than 50nm, and more preferably greater than 5nm and less than 20nm.

[0113] In addition, if Figure 3B As shown, in the channel width direction of the transistor 200, at least a portion of the oxide 230c in the region that does not overlap with the oxide 230b, the oxide 230a, and the insulator 224 is preferably in contact with the insulator 222. By adopting this structure, it is possible to prevent the oxygen in the oxide 230c from diffusing to the outside of the transistor 200 through the insulator 224. Alternatively, it is possible to prevent the oxygen in the oxide 230b and the oxide 230a from diffusing to the outside of the transistor 200 through the insulator 224. Alternatively, by reducing the area of ​​the insulator 224, the amount of oxygen entering the insulator 224 is reduced, thereby suppressing the reduction in the amount of oxygen supplied to the oxide 230. As a result, the oxygen in the oxide 230c can be efficiently supplied to the oxide 230b and the oxide 230a, thereby suppressing the low resistance of the oxide 230 in the region 234. As a result, it is possible to suppress the variation of the electrical characteristics of the transistor and achieve stable electrical characteristics while improving reliability.

[0114] Alternatively, by adopting the above structure, impurities such as hydrogen in the insulator 224 or the like can be suppressed from mixing into the oxide 230. That is to say, the low-resistivity of the oxide 230 can be suppressed. As a result, while suppressing the variation of the electrical characteristics of the transistor to achieve stable electrical characteristics, the reliability can be improved. In addition, this structure can be formed by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a.

[0115] In addition, by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a, as Figure 1C shown, in the channel width direction of the transistor 200, with the bottom surface of the insulator 222 as a reference, it is easy to make the bottom surface height of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 lower than the bottom surface height of the oxide 230b. As a result, the on-state current of the transistor 200 can be increased, thereby improving the frequency characteristics.

[0116] By adopting the above structure, a semiconductor device including a transistor with a large on-state current can be provided. In addition, a semiconductor device including a transistor with high frequency characteristics can be provided. In addition, a semiconductor device in which the variation of electrical characteristics is suppressed to have stable electrical characteristics while the reliability is improved can be provided. In addition, a semiconductor device including a transistor with a low off-state current can be provided.

[0117] The detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention is shown below.

[0118] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided in a manner of being embedded in the insulator 214 and the insulator 216. Here, it is preferable that the top surface of the conductor 205 has good flatness. For example, the average surface roughness (Ra) of the top surface of the conductor 205 can be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. As a result, the insulator 224 formed on the conductor 205 can have good flatness, thereby improving the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c.

[0119] Here, the conductor 260 is sometimes used as a first gate (also called a top gate) electrode. In addition, the conductor 205 is sometimes used as a second gate electrode. In this case, by independently changing the potential supplied to the conductor 205 without interlocking it with the potential supplied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by supplying a negative potential to the conductor 205, the Vth of the transistor 200 can be made larger and the off-state current can be reduced. Therefore, compared with when a negative potential is not applied to the conductor 205, when a negative potential is applied to the conductor 205, the drain current when the potential supplied to the conductor 260 is 0V can be reduced.

[0120] In addition, if Figure 1A As shown in FIG. 1 , the conductor 205 is preferably larger than the channel formation region in the oxide 230. In particular, Figure 1C As shown, the conductor 205 preferably extends to a region outside the end of the oxide 230 intersecting the channel width direction. That is, the conductor 205 and the conductor 260 preferably overlap with the insulator outside the side surface of the oxide 230 in the channel width direction.

[0121] By having the above structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, the structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0122] In addition, if Figure 1C As shown, the conductor 205 is extended to be used as wiring. However, the present invention is not limited to this, and a conductor used as wiring may be provided under the conductor 205. In addition, it is not necessary to provide a conductor 205 in each transistor. For example, the conductor 205 may be used in common in a plurality of transistors.

[0123] In addition, a conductive material mainly composed of tungsten, copper or aluminum is preferably used as the conductor 205. In the drawings, the conductor 205 is shown as a single layer, but the conductor 205 may have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials may be used.

[0124] In addition, a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not easily permeable to the above impurities) may be used under the conductor 205. In addition, a conductor having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not easily permeable to the above oxygen) is preferably used. In this specification, the "function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0125] In addition, when a conductor having a function of suppressing the diffusion of oxygen is used under the conductor 205, a decrease in conductivity due to oxidation of the conductor 205 can be suppressed. As the conductor having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, a single layer or a stack of the above conductive materials can be used as the conductor used under the conductor 205.

[0126] The insulator 214 is preferably used as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. Therefore, an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not easily permeable to the above impurities) is preferably used as the insulator 214. In addition, an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not easily permeable to the above oxygen) is preferably used.

[0127] For example, it is preferable to use alumina, silicon nitride, etc. as the insulator 214. Thereby, the diffusion of impurities such as water and hydrogen from the side closer to the substrate than the insulator 214 to the transistor 200 side can be suppressed. In addition, the diffusion of oxygen contained in the insulator 224, etc. to the side closer to the substrate than the insulator 214 can be suppressed.

[0128] In addition, the dielectric constants of the insulators 216, 280, and 281 used as the interlayer films are preferably lower than that of the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 216, 280, and 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon- and nitrogen-added silicon oxide, silicon oxide having pores, etc. are appropriately used.

[0129] In addition, the insulator 216 may also have a stacked structure. For example, a structure may also be adopted in which an insulator identical to the insulator 214 is provided in at least a portion of the insulator 216 that is in contact with the side surface of the conductor 205. By adopting such a structure, oxidation of the conductor 205 by oxygen contained in the insulator 216 can be suppressed. Alternatively, absorption of oxygen in the insulator 216 by the conductor 205 can be suppressed.

[0130] The insulators 222 and 224 are used as gate insulators.

[0131] Here, in the insulator 224 in contact with the oxide 230, it is preferable to remove oxygen by heating. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, etc. may be appropriately used as the insulator 224. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen defects in the oxide 230 can be reduced, and thus the reliability of the transistor 200 can be improved.

[0132] Specifically, as the insulator 224, an oxide material in which a part of oxygen is removed by heating is preferably used. The oxide film in which oxygen is removed by heating means that the amount of oxygen desorbed in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more of the oxide film. In addition, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0133] The insulator 222 is preferably used as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. For example, the hydrogen permeability of the insulator 222 is preferably lower than that of the insulator 224. By surrounding the insulator 224, the oxide 230, etc. with the insulators 222 and 254, diffusion of impurities such as water and hydrogen from the outside to the insulator 224 and the oxide 230 can be suppressed.

[0134] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (it is not easy for the above-mentioned oxygen to permeate through). For example, the oxygen permeability of the insulator 222 is preferably lower than that of the insulator 224. By making the insulator 222 have a function of suppressing the diffusion of oxygen or impurities, it is possible to reduce the diffusion of oxygen in the oxide 230 to the substrate side, so it is preferable. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen in the insulator 224 and the oxide 230.

[0135] The insulator 222 is preferably an insulator made of an oxide containing one or both of aluminum and hafnium as an insulating material. As the insulator made of an oxide containing one or both of aluminum and hafnium, alumina, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When using such a material to form the insulator 222, the insulator 222 is used as a layer that suppresses the release of oxygen from the oxide 230 or the diffusion of impurities such as hydrogen from the peripheral part of the transistor 200 to the oxide 230. In addition, the insulator 222 is particularly preferably hafnium oxide among the above materials. For example, when the insulator 222 is used as a gate insulating film, by using hafnium oxide as the insulator 222, the interface energy level density can sometimes be reduced compared with the case of using alumina.

[0136] Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may also be added to the above insulator. In addition, the above insulator may be nitrided. It is also possible to stack silicon oxide, silicon oxynitride, or silicon nitride on the above insulator.

[0137] In addition, as the insulator 222, for example, an insulator containing so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba, Sr)TiO3 (BST), etc. may be used in a single layer or a stacked layer. When miniaturizing and highly integrating transistors, due to the thinning of the gate insulator, problems such as leakage current sometimes occur. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0138] In addition, as Figure 1C shown, sometimes the film thickness of the region where the insulator 222 does not overlap with the oxide 230b is thinner than the thickness of the region other than this region. In the insulator 222, the film thickness of the region that does not overlap with the oxide 230b is preferably a thickness that can be used as an etch stop film when forming an opening provided in the insulator 280, etc., or a sufficient thickness that does not expose the surface of the insulator 216 or the conductor 205.

[0139] In addition, the insulators 222 and 224 may also have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being composed of the same material, and may also be a stacked structure formed of different materials. For example, an insulator similar to the insulator 224 may be provided under the insulator 222.

[0140] The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. When the oxide 230a is provided under the oxide 230b, diffusion of impurities from the structure formed under the oxide 230a into the oxide 230b can be suppressed. When the oxide 230c is provided on the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c into the oxide 230b can be suppressed.

[0141] In addition, the oxide 230 preferably has a stacked structure of oxides having different chemical compositions. Specifically, in the metal oxide for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably greater than the atomic ratio of the element M in the constituent elements of the metal oxide for the oxide 230b. In addition, the atomic ratio of the element M to In in the metal oxide for the oxide 230a is preferably greater than the atomic ratio of the element M to In in the metal oxide for the oxide 230b. In addition, the atomic ratio of In to the element M in the metal oxide for the oxide 230b is preferably greater than the atomic ratio of In to the element M in the metal oxide for the oxide 230a. In addition, the oxide 230c may use a metal oxide that can be used for the oxide 230a or the oxide 230b.

[0142] In addition, the oxides 230b and 230c preferably have crystallinity. For example, it is preferable to use the following CAAC-OS (c-axis aligned crystalline oxide semiconductor). Oxides having crystallinity such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen defects). Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Therefore, even when a heat treatment is performed, the oxygen extracted from the oxide 230b can be reduced, so that the transistor 200 is also stable with respect to a high temperature (so-called thermal budget) in the manufacturing process.

[0143] Preferably, the bottom of the conduction band of the oxide 230a and the oxide 230c is closer to the vacuum level than the bottom of the conduction band of the oxide 230b. In other words, the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b. In this case, the oxide 230c preferably uses a metal oxide that can be used for the oxide 230a. Specifically, in the metal oxide used for the oxide 230c, the atomic ratio of the element M in the constituent elements is preferably greater than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230c, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230c.

[0144] In addition, when the oxide 230c has a stacked structure including the oxide 230c1 and the oxide 230c2, it is preferable that the bottom of the conduction band of the oxide 230a and the oxide 230c2 is closer to the vacuum level than the bottom of the conduction band of the oxide 230b and the oxide 230c1. In addition, in other words, the electron affinity of the oxide 230a and the oxide 230c2 is preferably smaller than the electron affinity of the oxide 230b and the oxide 230c1. In this case, the oxide 230c2 preferably uses a metal oxide that can be used for the oxide 230a, and the oxide 230c1 preferably uses a metal oxide that can be used for the oxide 230b.

[0145] Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the bottom of the conduction band changes smoothly. In other words, the above situation can also be expressed as the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c changing continuously or being continuously joined. For this purpose, it is preferable to reduce the density of defect states in the mixed layer formed at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c.

[0146] Specifically, by making the oxide 230a, the oxide 230b, and the oxide 230c contain a common element (as the main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. can be used as the oxide 230a and the oxide 230c. In addition, when the oxide 230c adopts a stacked structure of the oxide 230c1 and the oxide 230c2, for example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide can be used. In other words, as the oxide 230c, a stacked structure of an In-Ga-Zn oxide and an oxide not containing In can also be used.

[0147] Specifically, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or In:Ga:Zn = 1:1:0.5 [atomic ratio] can be used as the oxide 230a. In addition, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] or In:Ga:Zn = 3:1:2 [atomic ratio] can be used as the oxide 230b. In addition, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] can be used as the oxide 230c. In addition, as specific examples in the case where the oxide 230c has a stacked structure, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] and In:Ga:Zn = 1:3:4 [atomic ratio], a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:1 [atomic ratio], a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:5 [atomic ratio], a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] and gallium oxide, etc. can be cited.

[0148] At this time, the main path of the carriers is the oxide 230b. Alternatively, when the oxide 230c has a stacked structure including the oxide 230c1 and the oxide 230c2, sometimes not only the oxide 230b but also the oxide 230c1 may become the main path of the carriers. By making the oxides 230a and 230c have the above structures, the density of defect states at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 200 can obtain a high on-state current and high-frequency characteristics. In addition, when the oxide 230c has a stacked structure, an effect of reducing the density of defect states at the interface between the above-mentioned oxide 230b and oxide 230c and an effect of suppressing the diffusion of constituent elements of the oxide 230c to the insulator 250 side are expected. More specifically, when the oxide 230c has a stacked structure, since an oxide not containing In is located above the stacked structure, the diffusion of In to the insulator 250 side can be suppressed. Since the insulator 250 is used as a gate insulator, when In enters the insulator 250 or the like, the characteristics of the transistor deteriorate. Thus, by making the oxide 230c have a stacked structure, a highly reliable semiconductor device can be provided.

[0149] As the oxide 230, a metal oxide used as an oxide semiconductor is preferably used. For example, as the metal oxide that becomes the region 234, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this way, by using a metal oxide with a relatively wide band gap, the off-state current of the transistor can be reduced. By adopting such a transistor, a low-power semiconductor device can be provided.

[0150] A conductor 242 (conductor 242a and conductor 242b) used as a source electrode and a drain electrode is provided on the oxide 230b. The thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0151] As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements, etc. are preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred.

[0152] The insulator 254, like the insulator 214 and the like, is preferably used as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the insulator 280 side to the transistor 200. For example, the hydrogen permeability of the insulator 254 is preferably lower than that of the insulator 224. Furthermore, as Figure 1B and Figure 1C shown, the insulator 254 preferably contacts the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the oxides 230a and 230b, and the top surface of the insulator 224. By adopting such a structure, the insulator 254 separates the insulator 280 from the insulator 224 and the oxides 230. Thereby, the diffusion of hydrogen contained in the insulator 280 from the top or side surfaces of the conductor 242a, the conductor 242b, the oxides 230a, the oxides 230b, and the insulator 224 to the oxides 230 can be suppressed, so that the transistor 200 can have good electrical characteristics and reliability.

[0153] Furthermore, the insulator 254 also has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (it is not easy for the above-mentioned oxygen to permeate). For example, the oxygen permeability of the insulator 254 is preferably lower than that of the insulator 280 or the insulator 224.

[0154] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region where the insulator 224 contacts the insulator 254. Thereby, oxygen can be supplied from this region to the oxides 230 through the insulator 224. Here, by making the insulator 254 have a function of suppressing the diffusion of oxygen to the upper side, oxygen diffusion from the oxides 230 to the insulator 280 can be prevented. In addition, by making the insulator 222 have a function of suppressing the diffusion of oxygen to the lower side, oxygen diffusion from the oxides 230 to the substrate side can be prevented. In this way, the channel formation region of the oxides 230 is supplied with oxygen. Thereby, the oxygen defects of the oxides 230 can be reduced and the constant turn-on of the transistor can be suppressed.

[0155] As the insulator 254, for example, an insulator containing one or more of aluminum and hafnium can be formed. In addition, as an insulator containing one or both of aluminum and hafnium oxides, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. At this time, the insulator 254 is preferably formed by an atomic layer deposition (ALD: Atomic Layer Deposition) method. Since the ALD method is a film-forming method with good coverage, disconnection and the like due to the unevenness of the insulator 254 can be prevented.

[0156] Thus, by covering the insulator 224 and the oxide 230 with the hydrogen-blocking insulator 254, the insulator 280 is separated from the insulator 224 and the oxide 230. As a result, impurities such as hydrogen can be prevented from mixing in from the outside of the transistor 200, and thus the transistor 200 can have good electrical characteristics and reliability.

[0157] As the insulator 254, for example, an insulator containing aluminum nitride can be used. As the insulator 254, a nitride insulator whose compositional formula satisfies AlNx (x is a real number greater than 0 and 2 or less, and x is preferably greater than 0.5 and 1.5 or less) is preferably used. Therefore, a film with high insulation and high thermal conductivity can be formed, and thus the heat dissipation of the heat generated when driving the transistor 200 can be improved. In addition, as the insulator 254, titanium aluminum nitride, titanium nitride, etc. can also be used. In this case, by using the sputtering method, a film can be formed without using a highly oxidizing gas such as oxygen or ozone as the deposition gas, so this is preferable. In addition, silicon nitride or silicon oxynitride can also be used.

[0158] In addition, the insulator 254 can have a multilayer structure of two or more layers. For example, as the insulator 254, the first layer can be formed by using the sputtering method in an oxygen-containing atmosphere, and then the second layer can be formed by using the ALD method to form a two-layer structure. Since the ALD method is a film-forming method with good coverage, disconnection and the like caused by the unevenness of the first layer can be prevented. When the insulator 254 has a multilayer structure of two or more layers, a multilayer structure composed of different materials can also be adopted. For example, a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride or silicon nitride and an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be adopted. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used.

[0159] The insulator 250 is used as a gate insulator. The insulator 250 is preferably arranged in contact with at least a part of the oxide 230c. As the insulator 250, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferable.

[0160] Similarly to the insulator 224, the insulator 250 is preferably formed of an insulator that releases oxygen by heating. By arranging the insulator that releases oxygen by heating as the insulator 250 in contact with at least a part of the oxide 230c, oxygen can be efficiently supplied to the region 234 of the oxide 230b. Similarly to the insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 250. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0161] In addition, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably inhibits the diffusion of oxygen from the insulator 250 to the conductor 260. By providing the metal oxide that inhibits the diffusion of oxygen, the oxygen diffusing from the insulator 250 to the conductor 260 is inhibited. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be inhibited. In addition, oxidation of the conductor 260 caused by oxygen in the insulator 250 can be inhibited.

[0162] In addition, the above metal oxide is sometimes used as part of a gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, etc. are used for the insulator 250, a metal oxide as a high-k material having a high relative dielectric constant is preferably used as the above metal oxide. By forming a stacked structure of the insulator 250 and the above metal oxide for the gate insulator, a stacked structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0163] In addition, the above metal oxide may also be used as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the above metal oxide. In this case, by forming the conductor 260 using a sputtering method, the resistance value of the above metal oxide can be reduced to make it a conductor. The above conductor may be referred to as an OC (Oxide Conductor) electrode.

[0164] By providing the above metal oxide, the on-state current of the transistor 200 can be increased without reducing the influence of the electric field from the conductor 260. In addition, by maintaining the distance between the conductor 260 and the oxide 230 using the physical thicknesses of the insulator 250 and the above metal oxide, leakage current between the conductor 260 and the oxide 230 can be inhibited. In addition, by providing a stacked structure of the insulator 250 and the above metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted.

[0165] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. which are insulators as oxides containing one or both of aluminum and hafnium are preferably used. In addition, an oxide semiconductor that can be used for the oxide 230 can be used as the above metal oxide by making it have a low resistance.

[0166] Although the conductor 260 is shown as an example of a bilayer structure in FIG. 1, it may also have a single-layer structure or a stacked structure of three or more layers.

[0167] As the conductor 260a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms is preferably used. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferably used.

[0168] In addition, when the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0169] In addition, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, as the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. In addition, the conductor 260b may also have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

[0170] The insulator 280 is preferably provided on the insulator 222, the insulator 224, the oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. are preferably used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is removed by heating.

[0171] In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 280. In addition, the top surface of the insulator 280 may also be flattened.

[0172] The insulator 274 is preferably used as a barrier insulating film for suppressing the diffusion of impurities such as water and hydrogen from above to the insulator 280 in the same manner as the insulator 214 and the like. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. can be used.

[0173] In addition, it is preferable to provide an insulator 281 used as an interlayer film on the insulator 274. Similar to the insulator 224 and the like, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 281.

[0174] In addition, conductors 240a and 240b are disposed in the openings formed in insulator 281, insulator 274, insulator 280, and insulator 254. Conductors 240a and 240b are arranged with conductor 260 therebetween. In addition, the top surfaces of conductors 240a and 240b may be in the same plane as the top surface of insulator 281.

[0175] In addition, insulator 241a is provided in contact with the side walls of the openings of insulator 281, insulator 274, insulator 280, and insulator 254, and a first conductor of conductor 240a is formed in contact with its side surface. Conductor 242a is located at at least a part of the bottom of the opening, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the side walls of the openings of insulator 281, insulator 274, insulator 280, and insulator 254, and a first conductor of conductor 240b is formed in contact with its side surface. Conductor 242b is located at at least a part of the bottom of the opening, and conductor 240b is in contact with conductor 242b.

[0176] Conductors 240a and 240b preferably use a conductive material mainly composed of tungsten, copper, or aluminum. In addition, conductors 240a and 240b may also have a laminated structure.

[0177] When a laminated structure is adopted for conductor 240, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used as the conductor in contact with oxide 230a, oxide 230b, conductor 242, insulator 254, insulator 280, insulator 274, and insulator 281. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. The conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. By using this conductive material, oxygen added to insulator 280 can be prevented from being absorbed into conductors 240a and 240b. In addition, impurities such as water and hydrogen contained in the layer above insulator 281 can be prevented from diffusing into oxide 230 through conductors 240a and 240b.

[0178] As the insulators 241a and 241b, for example, insulators that can be used for the insulator 254 or the like can be used. Since the insulators 241a and 241b are provided in contact with the insulator 254, impurities such as water and hydrogen contained in the insulator 280 or the like can be suppressed from diffusing into the oxide 230 through the conductors 240a and 240b. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b. Further, the insulators 241a and 241b can be formed by an ALD method or a chemical vapor deposition (CVD) method.

[0179] Although not shown, a conductor used as a wiring can be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b. As the conductor used as a wiring, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. In addition, the conductor can have a laminated structure. For example, it can have a laminated structure of titanium, titanium nitride, and the above conductive material. Further, the conductor can be embedded in an opening of an insulator.

[0180] In addition, although not shown, it is preferable to provide an insulator having a resistivity of 1.0×10 13 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more and 5.0×10 14 Ωcm or less so as to cover the above conductor. By providing an insulator having the above resistivity on the above conductor, the insulator can not only maintain insulation but also disperse charges accumulated in the transistor 200, the wiring (for example, the above conductor), etc., and can suppress characteristic deterioration or electrostatic breakdown of the transistor or an electronic device having the transistor due to the charges, and thus is preferable.

[0181] <Constituent Materials of Semiconductor Device>

[0182] Hereinafter, constituent materials that can be used for a semiconductor device will be described.

[0183] <Substrate>

[0184] As a substrate for forming the transistor 200, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttrium-stabilized zirconia substrate), a resin substrate, etc. can be cited, for example. In addition, as the semiconductor substrate, a semiconductor substrate made of silicon, germanium, etc., or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited, for example. Furthermore, a semiconductor substrate having an insulator region inside the above semiconductor substrate can be cited, such as a SOI (Silicon On Insulator) substrate, etc. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. Furthermore, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can be cited. Or, a substrate provided with elements on these substrates can also be used. As the elements provided on the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0185] "Insulator"

[0186] As the insulator, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrides having insulating properties, etc.

[0187] For example, when miniaturizing and highly integrating the transistor, due to the thinning of the gate insulator, problems such as leakage current sometimes occur. By using a high-k material as the insulator used as the gate insulator, low voltage operation of the transistor can be achieved while maintaining the physical thickness. On the other hand, by using a material with a relatively low relative dielectric constant for the insulator used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

[0188] In addition, as the insulator with a relatively high relative dielectric constant, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, etc. can be cited.

[0189] In addition, as the insulator with a relatively low relative dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon- and nitrogen-added silicon oxide, porous silicon oxide, or resin, etc. can be cited.

[0190] In addition, by surrounding a transistor using an oxide semiconductor with insulators (such as insulator 214, insulator 222, insulator 254, and insulator 274) that have a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, and metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0191] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that can be removed by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that can be removed by heating is brought into contact with the oxide 230, the oxygen defects contained in the oxide 230 can be filled.

[0192] 《Conductor》

[0193] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable. In addition, a semiconductor with high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0194] In addition, a plurality of conductive layers formed of the above materials can also be laminated. For example, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen can also be adopted. In addition, a laminated structure combining a material containing the above metal element and a conductive material containing nitrogen can also be adopted. In addition, a laminated structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can also be adopted.

[0195] In addition, in the case where an oxide is used for the channel formation region of a transistor, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen is preferably used as the conductor used as the gate electrode. In this case, the conductive material containing oxygen is preferably provided on the side of the channel formation region. By providing the conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material can be easily supplied to the channel formation region.

[0196] In particular, as the conductor used as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen can also be used. For example, a nitrogen-containing conductive material such as titanium nitride or tantalum nitride can also be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon can be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, it is sometimes possible to capture hydrogen contained in the metal oxide forming the channel. Or, it is sometimes possible to capture hydrogen entering from an external insulator or the like.

[0197] "Metal Oxide"

[0198] As the oxide 230, a metal oxide used as an oxide semiconductor is preferably used. Hereinafter, the metal oxide that can be used for the oxide 230 according to the present invention will be described.

[0199] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to this, it is preferably further contains aluminum, gallium, yttrium or tin, etc. Or, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten or magnesium, etc.

[0200] Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M and zinc. Note that element M is aluminum, gallium, yttrium or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Note that as element M, multiple of the above elements can sometimes be combined.

[0201] Note that in this specification and the like, a metal oxide containing nitrogen is sometimes also referred to as a metal oxide. In addition, a metal oxide containing nitrogen can also be referred to as a metal oxynitride.

[0202] [Structure of Metal Oxide]

[0203] Oxide semiconductors (metal oxides) are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0204] CAAC-OS has a c-axis orientation, and its multiple nanocrystals are connected in the a-b plane direction and the crystal structure has distortion. Note that distortion refers to the part where the direction of the lattice arrangement changes between the regions where the lattice arrangements are consistent in the region where multiple nanocrystals are connected and other regions where the lattice arrangements are consistent.

[0205] Although the nanocrystals are basically hexagonal, they are not limited to regular hexagons and there are cases where they are not regular hexagons. In addition, pentagonal, heptagonal, etc. lattice arrangements sometimes exist in the distortion. Also, in CAAC-OS, it is difficult to observe a clear grain boundary (also called grain boundary) even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the lattice arrangement distortion. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atom arrangement in the a-b plane direction or the change in the interatomic bonding distance due to the substitution of metal elements, etc.

[0206] In addition, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. In the case where indium replaces element M in the (M, Zn) layer, this layer can also be expressed as the (In, M, Zn) layer. Also, in the case where element M replaces indium in the In layer, this layer can also be expressed as the (In, M) layer.

[0207] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe a clear grain boundary in CAAC-OS, so it can be said that the decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of metal oxides sometimes decreases due to the entry of impurities or the generation of defects, etc., so it can be said that CAAC-OS is a metal oxide with few impurities or defects (such as oxygen vacancies (also called Vo)). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0208] In nc-OS, the atomic arrangement in a minute region (for example, a region of more than 1 nm and less than 10 nm, particularly a region of more than 1 nm and less than 3 nm) has periodicity. Further, no regularity in crystal orientation is observed among different nanocrystals in nc-OS. Therefore, no orientation is observed in the entire film. Thus, nc-OS sometimes shows no difference from a-like OS or an amorphous oxide semiconductor in some analysis methods.

[0209] Further, indium-gallium-zinc oxide (hereinafter, IGZO), which is one of metal oxides containing indium, gallium, and zinc, may have a stable structure when it is the above-described nanocrystal. In particular, IGZO has a tendency that crystal growth is not easily performed in the air, and thus may be structurally more stable when IGZO is a small crystal (for example, the above-described nanocrystal) than when IGZO is a large crystal (here, a crystal of several mm or a crystal of several cm).

[0210] a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS includes voids or low-density regions. That is, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0211] Oxide semiconductors (metal oxides) have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may also include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0212] [Impurities]

[0213] Here, the influence of each impurity in the metal oxide will be described.

[0214] When a metal oxide contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to form carriers. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region easily has normally-on characteristics. Thus, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or the alkaline earth metal in the metal oxide obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) (the concentration measured by SIMS) is 1×10 18 atoms / cm 3 Hereinafter, it is preferably 2×10 16 atoms / cm 3 Hereinafter.

[0215] Hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to form water, and thus oxygen defects are sometimes formed. When hydrogen enters the oxygen defects, electrons are sometimes generated as carriers. In addition, sometimes electrons are generated as carriers because a part of hydrogen bonds with oxygen bonded to the metal atom. Therefore, a transistor using a metal oxide containing hydrogen easily has normally-on characteristics.

[0216] Therefore, it is preferable to reduce hydrogen in the metal oxide as much as possible. Specifically, in the metal oxide, the hydrogen concentration measured by SIMS is set to be less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , further preferably less than 1×10 18 atoms / cm 3 . By using a metal oxide with sufficiently reduced impurities for the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[0217] As the metal oxide used as a semiconductor for a transistor, a thin film with high crystallinity is preferably used. By using this thin film, the stability or reliability of the transistor can be improved. Examples of such a thin film include a single-crystalline metal oxide thin film or a polycrystalline metal oxide thin film. However, forming a single-crystalline metal oxide thin film or a polycrystalline metal oxide thin film on a substrate requires a process of high-temperature or laser heating. Therefore, the cost of the manufacturing process becomes high and the throughput decreases.

[0218] Non-Patent Document 1 and Non-Patent Document 2 reported that in 2009, In-Ga-Zn oxide having a CAAC structure (also referred to as CAAC-IGZO) was discovered. In Non-Patent Document 1 and Non-Patent Document 2, it was reported that CAAC-IGZO has c-axis orientation, unclear grain boundaries, and can be formed on a substrate at low temperature. In addition, it was also reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

[0219] In addition, in 2013, In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (refer to Non-Patent Document 3). It was reported here that the atomic arrangement of nc-IGZO has periodicity in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity of crystal orientation is observed between different regions.

[0220] Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size when an electron beam is irradiated onto the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films. In the IGZO thin film with low crystallinity, crystalline IGZO of about 1 nm can be observed before irradiating the electron beam onto it. Therefore, it is reported here that the existence of a completely amorphous structure cannot be confirmed in IGZO. Furthermore, it is disclosed that the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability against electron beam irradiation compared with the IGZO thin film with low crystallinity. Therefore, the CAAC-IGZO thin film or the nc-IGZO thin film is preferably used as the semiconductor of a transistor.

[0221] Non-Patent Document 6 discloses that the leakage current of a transistor using a metal oxide in the non-conducting state is extremely low. Specifically, the off-state current per channel width of 1 μm of the transistor is on the order of yA / μm (10 -24 A / μm). For example, a low-power CPU etc. that applies the characteristic of low leakage current of a transistor using a metal oxide has been disclosed (refer to Non-Patent Document 7).

[0222] In addition, there is a report of applying a transistor using a metal oxide to a display device by utilizing the characteristic of low leakage current of the transistor (refer to Non-Patent Document 8). In a display device, the displayed image is switched dozens of times per second. The number of image switches per second is called the refresh frequency. In addition, the refresh frequency is sometimes called the drive frequency. Such a high-speed image switch that is difficult for the human eye to recognize is considered to be the cause of eye fatigue. Then, a technique of reducing the refresh frequency of the display device to reduce the number of image rewrites has been proposed. In addition, the drive with a reduced refresh frequency can reduce the power consumption of the display device. This drive method is called the idle stop (IDS) drive.

[0223] The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of a transistor using a CAAC structure or a metal oxide having an nc structure, the reduction of the cost of the manufacturing process, and the improvement of the throughput. In addition, research has been conducted on applying the transistor to a display device and an LSI by utilizing the characteristic of low leakage current of the above-mentioned transistor.

[0224] <Method of manufacturing a semiconductor device>

[0225] Next, a method of manufacturing a semiconductor device including a transistor 200 according to one embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 4 to 11. In FIGS. 4 to 11, A in each drawing shows a plan view. In addition, B in each drawing shows a cross-sectional view of a portion along the dotted line A1-A2 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. C in each drawing shows a cross-sectional view of a portion along the dotted line A3-A4 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. For clarity, some constituent elements are omitted in the plan view of A in each drawing.

[0226] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0227] Note that the CVD method can be classified into a plasma-enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Furthermore, the CVD method can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method according to the source gas used.

[0228] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since no plasma is used, the thermal CVD method is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged due to the accumulated charges. On the other hand, since the above-described plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during film formation does not occur, and thus a film with fewer defects can be obtained.

[0229] In addition, the ALD method can deposit atoms of each layer by utilizing the self-regulating property of atoms, thereby achieving effects such as being able to form an extremely thin film, being able to form a film on a structure with a high aspect ratio, being able to form a film with few defects such as pinholes, being able to form a film with excellent coverage, and being able to form a film at a low temperature. In addition, the ALD method also includes the PEALD (Plasma Enhanced ALD) method that utilizes plasma. By utilizing plasma, film formation can be carried out at a lower temperature, so it is sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, the film formed by the ALD method sometimes contains more impurities such as carbon compared to the film formed by other film formation methods. In addition, the quantification of impurities can be carried out using X-ray photoelectron spectroscopy (XPS).

[0230] Different from the film formation method in which particles released from a target or the like are deposited, the CVD method and the ALD method are film formation methods in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for cases such as covering the surface of an opening with a high aspect ratio. Note that the film formation speed of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other film formation methods with a high film formation speed such as CVD.

[0231] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow rate ratio of the source gas. For example, when using the CVD method or the ALD method, a film with an arbitrary composition can be formed by adjusting the flow rate ratio of the source gas. In addition, for example, when using the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gas while forming the film. When forming a film while changing the flow rate ratio of the source gas, since the time required for transferring and adjusting the pressure is not required, the film formation time can be shortened compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0232] In the present embodiment, alumina is formed by the sputtering method as the insulator 214. The insulator 214 can also adopt a multilayer structure. For example, a structure in which alumina is formed by the sputtering method and then another alumina is formed on the alumina by the ALD method can be adopted. Or, a structure in which alumina is formed by the ALD method and then another alumina is formed on the alumina by the sputtering method can be adopted.

[0233] Next, a conductive film that becomes the conductor 205 is formed on the insulator 214. The conductive film that becomes the conductor 205 is formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film that becomes the conductor 205 may be a multilayer film. In this embodiment, tungsten is formed as the conductive film that becomes the conductor 205.

[0234] Next, the conductive film to be the conductor 205 is processed using a photolithography method, whereby the conductor 205 is formed.

[0235] In addition, in the photolithography method, the resist is first exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, insulator, etc. into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above light. Note that the above-mentioned resist exposure mask is not required when an electron beam or an ion beam is used. In addition, when removing the resist mask, a dry etching process such as an ashing process or a wet etching process can be performed, or a wet etching process can be performed after a dry etching process, or a dry etching process can be performed after a wet etching process.

[0236] Alternatively, a hard mask made of an insulator or a conductor can be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film that becomes a hard mask material can be formed on the conductive film that becomes the conductor 205 and a resist mask can be formed thereon, and then the hard mask material is etched to form a hard mask of a desired shape. The etching of the conductive film that becomes the conductor 205 can be performed after removing the resist mask or without removing the resist mask. In the case of the latter, the resist mask sometimes disappears during etching. In addition, the hard mask can also be removed by etching after the etching of the conductive film that becomes the conductor 205. On the other hand, when the hard mask material does not affect the subsequent process or can be used in the subsequent process, the hard mask does not necessarily have to be removed.

[0237] As a dry etching device, a capacitively coupled plasma (CCP) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which high-frequency power is applied to one of the parallel plate electrodes. Alternatively, a structure in which different multiple high-frequency powers are applied to one of the parallel plate electrodes can also be adopted. Alternatively, a structure in which high-frequency power with the same frequency is applied to each of the parallel plate electrodes can also be adopted. Alternatively, a structure in which high-frequency power with different frequencies is applied to each of the parallel plate electrodes can also be adopted. Alternatively, a dry etching device having a high-density plasma source can be used. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP) etching device or the like can be used.

[0238] Next, an insulating film that becomes the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the top surface and the side surface of the conductor 205. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed by the CVD method as the insulating film that becomes the insulator 216.

[0239] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is 1 or more and 3 or less. In the present embodiment, the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film that becomes the insulator 216 is 350 nm.

[0240] Next, a part of the insulating film that becomes the insulator 216 is removed by performing a CMP (Chemical Mechanical Polishing) process on the insulating film that becomes the insulator 216, and the surface of the conductor 205 is exposed. Thereby, the conductor 205 having a flat top surface and the insulator 216 in contact with the side surface of the conductor 205 can be formed (see FIG. 4). By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of the CAAC-OS in which the oxides 230b and 230c are formed can be improved.

[0241] Hereinafter, a method for forming the conductor 205 different from the above will be described.

[0242] The insulator 216 is formed on the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0243] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove or a slit. In addition, the region where the opening is formed is sometimes referred to as an opening portion. When forming this opening, a wet etching method can be used, but a dry etching method is preferred for microfabrication. As the insulator 214, an insulator that serves as an etch stop film when etching the insulator 216 to form a groove is preferably selected. For example, when a silicon oxide film is used as the insulator 216 for forming the groove, the insulator 214 is preferably a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0244] After forming the opening, a conductive film that becomes the conductor 205 is formed. This conductive film preferably contains a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film of this conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film that becomes the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

[0245] In the present embodiment, the conductive film that becomes the conductor 205 has a multilayer structure. First, tantalum nitride is formed by a sputtering method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride for the lower layer of the conductive film that becomes the conductor 205, even if a metal such as copper that easily diffuses is used for the upper layer of the conductive film that becomes the conductor 205 described later, diffusion of this metal from the conductor 205 to the outside can be suppressed.

[0246] Next, a conductive film is formed on the upper layer of the conductive film that becomes the conductor 205. This conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In the present embodiment, a low-resistance conductive material such as copper is formed as the conductive film on the upper layer of the conductive film that becomes the conductor 205.

[0247] Next, by performing a CMP process, a part of the upper layer of the conductive film that becomes the conductor 205 and the lower layer of the conductive film that becomes the conductor 205 is removed to expose the insulator 216. As a result, only the conductive film that becomes the conductor 205 remains in the opening portion. Thus, a conductor 205 having a flat top surface can be formed. Note that a part of the insulator 216 may be removed due to this CMP process. The above is a method for forming the conductor 205 different from the above description.

[0248] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed. Further, as the insulator containing an oxide of one or both of aluminum and hafnium, alumina, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure around the transistor 200 can be suppressed from diffusing into the inside of the transistor 200 through the insulator 222, and thus generation of oxygen defects in the oxide 230 can be suppressed.

[0249] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0250] Next, an insulating film 224A that becomes the insulator 224 is formed on the insulator 222. The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0251] Next, a heat treatment is preferably performed. The heat treatment is carried out at 250°C or higher and 650°C or lower, preferably at 300°C or higher and 500°C or lower, more preferably at 320°C or higher and 450°C or lower. The heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment can also be carried out under a reduced pressure state. Alternatively, the heat treatment can be carried out in a nitrogen gas or inert gas atmosphere, and then the heat treatment is carried out in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to fill the escaped oxygen.

[0252] In the present embodiment, as the heat treatment, a treatment is carried out at 400°C for 1 hour in a nitrogen atmosphere after the insulating film 224A is formed. By this heat treatment, impurities such as water and hydrogen in the insulating film 224A can be removed. Further, the heat treatment can also be carried out at an appropriate timing after the insulator 222 is formed.

[0253] Here, in order to form an excess oxygen region in the insulating film 224A, plasma treatment containing oxygen may also be performed under a reduced pressure state. The plasma treatment containing oxygen preferably uses, for example, a device including a power source for generating high-density plasma using microwaves. Alternatively, it may also include a power source for applying RF (Radio Frequency) to one side of the substrate. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulating film 224A. Alternatively, after performing plasma treatment containing an inert gas using such a device, plasma treatment containing oxygen may be performed to fill the detached oxygen. In addition, by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. At this time, heat treatment may not be performed.

[0254] Here, an alumina film may also be formed on the insulating film 224A by, for example, sputtering method, and CMP treatment may be performed on the alumina until reaching the insulating film 224A. By performing this CMP treatment, planarization of the surface of the insulating film 224A and smoothing of the surface of the insulating film 224A can be performed. By disposing the alumina on the insulating film 224A and performing CMP treatment, the end point of the CMP treatment can be easily detected. In addition, sometimes a part of the insulating film 224A is polished by the CMP treatment and the thickness of the insulating film 224A becomes thinner, but it is sufficient to adjust the thickness when forming the insulating film 224A. By performing planarization and smoothing of the surface of the insulating film 224A, sometimes a decrease in the coverage rate of the oxide film formed below can be prevented and a decrease in the yield of the semiconductor device can be prevented. In addition, by forming an alumina film on the insulating film 224A by sputtering method, oxygen can be added to the insulating film 224A, so it is preferable.

[0255] Next, an oxide film 230A that becomes an oxide 230a and an oxide film 230B that becomes an oxide 230b are sequentially formed on the insulating film 224A (see FIG. 4). It is preferable to continuously form the above oxide films without being exposed to the atmospheric environment. By forming the oxide films in a manner not exposed to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, so the vicinity of the interface between the oxide film 230A and the oxide film 230B can be kept clean.

[0256] The oxide film 230A and the oxide film 230B can be formed by sputtering method, CVD method, MBE method, PLD method, ALD method, etc.

[0257] For example, in the case of forming the oxide film 230A and the oxide film 230B by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. In addition, in the case of forming the above-mentioned oxide film by sputtering, for example, the above-mentioned In-M-Zn oxide target can be used. Further, the target is connected to an AC power source such as a DC power source or an RF power source, and the required power can be applied according to the conductivity of the target.

[0258] In particular, when forming the oxide film 230A, sometimes a part of the oxygen contained in the sputtering gas is supplied to the insulating film 224A. Therefore, the ratio of oxygen contained in the sputtering gas of the oxide film 230A can be 70% or more, preferably 80% or more, and more preferably 100%.

[0259] In addition, in the case of forming the oxide film 230B by sputtering, when film formation is performed in a state where the ratio of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. A transistor using the oxygen-deficient oxide semiconductor for the channel formation region can have a high field-effect mobility. In addition, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited thereto. In the case of forming the oxide film that becomes the oxide 230b by sputtering, an oxygen-excess oxide semiconductor is formed by forming the film under the condition that the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less. A transistor using the oxygen-excess oxide semiconductor for the channel formation region can obtain relatively high reliability.

[0260] In the present embodiment, the oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target of In:Ga:Zn = 1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or In:Ga:Zn = 1:3:4 [atomic ratio]. In addition, the oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target of In:Ga:Zn = 4:2:4.1 [atomic ratio]. The above-mentioned oxide film can be formed by appropriately selecting the film formation conditions and the atomic ratio according to the required characteristics of the oxide 230.

[0261] Here, it is preferable to form the insulator 222, the insulating film 224A, the oxide film 230A, and the oxide film 230B in a manner that does not expose them to the atmosphere. For example, a film formation apparatus using a multi-chamber method can be used.

[0262] Next, heat treatment can also be performed. As the conditions for the heat treatment, the above-described heat treatment conditions can be used. By performing the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere, and then continuously at a temperature of 400°C for 1 hour in an oxygen atmosphere.

[0263] Next, a conductive film 242A is formed on the oxide film 230B. The conductive film 242A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see FIG. 4).

[0264] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into island shapes to form an insulator 224, an oxide 230a, an oxide 230b, and a conductive layer 242B (see FIG. 5).

[0265] Here, the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B are formed such that at least a part thereof overlaps with the conductor 205. In addition, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B are substantially perpendicular to the top surface of the insulator 222, miniaturization and high density can be achieved when a plurality of transistors 200 are provided. Alternatively, a structure in which the angle formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B and the top surface of the insulator 222 is low can also be employed. In this case, the angle formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B and the top surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 254 and the like in the subsequent processes can be improved, and defects such as voids can be reduced.

[0266] In addition, there is a curved surface between the side surface and the top surface of the conductive layer 242B. That is, the end of the side surface and the end of the top surface are preferably curved (hereinafter, also referred to as rounded). For example, at the end of the conductive layer 242B, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, and more preferably 5 nm or more and 6 nm or less. When the end portion does not have a corner portion, the coverage of the film in the subsequent film formation process can be improved.

[0267] In addition, the insulation film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A can be processed by photolithography. Additionally, dry etching or wet etching can be used for this processing. Processing using dry etching is suitable for microfabrication. Moreover, the insulation film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A can be formed under different conditions from each other.

[0268] Next, an insulation film 254A (see FIG. 6) is formed on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B.

[0269] As the insulation film 254A, an insulation film having a function of suppressing oxygen permeation is preferably used. For example, an alumina film is preferably formed by sputtering. By forming an alumina film by sputtering and using a gas containing oxygen, oxygen can be introduced into the insulator 224. In other words, the insulator 224 can have excess oxygen.

[0270] Next, an insulation film that becomes the insulator 280 is formed on the insulation film 254A. The insulation film that becomes the insulator 280 can be formed by sputtering, CVD, MBE, PLD, ALD, etc. Next, CMP processing is performed on the insulation film that becomes the insulator 280 to form the insulator 280 with a flat top surface (see FIG. 6).

[0271] Next, a part of the insulator 280, a part of the insulation film 254A, and a part of the conductive layer 242B are processed to form an opening reaching the oxide 230b. This opening is preferably formed so as to overlap with the conductor 205. The conductor 242a, the conductor 242b, and the insulator 254 are formed from this opening (see FIG. 7).

[0272] In addition, a part of the insulator 280, a part of the insulation film 254A, and a part of the conductive layer 242B can also be processed under different conditions. For example, a part of the insulator 280 can be processed by dry etching, a part of the insulation film 254A can be processed by wet etching, and a part of the conductive layer 242B can be processed by dry etching.

[0273] By performing the above processing such as dry etching, impurities such as etching gas may adhere to or diffuse into the surface or interior of the oxide 230a, the oxide 230b, etc. Examples of the impurities include fluorine, chlorine, etc.

[0274] Washing is performed to remove the above impurities, etc. As the washing method, there are wet washing using a washing liquid, etc., plasma treatment using plasma, washing using heat treatment, etc., and the above washings can also be appropriately combined.

[0275] As wet cleaning, an aqueous solution diluted with carbonated water or pure water of oxalic acid, phosphoric acid, hydrofluoric acid, etc. can be used for the cleaning treatment. Alternatively, ultrasonic cleaning using pure water or carbonated water can be performed.

[0276] Next, heat treatment can also be performed. The heat treatment can also be performed under reduced pressure, and the oxide film 230C is continuously formed in a manner not exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide 230b, etc. can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is 200°C (see FIG. 8).

[0277] The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. The oxide film that becomes the oxide film 230C can be formed by the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C. In the present embodiment, the oxide film 230C is formed using an In—Ga—Zn oxide target of In:Ga:Zn = 1:3:4 [atomic ratio] or In:Ga:Zn = 4:2:4.1 [atomic ratio] by a sputtering method.

[0278] In particular, when forming the oxide film 230C, a part of the oxygen contained in the sputtering gas is sometimes supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0279] Next, heat treatment can also be performed. The heat treatment can also be performed under reduced pressure, and the insulating film 250A is continuously formed in a manner not exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide film 230C, etc. can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower (see FIG. 9).

[0280] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. As the insulating film 250A, it is preferable to form oxynitride silicon by a CVD method. The film formation temperature when forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By forming the insulating film 250A at a temperature of 400°C, an insulating film with few impurities can be formed.

[0281] Next, the conductive film 260A and the conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the CVD method is preferably used. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method (see FIG. 10 ).

[0282] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 11). Thus, the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the opening that reaches the oxide 230b. The insulator 250 is arranged so as to cover the inner wall of the above-mentioned opening via the oxide 230c. In addition, the conductor 260 is arranged so as to be embedded in the above-mentioned opening via the oxide 230c and the insulator 250.

[0283] Next, a heat treatment may be performed. In this embodiment, the treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. The heat treatment can reduce the water concentration and hydrogen concentration in the insulator 250 and the insulator 280 .

[0284] Next, an insulator 274 may be formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The film formation of the insulator 274 may be performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the insulator 274 is preferably formed by forming an aluminum oxide film by a sputtering method. By forming the aluminum oxide film by a sputtering method, it is sometimes possible to suppress the diffusion of hydrogen in the insulator 281 to the oxide 230. In addition, by forming the insulator 274 in contact with the conductor 260, it is possible to suppress the oxidation of the conductor 260, which is preferred. In addition, by forming the insulator 274, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 is sometimes supplied to the region 234 in the oxide 230b through the oxide 230c. In addition, by supplying oxygen to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 274 is sometimes supplied to the region 234 in the oxide 230b through the oxide 230c. In addition, by supplying oxygen to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 274 is sometimes supplied to the region 234 in the oxide 230b through the oxide 230c.

[0285] Next, a heat treatment may be performed. The heat treatment conditions described above may be used. The heat treatment may reduce the water concentration and hydrogen concentration of the insulator 280 . In addition, oxygen in the insulator 274 may be implanted into the insulator 280 .

[0286] In addition, as a method of forming the insulator 274 on the insulator 280, first, an insulating film made of the same material as the insulator 274 can be formed using the same formation method as the insulator 274. Then, heat treatment is performed under the above heat treatment conditions. Then, the insulating film is removed by CMP treatment. Then, the insulator 274 is formed, and then heat treatment is performed under the above heating conditions. By this method, an excess oxygen region can be formed in the insulator 280. Note that in this step of removing the insulating film, a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.

[0287] In addition, an insulator can be provided between the insulator 280 and the insulator 274. As this insulator, for example, silicon oxide formed by sputtering can be used. By providing this insulator, an excess oxygen region can be formed in the insulator 280.

[0288] Next, an insulator 281 that becomes an insulating film can be formed on the insulator 274. The insulator 281 that becomes an insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, etc. (see FIG. 11).

[0289] Next, openings reaching the conductors 242a and 242b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281. This opening can be formed using photolithography.

[0290] Next, an insulating film that becomes the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. This insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, etc. As this insulating film, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, an alumina film is preferably formed by ALD. In addition, a silicon nitride film can be formed by ALD or CVD. When a silicon nitride film is formed by ALD, a precursor containing silicon and a halogen or an aminosilane-based precursor can be used. As the precursor containing silicon and a halogen, SiCl4, SiH2Cl2, Si2Cl6, Si3Cl8, etc. can be used. In addition, as the aminosilane-based precursor, monovalent, divalent, or trivalent aminosilane-based compounds can be used. In addition, ammonia or hydrazine can be used as the nitriding gas. In addition, as the anisotropic etching, for example, dry etching can be used. By making the side wall portion of the opening have such a structure, permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented. In addition, diffusion of impurities such as water and hydrogen from the conductors 240a and 240b to the outside can be prevented.

[0291] Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. This conductive film preferably has a laminated structure including a conductor having a function of suppressing the diffusion of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. This conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

[0292] Next, by performing CMP processing, a part of the above conductive film is removed to expose the insulator 281. As a result, only the conductive film remains in the above opening, and thus the conductor 240a and the conductor 240b having a flat top surface can be formed (see FIG. 1). Note that sometimes a part of the insulator 281 is removed due to this CMP processing.

[0293] Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 4 to 11, the transistor 200 can be manufactured by using the manufacturing method of the semiconductor device shown in this embodiment.

[0294] According to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high-frequency characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a low off-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0295] <Structural Example 2 of Semiconductor Device>

[0296] FIG. 12 is a top view and a cross-sectional view of the transistor 200A and the periphery of the transistor 200A according to one aspect of the present invention. The transistor 200A is a modified example of the transistor 200.

[0297] Figure 12A is a top view of a semiconductor device including the transistor 200A. In addition, Figure 12B and Figure 12C is a cross-sectional view of this semiconductor device. Here, Figure 12B is a cross-sectional view along the portion shown by the dotted line A1 - A2 in Figure 12A , and is also a cross-sectional view in the channel length direction of the transistor 200A. In addition, Figure 12C is along Figure 12AThe cross-sectional view of the portion shown by the dash-dotted line A3 - A4 is also the cross-sectional view in the channel width direction of the transistor 200A. Note that Figure 12A Some constituent elements are omitted in the top view for clarity.

[0298] Note that in the semiconductor device shown in FIG. 12, the constituent elements having the same functions as the constituent elements of the semiconductor device shown in <Structural Example 1 of Semiconductor Device> are assigned the same reference numerals.

[0299] The structure of the semiconductor device will be described below with reference to FIG. 12. Additionally, in this structure, the constituent materials of the semiconductor device can be the materials described in detail in <Structural Example 1 of Semiconductor Device>.

[0300] [Transistor 200A]

[0301] As shown in FIG. 12, the transistor 200A includes an insulator 216 provided on a substrate (not shown), a conductor 205 provided in a manner embedded in the insulator 216, an insulator 222 provided on the insulator 216 and the conductor 205, an insulator 224 provided on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) provided on the insulator 224, an insulator 250 provided on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) provided on the insulator 250, conductors 242a and 242b in contact with a part of the top surface of the oxide 230b, a barrier film 244a provided on the conductor 242a, a barrier film 244b provided on the conductor 242b, and insulators 254 (insulator 254a and insulator 254b) disposed in contact with a part of the top surface of the insulator 222, the side surface of the insulator 224, the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, the side surface of the conductor 242a, the top surface of the barrier film 244a, the side surface of the conductor 242b, and the top surface of the barrier film 244b.

[0302] The difference between the transistor 200A and the transistor 200 is that the insulator 254 has a double-layer stacked structure of the insulator 254a and the insulator 254b, the oxide 230c has a double-layer stacked structure of the oxide 230c1 and the oxide 230c2, and the transistor 200A further includes the barrier films 244a and 244b. The differences from the transistor 200 will be described below.

[0303] As shown in FIG. 12, the insulator 254 includes an insulator 254a and an insulator 254b provided on the insulator 254a. For example, the insulator 254a preferably has a function of a barrier film that inhibits the diffusion of impurities such as water and hydrogen from the side of the insulator 280 to the transistor 200A. In addition, for example, the insulator 254b preferably can inhibit the diffusion of oxygen in the oxide 230 to the side of the insulator 280. By adopting this double-layer laminated structure, hydrogen can be prevented from mixing into the channel formation region of the oxide 230. Furthermore, the release of oxygen from the channel formation region of the oxide 230 can be prevented. Specifically, the insulator 254a can use a silicon nitride film formed by a sputtering method, and the insulator 254b can use an aluminum oxide film formed by an ALD method.

[0304] In addition, for example, the insulator 254a preferably uses an insulating material having an excess oxygen region or an insulating material that easily forms an excess oxygen region, and the insulator 254b preferably uses an insulating material that easily forms an excess oxygen region in the film to be formed. Specifically, the insulator 254a can use a silicon oxide film formed by a sputtering method, and the insulator 254b can use an aluminum oxide film formed by a sputtering method. By adopting this double-layer laminated structure, the excess oxygen in the insulator 254a can be efficiently supplied to the oxide 230.

[0305] In addition, when the insulator 254a contains excess oxygen, it is preferable to provide a barrier film 244a in contact with the top surface of the conductor 242a and a barrier film 244b in contact with the top surface of the conductor 242b. The barrier film 244a and the barrier film 244b have a function of inhibiting the permeation of impurities such as water and hydrogen and oxygen. Thereby, the excess oxygen in the oxide 230c and the insulator 250 can be prevented from diffusing to the conductor 242a and the conductor 242b. That is, the excess oxygen around the conductor 242a and the conductor 242b can be prevented from being used for the oxidation of the conductor 242a and the conductor 242b. Furthermore, an increase in the resistance value of the conductor 242a and the conductor 242b due to the oxidation of the conductor 242a and the conductor 242b can be prevented. In addition, the resistance value of the conductor can be measured by a two-terminal method or the like.

[0306] The barrier film 244a and the barrier film 244b can use, for example, metal oxides such as alumina, magnesia, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc.

[0307] In addition, the barrier film 244a and the barrier film 244b can also use a conductive material that is not easily permeated by impurities. When using a conductive material as the barrier film 244a and the barrier film 244b, it is preferable to use a conductive material that does not easily release or absorb oxygen. In addition, the barrier film 244a and the barrier film 244b may not be provided.

[0308] Note that the insulator 254 is not limited to the structure of the stacked insulators 254a and 254b, and a single-layer structure may be employed, or a three-layer stacked structure of the insulator 254a, the insulator 254b, and the insulator 254c may be employed. When a three-layer stacked structure is employed, for example, the insulator 254a may use an insulating material capable of suppressing the diffusion of impurities such as water and hydrogen and oxygen, the insulator 254b may use an insulating material including an excess oxygen region, and the insulator 254c may use an insulating material capable of suppressing oxygen diffusion. By adopting the stacked structure of these three layers, the excess oxygen in the insulator 254b can be suppressed from diffusing to the outside of the insulator 254a and the insulator 254c. Therefore, the excess oxygen contained in the insulator 254b can be efficiently supplied to the oxide 230.

[0309] In addition, when the insulator 254 adopts a stacked structure of two or more layers, the combination and stacking order of the insulating materials used for the insulator 254 can be appropriately designed according to the required transistor characteristics.

[0310] In addition, as shown in FIG. 12, the oxide 230c includes an oxide 230c1 and an oxide 230c2 provided on the oxide 230c1. The oxide 230c1 preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230b, and more preferably contains all of the above metal elements. Thereby, the density of defect states at the interface between the oxide 230b and the oxide 230c1 can be reduced. In addition, the oxide 230c2 is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c1. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, the oxygen contained in the insulator 280 can be suppressed from diffusing into the insulator 250. Therefore, this oxygen can be easily supplied to the oxide 230 through the oxide 230c1.

[0311] In addition, the oxide 230c1 and the oxide 230c2 preferably have crystallinity, and more preferably the crystallinity of the oxide 230c2 is higher than that of the oxide 230c1. Particularly preferably, the oxide 230c1 and the oxide 230c2 use CAAC-OS, and the c-axis orientation of the crystals in the oxide 230c1 and the oxide 230c2 is substantially perpendicular to the formation surface or the top surface of the oxide 230c1 and the oxide 230c2. CAAC-OS has the property that oxygen is not easily moved in the c-axis direction. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, the oxygen in the oxide 230c1 can be prevented from diffusing into the insulator 250, and thus this oxygen can be efficiently supplied to the oxide 230.

[0312] Specifically, the oxide 230c1 may use a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio], and the oxide 230c2 may use a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio]. In the metal oxide used for the oxide 230c2, by making the atomic ratio of In in the constituent elements less than the atomic ratio of In in the constituent elements of the metal oxide used for the oxide 230c1, the diffusion of In to the insulator 250 side can be suppressed. Since the insulator 250 is used as a gate insulator, when In is mixed into the insulator 250 or the like, it will cause poor transistor characteristics. Therefore, by making the oxide 230c have a stacked structure, a semiconductor device with high reliability can be provided.

[0313] In addition, the insulator 280 may also adopt a double-layer stacked structure. As shown in FIG. 12, when the insulator 280 includes the insulator 280a and the insulator 280b provided on the insulator 280a, the insulator 280a preferably includes an excess oxygen region. The physical distance from the insulator 280a to the channel formation region of the oxide 230 is shorter than that of the insulator 280b, so the oxygen in the insulator 280 can be efficiently supplied to the channel formation region of the oxide 230.

[0314] Specifically, the insulator 280a may use a silicon oxide film formed by a sputtering method, and the insulator 280b may use a silicon oxynitride film formed by a CVD method. The film thickness of the insulator 280a is preferably 30 nm or more and 100 nm or less, more preferably 40 nm or more and 80 nm or less. Note that although the insulator 280 is shown to have a stacked structure in the transistor 200A, the present invention is not limited thereto. For example, the insulator 280 may also adopt a single-layer or a stacked structure of three layers or more.

[0315] In addition, as shown in FIG. 12, an insulator 282 may be provided between the insulator 274 and the insulator 281. The insulator 282 preferably uses an insulating film capable of suppressing the diffusion of impurities such as hydrogen or oxygen. For example, it is preferable to use a silicon nitride film, an aluminum oxide film, etc. formed by a sputtering method or an ALD method. By providing the insulator 282, the diffusion of oxygen in the insulator 280, the insulator 250, etc. to the insulator 281 side can be suppressed.

[0316] As described above, the structures, methods, etc. shown in the present embodiment can be implemented by appropriately combining with the structures, methods, etc. shown in other embodiments.

[0317] (Embodiment 2)

[0318] Hereinafter, an example of a semiconductor device including the transistor 200B according to one aspect of the present invention will be described.

[0319] <Structural Example 3 of the Semiconductor Device>

[0320] Figures 13A to 13D It is a top view and a cross-sectional view of the transistor 200B according to one embodiment of the present invention and the periphery of the transistor 200B. The transistor 200B is a modified example of the transistor 200.

[0321] Note that in the semiconductor device shown in the present embodiment, the same reference numerals are attached to the components having the same functions as the components constituting the semiconductor device shown in the above embodiment. In addition, for the details of the components, materials, etc. of the semiconductor device shown in the present embodiment that are commonly used with the components, materials, etc. of the semiconductor device shown in the above embodiment, and the details of the components, materials, etc. to which the same reference numerals are attached, reference may be made to the description of the above embodiment.

[0322] Figure 13A It is a top view of the semiconductor device including the transistor 200B. In addition, Figures 13B to 13D It is a cross-sectional view of the semiconductor device. Here, Figure 13B It is a cross-sectional view along the Figure 13A portion shown by the dotted line A1 - A2 in , and it is also a cross-sectional view in the channel length direction of the transistor 200B. In addition, Figure 13C It is a cross-sectional view along the Figure 13A portion shown by the dotted line A3 - A4 in , and it is also a cross-sectional view in the channel width direction of the transistor 200B. In addition, Figure 13D It is a cross-sectional view along the Figure 13A portion shown by the dotted line A5 - A6 in , and it is also a cross-sectional view near the region 243b which is used as a low-resistance region of the transistor 200B. Note that Figure 13A Some components are omitted from the top view for clarity.

[0323] A semiconductor device according to one embodiment of the present invention includes the transistor 200B, an insulator 214 used as an interlayer film, an insulator 280, an insulator 274, and an insulator 281. In addition, it also includes a conductor 240 (conductor 240a and conductor 240b) used as a plug and electrically connected to the transistor 200B. In addition, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 used as a plug.

[0324] In addition, an insulator 241 is provided in contact with the side walls of the openings of the insulators 254 (insulators 254a and 254b), insulator 280, insulator 274, and insulator 281, and a first conductor of the conductor 240 is provided in contact with its side surface, and a second conductor of the conductor 240 is provided inside thereof. Here, the top surface height of the conductor 240 can be made substantially equal to the top surface height of the insulator 281. In addition, although the stacked structure of the first conductor of the conductor 240 and the second conductor of the conductor 240 is shown in the transistor 200B, the present invention is not limited thereto. For example, the conductor 240 may also adopt a single-layer or a stacked structure of three or more layers. When the structure has a stacked structure, sometimes numbers are assigned in the formation order for distinction.

[0325] [Transistor 200B]

[0326] As shown in FIG. 13, the transistor 200B includes an insulator 216 provided on a substrate (not shown), a conductor 205 provided in a manner of being embedded in the insulator 216, an insulator 222 provided on the insulator 216 and the conductor 205, an insulator 224 provided on the insulator 222, an oxide 230 (oxides 230a, 230b, 230c1, and 230c2) provided on the insulator 224, an insulator 250 provided on the oxide 230, a conductor 260 (conductors 260a and 260b) provided on the insulator 250, and an insulator 254 (insulators 254a and 254b) provided in contact with a part of the top surface of the insulator 222, the side surface of the insulator 224, the side surfaces of the oxides 230a, 230b, and the top surface of the oxide 230b.

[0327] Hereinafter, the oxides 230c1 and 230c2 may also be collectively referred to as the oxide 230c.

[0328] As shown in FIG. 13, regions 243a and 243b separated from each other are formed on the top surface of the oxide 230b. In addition, an opening is provided in the insulator 280 so as to overlap with the region between the regions 243a and 243b.

[0329] The conductor 260 serves as the gate electrode of the transistor, and the regions 243a and 243b serve as the source region or the drain region, respectively. In the transistor 200B, the conductor 260 is formed self-alignedly in the openings formed in the insulator 280 and the insulator 254 and in the region sandwiched between the region 243a and the region 243b. By forming the conductor 260 in the above-described manner, the conductor 260 can be accurately disposed between the region 243a and the region 243b without alignment. As a result, the area occupied by the transistor 200B can be reduced, and thus miniaturization and high integration of the semiconductor device can be achieved.

[0330] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, it is preferable to dispose the conductor 260a so as to surround the bottom surface and the side surface of the conductor 260b. In addition, as Figure 13B shown, the top surface of the conductor 260 preferably substantially coincides with the top surfaces of the insulator 250, the oxide 230c, and the insulator 280.

[0331] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, an oxide 230c1 disposed on the oxide 230b and at least a part of which is in contact with the top surface of the oxide 230b, and an oxide 230c2 disposed on the oxide 230c1.

[0332] Note that although a four-layer stacked structure of the oxide 230a, the oxide 230b, the oxide 230c1, and the oxide 230c2 is shown in the channel formation region and its vicinity in the transistor 200B, the present invention is not limited thereto. For example, a single-layer structure of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c1, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c2, or a stacked structure of five or more layers may be used. In addition, the oxide 230a and the oxide 230b may each have a stacked structure of two or more layers. In addition, the oxide 230c may have a single-layer structure or a stacked structure of three or more layers.

[0333] In addition, for example, when the oxide 230c has a stacked structure composed of the oxide 230c1 and the oxide 230c2 on the oxide 230c1, the oxide 230c1 preferably has the same composition as the oxide 230b, and the oxide 230c2 preferably has the same composition as the oxide 230a.

[0334] In addition, the oxide 230 (oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) including the channel formation region in the transistor 200B preferably uses a metal oxide having semiconductor functions (hereinafter, also referred to as an oxide semiconductor).

[0335] Since the leakage current (off-state current) in the non-conducting state of the transistor 200B using the oxide semiconductor for the channel formation region is extremely small, a semiconductor device with low power consumption can be provided. In addition, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for the transistor 200B constituting a highly integrated semiconductor device.

[0336] For example, as the oxide 230, a metal oxide such as In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.) is preferably used. In particular, as the element M, aluminum, gallium, yttrium, or tin is preferably used. In addition, indium oxide, zinc oxide, In-Ga oxide, In-Zn oxide, Ga-Zn oxide, or gallium oxide can also be used as the oxide 230.

[0337] Here, by adding an element that forms oxygen defects or an element that bonds to oxygen defects to the oxide 230, the carrier density of the oxide 230 may increase and it may be made to have a low resistance. As such an element, typically boron or phosphorus. In addition to boron and phosphorus, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, and noble gases, etc. can also be used. In addition, typical examples of noble gases are helium, neon, argon, krypton, xenon, etc. In addition, one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, etc. can be added to the oxide 230. Among the above metal elements, boron and phosphorus are preferably used. When adding boron and phosphorus, the equipment of the amorphous silicon or low-temperature polycrystalline silicon production line can be used, whereby the equipment investment can be reduced. The concentration of the above elements can be measured using SIMS or the like.

[0338] Figure 14A Shows Figure 13B An enlarged view of a partial region of the transistor 200B shown. Region 243 is a layer formed by adding the above elements to the oxide 230. As Figure 13B And Figure 14AAs shown, region 243a and region 243b are formed opposite to each other with the conductor 260 therebetween, and their top surfaces preferably contact the insulator 254. Preferably, in a top view, the side surfaces of region 243a and region 243b on the side of the conductor 260 coincide with the side surfaces of the conductor 260, or a part of region 243a and region 243b overlaps with the conductor 260. Here, the concentration of the above elements in region 243 is preferably equal to or higher than the concentration of the above elements in the part of the oxide 230 where region 243 is not formed. In addition, the amount of oxygen defects contained in region 243 is preferably equal to or higher than the amount of oxygen defects in the part of the oxide 230 where region 243 is not formed. Thus, compared with the part of the oxide 230 where region 243 is not formed, region 243 has a higher carrier density and a lower resistance.

[0339] In the oxide 230, the region overlapping the conductor 260 is called region 234, the region overlapping the insulator 254 is called region 231 (region 231a and region 231b), and the region between region 234 and region 231 is called region 232 (region 232a and region 232b). As Figure 14A shown, region 234 is located between region 231a and region 231b, region 232a is located between region 231a and region 234, and region 232b is located between region 231b and region 234. Here, compared with region 234, region 231 has a higher carrier density and a lower resistance. In addition, compared with region 234, region 232 has a higher carrier density and a lower resistance, and compared with region 231, region 232 has a lower carrier density and a higher resistance. In addition, region 232 may have the same carrier density and resistance as region 231. Therefore, region 234 is used as the channel formation region of the transistor 200B, region 231 is used as the source region or the drain region, and region 232 is used as the junction region.

[0340] By adopting such a structure, it is possible to prevent the formation of a bias region between the channel formation region and the source region or the drain region of the oxide 230, and thus it is possible to suppress the effective channel length from being greater than the width of the conductor 260. As a result, the on-state current of the transistor 200B can be increased, the S value (Subthreshold Swing, also referred to as SS) can be made good, and thus the frequency characteristics can be improved.

[0341] By forming a region 231 that serves as a source region or a drain region in the oxide 230, a source electrode and a drain electrode formed of metal do not need to be provided, and the region 231 can be connected to a conductor 240 that serves as a plug. When a source electrode and a drain electrode formed of metal are formed in contact with the oxide 230, the source electrode and the drain electrode formed of metal may be oxidized during a high-temperature heat treatment in the manufacturing process or subsequent processes of the transistor 200B, resulting in deterioration of the on-state current, S value, and frequency characteristics of the transistor 200B. However, the semiconductor device shown in this embodiment does not require a source electrode and a drain electrode formed of metal. Therefore, even if a high-temperature heat treatment is performed in the manufacturing process or subsequent processes of the transistor 200B, a semiconductor device with good on-state current, S value, and frequency characteristics can be provided. For example, the semiconductor device shown in this embodiment can perform a process at a high temperature of 750 °C or more and about 800 °C or less after forming the transistor 200B.

[0342] In addition, as described above, by adding an element that forms oxygen defects to the region 243 and performing a heat treatment, the oxygen defects contained in the region 243 can sometimes capture hydrogen contained in the region 234 that serves as a channel formation region. Thereby, the transistor 200B can have stable electrical characteristics and its reliability can be improved.

[0343] In addition, in Figure 14A , the region 243 is formed near the interface between the oxide 230b and the insulator 254 in the thickness direction of the oxide 230b, but is not limited thereto. For example, the thickness of the region 243 may be substantially the same as the thickness of the oxide 230b, and the region 243 may also be formed in the oxide 230a. In addition, in Figure 14A , the region 243 is only formed in the region 231, but is not limited thereto. For example, the region 243 may also be formed in the region 231 and the region 232 or in a part of the region 231 and the region 232, and may also be formed in a part of the region 231, the region 232, and the region 234.

[0344] In the oxide 230, it is sometimes difficult to clearly observe the boundaries of the respective regions. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not have to change stepwise for each region, and may gradually change (also referred to as gradation) in each region. That is, the closer to the channel formation region, the smaller the concentrations of metal elements and impurity elements such as hydrogen and nitrogen can be.

[0345] In addition, as Figure 13BAs shown, an insulator 254 is preferably provided between the insulator 224, the oxides 230a and 230b, and the insulator 280. Here, the insulator 254 preferably contacts the top and side surfaces of the region 243a, the top and side surfaces of the region 243b, the side surfaces of the oxides 230a and 230b, the side surface of the insulator 224, and the top surface of the insulator 222. By adopting the above structure, the insulator 280 is separated from the insulator 224, the oxides 230a and 230b by the insulator 254. Thereby, entry of impurities such as hydrogen in the insulator 280, the insulator 281, etc. into the insulator 224, the oxides 230a and 230b can be suppressed.

[0346] In addition, the insulator 254 may adopt a stacked structure including an insulator 254a and an insulator 254b. In this case, the insulator 254a is preferably provided in a manner that contacts the top and side surfaces of the region 243a, the top and side surfaces of the region 243b, the side surfaces of the oxides 230a and 230b, the side surface of the insulator 224, and the top surface of the insulator 222. In addition, the insulator 254b is preferably provided on the insulator 254a in a manner that contacts the insulator 280. When the insulator 254 has the above stacked structure, one of the insulator 254a and the insulator 254b may have a function of suppressing hydrogen diffusion, and the other may have a function of suppressing oxygen diffusion.

[0347] In addition, the insulator 254a may have a function of supplying oxygen to the insulator 224, the oxides 230a and 230b.

[0348] The insulator 274 contacts the top surfaces of each of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280. In addition, as Figure 14A shown, in the transistor 200B of one embodiment of the present invention, the insulator 274 contacts the insulator 250. By adopting such a structure, entry of impurities such as hydrogen in the insulator 281, etc. into the insulator 250 can be suppressed. Thereby, negative impacts on the electrical characteristics of the transistor and the reliability of the transistor can be suppressed.

[0349] In addition, Figure 14B shows Figure 13C an enlarged view of a partial region of the transistor 200B shown. As Figure 13C and Figure 14BAs shown, in the channel width direction of the transistor 200B, with the bottom surface of the insulator 222 as a reference, the bottom surface height of the conductor 260 in the region where the oxide 260 and the oxide 230b do not overlap is preferably lower than the bottom surface height of the oxide 230b. By adopting a structure in which the conductor 260 used as a gate electrode covers the side and top surfaces of the oxide 230b in the channel formation region through the oxide 230c and the insulator 250, the structure makes it easy for the electric field of the conductor 260 to act on the entire region 234 of the oxide 230b. As a result, the on-state current of the transistor 200B can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is recorded as T2, and T2 is greater than 0nm and less than 100nm, preferably greater than 3nm and less than 50nm, and more preferably greater than 5nm and less than 20nm.

[0350] In addition, if Figure 14B As shown, in the channel width direction of the transistor 200B, it is preferred that at least a portion of the oxide 230c in the region that does not overlap with the oxide 230b, the oxide 230a, and the insulator 224 is in contact with the insulator 222. By adopting this structure, it is possible to prevent the oxygen in the oxide 230c from diffusing to the outside of the transistor 200B through the insulator 224. Alternatively, it is possible to prevent the oxygen in the oxide 230b and the oxide 230a from diffusing to the outside of the transistor 200B through the insulator 224. Alternatively, by reducing the area of ​​the insulator 224, the amount of oxygen entering the insulator 224 is reduced, thereby suppressing the reduction in the amount of oxygen supplied to the oxide 230. Thus, the oxygen in the oxide 230c can be efficiently supplied to the oxide 230b and the oxide 230a, thereby suppressing the low resistance of the oxide 230 in the region 234. Thus, it is possible to suppress the variation of the electrical characteristics of the transistor and achieve stable electrical characteristics while improving reliability.

[0351] Alternatively, by adopting the above structure, it is possible to suppress impurities such as hydrogen in the insulator 224 from being mixed into the oxide 230. In other words, it is possible to suppress the low resistance of the oxide 230. Thus, it is possible to suppress the variation of the electrical characteristics of the transistor and achieve stable electrical characteristics while improving reliability. In addition, this structure can be formed by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a.

[0352] In addition, if Figure 14BAs shown, it is preferable to remove the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a, thereby forming the insulator 224 into an island shape similar to the oxide 230a and the oxide 230b. By adopting this structure, in the channel width direction of the transistor 200B, based on the bottom surface of the insulator 222, it is easy to make the bottom surface height of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 lower than the bottom surface height of the oxide 230b. Thereby, the on-state current of the transistor 200B can be increased, and thus the frequency characteristics can be improved.

[0353] By adopting the above structure, a semiconductor device including a transistor with a large on-state current can be provided. In addition, a semiconductor device including a transistor with high frequency characteristics can be provided. In addition, a semiconductor device with improved reliability while suppressing variations in electrical characteristics to have stable electrical characteristics can be provided. In addition, a semiconductor device including a transistor with a low off-state current can be provided.

[0354] The detailed structure of the semiconductor device including the transistor 200B according to one aspect of the present invention will be described below. In addition, for the detailed contents of the constituent elements, materials, etc. of the semiconductor device shown in the present embodiment that are used in common with the constituent elements, materials, etc. of the semiconductor device shown in the above embodiment, and the detailed contents of the constituent elements, materials, etc. with the same reference numerals, reference can be made to the description of the above embodiment.

[0355] The oxides 230b and 230c preferably have crystallinity. For example, CAAC-OS is preferably used. Oxides with crystallinity such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen defects). By having the oxide 230, the transistor 200B is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0356] As Figure 13B and Figure 13C shown, the insulator 254 preferably contacts a part of the side surface of the oxide 230c, the top surface and the side surface of the region 243a, and the top surface and the side surface of the region 243b, that is, preferably contacts a part of the top surface and a part of the side surface of the oxide 230b, the side surface of the oxide 230a, the side surface of the insulator 224, and the top surface of the insulator 222. By adopting this structure, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 254. Thereby, diffusion of hydrogen in the insulator 280 from the top surface or the side surface of the oxide 230a, the oxide 230b, and the insulator 224 to the oxide 230 can be suppressed, and thus the transistor 200B can have good electrical characteristics and reliability.

[0357] In addition, as will be described later, the insulator 254 can also be used as a protective film when forming the regions 243a and 243b. When ion implantation or ion doping is used to form the regions 243a and 243b, by providing the insulator 254 as a protective film, the surface of the oxide 230 is not directly exposed to ions or plasma, so damage to the oxide 230 when forming the regions 243a and 243b can be suppressed, which is therefore preferable. Here, the damage to the oxide 230 means that oxygen vacancies are excessively formed in the oxide 230 or the crystallinity of the oxide 230 is excessively reduced. For example, as the insulator 254, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores, etc. can preferably be used.

[0358] In addition, in the present embodiment, the insulator 254 has a stacked structure. When the insulator 254 has a stacked structure of the insulator 254a and the insulator 254b, for example, the insulator 254a can be formed by sputtering in an oxygen-containing atmosphere, and then the insulator 254b can be formed by ALD method. The ALD method is a film-forming method with good coverage, and disconnection and the like caused by the unevenness of the insulator 254a can be prevented. Note that the insulator 254a and the insulator 254b can use the same material selected from the above materials, or different materials. For example, a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be adopted. In addition, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. Although an example in which the insulator 254 has a bilayer structure is shown in FIG. 13, it can also have a single-layer structure or a stacked structure of three or more layers.

[0359] The insulator 280 is provided on the insulator 222, the insulator 224, and the oxide 230 with the insulator 254 interposed therebetween.

[0360] In addition, the insulator 241a is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and the first conductor of the conductor 240a is formed in contact with its side surface. The region 243a is located at least in part at the bottom of the opening, and the conductor 240a is in contact with the region 243a. Similarly, the insulator 241b is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and the first conductor of the conductor 240b is formed in contact with its side surface. The region 243b is located at least in part at the bottom of the opening, and the conductor 240b is in contact with the region 243b.

[0361] When a laminated structure is adopted for the conductor 240, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used as the conductor in contact with the oxide 230a, the oxide 230b, the insulator 254, the insulator 280, the insulator 274, and the insulator 281.

[0362] <Method of manufacturing a semiconductor device>

[0363] Next, a method of manufacturing a semiconductor device including the transistor 200B according to one embodiment of the present invention shown in FIG. 13 will be described with reference to FIGS. 15 to 22. In FIGS. 15 to 22, A in each drawing shows a plan view. In addition, B in each drawing shows a cross-sectional view of the portion corresponding to the portion shown by the dotted line A1 - A2 in A, and is also a cross-sectional view in the channel length direction of the transistor 200B. In addition, C in each drawing shows a cross-sectional view of the portion corresponding to the portion shown by the dotted line A3 - A4 in A, and is also a cross-sectional view in the channel width direction of the transistor 200B. In addition, D in each drawing shows a cross-sectional view of the portion corresponding to the portion shown by the dotted line A5 - A6 in A, and is also a cross-sectional view near the region 243b of the transistor 200B. Note that, in the plan view of each drawing A, some components are omitted for clarity. In addition, note that the detailed description of the same parts as those in the first embodiment is omitted.

[0364] First, a substrate (not shown) is prepared, an insulator 214 is formed on the substrate, a conductor 205 and an insulator 216 are formed on the insulator 214, an insulator 222 is formed on the conductor 205 and the insulator 216, an insulating film 224A is formed on the insulator 222, and an oxide film 230A and an oxide film 230B are sequentially formed on the insulating film 224A (see FIG. 15).

[0365] Note that the processes up to the formation of the oxide film 230B in the method of manufacturing the semiconductor device including the transistor 200B are the same as those of the semiconductor device including the transistor 200 shown in the first embodiment, so the detailed description of the processes up to the formation of the oxide film 230B is omitted.

[0366] Next, the insulating film 224A, the oxide film 230A, and the oxide film 230B are processed into an island shape to form the insulator 224, the oxide 230a, and the oxide 230b. In addition, in this process, the thickness of the region of the insulator 222 that does not overlap with the insulator 224 may become thinner (see FIG. 16).

[0367] Here, the insulator 224, the oxide 230a, and the oxide 230b are formed such that at least a part of them overlaps with the conductor 205. In addition, the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are substantially perpendicular to the top surface of the insulator 222, when a plurality of transistors 200B are provided, miniaturization and high density can be achieved. Alternatively, a structure in which the angle formed by the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and the top surface of the insulator 222 is relatively low can also be employed. In this case, the angle formed by the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and the top surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 254 and the like in the subsequent processes can be improved, and defects such as voids can be reduced.

[0368] In addition, a curved surface exists between the side surface and the top surface of the oxide 230b. That is to say, the end of this side surface and the end of this top surface are preferably curved (hereinafter, also referred to as rounded). For example, at the end of the oxide 230b, this curved surface has a radius of curvature of 3 nm or more and 10 nm or less, and more preferably 5 nm or more and 6 nm or less. When the end does not have a corner, the coverage of the film in the subsequent film formation process can be improved.

[0369] In addition, the processing of the insulating film 224A, the oxide film 230A, and the oxide film 230B can be performed by photolithography. In addition, as this processing, dry etching or wet etching can be used. The processing using dry etching is suitable for microfabrication. In addition, the insulating film 224A, the oxide film 230A, and the oxide film 230B can be formed under different conditions from each other.

[0370] In addition, due to processing such as dry etching, impurities such as etching gases may adhere to the surfaces of the oxide 230a, the oxide 230b, etc. or diffuse into the oxide 230a, the oxide 230b, etc. Examples of the impurities include fluorine, chlorine, etc.

[0371] In order to remove the above-mentioned impurities and the like, washing is performed. As the washing method, there are wet washing using a washing liquid or the like, plasma treatment using plasma, and washing using heat treatment, etc., and the above-mentioned washing can also be appropriately combined.

[0372] As the wet washing, an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water can be used for washing treatment. Alternatively, ultrasonic washing can be performed using pure water or carbonated water. In the present embodiment, ultrasonic washing is performed using pure water or carbonated water.

[0373] Next, heat treatment can also be performed. The heat treatment can adopt the conditions of the above-mentioned heat treatment. In addition, it is preferable to perform the heat treatment before forming the insulating film 254A. The heat treatment is preferably performed at a temperature of 100°C or higher and 400°C or lower. For example, the heat treatment can be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film formation temperature of the insulating film 254A. Here, the film formation temperature is used not only to represent the substrate temperature when forming the film but also to represent the set temperature of the film formation apparatus. For example, when forming the insulating film 254A at a temperature of 200°C, the temperature of this heat treatment is preferably 200°C. This heat treatment is preferably performed under reduced pressure, and for example, it can also be performed in a vacuum atmosphere. By exhausting gas using a turbo molecular pump or the like, a vacuum atmosphere is maintained. In a vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0374] Next, an insulating film 254A that becomes the insulator 254a is formed on the insulator 222, insulator 224, oxide 230a, and oxide 230b (see FIG. 16). The insulating film 254A can be formed by a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. The insulating film 254A preferably uses an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. In this embodiment, a silicon nitride film is formed by a sputtering method.

[0375] Next, an insulating film 254B that becomes the insulator 254b is formed on the insulating film 254A (see FIG. 16). The insulating film 254B can be formed by a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. The insulating film 254B preferably uses an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For example, it is preferable to form an aluminum oxide film by a sputtering method. By adopting the sputtering method and using a gas containing oxygen to form the aluminum oxide film, oxygen can be introduced into the insulator 224. That is, the insulator 224 can be made to contain excess oxygen.

[0376] In addition, in order to form the insulating film 254B, aluminum oxide can also be formed while heating the substrate at a high temperature. The substrate heating temperature when forming the insulating film 254B can be 200°C or higher, preferably 250°C or higher, and more preferably 350°C or higher. In this embodiment, an aluminum oxide film is formed by a sputtering method.

[0377] Next, a dummy gate film that will become the dummy gate layer 262A is formed on the insulating film 254B. This dummy gate film is processed and used as a dummy gate. A dummy gate refers to a virtual gate electrode. That is, by processing this dummy gate film, a virtual gate electrode is formed, and in subsequent processes, this dummy gate is removed and replaced with a gate electrode formed of a conductive film or the like. Therefore, it is preferable to use a film that is easy to perform microfabrication and removal processing as this dummy gate film.

[0378] The above dummy gate film can be formed using sputtering, CVD, MBE, PLD, ALD, etc. For example, an insulator, semiconductor, or conductor can be used. Specifically, a silicon film such as polysilicon, microcrystalline silicon, or amorphous silicon, a metal film such as aluminum, titanium, or tungsten, etc. can be used. In addition, a film containing carbon, SOG (Spin On Glass), a resin film, etc. can also be formed using a coating method. As a material for the resin film, for example, photoresist, polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, acrylic resin, etc. can be cited. By forming SOG or a resin film using a coating method, the surface of the above dummy gate film can be made flat. Thus, by making the surface of the dummy gate film flat, microfabrication and removal processing become easy.

[0379] In addition, the above dummy gate film can use a multilayer film composed of films of different types. For example, a two-layer structure film composed of a conductive film and a resin film on this conductive film can be used as this dummy gate film. Because a dummy gate film having such a structure is used, for example, in a subsequent CMP process, this conductive film is sometimes used as a stop film for CMP processing. In addition, since the end point of CMP processing can sometimes be detected, processing unevenness can be reduced.

[0380] Next, the above dummy gate film is etched using photolithography to form the dummy gate layer 262A (see FIG. 17). At least a part of the dummy gate layer 262A overlaps with the conductor 205 and the oxide 230.

[0381] Next, the dummy gate layer 262A is used as a mask to add a dopant 257 to the oxide 230b (see FIG. 17). As a result, regions 243a and 243b containing the dopant 257 are formed in regions of the oxide 230b that do not overlap with the dummy gate layer 262A. Note that in FIG. 17, a case where the region of the oxide 230b that overlaps with the dummy gate layer 262A is not doped with the dopant 257 is shown. However, this embodiment is not limited to this. For example, sometimes the dopant 257 diffuses and is added to the region that overlaps with the dummy gate layer 262A (for example Figure 14AIn this case, the region 243a and a portion of the region 243b are formed in a region overlapping with the dummy gate layer 262A. In this way, the distance between the region 243a and the region 243b, that is, the channel length, can be controlled.

[0382] As a method for adding dopant 257, the following can be used: ion implantation method in which the ionized source gas is mass separated and then added; ion doping method in which the ionized source gas is not mass separated and then added; and plasma immersion ion implantation method, etc. When mass separation is performed, the added ion species and their concentration can be strictly controlled. On the other hand, when mass separation is not performed, a high concentration of ions can be added in a short time. In addition, an ion doping method in which ionization is performed by generating clusters of atoms or molecules can also be used. Note that dopants can also be referred to as ions, donors, acceptors, impurities, elements, etc.

[0383] As dopant 257, elements that form the above-mentioned oxygen defects or elements that bond to oxygen defects can be used. Such elements are typically boron or phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium and rare gases can be used. Typical examples of rare gases include helium, neon, argon, krypton and xenon. In addition, any one or more of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum can be added. Among the above-mentioned metal elements, boron and phosphorus are preferably used as dopant 257. When boron and phosphorus are used as dopant 257, the device of the production line of amorphous silicon or low-temperature polysilicon can be used, thereby reducing the equipment investment.

[0384] 17 , the dopant 257 is added to the top surface of the insulator 214 in a manner substantially perpendicular to the top surface of the insulator 214, but the invention is not limited thereto, and the dopant 257 may be added to the top surface of the insulator 214 in a manner oblique to the top surface of the insulator 214. By adding the dopant in a manner oblique to the top surface of the insulator 214, the region 243a and the region 243b can be easily formed in a part of the region overlapping with the dummy gate layer 262A.

[0385] In addition, in the manufacturing method of this embodiment, the dopant 257 is added to the oxide 230 via the insulating film 254A and the insulating film 254B. Since this manufacturing method is adopted, the dopant 257 is also added to the insulating film 254A and the insulating film 254B. That is, the oxide 230 and the insulating film 254A and the insulating film 254B all have the element contained in the dopant 257. In addition, when the insulating film 254A and the insulating film 254B have excess oxygen, the dopant 257 may suppress the diffusion of the excess oxygen to the outside.

[0386] As described above, by forming the region 243, the conductor 260 formed in a subsequent process can be disposed in a self-aligned manner between the regions 243a and 243b.

[0387] Next, an insulating film 280A that becomes the insulator 280 is formed on the insulating film 254B and the dummy gate layer 262A (see FIG. 18). The insulating film 280A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0388] Next, a part of the insulating film 280A and a part of the dummy gate layer 262A are removed until a part of the dummy gate layer 262A is exposed to form the insulator 280 and the dummy gate 262 (see FIG. 19). The insulator 280 and the dummy gate 262 are preferably formed by CMP processing.

[0389] In addition, for example, by using a film having a structure in which a first layer and a second layer formed on the first layer are used as the dummy gate layer 262A, the first layer is sometimes used as a stop film for CMP processing in the CMP process. In addition, since the termination point of the CMP processing of the first layer can sometimes be detected, the non-uniformity of the height of the dummy gate 262 can be reduced. As Figure 19B shown, the top surface of the dummy gate 262 and the top surface of the insulator 280 are substantially the same.

[0390] Next, the dummy gate 262 and a part of the insulating film 254A and the insulating film 254B overlapping the dummy gate 262 are removed to form an opening 263 (see FIG. 20). The dummy gate 262, the insulating film 254A, and the insulating film 254B can be removed by performing a wet etching, a dry etching, an ashing, or the like. Alternatively, the above processes can be appropriately combined. For example, a wet etching process or the like can also be performed after the ashing process. By removing a part of the insulating film 254A and the insulating film 254B, the insulators 254a and 254b are formed. By removing the dummy gate 262, the insulating film 254A, and the insulating film 254B, a part of the surface of the oxide 230b is exposed from the opening 263. At this time, it is possible that a part of the surface of the region 243 is exposed from the opening 263.

[0391] Next, a heat treatment is preferably performed before forming the oxide film 230C1. The heat treatment is preferably performed at a temperature of 100°C or higher and 400°C or lower. For example, the heat treatment can be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film formation temperature of the oxide film 230C1 or the oxide film 230C2. Here, the film formation temperature is used not only to represent the substrate temperature during film formation but also to represent the set temperature of the film formation apparatus. For example, when forming the oxide film 230C1 or the oxide film 230C2 at a temperature of 300°C, the temperature of this heat treatment is preferably 300°C. This heat treatment is preferably performed under reduced pressure, and for example, it can also be performed in a vacuum atmosphere. By exhausting gas using a turbo molecular pump or the like, a vacuum atmosphere is maintained. In the vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0392] Next, the oxide film 230C1 and the oxide film 230C2 are sequentially formed so as to embed the opening 263 (see FIG. 21). In addition, it is preferable to continuously form the oxide film 230C1 and the oxide film 230C2 without being exposed to the atmosphere after performing the above heat treatment. For example, it is preferable to continuously perform the heat treatment and the film formation treatment in different processing chambers using the following multi-chamber film formation apparatus or the like. By performing such a treatment, impurities such as moisture, hydrogen, and carbon adsorbed on the surfaces of the oxides 230a and 230b can be removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be further reduced. The impurities removed by the heat treatment include impurities containing a bond between hydrogen and carbon or a bond between hydrogen and oxygen. Furthermore, by continuously performing the heat treatment and the film formation treatment without being exposed to the outside air, it is possible to prevent impurities such as hydrogen from invading the oxide 230 again.

[0393] The oxide films 230C1 and 230C2 can be formed by methods such as sputtering, CVD, MBE, PLD, or ALD. The oxide films that become the oxide films 230C1 and 230C2 can be formed using the same film-forming method as the oxide film 230A or 230B according to the required characteristics of the oxide films 230C1 and 230C2. As the oxide films 230C1 and 230C2, In-Ga-Zn oxide or an oxide not containing In can be used. As the oxide not containing In, Ga-Zn oxide, gallium oxide, etc. can be used. In addition, as the oxide films 230C1 and 230C2, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can also be used. The oxide films 230C1 and 230C2 are formed using an oxide target with In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 4:2:4.1 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] by sputtering. In this embodiment, the oxide film 230C1 is formed using an oxide target with In:Ga:Zn = 4:2:4.1 [atomic ratio] by sputtering, and the oxide film 230C2 is formed using an oxide target with In:Ga:Zn = 1:3:4 [atomic ratio] by sputtering.

[0394] That is, the same target as the target used for forming the oxide film 230B can be used to form the oxide film 230C1, and the same target as the target used for forming the oxide film 230A can be used to form the oxide film 230C2.

[0395] Preferably, the oxide films 230C1 and 230C2 are formed while heating the substrate. At this time, by setting the substrate temperature to 300 °C or higher, oxygen defects in the oxide 230a, oxide 230b, and oxide films 230C1 and 230C2 can be reduced. In addition, for example, it can be formed at the same temperature as the film-forming temperature of the insulating film 250A described later. By forming the film while heating the substrate in this way, the crystallinity of the oxide 230a, oxide 230b, and oxide films 230C1 and 230C2 can also be improved.

[0396] In particular, when forming the oxide films 230C1 and 230C2, a part of the oxygen contained in the sputtering gas is sometimes supplied to the oxides 230a and 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide films 230C1 and 230C2 can be 70% or more, preferably 80% or more, and more preferably 100%. In addition, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

[0397] Next, a heat treatment is preferably performed before forming the insulating film 250A. The heat treatment is preferably performed at a temperature of 100°C or higher and 400°C or lower. For example, the heat treatment can be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film formation temperature of the insulating film 250A. Here, the film formation temperature is used not only to represent the substrate temperature during film formation but also to represent the set temperature of the film formation apparatus. For example, when forming the insulating film 250A at a temperature of 350°C, the temperature of this heat treatment is preferably 350°C. This heat treatment is preferably performed under reduced pressure, and for example, it can also be performed in a vacuum atmosphere. By exhausting gas using a turbo molecular pump or the like, a vacuum atmosphere is maintained. In the vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0398] Next, an insulating film 250A (see FIG. 21) is formed. The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, it is preferably formed of silicon oxide, hafnium oxide, gallium oxide, or the like by the ALD method. For example, as the insulating film 250A, a stacked film of silicon oxide and gallium oxide on silicon oxide can be used. Note that the film formation temperature when forming the insulating film 250A is preferably 300°C or higher and lower than 450°C, and preferably 350°C or higher and 400°C or lower. For example, by forming the insulating film 250A at a temperature of 400°C, a dense film with few impurities can be formed.

[0399] In addition, by using microwave-excited oxygen to generate high-density oxygen plasma and exposing the insulating film 250A to this oxygen plasma, oxygen can be introduced into the insulating film 250A.

[0400] In addition, a heat treatment can also be performed. The heat treatment can be performed using the above heat treatment conditions. By this heat treatment, the moisture concentration and hydrogen concentration in the insulating film 250A can be reduced.

[0401] Next, a conductive film 260A and a conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, or the like. For example, the CVD method is preferably used. In the present embodiment, the conductive film 260A is formed by the ALD method, and the conductive film 260B is formed by the CVD method (see FIG. 21).

[0402] Next, the oxide film 230C1, the oxide film 230C2, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c (oxide 230c1 and oxide 230c2), the insulator 250, and the conductor 260 (conductor 260a and conductor 260b) (see FIG. 22). Thus, the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the opening that reaches the oxide 230b. The insulator 250 is arranged so as to cover the inner wall of the above-mentioned opening via the oxide 230c. In addition, the conductor 260 is arranged so as to be embedded in the above-mentioned opening via the oxide 230c and the insulator 250.

[0403] Next, heat treatment may also be performed. The heat treatment is preferably performed at a temperature of 100°C to 400°C. For example, the heat treatment may be performed at 200°C. Alternatively, it is preferably performed at the same temperature as the film forming temperature of the insulator 274. Here, the film forming temperature is used not only to indicate the substrate temperature when the film is formed, but also to indicate the set temperature of the film forming device. For example, when the insulator 274 is formed at 250°C, the temperature of the heat treatment is preferably 250°C. The heat treatment is preferably performed under reduced pressure, for example, it may be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting gas using a turbomolecular pump or the like. In the vacuum atmosphere, the pressure of the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less. By this heat treatment, the water concentration and hydrogen concentration in the insulator 280 can be reduced.

[0404] Next, an insulator 274 may be formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The film formation of the insulator 274 may be performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the insulator 274 is preferably formed by forming an aluminum oxide film by a sputtering method. By forming the aluminum oxide film by a sputtering method, it is sometimes possible to suppress the diffusion of hydrogen in the insulator 281 to the oxide 230. In addition, by forming the insulator 274 in contact with the conductor 260, it is possible to suppress the oxidation of the conductor 260, which is therefore preferred. In addition, by forming the insulator 274, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 is sometimes supplied to the region 234 in the oxide 230b through the oxide 230c1. In addition, by supplying oxygen to the insulator 280 , oxygen contained in the insulator 280 before the insulator 274 is formed may be supplied to the region 234 in the oxide 230 b through the oxide 230 c 1 .

[0405] Next, heat treatment can be performed. As the heat treatment, the above heat treatment conditions can be utilized. Through this heat treatment, the moisture concentration and hydrogen concentration of the insulator 280 can be reduced. In addition, oxygen in the insulator 274 can be implanted into the insulator 280.

[0406] In addition, as a method of forming the insulator 274 on the insulator 280, first, an insulating film made of the same material as the insulator 274 is formed using the same formation method as the insulator 274. Then, heat treatment is performed using the above heat treatment conditions. Then, this insulating film is removed by CMP treatment. Next, the insulator 274 is formed. Then, heat treatment can be performed using the above heating conditions. Through this method, an excess oxygen region can be formed in the insulator 280. Note that in this step of removing the insulating film, a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.

[0407] In addition, an insulator can also be provided between the insulator 280 and the insulator 274. As this insulator, for example, silicon oxide formed by sputtering can be used. By providing this insulator, an excess oxygen region can be formed in the insulator 280.

[0408] Next, an insulator 281 that becomes an insulating film can also be formed on the insulator 274. The insulator 281 that becomes an insulating film can be formed by sputtering, CVD method, MBE method, PLD method, ALD method, etc. (refer to FIG. 22).

[0409] Next, openings reaching the region 243a and the region 243b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281. This opening can be formed using photolithography.

[0410] Note that in the semiconductor device including the transistor 200B, the steps after forming the above opening are the same as those of the semiconductor device including the transistor 200 shown in the first embodiment. Therefore, the detailed description of the steps after forming the above opening is omitted.

[0411] According to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high-frequency characteristics can be provided. In addition, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. In addition, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a small off-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0412] As described above, the structures, methods, etc. shown in this embodiment can be implemented in appropriate combination with those shown in other embodiments.

[0413] (Embodiment 3)

[0414] In this embodiment, with reference to Figures 23 to 26 one aspect of the semiconductor device will be described.

[0415] [Storage device 1]

[0416] Figure 23 An example of a semiconductor device (storage device) using a transistor according to one aspect of the present invention is shown. In the semiconductor device according to one aspect of the present invention, a transistor 200 is disposed above a transistor 300, and a capacitor 100 is disposed above the transistor 300 and the transistor 200. In addition, as the transistor 200, the transistor 200 described in the above embodiment or the like can be used.

[0417] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, by using it in a storage device, the stored content can be maintained for a long time. In other words, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

[0418] In Figure 23In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. In addition, wiring 1003 is electrically connected to either the source or the drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and the drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Note that hereinafter, the node where the gate of transistor 300, the other of the source and the drain of transistor 200 are connected to one of the electrodes of capacitor 100 may sometimes be referred to as node FG.

[0419] Figure 23 The semiconductor device shown has the property that the potential of the gate (node FG) of transistor 300 can be held by the switching of transistor 200, and thus data can be written, held, and read out.

[0420] In addition, by Figure 23 configuring the storage device shown in a matrix form, a memory cell array can be formed.

[0421] <Transistor 300>

[0422] Transistor 300 is provided on substrate 311 and includes a conductor 316 serving as a gate electrode, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed of a part of substrate 311, and low-resistance regions 314a and 314b serving as a source region or a drain region. Transistor 300 can be of p-channel type or n-channel type.

[0423] Here, in Figure 23 transistor 300 shown, the semiconductor region 313 (a part of substrate 311) where a channel is formed has a convex shape. In addition, conductor 316 is provided so as to cover the side surface and the top surface of semiconductor region 313 with insulator 315 interposed therebetween. In addition, a material for adjusting the work function can be used for conductor 316. Because of the convex portion of the semiconductor substrate, such transistor 300 is also referred to as a FIN type transistor. In addition, an insulator of a mask for forming the convex portion may be provided in contact with the upper surface of the convex portion. Furthermore, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, an SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0424] Note that Figure 23 the structure of transistor 300 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or the driving method.

[0425] <Capacitor 100>

[0426] The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric.

[0427] In addition, for example, the conductor 112 and the conductor 110 disposed on the conductor 240 can be formed simultaneously. Further, the conductor 112 serves as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0428] In Figure 23 the conductor 112 and the conductor 110 have a single-layer structure, but are not limited to this structure and may have a laminated structure of two or more layers. For example, a conductor having high tightness between a conductor having a barrier property and a conductor having high conductivity can be formed between the conductor having a barrier property and the conductor having high conductivity.

[0429] In addition, the insulator 130 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and is provided in a laminated or single-layer form.

[0430] For example, the insulator 130 preferably uses a laminated structure of a material having high insulation breakdown voltage such as silicon oxynitride and a high dielectric constant (high-k) material. By adopting this structure, the capacitor 100 can include a high dielectric constant (high-k) insulator to ensure sufficient capacitance and can include an insulator having high insulation breakdown voltage to improve the insulation breakdown voltage, thereby suppressing electrostatic breakdown of the capacitor 100.

[0431] Note that as an insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant), there are gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, a nitride containing silicon and hafnium, etc.

[0432] On the other hand, as a material having high insulation breakdown voltage (a material having a low relative dielectric constant), there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, resin, etc.

[0433] <Wiring layer>

[0434] A wiring layer including an interlayer film, wirings, plugs, etc. may also be provided between the respective structures. In addition, the wiring layer may be provided as multiple layers according to the design. Here, in a conductor having the function of a plug or a wiring, multiple structures are sometimes denoted by the same reference numeral. In addition, in this specification and the like, a wiring and a plug electrically connected to the wiring may also be one component. That is to say, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.

[0435] For example, on a substrate 311, insulators 320, 322, 324, and 326 are sequentially stacked as an interlayer film. The insulator 315 and the conductor 316 are provided in such a manner as to be embedded in the insulator 320. In addition, conductors 328, 330, etc. electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. In addition, the conductors 328 and 330 are used as plugs or wirings.

[0436] In addition, the insulator used as the interlayer film can be used as a planarization film covering the uneven shape below it. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by a planarization process such as a chemical mechanical polishing (CMP) method.

[0437] A wiring layer may also be provided on the insulator 326 and the conductor 330. For example, in Figure 23 insulators 350, 352, and 354 are sequentially stacked. In addition, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 is used as a plug or a wiring.

[0438] Insulators 210, 212, 214, and 216 are sequentially stacked on the insulator 354 and the conductor 356. In addition, conductors 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. In addition, the conductor 218 is used as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided on the conductor 120 and the insulator 130.

[0439] As the insulator that can be used as the interlayer film, there are oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc. having insulation properties.

[0440] For example, by using a material with a low relative dielectric constant for the insulator used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0441] For example, insulators such as insulator 212, insulator 352, and insulator 354 are preferably insulators having a low relative dielectric constant. For example, the insulator preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, resin, etc. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride have thermal stability, a laminated structure having thermal stability and a low relative dielectric constant can be achieved by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, acrylic resin, etc.

[0442] In addition, the resistivity of one or both of insulator 130 and insulator 150 provided on conductor 112 or conductor 120 is 1.0×10 12 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more and 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more and 5.0×10 13 Ωcm or less of the insulator. When one or both of insulator 130 and insulator 150 have the above resistivity, while maintaining the insulation of the insulator, the charge between the wiring of accumulation transistor 200, transistor 300, capacitor 100, conductor 112, conductor 120, etc. is dispersed, and it is possible to suppress the deterioration of the characteristics of the transistor and the storage device including the transistor and electrostatic breakdown caused by the charge, so it is preferred. As the above insulator, silicon nitride or silicon nitride oxide can be used.

[0443] In addition, as the insulator having the above resistivity, insulator 140 can also be provided under conductor 112. In this case, insulator 140 is formed on insulator 281, and openings are formed in insulator 140, insulator 281, insulator 274, insulator 280, insulator 254, etc., and insulator 241 is formed in the opening and conductor 240 electrically connected to transistor 200, conductor 218, etc. can be formed. Insulator 140 can use the same material as insulator 130 or insulator 150.

[0444] In addition, by surrounding a transistor using an oxide semiconductor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, as the insulator 210, the insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

[0445] As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. may be used.

[0446] As the conductor that can be used for wiring and plugs, a material containing one or more of the metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium is preferably used. In addition, a semiconductor with high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide may also be used.

[0447] For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 110, the conductor 112, and the conductor 120, etc., a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials may be used in a single layer or a stacked layer. A high melting point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used, and tungsten is particularly preferably used. Or, it is preferably formed of a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0448] "Wiring or Plug Provided with a Layer of Oxide Semiconductor"

[0449] Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may sometimes be provided near the oxide semiconductor. In this case, it is preferable to provide a blocking insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0450] For example, in Figure 23 , it is preferable to provide the insulator 241 between the insulators 280 and 281 and the conductor 240. Since the insulator 241 exists between the insulators 280 and 281 and the conductor 240, oxidation of the conductor 240, that is, absorption of oxygen contained in the insulators 280 and 281 by the conductor 240 can be suppressed.

[0451] That is to say, by providing the insulator 241, absorption of excess oxygen contained in the insulator 280 by the conductor 240 can be suppressed. In addition, by having the insulator 241, diffusion of hydrogen as an impurity through the conductor 240 into the transistor 200 can be suppressed.

[0452] In addition, as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen is preferably used. For example, alumina, hafnium oxide, etc. are preferably used. In addition, for example, metal oxides such as magnesia, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. can also be used.

[0453] The above is the description of the structural example. By adopting this structure, in a semiconductor device using a transistor including an oxide semiconductor, while suppressing electrical characteristic variations, reliability can be improved. In addition, a transistor including an oxide semiconductor having a large on-state current can be provided. In addition, a transistor including an oxide semiconductor having a small off-state current can be provided. In addition, a semiconductor device with reduced power consumption can be provided.

[0454] [Storage device 2]

[0455] Figure 24 An example of a semiconductor device (storage device) using a transistor as one mode of the present invention is shown. In a semiconductor device of one mode of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. In addition, as the transistor 200, the transistor 200B etc. described in the above embodiment can be used.

[0456] Note that in the semiconductor device (storage device) shown in [Storage device 2], the same reference signs are attached to structures having the same functions as the structures constituting the semiconductor device (storage device) shown in [Storage device 1]. In addition, for the detailed description of the structures, materials, etc. of the semiconductor device (storage device) shown in [Storage device 2] that are common to the structures, materials, etc. of the semiconductor device (storage device) shown in [Storage device 1], and for the detailed description of the structures, materials, etc. to which the same reference signs are attached, reference can be made to the previous description.

[0457] [Storage device 3]

[0458] Figure 25 An example of a storage device using a semiconductor device as one mode of the present invention is shown. Figure 25 The storage device shown includes, in addition to Figure 23 the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown, a transistor 400.

[0459] The transistor 400 can control the second gate voltage of the transistor 200. For example, a structure is adopted in which the first gate and the second gate of the transistor 400 are connected to the source diode, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is maintained in this structure, the voltage between the first gate and the source and the voltage between the second gate and the source of the transistor 400 become 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the negative potential of the second gate of the transistor 200 can be maintained for a long time even without supplying power to the transistor 200 and the transistor 400. Thus, the storage device including the transistor 200 and the transistor 400 can maintain the stored content for a long period of time.

[0460] Therefore, in Figure 25 the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. In addition, the wiring 1003 is electrically connected to either the source or the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. Furthermore, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the second gate of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

[0461] In addition, by arranging the storage device shown in Figure 25 in a matrix form in the same manner as the storage device shown in Figure 23 a memory cell array can be formed. Note that one transistor 400 can control the second gate voltages of a plurality of transistors 200. Therefore, it is preferable that the number of transistors 400 is less than the number of transistors 200.

[0462] <Transistor 400>

[0463] The transistor 400 is formed on the same layer as the transistor 200, and thus they can be manufactured simultaneously. The transistor 400 includes: conductors 460 (conductor 460a and conductor 460b) serving as a first gate electrode; conductors 405 (conductor 405a and conductor 405b) serving as a second gate electrode; insulators 222, insulator 424a, insulator 424b, and insulator 450 serving as gate insulators; an oxide 430c including a region where a channel is formed; conductors 442a, oxide 431a, and oxide 431b serving as one of a source and a drain; conductors 442b, oxide 432a, and oxide 432b serving as the other of the source and the drain; and conductors 440 (conductor 440a and conductor 440b).

[0464] In the transistor 400, the conductor 405 and the conductor 205 are formed on the same layer. The insulator 424a and the insulator 424b are formed on the same layer as the insulator 224. The oxide 431a and the oxide 432a are formed on the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are formed on the same layer as the oxide 230b. The conductor 442 and the conductor 242 are formed on the same layer. The oxide 430c and the oxide 230c are formed on the same layer. The insulator 450 and the insulator 250 are formed on the same layer. The conductor 460 and the conductor 260 are formed on the same layer.

[0465] Note that the structures formed on the same layer can be formed simultaneously. For example, the oxide 430c can be formed by processing the oxide film that becomes the oxide 230c.

[0466] Similar to the oxide 230 and the like, in the oxide 430c serving as the active layer of the transistor 400, oxygen defects and impurities such as water and hydrogen are reduced. Therefore, the threshold voltage of the transistor 400 can be made larger, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.

[0467] 《Scoring line》

[0468] Next, a scoring line (also referred to as a dividing line, breaking line, or truncating line) provided when a large-area substrate is divided into a plurality of semiconductor devices in a chip shape for each semiconductor element will be described. As a dividing method, for example, sometimes, first, a groove (scoring line) for dividing the semiconductor element is formed in the substrate, and then, the substrate is truncated at the scoring line to obtain a plurality of divided (divided) semiconductor devices.

[0469] At the edges of the transistor 200 shown in the above embodiment and the transistor 400 shown in this embodiment, as Figure 25As shown, insulator 254 and insulator 222 are in contact. Therefore, when designing with the region where insulator 254 and insulator 222 are in contact as the cutting line, the design freedom of the cutting line can be improved. At this time, the same material and the same method can also be used to form insulator 222 and insulator 254. By forming insulator 222 and insulator 254 using the same material and the same method, the tightness can be improved. For example, alumina is preferably used.

[0470] By adopting this structure, insulator 222 and insulator 254 can surround insulator 224, transistor 200, and transistor 400. Since insulator 222 and insulator 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided and processed into a plurality of chips according to each circuit region of the semiconductor element as shown in this embodiment, it is possible to prevent impurities such as water and hydrogen from mixing in from the side direction of the truncated substrate and diffusing into transistor 200 or transistor 400.

[0471] By adopting this structure, the excess oxygen in insulator 224 can be prevented from diffusing outside insulator 254 and insulator 222. Therefore, the excess oxygen in insulator 224 is efficiently supplied to the oxide forming the channel of transistor 200 or transistor 400. Through this oxygen, the oxygen defects of the oxide forming the channel of transistor 200 or transistor 400 can be reduced. As a result, the oxide forming the channel of transistor 200 or transistor 400 can be an oxide semiconductor with a low defect state density and stable characteristics. That is, the reliability can be improved while suppressing the variation of the electrical characteristics of transistor 200 or transistor 400.

[0472] [Storage device 4]

[0473] Figure 26 An example of a storage device using a semiconductor device as one mode of the present invention is shown. Figure 26 The storage device shown in addition to including Figure 24 the semiconductor device including transistor 200, transistor 300, and capacitor 100 shown also includes transistor 400.

[0474] Note that in the storage device shown in [Storage device 4], the same reference numerals are attached to the structures having the same functions as the structures constituting the storage device shown in [Storage device 3]. In addition, for the detailed description of the structures, materials, etc. of the storage device shown in [Storage device 4] that are common to the structures, materials, etc. of the storage device shown in [Storage device 3], and for the detailed description of the structures, materials, etc. to which the same reference numerals are attached, reference can be made to the previous description.

[0475] 〈Transistor 400〉

[0476] The transistor 400 is formed on the same layer as the transistor 200, and thus they can be manufactured simultaneously. The transistor 400 includes: conductors 460 (conductor 460a and conductor 460b) serving as a first gate electrode; conductors 405 (conductor 405a and conductor 405b) serving as a second gate electrode; insulators 222, insulator 424a, insulator 424b, and insulator 450 serving as a gate insulator; oxides 430c (oxide 430c1 and oxide 403c2) including a region where a channel is formed; regions 443a, oxide 431a, and oxide 431b serving as one of a source and a drain; regions 443b, oxide 432a, and oxide 432b serving as the other of the source and the drain; and conductors 440 (conductor 440a and conductor 440b).

[0477] In the transistor 400, the conductor 405 and the conductor 205 are formed on the same layer. The insulator 424a and the insulator 424b are formed on the same layer as the insulator 224. The oxide 431a and the oxide 432a are formed on the same layer as the oxide 230a. The oxide 431b and the oxide 432b are formed on the same layer as the oxide 230b. The regions 443a and the region 443b and the regions 243a and the region 243b are formed by the same process. The oxide 430c1 and the oxide 430c2 and the oxide 230c1 and the oxide 230c2 are respectively formed on the same layer. The insulator 450 and the insulator 250 are formed on the same layer. The conductor 460 and the conductor 260 are formed on the same layer.

[0478] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0479] (Embodiment 4)

[0480] In this embodiment, a storage device (hereinafter sometimes referred to as an OS storage device) using a transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor in which an oxide is used for a semiconductor according to one aspect of the present invention will be described with reference to FIGS. 27 and 28. The OS storage device is a storage device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS storage device has excellent holding characteristics and can thus be used as a non-volatile memory.

[0481] <Structural Example of Storage Device>

[0482] Figure 27A An example of the structure of the OS storage device is shown. The storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0483] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wirings. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above-mentioned wirings are the wirings connected to the memory cells included in the memory cell array 1470, and the details thereof will be described below. The amplified data signal is output to the outside of the memory device 1400 as the data signal RDATA through the output circuit 1440. In addition, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0484] A low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside. In addition, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the memory device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

[0485] The control logic circuit 1460 processes the control signals (CE, WE, RE) from the outside to generate control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to this, and other control signals can be input as needed.

[0486] The memory cell array 1470 includes a plurality of memory cells MC and a plurality of wirings configured in a row and column shape. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in one column, etc. In addition, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in one row, etc.

[0487] In addition, although Figure 27A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as Figure 27B shown, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a structure in which the sense amplifier is provided so as to overlap under the memory cell array 1470 may also be employed.

[0488] An example of the structure of a memory cell applicable to the above-described memory cell MC is illustrated in FIG. 28.

[0489] [DOSRAM]

[0490] Figures 28A to 28C An example of the circuit structure of a memory cell of a DRAM is shown. In this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell is sometimes referred to as a DOSRAM. Figure 28A The memory cell 1471 shown includes a transistor M1 and a capacitor CA. In addition, the transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0491] The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

[0492] The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0493] In addition, the memory cell MC is not limited to the memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt a structure such as Figure 28B the memory cell 1472 shown, in which the back gate of the transistor M1 is not connected to the wiring BGL but to the wiring WOL. In addition, for example, the memory cell MC can also be a memory cell composed of a transistor M1 having a single-gate structure, that is, a transistor M1 that does not include a back gate, such as Figure 28C the memory cell 1473 shown.

[0494] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. In other words, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can also be omitted. In addition, since the leakage current is extremely small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0495] In addition, in the DOSRAM, when the structure in which the sense amplifier is provided so as to overlap the memory cell array 1470 as described above is adopted, the bit lines can be shortened. As a result, the bit line capacitance is reduced, and thus the storage capacitance of the memory cell can be decreased.

[0496] [NOSRAM]

[0497] Figures 28D to 28G An example of the circuit structure of a gain cell type memory cell of a 2-transistor 1-capacitor is shown. Figure 28D The memory cell 1474 shown includes a transistor M2, a transistor M3, and a capacitor CB. In addition, the transistor M2 includes a top gate (sometimes only referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell type memory cell using an OS transistor for the transistor M2 is sometimes referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0498] The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0499] The wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CB. When writing, holding, and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0500] In addition, the memory cell MC is not limited to the memory cell 1474, and its circuit structure can be appropriately changed. For example, the memory cell MC can also adopt a structure such as Figure 28E the memory cell 1475 shown, in which the back gate of the transistor M2 is not connected to the wiring BGL but to the wiring WOL. In addition, for example, the memory cell MC can also be a memory cell such as Figure 28F the memory cell 1476 shown, which is composed of a transistor having a single-gate structure, that is, a transistor M2 not including a back gate. In addition, for example, the memory cell MC can also have a structure such as Figure 28G the memory cell 1477 shown, in which the wiring WBL and the wiring RBL are combined into one wiring BIL.

[0501] When the semiconductor device shown in the above embodiment is used for a memory cell 1474 or the like, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made extremely small. Thus, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can also be omitted. Further, since the leakage current is extremely small, multi-valued data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0502] In addition, transistor M3 can also be a transistor including silicon in the channel formation region (hereinafter sometimes referred to as an Si transistor). The conductivity type of the Si transistor can be an n-channel type or a p-channel type. The field-effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, an Si transistor can also be used as transistor M3 which serves as a read transistor. Further, by using an Si transistor for transistor M3, transistor M2 can be provided stacked on transistor M3, so that the occupied area of the memory cell can be reduced and high integration of the memory device can be achieved.

[0503] In addition, transistor M3 can also be an OS transistor. When an OS transistor is used for transistor M2 and transistor M3, only n-type transistors can be used to form a circuit in memory cell array 1470.

[0504] In addition, Figure 28H An example of a gain cell type memory cell of a three-transistor one-capacitor is shown. Figure 28H The shown memory cell 1478 includes transistors M4 to M6 and capacitor CC. Capacitor CC can be appropriately provided. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring for supplying a low-level potential. In addition, memory cell 1478 can also be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0505] Transistor M4 is an OS transistor including a back gate which is electrically connected to wiring BGL. In addition, the back gate and the gate of transistor M4 can be electrically connected to each other. Alternatively, transistor M4 may not include a back gate.

[0506] In addition, each of the transistors M5 and M6 can be an n-channel Si transistor or a p-channel Si transistor. Alternatively, all of the transistors M4 to M6 are OS transistors. In this case, only n-type transistors can be used to form a circuit in the memory cell array 1470.

[0507] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0508] Note that the structures of the peripheral circuit 1411 and the memory cell array 1470 shown in this embodiment are not limited to the above structures. They can be changed, removed, or added as needed, and the configurations or functions of these circuits, the wirings connected to the circuits, and the circuit elements can be adjusted.

[0509] The structure shown in this embodiment can be implemented in appropriate combination with the structures shown in other embodiments.

[0510] Embodiment 5

[0511] In this embodiment, an example of the chip 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIG. 29. A plurality of circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a System on Chip (SoC).

[0512] As Figure 29A shown, the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and so on.

[0513] Bumps (not shown) are provided on the chip 1200, and the bumps are connected to the first surface of the printed circuit board (PCB) 1201 as Figure 29B shown. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and the bumps 1202 are connected to the mother board 1203.

[0514] In addition, storage devices such as a DRAM 1221 and a flash memory 1222 can be provided on the mother board 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. In addition, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0515] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory shared by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned NOSRAM or DOSRAM can be applied to this memory. In addition, the GPU 1212 is suitable for parallel computing of a plurality of data, and can be used for image processing or sum-of-products operation. By providing an image processing circuit or a sum-of-products operation circuit using the oxide semiconductor of the present invention as the GPU 1212, image processing and sum-of-products operation can be performed with low power consumption.

[0516] In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the operation result from the GPU 1212 to the CPU 1211 after the operation in the GPU 1212 can be performed at high speed.

[0517] The analog operation unit 1213 has one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. In addition, the above-mentioned sum-of-products operation circuit may be provided in the analog operation unit 1213.

[0518] The memory controller 1214 has a circuit serving as a controller for the DRAM 1221 and a circuit serving as an interface for the flash memory 1222.

[0519] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, an image capturing device, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As the above-mentioned interface, a universal serial bus (USB), a high-definition multimedia interface (HDMI) (registered trademark), etc. can be used.

[0520] The network circuit 1216 has a network circuit such as a local area network (LAN). In addition, it may also have a network security circuit.

[0521] The above-mentioned circuit (system) can be formed on the chip 1200 through the same manufacturing process. Thus, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0522] The motherboard 1203 including the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the flash memory 1222 may be referred to as the GPU module 1204.

[0523] The GPU module 1204 can reduce its size due to the chip 1200 using the SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing ability. In addition, by using the sum-of-products operation circuit using the GPU 1212, methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be executed. Thus, the chip 1200 can be used as an AI chip, or the GPU module can be used as an AI system module.

[0524] The structure shown in this embodiment can be implemented in appropriate combination with the structures shown in other embodiments and the like.

[0525] (Embodiment 6)

[0526] In this embodiment, application examples of a storage device using the semiconductor device shown in the above embodiment will be described. The semiconductor device shown in the above embodiment can be applied to, for example, storage devices of various electronic devices (such as information terminals, computers, smartphones, e-book reader terminals, digital cameras (including video cameras), video playback devices, navigation systems, etc.). Note that here, the computer includes tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as memory cards (such as SD cards), USB memories, and SSDs (solid state drives). FIG. 30 schematically shows several structural examples of a removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices or removable memories.

[0527] Figure 30A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a lid 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled into the memory chip 1105 or the like.

[0528] Figure 30B is an external view schematic diagram of an SD card, Figure 30CIt is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled in the memory chip 1114 or the like.

[0529] Figure 30D It is a schematic diagram of the appearance of an SSD. Figure 30E It is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled in the memory chip 1154 or the like.

[0530] This embodiment can be implemented by appropriately combining the structures described in other embodiments or the like.

[0531] (Embodiment 7)

[0532] The semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. FIG. 31 shows a specific example of an electronic device having a processor or chip such as a CPU or GPU according to one aspect of the present invention.

[0533] 〈Electronic Devices and Systems〉

[0534] A GPU or chip according to one embodiment of the present invention can be installed in various electronic devices. As examples of electronic devices, in addition to electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, monitors for computers, etc., digital signage, large game machines such as pachinko machines, etc., digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. can also be cited. In addition, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, the electronic device can be made to have artificial intelligence.

[0535] An electronic device according to one embodiment of the present invention may also include an antenna. By receiving a signal by the antenna, an image, information, etc. can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for non-contact power transfer.

[0536] An electronic device according to one embodiment of the present invention may also include a sensor (the sensor has a function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0537] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have the following functions: a function of displaying various information (static images, moving pictures, text images, etc.) on the display unit; a function of a touch panel; a function of displaying a calendar, date, time, etc.; a function of executing various software (programs); a function of performing wireless communication; a function of reading a program or data stored in a storage medium; etc. FIG. 31 shows an example of an electronic device.

[0538] [Mobile phone]

[0539] Figure 31A A mobile phone (smartphone), which is one of the information terminals, is shown. The information terminal 5500 includes a housing 5510 and a display unit 5511, has a touch panel in the display unit 5511 as an input interface, and buttons are provided on the housing 5510.

[0540] By applying a chip according to one embodiment of the present invention to the information terminal 5500, an application program using artificial intelligence can be executed. As an application program using artificial intelligence, for example, an application program that recognizes a conversation and displays the content of the conversation on the display unit 5511, an application program that recognizes text or a graphic input by a user to the touch panel provided in the display unit 5511 and displays the text or the graphic on the display unit 5511, an application program that performs biometric identification such as fingerprint or voiceprint, etc. can be cited.

[0541] [Information terminal]

[0542] Figure 31B A desktop information terminal 5300 is shown. The desktop information terminal 5300 includes an information terminal main body 5301, a display 5302, and a keyboard 5303.

[0543] Similar to the above-mentioned information terminal 5500, by applying a chip of one embodiment of the present invention to the desktop information terminal 5300, application programs using artificial intelligence can be executed. As application programs using artificial intelligence, for example, design support software, article proofreading software, menu automatic generation software, etc. can be cited. In addition, by using the desktop information terminal 5300, novel artificial intelligence can be developed.

[0544] Note that in the above example, Figure 31A and Figure 31B a smartphone and a desktop information terminal are shown as examples of electronic devices, but information terminals other than smartphones and desktop information terminals can also be applied. As information terminals other than smartphones and desktop information terminals, for example, a PDA (Personal Digital Assistant), a notebook information terminal, a workstation, etc. can be cited.

[0545] [Electrical appliance]

[0546] Figure 31C An electric refrigerator-freezer 5800, which is an example of an electrical appliance, is shown. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0547] By applying a chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 with artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 can be made to have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food, and a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food.

[0548] In the above example, an electric refrigerator-freezer was described as an electrical appliance, but as other electrical appliances, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water dispenser, a heating and cooling air conditioner including an air conditioner, a washing machine, a dryer, an audio-visual device, etc. can be cited.

[0549] [Game console]

[0550] Figure 31DThe portable game console 5200 showing an example of a game console. The portable game console includes a housing 5201, a display unit 5202, buttons 5203, etc.

[0551] By applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, a portable game console 5200 with low power consumption can be realized. In addition, due to the low power consumption, the heat generation from the circuit can be reduced, thereby reducing the negative impacts on the circuit itself, the peripheral circuit, and the module caused by heat.

[0552] In addition, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0553] The performance of the progress of the game, the words and deeds of the creatures appearing in the game, the phenomena occurring in the game, etc. are originally defined by the program possessed by the game. However, by applying artificial intelligence to the portable game console 5200, a performance not limited to the game program can be realized. For example, the performance of the content of the questions asked by the game player, the progress of the game, the time, the changes in the words and deeds of the characters appearing in the game, etc. can be realized.

[0554] In addition, when using the portable game console 5200 to play a game that requires multiple players, an anthropomorphic game player can be constructed using artificial intelligence. Thus, the artificial intelligence game player can be used as an opponent, and a single person can play a game for multiple players.

[0555] Although Figure 31D The portable game console is shown as an example of a game console, but the game console applying the GPU or chip of one embodiment of the present invention is not limited thereto. As the game console applying the GPU or chip of one embodiment of the present invention, for example, a home stationary game console, an arcade game console installed in an entertainment facility (such as a game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, etc. can be cited.

[0556] [Mobile body]

[0557] The GPU or chip of one embodiment of the present invention can be applied to an automobile as a mobile body and the periphery of the driver's seat of the automobile.

[0558] Figure 31E1 It is a diagram showing an example of a mobile body, an automobile 5700, Figure 31E2 It is a diagram showing the periphery of the front windshield inside the automobile. Figure 31E2 It shows the display panels 5701, 5702, 5703 installed on the instrument panel and the display panel 5704 installed on the pillar.

[0559] The display panels 5701 to 5703 can provide a speedometer, a tachometer, a driving distance, a fuel level, a gear position, settings of an air conditioner, and various other information. In addition, the user can appropriately change the display content, layout, etc. shown on the display panels according to their preferences, which can improve the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0560] By displaying the images captured by a camera device (not shown) provided in the vehicle 5700 on the display panel 5704, the field of view (blind spot) blocked by a pillar can be supplemented. That is, by displaying the images captured by a camera device provided outside the vehicle 5700, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the images of the parts that cannot be seen, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0561] Since the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in the autonomous driving system of the vehicle 5700. The chip can also be used in systems for navigation, danger prediction, etc. In addition, information such as navigation and danger prediction can be displayed on the display panels 5701 to 5704.

[0562] Although a vehicle is illustrated as an example of a moving body in the above example, the moving body is not limited to a vehicle. For example, as a moving body, a tram, a monorail, a ship, a flying object (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc. can also be cited, and the chip of one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0563] [Broadcast television system]

[0564] The GPU or chip of one aspect of the present invention can be applied to a broadcast television system.

[0565] Figure 31F Schematically shows data transmission in a broadcast television system. Specifically, Figure 31F Shows the path of the radio wave (broadcast television signal) transmitted from the broadcasting station 5680 reaching the television receiver (TV) 5600 of each household. The TV 5600 is equipped with a receiver (not shown), and thus the broadcast television signal received by the antenna 5650 is input to the TV 5600 through this receiver.

[0566] Although Figure 31F shows a ultra-high frequency (UHF) antenna as the antenna 5650, a BS and 110-degree CS antenna, a CS antenna, etc. can be used as the antenna 5650.

[0567] Radio waves 5675A and radio waves 5675B are terrestrial broadcast television signals. The radio wave tower 5670 amplifies the received radio waves 5675A and transmits radio waves 5675B. Each household can watch terrestrial TV broadcasts on the TV 5600 by receiving the radio waves 5675B with the antenna 5650. In addition, the broadcast television system can be satellite broadcast television using artificial satellites, data broadcast television using optical lines, etc., and is not limited to Figure 31F the terrestrial broadcast television shown

[0568] In addition, a chip of one embodiment of the present invention can also be applied to the above broadcast television system to form a broadcast television system using artificial intelligence. When sending broadcast television data from the broadcast station 5680 to the TV 5600 of each household, the encoder is used to compress the broadcast television data; when the antenna 5650 receives the broadcast television data, the decoder including the receiver in the TV 5600 is used to recover the broadcast television data. By using artificial intelligence, for example, in the motion compensation prediction which is one of the compression methods of the encoder, the display model included in the display image can be identified. In addition, intra-frame prediction using artificial intelligence can also be performed. For example, when the TV 5600 receives low-resolution broadcast television data and performs high-resolution display, supplementary processing of images such as upscaling can be performed in the recovery of the broadcast television data performed by the decoder.

[0569] The above broadcast television system using artificial intelligence is suitable for ultra-high-definition television (UHDTV: 4K, 8K) broadcasts with an increasing amount of broadcast television data.

[0570] In addition, as an application of artificial intelligence on the TV 5600 side, for example, a video recording device with artificial intelligence can be set inside the TV 5600. By adopting such a structure, the video recording device with artificial intelligence can learn the user's preferences, and can automatically record TV programs that match the user's preferences.

[0571] The electronic device, the functions of the electronic device, application examples of artificial intelligence, and their effects, etc. described in this embodiment can be implemented by appropriately combining with the descriptions of other electronic devices.

[0572] This embodiment can be implemented by appropriately combining with the structures described in other embodiments, etc.

[0573] [Symbol description]

[0574] 100 Capacitor, 110 Conductor, 112 Conductor, 120 Conductor, 130 Insulator, 140 Insulator, 150 Insulator, 200 Transistor, 200A Transistor, 200B Transistor, 205 Conductor, 210 Insulator, 212 Insulator, 214 Insulator, 216 Insulator, 218 Conductor, 222 Insulator, 224 Insulator, 224A Insulating Film, 230 Oxide, 230a Oxide, 230A Oxide Film, 230b Oxide, 230B Oxide Film, 230c Oxide, 230c1 Oxide, 230c2 Oxide, 230C Oxide Film, 230C1 Oxide Film, 230C2 Oxide Film, 231 Region, 231a Region, 231b Region, 232 Region, 232a Region, 232b Region, 234 Region, 240 Conductor, 240a Conductor, 240b Conductor, 241 Insulator, 241a Insulator, 241b Insulator, 242 Conductor, 242a Conductor, 242A Conductive Film, 242b Conductor, 242B Conductive Layer, 243 Region, 243a Region, 243b Region, 250 Insulator, 250A Insulating Film, 254 Insulator, 254a Insulator, 254A Insulating Film, 254b Insulator, 254B Insulating Film, 254c Insulator, 260 Conductor, 260a Conductor, 260A Conductive Film, 260B Conductive Film, 260b Conductor, 262 Pseudo Gate, 262A Pseudo Gate Layer, 274 Insulator, 280 Insulator, 280a Insulator, 280A Insulating Film, 280b Insulator, 281 Insulator, 282 Insulator, 300 Transistor, 311 Substrate, 313 Semiconductor Region, 314a Low-Resistance Region, 314b Low-Resistance Region, 315 Insulator, 316 Conductor, 320 Insulator, 322 Insulator, 324 Insulator, 326 Insulator, 328 Conductor, 330 Conductor, 350 Insulator, 352 Insulator, 354 Insulator, 356 Conductor, 400 Transistor, 405 Conductor, 405a Conductor, 405b Conductor, 424a Insulator, 424b Insulator, 430c Oxide, 430c1 Oxide, 430c2 Oxide, 431a Oxide, 431b Oxide, 432a Oxide, 432b Oxide, 440 Conductor, 440a Conductor, 440b Conductor, 442 Conductor, 442a Conductor, 442b Conductor, 443a Region, 443b Region, 450 Insulator, 460 Conductor, 460a Conductor, 460b Conductor, 1001 Wiring, 1002 Wiring, 1003wiring, 1004 wiring, 1005 wiring, 1006 wiring, 1007 wiring, 1008 wiring, 1009 wiring, 1010 wiring, 1100 USB memory, 1101 housing, 1102 cover, 1103 USB connector, 1104 substrate, 1105 memory chip, 1106 controller chip, 1110 SD card, 1111 housing, 1112 connector, 1113 substrate, 1114 memory chip, 1115 controller chip, 1150 SSD, 1151 housing, 1152 connector, 1153 substrate, 1154 memory chip, 1155 memory chip, 1156 controller chip, 1200 chip, 1201 PCB, 1202 bump, 1203 motherboard, 1204 GPU module, 1211 CPU, 1212 GPU, 1213 analog computing unit, 1214 storage controller, 1215 interface, 1216 network circuit, 1221 DRAM, 1222 flash memory, 1400 storage device, 1411 peripheral circuit, 1420 row circuit, 1430 column circuit, 1440 output circuit, 1460 control logic circuit, 1470 storage cell array, 1471 storage cell, 1472 storage cell, 1473 storage cell, 1474 storage cell, 1475 storage cell, 1476 storage cell, 1477 storage cell, 1478 storage cell, 5200 portable game console, 5201 housing, 5202 display unit, 5203 button, 5300 desktop information terminal, 5301 main body, 5302 display, 5303 keyboard, 5500 Information terminal, 5510 casing, 5511 display unit, 5600 TV, 5650 antenna, 5670 radio tower, 5675A radio wave, 5675B radio wave, 5680 radio and television station, 5700 automobile, 5701 display panel, 5702 display panel, 5703 display panel, 5704 display panel, 5800 electric refrigerator-freezer, 5801 casing, 5802 refrigerator door, 5803 freezer door.

Claims

1. A semiconductor device including a transistor, wherein the transistor includes: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a second oxide on the first oxide; a third oxide on the second oxide; a first conductor and a second conductor on the second oxide; a third insulator on the third oxide; a third conductor on the third insulator; a fourth insulator on the first conductor and the second conductor; and a fifth insulator on the fourth insulator, wherein an opening reaching the second oxide is provided in the fourth insulator and the fifth insulator, the third oxide is provided so as to cover the inner wall of the opening, the third insulator is provided so as to cover the inner wall of the opening with the third oxide interposed therebetween, the third conductor is provided so as to be embedded in the opening with the third oxide and the third insulator interposed therebetween, in the channel length direction of the transistor, at least a part of the fourth insulator in a region where the fourth insulator does not overlap with the second oxide is in contact with the first insulator, in the channel width direction of the transistor, based on the bottom surface height of the first insulator, the bottom surface height of the third conductor in a region where the third conductor does not overlap with the second oxide is lower than the bottom surface height of the second oxide, in the channel width direction of the transistor, at least a part of the third oxide in a region where the third oxide does not overlap with the second oxide is in contact with the first insulator, and the permeability of one or both of hydrogen and oxygen in the first insulator is lower than that of the second insulator.

2. The semiconductor device according to claim 1, wherein the third oxide has a stacked structure including a first layer and a second layer, the first layer is in contact with the second oxide and the fifth insulator, and the second layer is provided between the first layer and the third insulator.

3. The semiconductor device according to claim 2, wherein the crystallinity of the second layer is higher than that of the first layer.

4. The semiconductor device according to claim 2, wherein both the first layer and the second layer contain In, element M, and Zn, where M is Al, Ga, Y, or Sn, and the atomic ratio of In in the constituent elements of the second layer is smaller than the atomic ratio of In in the constituent elements of the first layer.

5. A semiconductor device including a transistor, wherein the transistor includes: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a second oxide on the first oxide; a third oxide on the second oxide; a third insulator on the third oxide; a conductor on the third insulator; A fourth insulator that contacts at least a portion of the third oxide, at least a portion of the top surface of the second oxide, at least a portion of the side surface of the second oxide, at least a portion of the side surface of the first oxide, at least a portion of the side surface of the second insulator, and at least a portion of the first insulator; A fifth insulator on the fourth insulator; And A sixth insulator that contacts at least a portion of the top surface of the third oxide, at least a portion of the top surface of the third insulator, at least a portion of the top surface of the conductor, and at least a portion of the top surface of the fifth insulator, wherein the second oxide includes a first region, a second region, and a third region located between the first region and the second region, the resistance of the first region and the second region is lower than the resistance of the third region, the conductor is disposed above the third region in a manner overlapping the third region, a portion of the third oxide and a portion of the third insulator are disposed between the side surface of the conductor and the side surface of the fifth insulator, the fourth insulator includes a region that contacts the first region and the second region, in the channel width direction of the transistor, based on the bottom surface height of the first insulator, the bottom surface height of the conductor in the region where the conductor does not overlap with the second oxide is lower than the bottom surface height of the second oxide, in the channel width direction of the transistor, at least a portion of the third oxide in the region where the third oxide does not overlap with the second oxide contacts the first insulator, and the permeability of one or both of hydrogen and oxygen in the first insulator is lower than that of the second insulator.

6. The semiconductor device according to claim 5, wherein the first region and the second region contain phosphorus or boron.

7. The semiconductor device according to claim 5 or 6, wherein the first region and the second region contain more oxygen defects than the third region.

8. The semiconductor device according to claim 5 or 6, wherein the fourth insulator has a stacked structure including a third layer and a fourth layer, the third layer contacts the first insulator, and the fourth layer contacts the fifth insulator.

9. The semiconductor device according to claim 8, wherein the third layer contains silicon oxide, the fourth layer contains aluminum oxide.

10. The semiconductor device according to any one of claims 5, 6, and 9, wherein the third oxide has a stacked structure including a first layer and a second layer, the first layer contacts the second oxide and the fifth insulator, and the second layer is disposed between the first layer and the third insulator.

11. The semiconductor device according to claim 10, wherein both the first layer and the second layer contain In, element M, and Zn, where M is Al, Ga, Y, or Sn, and the atomic ratio of In to element M in the second layer is less than the atomic ratio of In to element M in the first layer.

12. The semiconductor device according to claim 7, Wherein the fourth insulator has a stacked structure including a third layer and a fourth layer, The third layer is in contact with the first insulator, and the fourth layer is in contact with the fifth insulator.

13. The semiconductor device according to claim 7, Wherein the third oxide has a stacked structure including a first layer and a second layer, The first layer is in contact with the second oxide and the fifth insulator, and the second layer is disposed between the first layer and the third insulator.

14. The semiconductor device according to claim 8, Wherein the third oxide has a stacked structure including a first layer and a second layer, The first layer is in contact with the second oxide and the fifth insulator, and the second layer is disposed between the first layer and the third insulator.

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