Memory device and method of operating the same

Abstract

The present disclosure relates to a memory device and an operation method thereof. An operation method of a memory device including a first memory area and a second memory area includes: reading first data from the first memory area and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and the second data read from the second memory area to generate first result data, writing the first data stored in the data buffer block to the second memory area, performing a second XOR operation on the first data and the first result data to generate second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block to the first memory area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0040123 filed on April 5, 2019, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a semiconductor device, and more particularly, to a memory device for exchanging data stored in different memory areas and a method of operating the same. Background Art

[0004] Semiconductor memory devices are classified into volatile memory devices in which stored data disappears when power is turned off and nonvolatile memory devices in which stored data is retained even if power is turned off.

[0005] The memory device may exchange data stored in different memory areas for the purpose of bad block management, wear leveling, etc. In order to exchange data, the data stored in the memory device may be transferred to the memory controller, and the data transferred to the memory controller may be transferred to the memory device again. In this case, the data communication between the memory device and the memory controller may result in an increase in overhead. In addition, the memory controller may require a separate exchange buffer for data exchange, and the data communication between the memory device and the memory controller may result in a decrease in exchange speed. Summary of the invention

[0006] Embodiments of the present disclosure provide a memory device capable of exchanging data within the memory device without using a memory controller and an operating method thereof.

[0007] According to an exemplary embodiment, an operating method of a memory device including a first memory area and a second memory area includes: reading first data from the first memory area and storing the read first data in a data buffer block; performing a first exclusive OR (XOR) operation on the first data provided from the data buffer block and the second data read from the second memory area to generate first result data, writing the first data stored in the data buffer block to the second memory area, performing a second XOR operation on the first data and the first result data to generate second data, storing the generated second data in the data buffer block, and writing the generated second data stored in the data buffer block to the first memory area.

[0008] According to an exemplary embodiment, a memory device includes: a memory cell array including a first memory area storing first data and a second memory area storing second data; a read circuit that reads the first data from the first memory area; a data generation logic that generates third data that is the same as the second data based on the second data from the second memory area; a selection circuit that outputs one of the first data from the read circuit and the third data from the data generation logic based on a control signal; a data buffer block that stores the first data or the third data output from the selection circuit; and a write circuit that writes the first data of the data buffer block into the second memory area and writes the third data of the data buffer block into the first memory area.

[0009] According to an exemplary embodiment, an operating method of a memory device including a first memory area and a second memory area includes: reading first data from the first memory area and storing the read first data in a data buffer, reading second data from the second memory area and storing the read second data in a swap buffer, writing the first data stored in the data buffer to the second memory area, and writing the second data stored in the swap buffer to the first memory area.

[0010] According to an exemplary embodiment, a memory device may include: a memory cell array including a first memory cell area and a second memory cell area; a data buffer block storing first data from the first memory area; a data comparison write circuit performing a first XOR operation on the first data from the data buffer block and the second data from the second memory area and outputting first result data; a write circuit writing the first data from the data buffer block to the second memory area; a read circuit reading the first data stored in the first memory area or the second memory area; an XOR gate performing a second XOR operation on the first result data of the data comparison write circuit and the first data from the read circuit and generating second data; and a selection circuit outputting one of the second data from the XOR gate and the output of the read circuit. The second data from the selection circuit is stored in the data buffer block, and the write circuit writes the second data from the data buffer block to the first memory area.

[0011] According to an exemplary embodiment, an operating method of a memory device including a first memory area and a second memory area may include: reading first data from a first memory area of ​​a first memory bank, storing the read first data in a first memory area corresponding to the first memory bank, reading second data from a second memory area of ​​a second memory bank, storing the read second data in a second data buffer corresponding to the second memory bank, writing the second data stored in the second data buffer to the first memory area, and writing the first data stored in the first data buffer to the second memory area.

[0012] According to an exemplary embodiment, an operation method of a memory device having a memory cell array, a row decoder, a control circuit, a read circuit, a write circuit, a first buffer, and a second buffer can be performed by a control circuit. The method includes the following operations: 1) controlling the read circuit to read first data from a first position of the memory cell array identified by a first address; 2) controlling the first buffer to store the first data or an error-corrected version of the first data read in operation (1); and 3) controlling the write circuit to write the first data or the error-corrected version of the first data stored in the first buffer to a second position of the memory cell array identified by a second address. Operations (1) to (3) are performed in response to the control circuit receiving one or more commands from a memory controller arranged outside the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects and features of the present disclosure will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0014] Figure 1 A memory system according to an exemplary embodiment of the present disclosure is shown.

[0015] Figure 2 Shown for Figure 1 An exemplary block diagram of a memory device for exchanging data within a memory device.

[0016] Figure 3 It is shown Figure 2 A flowchart of an example of the operation of a memory device.

[0017] Figure 4 Show Figure 2 An example of an operation of a memory device to exchange data stored in a memory bank.

[0018] Figure 5 Show Figure 2 An example of an operation of a memory device exchanging data stored in different memory banks.

[0019] Figure 6 Shown for Figure 1 Another exemplary block diagram of a memory device for exchanging data within a memory device.

[0020] Figure 7 Shown for Figure 1 Another exemplary block diagram of a memory device for exchanging data within a memory device.

[0021] Figure 8 It is shown Figure 7 A flowchart of an example of the operation of a memory device.

[0022] Fig. 9 Shown provided to Figure 7 An example of a memory device with commands and addresses for data exchange.

[0023] FIG. 10A to FIG. 10D Show Figure 7 The memory devices are based on Fig. 9 An example of an operation that uses commands and addresses to exchange data.

[0024] Fig.11 Show Figure 7 The memory devices are based on Fig. 9 Another example of an operation that uses commands and addresses to exchange data.

[0025] Fig.12 Shown provided to Figure 7 An example of a memory device with commands and addresses for exchanging data stored in different memory banks.

[0026] Fig.13 Show Figure 7 The memory devices are based on Fig.12 An example of an operation that uses commands and addresses to exchange data.

[0027] Fig.14 A block diagram of a memory system according to an exemplary embodiment of the present disclosure is shown.

[0028] Fig.15 A block diagram of a memory system according to an exemplary embodiment of the present disclosure is shown.

[0029] Fig.16 is a block diagram of a computing device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure may be described in detail and clearly to the extent that a person having ordinary skill in the art can easily implement the present disclosure.

[0031] Figure 1 A memory system according to an exemplary embodiment of the present disclosure is shown. Figure 1, the memory system 1000 may include a memory controller 10 and a memory device 100 .

[0032] The memory controller 10 may control the operation of the memory device 100. The memory controller 10 may provide a command CMD and an address ADDR for the purpose of controlling the memory device 100. The memory device 100 may operate in response to the command CMD and the address ADDR. For example, the memory device 100 may write data (e.g., write data) to a memory area corresponding to the address ADDR in response to a write command WC and the address ADDR. For example, the memory device 100 may read data (e.g., read data) from a memory area corresponding to the address ADDR in response to a read command RC and the address ADDR.

[0033] The memory device 100 includes a memory cell array 110. The memory cell array 110 may include one or more memory banks. Each of the memory banks may include a memory region for storing data. Each of the memory regions may include a plurality of memory cells.

[0034] For example, the memory cell array 110 may include a first memory area MA1 and a second memory area MA2. The first memory area MA1 and the second memory area MA2 may be included in one bank or different banks. The first memory area MA1 may store first data DATA1, and the second memory area MA2 may store second data DATA2.

[0035] The memory device 100 may include a phase-change random access memory (PRAM). However, the present disclosure is not limited thereto. For example, the memory device 100 may include a volatile memory such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), or a non-volatile memory such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM).

[0036] According to an exemplary embodiment of the present disclosure, the memory controller 10 may provide a command CMD and an address ADDR to the memory device 100 for the purpose of exchanging data stored in different memory areas of the memory device 100 .

[0037] For example, for data exchange, the memory controller 10 may provide a exchange command SWAP and two addresses ADDR1 and ADDR2. The first address ADDR1 may correspond to the first memory area MA1, and the second address ADDR2 may correspond to the second memory area MA2. In this case, the memory device 100 may exchange the first data DATA1 stored in the first memory area MA1 with the second data DATA2 stored in the second memory area MA2 in response to the exchange command SWAP. In this way, the second data DATA2 may be stored in the first memory area MA1, and the first data DATA1 may be stored in the second memory area MA2.

[0038] Alternatively, for data exchange, the memory controller 10 may provide a plurality of commands CMD and a plurality of addresses ADDR. The plurality of commands CMD may include an active command ACT and a write command WC. That is, the memory controller 10 may exchange the first data DATA1 stored in the first memory area MA1 with the second data DATA2 stored in the second memory area MA2 without using a separate exchange command SWAP.

[0039] As described above, the memory device 100 can receive the command CMD and the address ADDR from the memory controller 10, and can exchange data. That is, the memory device 100 can exchange data therein without transmitting the data stored in the memory cell array 110 to the memory controller 10. Therefore, the data exchange speed can be increased, and the communication overhead between the memory device 100 and the memory controller 10 caused by the data exchange can be reduced.

[0040] Figure 2 A method for exchanging data within a memory device is shown. Figure 1 An exemplary block diagram of a memory device of FIG. Figure 2 , the memory device 200 may include a memory cell array 210 , a row decoder 220 , a read circuit 230 , a write circuit 240 , a data buffer block 250 , a swap buffer block 260 , and a control logic 270 .

[0041] The memory cell array 210 may include one or more memory banks, each of which includes a memory area for storing data. Each of the memory areas may include a memory cell connected to a word line WL and a bit line BL. For example, the memory cells in each row may be connected to a word line WL. The memory cells in each column may be connected to a bit line BL. However, the present disclosure is not limited thereto. For example, the memory cells in each column may be connected to a source line and a bit line BL.

[0042] The row decoder 220 is connected to the memory cell array 210 through the word line WL. The row decoder 220 may receive an address ADDR. In this case, the address ADDR may indicate a row address. The row decoder 220 may select one of the word lines WL based on the address ADDR. The row decoder 220 may apply a selection voltage or a selection current to the selected word line, and may apply a non-selection voltage or a non-selection current to each of the unselected word lines.

[0043] The read circuit 230 is connected to the memory cell array 210 through the bit lines BL. The read circuit 230 may apply a voltage or a current to the bit lines BL so that data is read from a selected memory cell connected to the selected word line WL, and the write circuit 240 may apply a voltage or a current to the bit lines BL so that data is written into a selected memory cell connected to the selected word line WL.

[0044] For example, in the case where the memory cell array 210 includes a PRAM cell, the read circuit 230 can sense the voltage or current of the bit line BL to read data from the selected memory cell. The write circuit 240 can perform a set operation or a reset operation on the selected memory cell to change the resistance value of the selected memory cell. In this way, data can be written into the selected memory cell. In an exemplary embodiment, the read circuit 230 can be a sense amplifier, and the write circuit 240 can be a write driver. However, the present disclosure is not limited to this. For example, the read circuit 230 can be implemented with various circuits capable of reading data from the memory cell array 210, and the write circuit 240 can be implemented with various circuits capable of writing data in the memory cell array 210.

[0045] The data buffer block 250 may store data read from the memory cell array 210 through the read circuit 230 and data received from an external device (eg, Figure 1 The data buffer block 250 may be output to an external device or may be written to the memory cell array 210 through the write circuit 240. For example, the data buffer block 250 may be a page buffer. However, the present disclosure is not limited thereto.

[0046] The data buffer block 250 may include one or more data buffers. For example, the data buffer block 250 may include a data buffer corresponding to each of the banks of the memory cell array 210. In this case, data transfer may be performed between the data buffer and the corresponding bank among the banks of the memory cell array 210.

[0047] The swap buffer block 260 may include one or more swap buffers. For example, the swap buffer block 260 may include a swap buffer corresponding to each of the banks of the memory cell array 210. In this case, the swap buffer may be used to swap data of the memory cell array 210.

[0048] Data transfer may be performed between the swap buffer block 260 and the memory cell array 210 through the read circuit 230 and the write circuit 240. In an exemplary embodiment, the swap buffer block 260 may store data read from a certain region of the memory cell array 210. In this case, the data stored in the swap buffer block 260 may be provided to a region of the memory cell array 210 other than the certain region.

[0049] That is, the data buffer block 250 may be used to provide data input from an external device to the memory cell array 210 or output data read from the memory cell array 210 to an external device. Conversely, the swap buffer block 260 may be used to swap data stored in the memory cell array 210.

[0050] The control logic 270 may control the operation of each component of the memory device 200. For example, the control logic 270 may control the operation of the row decoder 220, the read circuit 230, the write circuit 240, the data buffer block 250, and the exchange buffer block 260. The control logic 270 may control the operation of each component based on the received command CMD. For example, when the command CMD for exchange is provided, the control logic 270 may control the components to exchange data of the memory cell array 210.

[0051] Next, we will refer to Figures 3 to 5 The operation of the memory device 200 to exchange data is described in detail.

[0052] Figure 3 It is shown Figure 2 Flowchart of an example of the operation of a memory device. In detail, Figure 3 An example is shown in which the memory device 200 exchanges first data stored in a first memory region of the memory cell array 210 with second data stored in a second memory region of the memory cell array 210 .

[0053] refer to Figure 2 and Figure 3 In operation S201 , the memory device 200 may read first data from a first memory area through the read circuit 230 , and may store the first data in a data buffer. Here, the data buffer may be included in the data buffer block 250 .

[0054] In operation S202 , the memory device 200 may read second data from the second memory area through the read circuit 230 , and may store the second data in a swap buffer. Here, the swap buffer may be included in the swap buffer block 260 .

[0055] In operation S203, the memory device 200 may write the first data stored in the data buffer into the second memory area through the write circuit 240. In this way, the second data stored in the second memory area may be replaced with the first data.

[0056] In operation S204, the memory device 200 may write the second data stored in the swap buffer into the first memory area through the write circuit 240. In this way, the first data stored in the first memory area may be replaced with the second data.

[0057] As described above, the memory device 200 may execute the following operations in response to one swap command SWAP, or a plurality of commands such as an active command ACT and a write command WC. Figure 3 operation.

[0058] exist Figure 3 The description given in is that operation S202 is performed after operation S201, but the present disclosure is not limited thereto. For example, operation S202 may be performed before operation S201. Figure 3 The description given in FIG. 1 is that operation S204 is performed after operation S203, but the present disclosure is not limited thereto. For example, operation S204 may be performed before operation S203.

[0059] Figure 4 Show Figure 2 An example of an operation of a memory device to exchange data stored in a memory bank. Figure 4 , the memory cell array 210 may include a first memory bank 211. The first memory bank 211 may include a first memory area MA1 and a second memory area MA2. The first memory area MA1 may store first data DATA1, and the second memory area MA2 may store second data DATA2.

[0060] The data buffer block 250 may include a first data buffer 251. The first data buffer 251 may correspond to the first memory bank 211. The swap buffer block 260 may include a first swap buffer 261. The first swap buffer 261 may correspond to the first memory bank 211.

[0061] In order to exchange the first data DATA1 stored in the first memory area MA1 with the second data DATA2 stored in the second memory area MA2, the first data DATA1 of the first memory area MA1 may be read by the read circuit 230. The first data DATA1 thus read may be stored in the first data buffer 251 (①). The second data DATA2 of the second memory area MA2 may be read by the read circuit 230. The second data DATA2 thus read may be stored in the first exchange buffer 261 (②).

[0062] Then, the first data DATA1 stored in the first data buffer 251 may be written into the second memory area MA2 through the write circuit 240 (③). In this way, the second data DATA2 stored in the second memory area MA2 may be replaced by the first data DATA1. The second data DATA2 stored in the first exchange buffer 261 may be written into the first memory area MA1 through the write circuit 240 (④). In this way, the first data DATA1 stored in the first memory area MA1 may be replaced by the second data DATA2.

[0063] Figure 5 Show Figure 2 An example of an operation of a memory device to exchange data stored in different memory banks. Figure 5 , the memory cell array 210 may include a first memory bank 211 and a second memory bank 212. The first memory bank 211 may include a first memory area MA1. The second memory bank 212 may include a second memory area MA2. The first memory area MA1 may store first data DATA1, and the second memory area MA2 may store second data DATA2.

[0064] The data buffer block 250 may include a first data buffer 251 and a second data buffer 252. The first data buffer 251 may correspond to the first memory bank 211, and the second data buffer 252 may correspond to the second memory bank 212. The exchange buffer block 260 may include a first exchange buffer 261 and a second exchange buffer 262. The first exchange buffer 261 may correspond to the first memory bank 211, and the second exchange buffer 262 may correspond to the second memory bank 212.

[0065] In order to exchange the first data DATA1 stored in the first memory area MA1 with the second data DATA2 stored in the second memory area MA2, the first data DATA1 of the first memory area MA1 may be read by the read circuit 230. The first data DATA1 thus read may be stored in the data buffer block 250 (①). In this case, the first data DATA1 may be stored in the first data buffer 251 corresponding to the first memory bank 211. The second data DATA2 of the second memory area MA2 may be read by the read circuit 230. The second data DATA2 thus read may be stored in the exchange buffer block 260 (②). In this case, the second data DATA2 may be stored in the second exchange buffer 262 corresponding to the second memory bank 212.

[0066] Then, the first data DATA1 stored in the first data buffer 251 can be written to the second memory area MA2 through the write circuit 240 (③). In this way, the second data DATA2 stored in the second memory area MA2 can be replaced by the first data DATA1. In this case, the first data DATA1 stored in the first data buffer 251 can be transferred to the second data buffer 252, and the first data DATA1 can be provided from the second data buffer 252 to the write circuit 240.

[0067] The second data DATA2 stored in the second exchange buffer 262 may be written to the first memory area MA1 (④) through the write circuit 240. In this way, the first data DATA1 stored in the first memory area MA1 may be replaced by the second data DATA2. In this case, the second data DATA2 stored in the second exchange buffer 262 may be transferred to the first exchange buffer 261, and the second data DATA2 may be provided from the first exchange buffer 261 to the write circuit 240.

[0068] As described above, the memory device 200 according to the exemplary embodiment of the present disclosure can exchange data stored in one or two memory banks by using a data buffer and a separate exchange buffer. In this way, the memory device 200 can exchange data without using an external memory controller. Therefore, data exchange can be performed quickly, and the communication overhead between the memory device 200 and the memory controller 10 can be reduced.

[0069] Figure 6 A method for exchanging data within a memory device is shown. Figure 1 Another exemplary block diagram of a memory device of FIG. Figure 6, the memory device 300 may include a memory cell array 310, a row decoder 320, a read circuit 330, a write circuit 340, a data buffer block 350, a data comparison write (DCW) circuit 360, and a control logic 370. The operation of the memory cell array 310, the row decoder 320, the read circuit 330, the write circuit 340, the data buffer block 350, and the control logic 370 is similar to Figure 2 Operations of the memory cell array 210, the row decoder 220, the read circuit 230, the write circuit 240, the data buffer block 250, and the control logic 270 are described, and therefore, additional description will be omitted to avoid redundancy.

[0070] The data comparison write circuit 360 may include a DCW register 361. The DCW register 361 may be a buffer circuit for storing data. The data comparison write circuit 360 may be used for a data write operation or a data exchange operation.

[0071] In response to the write command WC, the data comparison write circuit 360 can compare the data transmitted to the data buffer block 350 and the data read from the memory cell array 310. In detail, the data comparison write circuit 360 can compare the data in bits by an exclusive OR (XOR) operation. For example, in a write operation, new write data and an address ADDR to store the new write data can be provided to the memory device 300. The new write data can be stored in the data buffer block 350. The data comparison write circuit 360 can compare the new write data of the data buffer block 350 with the data of the memory area corresponding to the address ADDR of the memory cell array 310. When the comparison result indicates that the two data are the same, the data of the memory area can be maintained. When the comparison result indicates that the two data are different, the data of the memory area can be replaced with the new write data. In this case, at least one of the new write data of the data buffer block 350, the data read from the memory area, and the comparison result (e.g., data obtained by performing an XOR operation on the new write data and the data read from the memory area) can be stored in the DCW register 361. That is, when the comparison result indicates that the two data are different, new write data may be written to the memory area of ​​the memory cell array 310 through the write circuit 340. Therefore, the memory device 300 may perform a write operation with low power through the data comparison write circuit 360.

[0072] When a swap command SWAP is provided to swap the first data and the second data stored in the memory cell array 310, the first data may be stored in the data buffer block 350 through the read circuit 330, and the second data may be stored in the DCW register 361 of the data comparison write circuit 360 through the read circuit 330. The write circuit 340 may replace the second data of the memory cell array 310 with the first data stored in the data buffer block 350, and may replace the first data of the memory cell array 310 with the second data stored in the DCW register 361. In this way, data stored in different memory areas may be swapped. That is, in the swap operation, the operation of the DCW register 361 may be similar to Figure 2 The operation of the swap buffer block 260.

[0073] As described above, the memory device 300 may be used without Figure 2 In the case of a separate exchange buffer block 260, data is exchanged by using a DCW register 361 of a data comparison write circuit 360. In this case, the DCW register 361 may be used as a buffer circuit for storing data to be exchanged in an exchange operation, or may be used as a buffer circuit for storing at least one of new write data, data read from a memory area to which the new write data is to be written, and XOR data as a comparison result of the new write data and the read data.

[0074] exist Figure 6 3. In the description of including the DCW register 361 in the data comparison write circuit 360 and storing the data of the memory cell array 310 in the DCW register 361, the present disclosure is not limited thereto. For example, for data exchange, the data of the memory cell array 310 may be stored in any circuit that exists within the data comparison write circuit 360 and provides a buffer function.

[0075] As described above, the memory device 300 may exchange data by using the existing data comparison write circuit 360 that provides an efficient write operation. In this case, since a separate exchange buffer is not required, the area of ​​the memory device 300 may not increase.

[0076] Figure 7 A method for exchanging data within a memory device is shown. Figure 1 Another exemplary block diagram of a memory device of FIG. Figure 7, the memory device 400 may include a memory cell array 410, a row decoder 420, a read circuit 430, a write circuit 440, a data comparison write circuit 450, an XOR gate 460, a selection circuit 470, a data buffer block 480, and a control logic 490. The operation of the memory cell array 410, the row decoder 420, the read circuit 430, the write circuit 440, the data buffer block 480, and the control logic 490 is similar to Figure 2 Operations of the memory cell array 210, the row decoder 220, the read circuit 230, the write circuit 240, the data buffer block 250, and the control logic 270 are described, and therefore, additional description will be omitted to avoid redundancy.

[0077] The data comparison write circuit 450 may receive data read from the memory cell array 410 by the read circuit 430. The data comparison write circuit 450 may receive data from the data buffer block 480. The data comparison write circuit 450 may compare the data stored in the memory cell array 410 with the data stored in the data buffer block 480. In detail, the data comparison write circuit 450 may compare the data in units of bits. For example, the data comparison write circuit 450 may perform an XOR operation to compare the data. The data comparison write circuit 450 may provide an enable signal EN to the write circuit 440 based on the comparison result. For example, the data comparison write circuit 450 may perform an XOR operation, and may output the result of the XOR operation as an enable signal EN.

[0078] The result of the XOR operation may be stored in the data comparison write circuit 450. For example, the result of the XOR operation may be stored in a data comparison write circuit 450. Figure 6 The DCW register 361 is a separate register, but the present disclosure is not limited thereto.

[0079] The write circuit 440 can perform a write operation based on the enable signal EN. When the data stored in the memory cell array 410 and the data stored in the data buffer block 480 are the same, the write circuit 440 can not operate based on the enable signal EN. In this case, the data of the memory cell array 410 can be maintained. When the data stored in the memory cell array 410 and the data stored in the data buffer block 480 are different, the write circuit 440 can operate based on the enable signal EN. In this case, the data of the memory cell array 410 can be replaced with the data of the data buffer block 480. In this way, the data of the data buffer block 480 can be written to the memory cell array 410 with low power based on the comparison result of the data comparison write circuit 450. However, the present disclosure is not limited to this. For example, the write circuit 440 can operate regardless of the comparison result of the data comparison write circuit 450, so that the data of the data buffer block 480 is written to the memory cell array 410.

[0080] The XOR gate 460 may perform an XOR operation on the data output from the data comparison write circuit 450 and the data output from the read circuit 430. A result of the XOR operation output from the XOR gate 460 may be provided to the selection circuit 470.

[0081] The selection circuit 470 may output one of the data output from the XOR gate 460 and the data output from the read circuit 430 to the data buffer block 480. The selection circuit 470 may select the data to be output to the data buffer block 480 based on a control signal from the control logic 490.

[0082] The data buffer block 480 may store data output from the selection circuit 470. Also, the data buffer block 480 may store data provided from an external device. The data stored in the data buffer block 480 may be written to the memory cell array 410 through the write circuit 440. In this case, the data stored in the data buffer block 480 may be written to the memory cell array 410 based on the enable signal EN.

[0083] The control logic 490 may control operations of the components of the memory device 400. In detail, the control logic 490 may control the row decoder 420, the read circuit 430, the write circuit 440, the data comparison write circuit 450, the XOR gate 460, the selection circuit 470, and the data buffer block 480. For example, when a command CMD for data exchange is provided, the control logic 490 may control the components to exchange data.

[0084] exist Figure 7 4 shows an example in which the XOR gate 460 receives the data output from the data comparison write circuit 450 and the data output from the read circuit 430, but the present disclosure is not limited thereto. For example, the XOR gate 460 may receive data stored in the data buffer block 480 instead of the data output from the read circuit 430. The XOR gate 460 may perform an XOR operation on the data output from the data comparison write circuit 450 and the data output from the data buffer block 480.

[0085] Next, we will refer to Figures 8 to 12 The operation of the memory device 400 to exchange data is described in detail.

[0086] Figure 8 It is shown Figure 7 Flowchart of an example of the operation of a memory device. In detail, Figure 8 An example of an operation in which the memory device 400 exchanges first data stored in a first memory region of the memory cell array 410 with second data stored in a second memory region of the memory cell array 410 is shown.

[0087] refer to Figure 7 and Figure 8 In operation S401, the memory device 400 may read first data from the first memory area and may store the first data in a data buffer. The data buffer may be included in the data buffer block 480. In this case, the control logic 490 may control the selection circuit 470 so that the data output from the read circuit 430 is selected. In this way, the first data may be selected by the selection circuit 470 and may then be stored in the data buffer block 480.

[0088] In operation S402, the memory device 400 may perform an XOR operation on the first data provided from the data buffer and the second data read from the second memory area, and may store the result of the XOR operation. The memory device 400 may perform the XOR operation through the data comparison write circuit 450, and may store the result of the XOR operation.

[0089] In operation S403 , the memory device 400 may write the first data stored in the data buffer to the second memory area. For example, the write circuit 440 may write the first data based on the result of the XOR operation (ie, the enable signal EN) output from the data comparison write circuit 450 .

[0090] In operation S404, the memory device 400 may perform an XOR operation on the result of the XOR operation and the first data through the XOR gate 460, and may generate second data. Here, the first data may be read from the first memory area or the second memory area through the read circuit 430. Alternatively, the first data may be read from the data buffer of the data buffer block 480. The result of the XOR operation performed on the result of the XOR operation output from the data comparison write circuit 450 and the first data may be the same as the second data. In this way, the second data may be generated through the XOR gate 460.

[0091] In operation S405, the memory device 400 may store the generated second data in the data buffer. In this case, the control logic 490 may control the selection circuit 470 so that the data output from the XOR gate 460 is selected. The selection circuit 470 may output the data output from the XOR gate 460 to the data buffer block 480. In this way, the second data may be stored in the data buffer.

[0092] In operation S406, the memory device 400 may write the second data stored in the data buffer to the first memory area. For example, when the second data is written, the data comparison write circuit 450 may compare the first data stored in the first memory area with the second data stored in the data buffer. The write circuit 440 may write the second data based on the comparison result (i.e., the enable signal EN).

[0093] Fig. 9 Shown provided to Figure 7 An example of a memory device with commands and addresses for data exchange. FIG. 10A to FIG. 10D Show Figure 7 The memory devices are based on Fig. 9 The following is an example of an operation that uses commands and addresses to exchange data. Figures 9 to 10D describe Figure 7 The memory controller may provide a memory device for exchanging data stored in one memory bank. Fig. 9 The command CMD and address ADDR.

[0094] refer to Fig. 9 and 10A , at a first time t1, an activation command ACT and an address A1 may be provided. The address A1 may indicate a first memory area MA1 of the first memory bank 411. In response to the activation command ACT and the address A1, the read circuit 430 may read the first data DATA1 from the first memory area MA1. The first data DATA1 thus read may be output to the selection circuit 470. The selection circuit 470 may select the first data DATA1 output from the read circuit 430, and may store the first data DATA1 in the first data buffer 481 (①). The first data buffer 481 may correspond to the first memory bank 411.

[0095] refer to Fig. 9 and Fig. 10B , after the activation command ACT is provided and the delay time tRCD has passed, that is, at the second time t2, the write command WC1 and the address A2 may be provided. The address A2 may indicate the second memory area MA2 of the first memory bank 411. In response to the write command WC1 and the address A2, the read circuit 430 may read the second data DATA2 stored in the second memory area MA2, and may provide the second data DATA2 to the data comparison write circuit 450. The first data DATA1 stored in the first data buffer 481 may be provided to the data comparison write circuit 450. The data comparison write circuit 450 may perform an XOR operation on the first data DATA1 provided from the first data buffer 481 and the second data DATA2 read from the second memory area MA2, and may store the first operation result ORD1 as the result of the XOR operation (②). The write circuit 440 may write the first data DATA1 stored in the first data buffer 481 to the second memory area MA2 (③). For example, the write circuit 440 may write the first data DATA1 to the second memory area MA2 based on the first operation result ORD1.

[0096] refer to Fig. 9 and Fig. 10C , after the write command WC1 is provided and the data recovery time tWR has passed, that is, at the third time t3, the exchange activation command SACT and the address A3 may be provided. The address A3 may indicate the second memory area MA2 of the first memory body 411. In response to the exchange activation command SACT and the address A3, the read circuit 430 may read the first data DATA1 stored in the second memory area MA2, and may provide the first data DATA1 to the XOR gate 460. The XOR gate 460 may perform an XOR operation on the first operation result ORD1 and the first data DATA1 to generate the second data DATA2 (④). The selection circuit 470 may output the second data DATA2 output from the XOR gate 460 to the data buffer block 480. In this way, the second data DATA2 may be stored in the first data buffer 481 (⑤).

[0097] Here, the swap activation command SACT may be a command different from the activation command ACT. Figure 7 The control logic 490 may control the selection circuit 470 in response to the activation command ACT so that the data output from the read circuit 430 is stored in the data buffer block 480. In contrast, the control logic 490 may control the selection circuit 470 in response to the swap activation command SACT so that the data output from the XOR gate 460 is stored in the data buffer block 480. For example, the activation command ACT and the swap activation command SACT may be identified based on separate flag bits.

[0098] refer to Fig. 9 and Fig. 10D, after the exchange activation command SACT is provided and the delay time tRCD has passed, that is, at the fourth time t4, a write command WC2 and an address A4 may be provided. Address A4 may indicate the first memory area MA1 of the first memory body 411. In response to the write command WC2 and the address A4, the read circuit 430 may read the first data DATA1 stored in the first memory area MA1 and may provide the first data DATA1 to the data comparison write circuit 450. The second data DATA2 stored in the first data buffer 481 may be provided to the data comparison write circuit 450. The data comparison write circuit 450 may perform an XOR operation on the first data DATA1 read from the first memory area MA1 and the second data DATA2 provided from the first data buffer 481, and may store the second operation result ORD2 as the result of the XOR operation (⑥). The write circuit 440 may write the second data DATA2 stored in the first data buffer 481 to the first memory area MA1 (⑦). For example, the write circuit 440 may write the second data DATA2 to the first memory area MA1 based on the second operation result ORD2.

[0099] Fig.11 Show Figure 7 The memory devices are based on Fig. 9 Another example of the operation of exchanging data with a command and address. Fig. 9 and Fig.11 describe Figure 7 An operation in which a memory device exchanges data stored in different memory banks.

[0100] refer to Fig. 9 and Fig.11 , may be provided from the memory controller for the purpose of exchanging the first data DATA1 stored in the first memory bank 411 and the second data DATA2 stored in the second memory bank 412. Fig. 9 The data buffer block 480 may include a first data buffer 481 and a second data buffer 482. The first data buffer 481 may correspond to the first memory bank 411, and the second data buffer 482 may correspond to the second memory bank 412.

[0101] At the first time t1, an activation command ACT and an address A1 may be provided. The address A1 may indicate a first memory area MA1 of the first memory bank 411. In response to the activation command ACT and the address A1, the read circuit 430 may read the first data DATA1 from the first memory area MA1. The first data DATA1 thus read may be stored in the first data buffer 481 (①).

[0102] After the activation command ACT is provided and the delay time tRCD has passed, that is, at the second time t2, a write command WC1 and an address A2 may be provided. Address A2 may indicate the second memory area MA2 of the second memory bank 412. In response to the write command WC1 and the address A2, the data comparison write circuit 450 may perform an XOR operation on the first data DATA1 provided from the first data buffer 481 and the second data DATA2 read from the second memory area MA2, and may store the operation result ORD as the result of the XOR operation (②). The write circuit 440 may write the first data DATA1 stored in the first data buffer 481 to the second memory area MA2 (③). In this way, the second data DATA2 stored in the second memory area MA2 may be replaced by the first data DATA1. In this case, the first data DATA1 stored in the first data buffer 481 may be transferred to the second data buffer 482, and the first data DATA1 may be provided to the write circuit 440 from the second data buffer 482.

[0103] After the write command WC1 is provided and the data recovery time tWR has passed, that is, at the third time t3, the exchange activation command SACT and the address A3 may be provided. The address A3 may indicate the second memory area MA2 of the second memory bank 412. In response to the exchange activation command SACT and the address A3, the read circuit 430 may read the first data DATA1 stored in the second memory area MA2, and may provide the first data DATA1 to the XOR gate 460. The XOR gate 460 may perform an XOR operation on the operation result ORD and the first data DATA1 to generate the second data DATA2 (④). The selection circuit 470 may select the second data DATA2 output from the XOR gate 460, and may output the second data DATA2 to the data buffer block 480. The second data DATA2 may be stored in the second data buffer 482 corresponding to the second memory bank 412 (⑤).

[0104] After the exchange activation command SACT is provided and the delay time tRCD has passed, that is, at the fourth time t4, a write command WC2 and an address A4 may be provided. Address A4 may indicate the first memory area MA1 of the first memory body 411. In response to the write command WC2 and the address A4, the write circuit 440 may write the second data DATA2 stored in the second data buffer 482 to the first memory area MA1 (⑥). In this way, the first data DATA1 stored in the first memory area MA1 may be replaced with the second data DATA2. In this case, the second data DATA2 stored in the second data buffer 482 may be transferred to the first data buffer 481, and the second data DATA2 may be provided from the first data buffer 481 to the write circuit 440.

[0105] exist Fig. 9 2 shows an example in which an address ADDR is provided separately from a command CMD when an activation command ACT and / or a write command WC is provided, but the present disclosure is not limited thereto. For example, the activation command ACT and / or the write command WC may include information about a row address, and the address ADDR corresponding to the activation command ACT and / or the write command WC may include information about a memory cell address and a column address.

[0106] As described above, the memory device 400 may execute the following operations in response to the active command ACT, the write command WC, and the swap active command SACT. Figure 8 However, the present disclosure is not limited thereto. For example, the memory device 400 may execute in response to a swap command SWAP. Figure 8 operation.

[0107] Next, we will refer to Fig.12 and Fig.13 Detailed Description Figure 7 Another example of the operation of exchanging data by the memory device 400. In detail, reference will be made to Fig.12 and Fig.13 Describes the operation in which data stored in different memory banks are exchanged.

[0108] Fig.12 shows the commands and addresses that are provided to Figure 7 An example of a memory device for exchanging data stored in different memory banks. Fig.13 Show Figure 7 The memory devices are based on Fig.12 An example of an operation that uses commands and addresses to exchange data.

[0109] refer to Fig.12 and Fig.13, a memory controller may be provided for the purpose of exchanging the first data DATA1 stored in the first memory bank 411 with the second data DATA2 stored in the second memory bank 412. Fig.12 The command CMD and address ADDR.

[0110] At the first time t1, an activation command ACT1 and an address A1 may be provided. The address A1 may indicate a first memory area MA1 of the first memory bank 411. In response to the activation command ACT1 and the address A1, the read circuit 430 may read the first data DATA1 from the first memory area MA1. The first data DATA1 thus read may be stored in the first data buffer 481 through the selection circuit 470 (①).

[0111] After the activation command ACT1 is provided and the delay time tCCD has passed, that is, at the second time t2, the activation command ACT2 and the address A2 may be provided. The address A2 may indicate the second memory area MA2 of the second memory bank 412. In response to the activation command ACT2 and the address A2, the read circuit 430 may read the second data DATA2 from the second memory area MA2. The second data DATA2 thus read may be stored in the second data buffer 482 through the selection circuit 470 (②).

[0112] After the activation command ACT1 is provided and the delay time tRCD has passed, that is, at the third time t3, a write command WC1 and an address A3 may be provided. Address A3 may indicate the first memory area MA1 of the first memory body 411. In response to the write command WC1 and the address A3, the write circuit 440 may write the second data DATA2 stored in the second data buffer 482 into the first memory area MA1 (③). In this way, the first data DATA1 stored in the first memory area MA1 may be replaced with the second data DATA2. In this case, the second data DATA2 stored in the second data buffer 482 may be transferred to the first data buffer 481, and the second data DATA2 may be provided from the first data buffer 481 to the write circuit 440. In an exemplary embodiment, as shown in reference Figure 7 As described, the second data DATA2 may be written based on the comparison result obtained by the data comparison write circuit 450 with respect to the first data DATA1 and the second data DATA2 .

[0113] After the write command WC1 is provided and the delay time tWC2WC has passed, that is, at the fourth time t4, the write command WC2 and the address A4 may be provided. The address A4 may indicate the second memory area MA2 of the second memory body 412. In response to the write command WC2 and the address A4, the write circuit 440 may write the first data DATA1 stored in the first data buffer 481 into the second memory area MA2 (④). In this way, the second data DATA2 stored in the second memory area MA2 may be replaced with the first data DATA1. In this case, the first data DATA1 stored in the first data buffer 481 may be transferred to the second data buffer 482, and the first data DATA1 may be provided from the second data buffer 482 to the write circuit 440. In an exemplary embodiment, as shown in reference Figure 7 As described, the first data DATA1 may be written based on the comparison result of the data comparison write circuit 450 obtained with respect to the first data DATA1 and the second data DATA2 .

[0114] As described above, in the case of exchanging data stored in different memory banks, such as referring to Fig. 9 and Fig.11 As described above, the memory device 400 can exchange data by using the activation command ACT and the exchange activation command SACT. In this case, the memory device 400 can control the selection circuit 470 to exchange data based on the data generated by the data comparison write circuit 450 and the XOR gate 460. Alternatively, in the case of exchanging data stored in different memory banks, as shown in FIG. Fig.12 and Fig.13 As described, the memory device 400 can exchange data by using the activation command ACT without exchanging the activation command SACT. In this case, the memory device 400 can control the selection circuit 470 to exchange data without using the data generated by the data comparison write circuit 450 and the XOR gate 460. Fig.12 and Fig.13 The data exchange operations described in this article are similar to those described in the reference section in the case of exchanging data stored in different memory banks. Fig. 9 and Fig.11 Compared with the case of the data exchange operation described above, data can be exchanged faster.

[0115] As described above, the memory device 400 according to the exemplary embodiment of the present disclosure can generate data identical to the data to be exchanged (e.g., the second data DATA2) by using the data comparison write (DCW) circuit 450 and the XOR gate 460. In this case, the data to be exchanged can be understood as being temporarily stored (or buffered or latched) by the data comparison write circuit 450 and the XOR gate 460 before the data to be exchanged is stored in the data buffer block 480.

[0116] In this way, the memory device 400 can generate or temporarily store the data to be exchanged (eg, the second data DATA2) by using a separate data generation logic such as the data comparison write circuit 450 and the XOR gate 460. Figures 7 to 13 As shown, the memory device 400 may include a data comparison write circuit 450 and an XOR gate 460 as data generation logic, but the present disclosure is not limited thereto. For example, the memory device 400 may be implemented as having any logic (or block or circuit) capable of generating data to be exchanged or temporarily storing data to be exchanged.

[0117] Fig.14 A block diagram of a memory system according to an exemplary embodiment of the present disclosure is shown. Fig.14 , the memory system 2000 may include a memory controller 20 and a memory device 500. The memory device 500 may include a memory cell array 510, a data buffer block 520, and an error detection circuit 530. The operation of the memory device 500 is similar to Figure 7 The operation of the memory device 400 is described in detail, and therefore, additional description will be omitted to avoid redundancy. That is, the memory device 500 may further include components such as a data comparison write circuit, but for ease of description, the following description is omitted. Fig.14 Such components are omitted.

[0118] The memory device 500 may exchange the first data DATA1 stored in the first memory area MA1 with the second data DATA2 stored in the second memory area MA2. The memory device 500 may exchange data by using the data buffer block 520, as shown in FIG. Figures 7 to 13 During the exchange process, the data buffer block 520 may store the first data DATA1 and the second data DATA2.

[0119] Before being written into the memory cell array 510, the first data DATA1 and the second data DATA2 stored in the data buffer block 520 may be provided to the error detection circuit 530. The error detection circuit 530 may detect errors of the first data DATA1 and the second data DATA2. For example, the error detection circuit 530 may perform a parity check to detect errors.

[0120] When an error is detected, the memory device 500 may provide an error detection signal ALERT to the memory controller 20. In response to the error detection signal ALERT, the memory controller 20 may provide error-corrected data ECDAT to the memory device. For example, when an error is detected from the first data DATA1, the memory controller 20 may provide the error-corrected first data to the memory device 500.

[0121] The error-corrected data ECDAT may be stored in the data buffer block 520. In this case, the data of the data buffer block 520 may be replaced with the error-corrected data ECDAT. In this way, the error-corrected data ECDAT of the data buffer block 520 may be written to the memory cell array 510. For example, when an error is detected from the first data DATA1 stored in the first memory area MA1, the error-corrected first data may be written to the second memory area MA2 in the swap process.

[0122] exist Fig.14 2 shows an example in which the memory device 500 detects an error in the data and receives the error-corrected data ECDAT from the memory controller 20 during the data exchange process, but the present disclosure is not limited thereto. For example, the memory device 500 may detect and directly correct the error in the data during the data exchange process. In this case, the memory device 500 may not provide the error detection signal ALERT to the memory controller 20. That is, the memory device 500 may directly correct the error in the data and may perform the exchange operation based on the error-corrected data.

[0123] Fig.15 A block diagram of a memory system according to an exemplary embodiment of the present disclosure is shown. Fig.15 , the memory system 3000 may include a memory controller 30 and a memory device 600. The memory device 600 may include a memory cell array 610, a data buffer block 620, a swap buffer block 630, and an error detection circuit 640. The operation of the memory device 600 is similar to Figure 2 The operation of the memory device 200 is described in detail, and therefore, additional description will be omitted to avoid redundancy. That is, the memory device 600 may further include components such as a data comparison write circuit, but for ease of description, the following description is omitted. Fig.15 Omit such components.

[0124] The memory device 600 may exchange the first data DATA1 stored in the first memory area MA1 with the second data DATA2 stored in the second memory area MA2. The memory device 600 may exchange data by using the data buffer block 620 and the exchange buffer block 630, as shown in FIG. Figures 2 to 5During the swap process, the data buffer block 620 may store the first data DATA1, and the swap buffer block 630 may store the second data DATA2.

[0125] Before being written into the memory cell array 610, the first data DATA1 stored in the data buffer block 620 and the second data DATA2 stored in the exchange buffer block 630 may be provided to the error detection circuit 640. The error detection circuit 640 may detect errors of the first data DATA1 and the second data DATA2. For example, the error detection circuit 640 may perform a parity check to detect an error.

[0126] When an error is detected, the memory device 600 may provide an error detection signal ALERT to the memory controller 30. In response to the error detection signal ALERT, the memory controller 30 may provide error-corrected data ECDAT to the memory device 600. For example, when an error is detected from the first data DATA1, the memory controller 30 may provide the error-corrected first data to the memory device 600.

[0127] The error-corrected data ECDAT may be stored in the data buffer block 620 or the exchange buffer block 630. For example, the error-corrected first data may be stored in the data buffer block 620, and the error-corrected second data may be stored in the exchange buffer block 630. In this case, the data of the data buffer block 620 or the exchange buffer block 630 may be replaced with the error-corrected data ECDAT. In this way, the error-corrected data ECDAT may be written to the memory cell array 610.

[0128] Fig.15 2 shows an example in which the memory device 600 detects an error in the data and receives the error-corrected data ECDAT from the memory controller 30 during the data exchange process, but the present disclosure is not limited thereto. For example, the memory device 600 may detect and directly correct the error in the data during the data exchange process. In this case, the memory device 600 may not provide the error detection signal ALERT to the memory controller 30. That is, the memory device 600 may directly correct the error in the data and may perform the exchange operation based on the error-corrected data.

[0129] As described above, according to the exemplary embodiments of the present disclosure, data errors can be corrected during the data exchange process, thereby improving the reliability of the data stored during the data exchange process.

[0130] Fig.16 is a block diagram of a computing device according to an exemplary embodiment of the present disclosure. Fig.16, computing device 4000 may include processor 4100, memory controller 4200, main memory 4300, system interconnect 4400, storage device 4500, user interface 4600, and modem 4700. Computing device 4000 may be implemented with one of various computing devices such as a desktop computer, a notebook computer, a data server, an application server, a smart phone, and a smart tablet computer.

[0131] The processor 4100 may be a central processing unit (CPU) or an application processor (AP) that performs various operations. The processor 4100 controls various components of the computing device 4000 to perform a write operation, a read operation, or any other operation. For example, the processor 4100 may access the main memory 4300 by using the memory controller 4200.

[0132] The memory controller 4200 may allow the main memory 4300 to perform a write operation or a read operation under the control of the processor 4100. For example, the memory controller 4200 may allow the main memory 4300 to perform a write operation on the data signal DQ.

[0133] In an embodiment, the memory controller 4200 may include a reference Figures 1 to 15 The functions of the memory controllers 10 to 30 are described. For example, the memory controller 4200 may provide a command CMD and address ADDR data for exchange to the main memory 4300.

[0134] The main memory 4300 may receive an address ADDR and a command CMD from the memory controller 4200. The main memory 4300 may exchange a data signal DQ with the memory controller 4200. The main memory 4300 may include a volatile memory such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), or a nonvolatile memory such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM).

[0135] In an embodiment, the main memory 4300 may include a reference Figures 1 to 15One of the memory devices 100 to 600 described above. For example, the main memory 4300 may exchange data in response to a command CMD and an address ADDR for exchange. The main memory 4300 may exchange data internally without using the memory controller 4200. Therefore, the data exchange speed may be increased, and the communication overhead between the main memory 4300 and the memory controller 4200 caused by the data exchange may be reduced.

[0136] System interconnect 4400 may provide a channel between components of computing device 4000. System interconnect 4400 may be implemented in accordance with one of various standards such as peripheral component interconnect express (PCIe) and advanced microcontroller bus architecture (AMBA).

[0137] The storage device 4500 may be used as a secondary memory of the computing device 4000. The storage device 4500 may have a slower access speed than the main memory 4300, and may have a larger storage capacity than the main memory 4300. The storage device 4500 may include a hard disk drive (HDD), a solid-state drive (SSD), a portable memory, etc.

[0138] The user interface 4600 may exchange information with the user. The user interface 2400 may include a user input interface such as a keyboard, a mouse, a touch panel or a microphone to receive information from the user, and a user output interface such as a monitor, a speaker or a motor to provide information to the user.

[0139] Modem 4700 is configured to perform wired or wireless communication with an external device. Modem 4700 may be configured to implement at least one of various standards such as long-term evolution (LTE), Ethernet, wireless fidelity (Wi-Fi), and Bluetooth. In an exemplary embodiment, modem 4700 may be included in processor 4100.

[0140] The memory device according to the present disclosure can exchange data stored in one memory bank or different memory banks without using a memory controller. Therefore, data exchange can be performed quickly and communication overhead between the memory device and the memory controller can be reduced.

[0141] In addition, the memory device according to the exemplary embodiment of the present disclosure can exchange data by using an internal data comparison write circuit without using a memory controller. In this way, the data exchange operation can be performed within the memory device without adding a separate buffer for exchange.

[0142] Embodiments can be described and illustrated according to the blocks that perform one or more functions described.These blocks, which may be referred to as units or modules, etc. in this article, are physically implemented by analog and / or digital circuits (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.), and can be optionally driven by firmware and / or software.Circuit, for example, can be specifically implemented in one or more semiconductor chips, or be specifically implemented on substrate supports such as printed circuit boards.The circuit constituting the block can be realized by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware of some functions of the execution block and a processor that performs other functions of the block.Without departing from the scope of the present disclosure, each block of the embodiment can be physically divided into two or more interactive discrete blocks.Similarly, without departing from the scope of the present disclosure, the blocks of the embodiment can be physically combined into more complex frames.The aspects of the embodiment can be realized by instructions stored in a non-transitory storage medium and executed by a processor.

[0143] Although the present disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for operating a memory device, the memory device comprising a first memory area and a second memory area, the method comprising: Reading first data from a first memory area and storing the read first data in a data buffer block; performing a first exclusive-OR (XOR) operation on first data provided from the data buffer block and second data read from the second memory area to generate first result data; writing the first data stored in the data buffer block into the second memory area; performing a second XOR operation on the first data and the first result data acquired from the first memory area, the data buffer block, or the second memory area to obtain generated second data; storing the generated second data in the data buffer block; and The generated second data stored in the data buffer block is written to the first memory area.

2. The method according to claim 1, wherein: The first memory area and the second memory area are included in one memory bank.

3. The method according to claim 2, wherein: The read first data and the generated second data are stored in a first data buffer of the data buffer block, and The first data buffer corresponds to the memory bank.

4. The method according to claim 1, wherein: The first memory area is included in a first memory bank, and the second memory area is included in a second memory bank.

5. The method according to claim 4, wherein: The read first data is stored in a first data buffer of the data buffer block, and the generated second data is stored in a second data buffer of the data buffer block, and The first data buffer corresponds to the first memory bank, and the second data buffer corresponds to the second memory bank.

6. The method according to claim 5, wherein: Writing the first data stored in the data buffer block into the second memory area comprises: transferring the first data stored in the first data buffer to the second data buffer; and The first data transferred to the second data buffer is written into the second memory area.

7. The method of claim 1 , wherein writing the first data stored in the data buffer block to the second memory area comprises: When the first result data indicates that the first data of the data buffer block is identical to the second data of the second memory area, retaining the second data of the second memory area; and When the first result data indicates that the first data of the data buffer block is different from the second data of the second memory area, the second data of the second memory area is replaced with the first data.

8. The method according to claim 1, wherein: When an error is detected from the first data stored in the data buffer block, the error-corrected first data is written to the second memory area.

9. The method according to claim 1, wherein: The memory device is a phase change random access memory (PRAM).

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