A transmission electron microscope high-resolution in-situ liquid phase temperature change chip and its preparation method

Abstract

The invention discloses a transmission electron microscope high-resolution in-situ liquid phase temperature change chip and its preparation method. The lower plate of the chip has a support layer, a freezing layer, an insulating layer, a heating layer, an insulating layer, a channel and a central window; the freezing layer has four contact electrodes, a semiconductor refrigeration film and a conductive metal film; in the area where the central window and the semiconductor refrigeration film are located, the silicon is etched away to leave the channel, and the support layer covers the channel; the semiconductor refrigeration film and the conductive metal film are both placed on the support layer; with the central window as the center, a circle of metal film is deposited on the support layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the rear end is connected to the four contact electrodes; the freezing layer and the heating layer are separated by an insulating layer; the heating layer has two contact electrodes and a spiral ring heating wire, and the heating wire is located above the semiconductor refrigeration film; there are multiple small holes on the central window. The chip has the advantages of a large temperature control range, a fast temperature change rate, and can realize in-situ dynamic observation.

Description

Technical Field

[0001] The invention relates to the field of liquid phase chips, and in particular to a transmission electron microscope high-resolution in-situ liquid phase temperature-variable chip and a preparation method thereof. Background Art

[0002] In recent years, the new technology developed in the field of transmission electron microscopy technology - in-situ chip transmission electron microscope can realize the in-situ atomic scale observation of the morphological evolution and molecular structure changes of substances in solution environment. In-situ chip electron microscope technology can observe the chemical reaction process in gas-liquid environment, which is of great significance for studying the reaction principle and controlling the reaction process. The existing transmission electron microscope cryo-technique characterization is to quickly cool the sample, the solvent molecules become glassy, ​​and the sample is also instantly frozen, so as to obtain a more realistic sample morphology. Limited by the freezing state of the sample, we can often only observe the single static state of the sample when it is frozen, and cannot observe the entire three-dimensional dynamic change process of the sample in the real solution environment, which greatly limits our research on the real reaction system. The single state of matter after freezing and the inability to achieve alternating transformation are the biggest obstacles to its application. Summary of the invention

[0003] In order to overcome the above-mentioned scientific and technological bottlenecks, it is necessary to design a high-resolution in-situ liquid phase temperature-variable chip for transmission electron microscopy. The present invention provides a liquid phase freezing environment through semiconductor refrigeration and thaws with the Joule heat of the heating wire. The cooling and heating effects can be precisely controlled by the current size, thereby realizing free and flexible alternating freezing and thawing of solution phase samples.

[0004] To achieve the above-mentioned purpose, the present invention provides a transmission electron microscope high-resolution in-situ liquid phase temperature change chip, which has a structure that an upper plate and a lower plate are combined through a metal bonding layer to form a self-sealed ultra-thin chamber; the upper plate and the lower plate are both made of silicon substrates with silicon nitride or silicon oxide on both sides, the upper plate has two injection ports and a first central window, and is characterized in that the lower plate is provided with a support layer, a freezing layer, a first insulating layer, a heating layer, a second insulating layer, a channel and a second central window; the freezing layer is provided with four contact electrodes, a semiconductor refrigeration film of not less than one level and a conductive metal film, wherein the four contact electrodes are placed at the edge of the chip; in the second central window and the area where the semiconductor refrigeration film is located, the silicon is etched away to leave the channel, and the support layer covers above the hole; the semiconductor refrigeration film and the conductive metal film are both placed on the support layer on the hole, and are not directly in contact with the silicon substrate; a circle of metal film is deposited on the support layer with the second central window as the center; the front end of the semiconductor refrigeration film is placed on the metal film, and the rear end is connected to the four contact electrodes on the freezing layer; if there are at least two levels of semiconductor refrigeration films, the rear end thereof is sequentially connected to each level of semiconductor refrigeration film with metal films until the last level of semiconductor refrigeration film is connected to the four contact electrodes on the freezing layer; the freezing layer is separated from the heating layer by the first insulating layer, and the heating layer is separated from the outside by the second insulating layer; the heating layer has two contact electrodes and a spiral ring heating wire, and the heating wire is located above the semiconductor refrigeration film;

[0005] The area of ​​the upper piece is slightly smaller than that of the lower piece, the first central window of the upper piece is aligned with the second central window of the lower piece, and a plurality of small holes are formed on the first central window and the second central window.

[0006] Further, the outer dimensions of the lower piece are 2*2-10*10mm; preferably, the outer dimensions of the lower piece are 4*8mm;

[0007] Optionally, the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;

[0008] Optionally, the thickness of the silicon nitride or silicon oxide is 5-200 nm;

[0009] Optionally, the silicon substrate has a thickness of 50-500 μm.

[0010] Furthermore, a circle of U-shaped metal film is deposited on the support layer;

[0011] Optionally, the support layer is silicon nitride or silicon oxide, and has a thickness of 0.5-5 μm.

[0012] Furthermore, the freezing layer is configured as two sets of equivalent circuits, and the two sets of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; one set of circuits in the two sets of equivalent circuits is responsible for power supply and refrigeration, and the other set of circuits is responsible for real-time monitoring of the current value during semiconductor refrigeration;

[0013] Optionally, the shape of the semiconductor refrigeration film of the freezing layer is a regular rectangle; the length is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm; preferably, the semiconductor in the semiconductor refrigeration film is an n-type semiconductor and a p-type semiconductor, wherein the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0014] Optionally, the conductive metal in the conductive metal film is gold, silver or copper, with a thickness of 50nm-300nm;

[0015] Optionally, the outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm.

[0016] Furthermore, the first insulating layer and the second insulating layer are both one layer with a thickness of 30-150 nm; preferably, the first insulating layer and the second insulating layer are made of silicon nitride, silicon oxide or aluminum oxide.

[0017] Furthermore, the outer diameter of the spiral annular heating wire of the heating layer is 0.15-0.5 mm, and the thickness is 50 nm-500 nm;

[0018] Optionally, the spiral annular heating wire is made of metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide;

[0019] Optionally, the spiral ring-shaped heating wire on the heating layer is relatively symmetrical in shape, with gaps between the heating wires and no connection with each other; the heating wire at the center of the heating layer is placed on the middle insulating layer and is not in direct contact with the freezing layer.

[0020] Further, the hole is square; preferably, the length of the hole is 4-7 mm; the width is 0.25-0.9 mm;

[0021] Optionally, the first central window and the second central window are square central windows; preferably, the size of the square central window is 5 μm*5 μm-100 μm*100 μm; more preferably, the size of the square central window is 20 μm*50 μm;

[0022] Optionally, the size of the pores is 0.5 μm-5 μm.

[0023] Furthermore, the preparation method of the upper sheet is:

[0024] S1. Using a photolithography process, the first central window pattern is transferred from a photolithography mask to a Si (100) wafer A having a silicon nitride or silicon oxide layer on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1;

[0025] Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; and the development time is 50 s;

[0026] More preferably, the exposure time is 15 s;

[0027] S2. Using a reactive ion etching process, a first central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0028] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the first central window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer A-3;

[0029] Preferably, the development time is 50s;

[0030] S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0031] Preferably, the size of the pores is 0.5 μm-5 μm;

[0032] S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0033] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours;

[0034] More preferably, the etching time is 2h;

[0035] S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0036] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0037] More preferably, the exposure time is 15 s;

[0038] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0039] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000nm;

[0040] More preferably, the metal is In, Sn or Al;

[0041] S8. Laser scribe the wafer A-7 into independent chips.

[0042] Further, the preparation method of the lower sheet is:

[0043] S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

[0044] Preferably, the silicon nitride or silicon oxide layer has a thickness of 5-200 nm;

[0045] S2. Using a photolithography process, the frozen region carrier film pattern is transferred from the photolithography mask to the front side of the above wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1;

[0046] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0047] More preferably, the exposure time is 20 s;

[0048] S3. Using a reactive ion etching process, a second central window is etched on the silicon nitride layer on the back of wafer B-1, and the silicon nitride or silicon oxide in the frozen area is etched away. Then, the wafer is placed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2;

[0049] Preferably, the length of the freezing layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm;

[0050] S4. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3;

[0051] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90° C., and the etching time is 1.5-4 hours;

[0052] More preferably, the etching temperature is 80° C. and the etching time is 2 h;

[0053] S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-3 to obtain a wafer B-4;

[0054] Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

[0055] S6. Using a photolithography process, the metal film pattern is transferred from the photolithography mask to the front side of the wafer B-4, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-5;

[0056] S7. Using DC magnetron sputtering, a layer of conductive metal film is sputtered on the front side of wafer B-5, and then the front side of wafer B-7 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, to obtain wafer B-6;

[0057] Preferably, the conductive metal is gold, silver or copper, with a thickness of 50nm-300nm;

[0058] S8. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-7;

[0059] Preferably, the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0060] S9. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor refrigeration film, and obtain wafer B-8;

[0061] Preferably, the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0062] S10. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-8, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-9;

[0063] Preferably, the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0064] S11. Using radio frequency magnetron sputtering, a layer of p-type semiconductor refrigeration film is sputtered on the front side of wafer B-9, and then the front side of wafer B-9 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor refrigeration film, to obtain wafer B-10;

[0065] Preferably, the p-type semiconductor is bismuth telluride or antimony telluride;

[0066] S12. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of the wafer B-10 as an insulating layer to obtain a wafer B-11;

[0067] Preferably, the thickness of the insulating layer is 30-150 nm;

[0068] S13. Using electron beam evaporation, a layer of metal heating wire is evaporated on the front side of wafer B-11, and then the front side of wafer B-11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining wafer B-12;

[0069] Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

[0070] S14. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-12 as an insulating layer to obtain a wafer B-13;

[0071] Preferably, the thickness of the insulating layer is 30-150 nm;

[0072] S15. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the second center window is transferred from the photolithography mask to the front side of the wafer B-13, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-14;

[0073] Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W / us;

[0074] S16. Using a reactive ion etching process, the silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-14, and then the front side of the wafer B-14 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-15;

[0075] Preferably, the size of the pores is 0.5 μm-5 μm;

[0076] S17. Laser scribe the wafer B-15 into independent chips.

[0077] The present invention provides a method for preparing the transmission electron microscope high-resolution in-situ liquid phase freezing chip, characterized in that:

[0078] The preparation method of the upper sheet is:

[0079] S1. Using a photolithography process, the second center window pattern is transferred from a photolithography mask to a Si(100) wafer A having a silicon nitride or silicon oxide layer on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1;

[0080] Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; and the development time is 50 s;

[0081] More preferably, the exposure time is 15 s;

[0082] S2. Using a reactive ion etching process, a first central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0083] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the first central window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer A-3;

[0084] Preferably, the development time is 50s;

[0085] S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0086] Preferably, the size of the pores is 0.5 μm-5 μm;

[0087] S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0088] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours;

[0089] More preferably, the etching time is 2h;

[0090] S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0091] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0092] More preferably, the exposure time is 15 s;

[0093] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0094] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000nm;

[0095] More preferably, the metal is In, Sn or Al;

[0096] S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading;

[0097] The preparation method of the lower sheet is:

[0098] S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

[0099] Preferably, the silicon nitride or silicon oxide layer has a thickness of 5-200 nm;

[0100] S2. Using a photolithography process, the frozen region carrier film pattern is transferred from the photolithography mask to the front side of the above wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1;

[0101] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0102] More preferably, the exposure time is 20 s;

[0103] S3. Using a reactive ion etching process, a second central window is etched on the silicon nitride layer on the back of wafer B-1, and the silicon nitride or silicon oxide in the frozen area is etched away. Then, the wafer is placed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2;

[0104] Preferably, the length of the freezing layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm;

[0105] S4. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3;

[0106] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90° C., and the etching time is 1.5-4 hours;

[0107] More preferably, the etching temperature is 80° C. and the etching time is 2 h;

[0108] S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-3 to obtain a wafer B-4;

[0109] Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

[0110] S6. Using a photolithography process, the metal film pattern is transferred from the photolithography mask to the front side of the wafer B-4, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-5;

[0111] S7. Using DC magnetron sputtering, a layer of conductive metal film is sputtered on the front side of wafer B-5, and then the front side of wafer B-7 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, to obtain wafer B-6;

[0112] Preferably, the conductive metal is gold, silver or copper, with a thickness of 50nm-300nm;

[0113] S8. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-7;

[0114] Preferably, the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0115] S9. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor refrigeration film, and obtain wafer B-8;

[0116] Preferably, the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0117] S10. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-8, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-9;

[0118] Preferably, the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0119] S11. Using radio frequency magnetron sputtering, a layer of p-type semiconductor refrigeration film is sputtered on the front side of wafer B-9, and then the front side of wafer B-9 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor refrigeration film, to obtain wafer B-10;

[0120] Preferably, the p-type semiconductor is bismuth telluride or antimony telluride;

[0121] S12. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of the wafer B-10 as an insulating layer to obtain a wafer B-11;

[0122] Preferably, the thickness of the insulating layer is 30-150 nm;

[0123] S13. Using electron beam evaporation, a layer of metal heating wire is evaporated on the front side of wafer B-11, and then the front side of wafer B-11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining wafer B-12;

[0124] Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

[0125] S14. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-12 as an insulating layer to obtain a wafer B-13;

[0126] Preferably, the thickness of the insulating layer is 30-150 nm;

[0127] S15. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the second center window is transferred from the photolithography mask to the front side of the wafer B-13, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-14;

[0128] Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W / us;

[0129] S16. Using a reactive ion etching process, the silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-14, and then the front side of the wafer B-14 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-15;

[0130] Preferably, the size of the pores is 0.5 μm-5 μm;

[0131] S17. Laser scribing the wafer B-15 into independent chips is performed as the bottom wafer;

[0132] Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

[0133] The small hole is formed by etching the first insulating layer, the second insulating layer and the support layer. The second central window is deposited with multiple layers of silicon nitride (support layer, first insulating layer and second insulating layer). The thickness of silicon nitride is too large, and etching is required to make the window silicon nitride thinner for electron microscope observation.

[0134] The chip has the advantages of a large temperature control range (temperature range can reach -120℃ to +100℃, up to +1000 degrees), fast temperature change rate, and can realize in-situ dynamic observation. Conventional products only have a single function of heating or freezing.

[0135] The chip temperature control area of ​​the present invention is small (100μm*100μm-500μm*500μm area), and is designed with heat insulation treatment, so the heat transfer is small, so that micro-area rapid temperature control can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0136] Figure 1 It is a schematic diagram of the back channel of the lower chip of the present invention.

[0137] Figure 2 It is a schematic diagram of the front structure of the lower chip of the present invention.

[0138] Figure 3 It is a schematic diagram of the structure of each layer of the chip of the present invention.

[0139] Figure 4 It is a schematic diagram of the structure of the chip after assembly of the present invention.

[0140] Figure 5 It is an enlarged view of the first central window of the upper chip of the chip of the present invention.

[0141] Figure 6 It is an enlarged view of the second central window of the lower chip of the present invention.

[0142] Figure 7 This is an electron microscope image of a sample observed using the chip of the present invention.

[0143] Figure 8 It is a temperature standard curve diagram obtained by using the chip of the present invention. DETAILED DESCRIPTION

[0144] Embodiments of the present invention are described in detail below, and the examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by reference to the accompanying drawings are exemplary, are intended to be used to explain the present invention, and are not to be construed as limitations of the present invention. Those who do not indicate specific techniques or conditions in the embodiments are carried out according to the techniques or conditions described in the documents in this area or according to the product specification. Those who do not indicate the manufacturer of reagents or instruments used are all conventional products that can be obtained commercially.

[0145] The preparation method of the upper sheet is:

[0146] S1. Using a photolithography process, the first central window pattern is transferred from a photolithography mask to a Si (100) wafer A having a silicon nitride or silicon oxide layer on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1;

[0147] Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; and the development time is 50 s;

[0148] More preferably, the exposure time is 15 s;

[0149] S2. Using a reactive ion etching process, a first central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0150] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the first central window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer A-3;

[0151] Preferably, the development time is 50s;

[0152] S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0153] Preferably, the size of the pores is 0.5 μm-5 μm;

[0154] S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0155] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours;

[0156] More preferably, the etching time is 2h;

[0157] S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0158] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0159] More preferably, the exposure time is 15 s;

[0160] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0161] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000nm;

[0162] More preferably, the metal is In, Sn or Al;

[0163] S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading;

[0164] The preparation method of the lower sheet is:

[0165] S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

[0166] Preferably, the silicon nitride or silicon oxide layer has a thickness of 5-200 nm;

[0167] S2. Using a photolithography process, the frozen region carrier film pattern is transferred from the photolithography mask to the front side of the above wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1;

[0168] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0169] More preferably, the exposure time is 20 s;

[0170] S3. Using a reactive ion etching process, a second central window is etched on the silicon nitride layer on the back of wafer B-1, and the silicon nitride or silicon oxide in the frozen area is etched away. Then, the wafer is placed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2;

[0171] Preferably, the length of the freezing layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm;

[0172] S4. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3;

[0173] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90° C., and the etching time is 1.5-4 hours;

[0174] More preferably, the etching temperature is 80° C. and the etching time is 2 h;

[0175] S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-3 to obtain a wafer B-4;

[0176] Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

[0177] S6. Using a photolithography process, the metal film pattern is transferred from the photolithography mask to the front side of the wafer B-4, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-5;

[0178] S7. Using DC magnetron sputtering, a layer of conductive metal film is sputtered on the front side of wafer B-5, and then the front side of wafer B-7 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, to obtain wafer B-6;

[0179] Preferably, the conductive metal is gold, silver or copper, with a thickness of 50nm-300nm;

[0180] S8. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-7;

[0181] Preferably, the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0182] S9. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor refrigeration film, and obtain wafer B-8;

[0183] Preferably, the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0184] S10. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-8, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-9;

[0185] Preferably, the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0186] S11. Using radio frequency magnetron sputtering, a layer of p-type semiconductor refrigeration film is sputtered on the front side of wafer B-9, and then the front side of wafer B-9 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor refrigeration film, to obtain wafer B-10;

[0187] Preferably, the p-type semiconductor is bismuth telluride or antimony telluride;

[0188] S12. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of the wafer B-10 as an insulating layer to obtain a wafer B-11;

[0189] Preferably, the thickness of the insulating layer is 30-150 nm;

[0190] S13. Using electron beam evaporation, a layer of metal heating wire is evaporated on the front side of wafer B-11, and then the front side of wafer B-11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining wafer B-12;

[0191] Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

[0192] S14. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-12 as an insulating layer to obtain a wafer B-13;

[0193] Preferably, the thickness of the insulating layer is 30-150 nm;

[0194] S15. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the second center window is transferred from the photolithography mask to the front side of the wafer B-13, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-14;

[0195] Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W / us;

[0196] S16. Using a reactive ion etching process, the silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-14, and then the front side of the wafer B-14 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-15;

[0197] Preferably, the size of the pores is 0.5 μm-5 μm;

[0198] S17. Laser scribing the wafer B-15 into independent chips is performed as the bottom wafer;

[0199] Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

[0200] according to Figure 1-Figure 6 The following chip is made according to the structure. 1 is a transmission electron microscope high-resolution in-situ liquid phase temperature change chip; 2 is an upper chip; 3 is a lower chip; 5 is a central window; 51 is the first central window of the upper chip; 52 is the second central window of the lower chip; 6 is a small hole; 7 is a sample injection port; 8 is a heating layer, 9 is a heating wire; 10 is the central area of ​​the heating wire; 11 is four contact electrodes; 11' is a heating unit contact electrode; 12 is a silicon substrate; 13 and 14 are both silicon nitride or silicon oxide layers; 15 is a support layer; 16 is a first insulating layer; 17 is a second insulating layer; 18 is a channel; 19 is a semiconductor refrigeration film; 191 is an n-type semiconductor refrigeration film; 192 is a p-type semiconductor refrigeration film; 20 is a conductive metal film.

[0201] Example 1: Preparation of high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy

[0202] The preparation method of the upper sheet is as follows:

[0203] S1. Using a photolithography process (exposure for 15 seconds in the hard contact mode of a UV lithography machine), the first central window pattern is transferred from the photolithography mask to Si (100) wafer A with silicon nitride or silicon oxide layers on both sides, and then developed in a positive photoresist developer for 50 seconds to obtain wafer A-1; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

[0204] S2. Using a reactive ion etching process, a first central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0205] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the first central window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer for 50 seconds, and then rinsed and cleaned the surface with deionized water to obtain a wafer A-3;

[0206] S4. Using a reactive ion etching process, the thickness of silicon nitride at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and the size of the small hole is 0.5μm-5μm; then the front side of the wafer A-3 is successively immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0207] S5. Place the back side of wafer A-4 upward in a potassium hydroxide solution with a mass percentage concentration of 20% for wet etching (etching temperature is 80° C., time is 2 h) until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0208] S6. Using a photolithography process (exposure for 15 seconds in the hard contact mode of a UV lithography machine), the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer for 50 seconds, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0209] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer with a thickness of 50-2000nm to obtain a wafer A-7; the metal is a low melting point metal; the low melting point metal is In, Sn or Al;

[0210] S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading;

[0211] The preparation method of the lower sheet is:

[0212] S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

[0213] Preferably, the silicon nitride or silicon oxide layer has a thickness of 5-200 nm;

[0214] S2. Using a photolithography process (exposure for 20 seconds in hard contact mode of a UV lithography machine, using AZ5214E ​​photoresist), the frozen region carrier film pattern was transferred from the photolithography mask to the front side of the above wafer, and then developed in a positive photoresist developer for 65 seconds, and then the surface was cleaned with deionized water to obtain wafer B-1;

[0215] S3. Using a reactive ion etching process, a second central window is etched on the silicon nitride layer on the back of the wafer B-1, and the silicon nitride or silicon oxide in the freezing area is etched away, and then the wafer is placed in acetone with the back side facing up, and then rinsed with acetone to remove the photoresist to obtain a wafer B-2; the length of the freezing layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50nm-500nm;

[0216] S4. Place the back side of wafer B-2 upward into a 20% by mass potassium hydroxide solution for wet etching (etching temperature is 80°C, etching time is 2h) until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3;

[0217] S5. Using the PECVD process, silicon oxide or silicon nitride with a thickness of 0.5-5 μm is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;

[0218] S6. Using a photolithography process, the metal film pattern is transferred from the photolithography mask to the front side of the wafer B-4, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-5;

[0219] S7. Using DC magnetron sputtering, a layer of conductive metal film is sputtered on the front side of wafer B-5, and then the front side of wafer B-7 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, to obtain wafer B-6; the conductive metal is gold, silver or copper, with a thickness of 50nm-300nm;

[0220] S8. Using a photolithography process, transfer the n-type semiconductor pattern from the photolithography mask to the front side of the wafer B-6, then develop it in a positive photoresist developer, and then rinse and clean the surface with deionized water to obtain a wafer B-7; the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0221] S9. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor refrigeration film, and obtain wafer B-8; the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0222] S10. Using a photolithography process, a p-type semiconductor pattern is transferred from a photolithography mask to the front side of the wafer B-8, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-9; the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0223] S11. Using radio frequency magnetron sputtering, a layer of p-type semiconductor refrigeration film is sputtered on the front side of wafer B-9, and then the front side of wafer B-9 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor refrigeration film, to obtain wafer B-10; the p-type semiconductor is bismuth telluride or antimony telluride;

[0224] S12. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide with a thickness of 30-150 nm is grown on the semiconductor refrigeration film of the wafer B-10 as an insulating layer to obtain a wafer B-11;

[0225] S13. Using electron beam evaporation, a layer of metal heating wire is evaporated on the front side of wafer B-11, and then the front side of wafer B-11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining wafer B-12; the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

[0226] S14. Using a PECVD process, a layer of silicon nitride or silicon oxide or aluminum oxide with a thickness of 30-150 nm is grown on the metal heating wire of the wafer B-12 as an insulating layer to obtain a wafer B-13;

[0227] S15. Using an ultraviolet laser direct writing lithography process (photoresist is AZ5214E; output power is 260W / us), the small hole pattern of the second center window is transferred from the photolithography mask to the front side of the wafer B-13, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-14;

[0228] S16. Using a reactive ion etching process, the silicon nitride or silicon oxide is etched at the small hole (the size of the small hole is 0.5 μm-5 μm) on the back side of the wafer B-14, and then the front side of the wafer B-14 is placed in acetone for immersion, and finally rinsed with acetone to remove the photoresist, thereby obtaining a wafer B-15;

[0229] S17. Laser scribing the wafer B-15 into independent chips is performed as the bottom wafer;

[0230] Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

[0231] Example 2: Use of high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy

[0232] A supersaturated calcium hydroxide aqueous solution (containing trace calcium hydroxide particles) was injected into the injection port of the transmission electron microscope high-resolution in-situ liquid phase temperature change chip prepared in Example 1, and the chip temperature was set to -30°C by an external temperature control device combined with temperature control software to obtain Figure 7 Electron micrographs from Figure 7 From A and B, we can see that as the temperature increases, the solubility of the solute gradually decreases, and solid calcium hydroxide is precipitated. The nanoparticles are solid calcium hydroxide precipitated during the chip temperature increase process. By controlling the amount of power supplied to the chip, the temperature of the solution in the chip can be monitored and controlled in real time. This temperature range can be reached for liquid phase reactions.

[0233] Example 3: Temperature Standard Curve

[0234] Before using the TEM high-resolution in-situ liquid phase temperature-variable chip, a temperature meter was used to measure the temperature reached by the chip under different output powers to obtain a temperature standard curve, and then the temperature was precisely controlled by precisely adjusting the output power of the power supply device. Figure 8 . Figure 8 The slope of the line graph roughly reflects the heating and cooling rate of 5-6℃ per second, indicating that the temperature change rate is fast. The temperature range can reach -120℃ to +100℃, and the highest can reach +1000 degrees, indicating that the chip of the present invention has a large temperature control range, from low temperature to high temperature. Conventional products only have a single function of heating or freezing.

[0235] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention.

Claims

1. A high-resolution in-situ liquid phase temperature-variable chip for transmission electron microscopy, wherein the upper chip and the lower chip are combined through a metal bonding layer to form a self-enclosed ultra-thin chamber; the upper chip and the lower chip are both made of silicon substrates with silicon nitride or silicon oxide on both sides, the upper chip has two injection ports and a first central window, and is characterized in that: The lower chip is provided with a support layer, a freezing layer, a first insulating layer, a heating layer, a second insulating layer, a hole and a second central window; the freezing layer is provided with four contact electrodes, a semiconductor refrigeration film of not less than one level and a conductive metal film, wherein the four contact electrodes are placed at the edge of the chip; in the area where the second central window and the semiconductor refrigeration film are located, the silicon is etched away to leave the hole, and the support layer covers the hole; the semiconductor refrigeration film and the conductive metal film are both placed on the support layer on the hole, and are not directly in contact with the silicon substrate; with the second central window as the center, a metal film is deposited on the support layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the rear end is connected to the four contact electrodes on the freezing layer; if there are at least two levels of semiconductor refrigeration films, the rear end thereof is sequentially connected to each level of semiconductor refrigeration films with metal films until the last level of semiconductor refrigeration film is connected to the four contact electrodes on the freezing layer; the freezing layer and the heating layer are separated by the first insulating layer, and the heating layer is separated from the outside by the second insulating layer; the heating layer has two contact electrodes and a spiral ring heating wire, and the heating wire is located above the semiconductor refrigeration film; The area of ​​the upper sheet is smaller than that of the lower sheet, the first central window of the upper sheet is aligned with the second central window of the lower sheet, and the first central window and the second central window are both provided with a plurality of small holes; The outer dimensions of the lower sheet are 2*2-10*10mm; the semiconductors in the semiconductor refrigeration film are n-type semiconductors and p-type semiconductors, wherein the n-type semiconductor is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride.

2. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; and / or The thickness of the silicon nitride or silicon oxide is 5-200 nm; and / or The thickness of the silicon substrate is 50-500 μm.

3. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 2, characterized in that: The material of the metal bonding layer is In, Sn or Al.

4. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The outer dimensions of the lower piece are 4*8mm.

5. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: A circle of U-shaped metal film is deposited on the support layer; and / or The support layer is silicon nitride or silicon oxide, and has a thickness of 0.5-5 μm.

6. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The freezing layer is configured as two sets of equivalent circuits, and the two sets of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; one set of circuits in the two sets of equivalent circuits is responsible for power supply and refrigeration, and the other set of circuits is responsible for real-time monitoring of the current value during semiconductor refrigeration; and / or The shape of the semiconductor refrigeration film of the freezing layer is a regular rectangle; the length is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm; and / or The conductive metal in the conductive metal film is gold, silver or copper, and has a thickness of 50nm-300nm; and / or The outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm.

7. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The first insulating layer and the second insulating layer are both one layer, and the thickness is 30-150 nm.

8. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 7, characterized in that: The first insulating layer and the second insulating layer are both made of silicon nitride, silicon oxide or aluminum oxide.

9. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The outer diameter of the spiral annular heating wire of the heating layer is 0.15-0.5 mm, and the thickness is 50 nm-500 nm; and / or The spiral annular heating wire is made of metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; and / or The spiral ring-shaped heating wires on the heating layer are relatively symmetrical in shape, with gaps between the heating wires and no connection with each other; the heating wires at the center of the heating layer are placed on the middle insulating layer and are not in direct contact with the freezing layer.

10. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The hole is square; and / or The first central window and the second central window are square central windows; and / or The size of the small holes is 0.5 μm-5 μm.

11. The transmission electron microscope high-resolution in-situ liquid phase temperature change chip according to claim 10, characterized in that: The size of the square central window is 5 μm*5 μm-100 μm*100 μm.

12. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy according to claim 11, characterized in that: The size of the square central window is 20 μm*50 μm.

13. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 10, characterized in that: The length of the channel is 4-7 mm, and the width is 0.25-0.9 mm.

14. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The preparation method of the upper sheet is: S1. Using a photolithography process, the first central window pattern is transferred from a photolithography mask to a Si (100) wafer A having a silicon nitride or silicon oxide layer on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1; S2. Using a reactive ion etching process, a first central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2; S3. Using an ultraviolet laser direct writing process, the small hole pattern of the first central window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer A-3; S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4; S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5; S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6; S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7; S8. Laser scribe the wafer A-7 into independent chips.

15. The transmission electron microscope high-resolution in-situ liquid phase temperature change chip according to claim 14, characterized in that: In the preparation method of the upper sheet, The photolithography process in step S1 is exposure in the hard contact mode of the UV photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s; and / or S2. using a reactive ion etching process to etch a first central window on the silicon nitride layer on the front side of the wafer A-1, and then immersing the wafer A-1 with the front side facing up in acetone, and finally rinsing with a large amount of deionized water to remove the photoresist, thereby obtaining a wafer A-2; and / or The development time in step S3 is 50s; and / or The size of the small hole in step S4 is 0.5 μm-5 μm; and / or The mass percentage concentration of the potassium hydroxide solution in step S5 is 20%; the etching temperature is 80° C. and the etching time is 1.5-4 hours; and / or The photolithography process in step S6 is exposure in the hard contact mode of the UV photolithography machine; the development time is 50s; and / or In step S7, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm; and / or S8. Laser scribe the wafer A-7 into independent chips.

16. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 15, characterized in that: In the method for preparing the upper film, the exposure time in step S1 is 15 seconds; and / or The etching time in step S5 is 2 hours; and / or The exposure time in step S6 is 15 s; and / or The metal in step S7 is In, Sn or Al.

17. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 1, characterized in that: The preparation method of the lower sheet is: S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides; S2. Using a photolithography process, the frozen region carrier film pattern is transferred from the photolithography mask to the front side of the above wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1; S3. Using a reactive ion etching process, a second central window is etched on the silicon nitride layer on the back of wafer B-1, and the silicon nitride or silicon oxide in the frozen area is etched away. Then, the wafer is placed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2; S4. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3; S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-3 to obtain a wafer B-4; S6. Using a photolithography process, the metal film pattern is transferred from the photolithography mask to the front side of the wafer B-4, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-5; S7. Using DC magnetron sputtering, a layer of conductive metal film is sputtered on the front side of wafer B-5, and then the front side of wafer B-7 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, to obtain wafer B-6; S8. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-7; S9. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor refrigeration film, and obtain wafer B-8; S10. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-8, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-9; S11. Using radio frequency magnetron sputtering, a layer of p-type semiconductor refrigeration film is sputtered on the front side of wafer B-9, and then the front side of wafer B-9 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor refrigeration film, to obtain wafer B-10; S12. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of the wafer B-10 as an insulating layer to obtain a wafer B-11; S13. Using electron beam evaporation, a layer of metal heating wire is evaporated on the front side of wafer B-11, and then the front side of wafer B-11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining wafer B-12; S14. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-12 as an insulating layer to obtain a wafer B-13; S15. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the second center window is transferred from the photolithography mask to the front side of the wafer B-13, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-14; S16. Using a reactive ion etching process, the silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-14, and then the front side of the wafer B-14 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-15; S17. Laser scribe the wafer B-15 into independent chips.

18. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 17, characterized in that: In the preparation method of the lower sheet, The silicon nitride or silicon oxide layer in step S1 has a thickness of 5-200 nm; and / or The photolithography process in step S2 is exposure in the hard contact mode of the UV lithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s; and / or The length of the freezing layer semiconductor refrigeration film in step S3 is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm; and / or The mass percentage concentration of the potassium hydroxide solution in step S4 is 20%; the etching temperature is 70-90° C., and the etching time is 1.5-4 h; and / or In step S5, the thickness of silicon oxide or silicon nitride is 0.5-5 μm; and / or The conductive metal in step S7 is gold, silver or copper, with a thickness of 50nm-300nm; and / or The n-type semiconductor in step S8 is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; and / or The n-type semiconductor in step S9 is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; and / or The p-type semiconductor in step S10 is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride; and / or The p-type semiconductor in step S11 is bismuth telluride or antimony telluride; and / or The thickness of the insulating layer in step S12 is 30-150 nm; and / or In step S13, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm; and / or The thickness of the insulating layer in step S14 is 30-150 nm; and / or The photoresist used in the UV laser direct writing process in step S15 is AZ5214E; the output power is 260W / us; and / or The size of the small hole in step S16 is 0.5 μm-5 μm.

19. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 18, characterized in that: The exposure time in step S2 is 20 seconds; and / or The etching temperature in step S4 is 80° C. and the etching time is 2 h.

20. A method for preparing a transmission electron microscope high-resolution in-situ liquid phase freezing chip according to any one of claims 1 to 19, characterized in that: The preparation method of the upper sheet is: S1. Using a photolithography process, the first central window pattern is transferred from a photolithography mask to a Si (100) wafer A having a silicon nitride or silicon oxide layer on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1; S2. Using a reactive ion etching process, a first central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2; S3. Using an ultraviolet laser direct writing process, the small hole pattern of the first central window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer A-3; S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4; S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5; S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6; S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7; S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading; The preparation method of the lower sheet is: S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides; S2. Using a photolithography process, the frozen region carrier film pattern is transferred from the photolithography mask to the front side of the above wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1; S3. Using a reactive ion etching process, a second central window is etched on the silicon nitride layer on the back of wafer B-1, and the silicon nitride or silicon oxide in the frozen area is etched away. Then, the wafer is placed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2; S4. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3; S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-3 to obtain a wafer B-4; S6. Using a photolithography process, the metal film pattern is transferred from the photolithography mask to the front side of the wafer B-4, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-5; S7. Using DC magnetron sputtering, a layer of conductive metal film is sputtered on the front side of wafer B-5, and then the front side of wafer B-7 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, to obtain wafer B-6; S8. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-7; S9. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor refrigeration film, and obtain wafer B-8; S10. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-8, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-9; S11. Using radio frequency magnetron sputtering, a layer of p-type semiconductor refrigeration film is sputtered on the front side of wafer B-9, and then the front side of wafer B-9 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor refrigeration film, to obtain wafer B-10; S12. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of the wafer B-10 as an insulating layer to obtain a wafer B-11; S13. Using electron beam evaporation, a layer of metal heating wire is evaporated on the front side of wafer B-11, and then the front side of wafer B-11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining wafer B-12; S14. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-12 as an insulating layer to obtain a wafer B-13; S15. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the second center window is transferred from the photolithography mask to the front side of the wafer B-13, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-14; S16. Using a reactive ion etching process, the silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-14, and then the front side of the wafer B-14 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-15; S17. Laser scribing the wafer B-15 into independent chips is performed as the bottom wafer; Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

21. The method for preparing a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 20, characterized in that: In the preparation method of the upper sheet, The photolithography process in step S1 is exposure in the hard contact mode of the UV photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s; and / or S2. using a reactive ion etching process to etch a first central window on the silicon nitride layer on the front side of the wafer A-1, and then immersing the wafer A-1 with the front side facing up in acetone, and finally rinsing with a large amount of deionized water to remove the photoresist, thereby obtaining a wafer A-2; and / or The development time in step S3 is 50s; and / or The size of the small hole in step S4 is 0.5 μm-5 μm; and / or The mass percentage concentration of the potassium hydroxide solution in step S5 is 20%; the etching temperature is 80° C. and the etching time is 1.5-4 hours; and / or The photolithography process in step S6 is exposure in the hard contact mode of the UV photolithography machine; the development time is 50s; and / or In step S7, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm; and / or S8. Laser scribe the wafer A-7 into independent chips.

22. The method for preparing a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 21, characterized in that: In the method for preparing the upper film, the exposure time in step S1 is 15 seconds; and / or The etching time in step S5 is 2 hours; and / or The exposure time in step S6 is 15 s; and / or The metal in step S7 is In, Sn or Al.

23. The method for preparing a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 20, characterized in that: In the preparation method of the lower sheet, The silicon nitride or silicon oxide layer in step S1 has a thickness of 5-200 nm; and / or The photolithography process in step S2 is exposure in the hard contact mode of the UV lithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s; and / or The length of the freezing layer semiconductor refrigeration film in step S3 is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50 nm-500 nm; and / or The mass percentage concentration of the potassium hydroxide solution in step S4 is 20%; the etching temperature is 70-90° C., and the etching time is 1.5-4 h; and / or In step S5, the thickness of silicon oxide or silicon nitride is 0.5-5 μm; and / or The conductive metal in step S7 is gold, silver or copper, with a thickness of 50nm-300nm; and / or The n-type semiconductor in step S8 is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; and / or The n-type semiconductor in step S9 is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; and / or The p-type semiconductor in step S10 is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride; and / or The p-type semiconductor in step S11 is bismuth telluride or antimony telluride; and / or The thickness of the insulating layer in step S12 is 30-150 nm; and / or In step S13, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm; and / or The thickness of the insulating layer in step S14 is 30-150 nm; and / or The photoresist used in the UV laser direct writing process in step S15 is AZ5214E; the output power is 260W / us; and / or The size of the small hole in step S16 is 0.5 μm-5 μm.

24. The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy as claimed in claim 23, characterized in that: The exposure time in step S2 is 20 seconds; and / or The etching temperature in step S4 is 80° C. and the etching time is 2 h.

Images