Chip package and forming method thereof, semiconductor device and forming method thereof, semiconductor device and forming method thereof, three-phase system

Abstract

The present invention provides a chip package. The chip package may include: a semiconductor chip, which includes a first connection pad and a second connection pad on the front side; a carrier, which includes a pad contact area and a recess; an encapsulation material, which encapsulates the semiconductor chip; a first external connection, which is free of encapsulation material or extends out of the encapsulation material; a conductive clamp; and a contact structure, wherein the semiconductor chip is arranged so that its front side faces the carrier, wherein the first connection pad is above the recess and the second connection pad contacts the pad contact area, wherein the clamp is arranged on the back side of the semiconductor chip, covering the semiconductor chip, at the semiconductor chip, the clamp extends above the recess, and wherein the conductive contact structure conductively connects the first connection pad to the first external connection.

Description

Technical Field

[0001] Various embodiments generally relate to semiconductor devices, semiconductor apparatus, three-phase systems, methods of forming semiconductor devices, and methods of forming semiconductor apparatus. Background Art

[0002] Surface mount devices (SMD packages) of packages including semiconductor chips are often used in high current devices. SMD packages may generate considerable amounts of heat during operation. The heat generated in the semiconductor chip may have to be dissipated to the outside of the package as effectively as possible.

[0003] However, currently, all SMD packages (power and standard) rely only on bottom side cooling, for example, by mounting the SMD package on a printed circuit board (PCB) with high thermal conductivity, such as an insulated metal substrate (IMS). Summary of the invention

[0004] A chip package is provided. The chip package may include: a semiconductor chip including a first connection pad and a second connection pad on a front side; a carrier including a pad contact area and a recess; an encapsulation material encapsulating the semiconductor chip; a first external connection, the first external connection having no encapsulation material or extending out of the encapsulation material; a conductive clamp; and a contact structure, wherein the semiconductor chip is arranged so that its front side faces the carrier, the first connection pad is above the recess, and the second connection pad contacts the pad contact area, wherein the clamp is arranged on the back side of the semiconductor chip, covering the semiconductor chip, at the semiconductor chip, the clamp extends above the recess, and wherein the conductive contact structure conductively connects the first connection pad to the first external connection.

[0005] A semiconductor device is provided. The semiconductor device may include: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, wherein each chip package includes: an encapsulation body encapsulating a semiconductor chip; a plurality of contact structures electrically connecting the semiconductor chip to the electronic circuit; and at least one cooling structure protruding from the encapsulation body; and a cooling element thermally connected to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, like reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0007] Figure 1shows a schematic top view (top) and a schematic cross-sectional view (bottom) of a three-phase motor drive known in the art;

[0008] Figure 2 Schematic top views of several semiconductor devices and semiconductor chip packages used in the semiconductor devices according to various embodiments are shown;

[0009] Figure 3 shows a schematic circuit (top), a schematic top view (middle), and a schematic cross-sectional view (bottom) of a three-phase motor drive according to various embodiments;

[0010] Figure 4 A flow chart showing a method of forming a semiconductor device;

[0011] Figure 5 A flow chart of a method of forming a semiconductor device is shown.

[0012] FIG. 6A to FIG. 6C shows schematic perspective views of a chip package and elements for forming a chip package according to various embodiments;

[0013] Fig. 7A and Figure 7B each of which visualizes a process of forming a chip package according to various embodiments;

[0014] Fig. 8A and Figure 8B Each of which shows a schematic diagram of a semiconductor device according to various embodiments;

[0015] Fig. 9 shows a schematic diagram of a three-phase system according to various embodiments;

[0016] Fig. 10A and Fig. 10B Each of which shows a schematic diagram of a half-bridge module according to various embodiments;

[0017] Fig.11A shows a schematic cross-sectional view of a transistor package having a source-down configuration for use in a half-bridge module according to various embodiments;

[0018] Fig. 11B shows a schematic cross-sectional view of a transistor package having a drain-down configuration for use in a half-bridge module according to various embodiments;

[0019] Fig. 12A shows a schematic diagram of a three-phase system and elements forming the three-phase system according to various embodiments;

[0020] Fig. 12Bshows a schematic diagram of a three-phase system according to various embodiments;

[0021] Fig.13 A flow chart of a method of forming a chip package according to various embodiments is shown. DETAILED DESCRIPTION

[0022] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0023] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0024] The term "over" used in relation to a deposited material formed "over" a side or surface may be used herein to indicate that the deposited material may be formed "directly" "over" an implied side or surface, such as in direct contact with the implied side or surface. The term "over" used in relation to a deposited material formed over a side or surface may be used herein to indicate that the deposited material may be formed "indirectly" "over" an implied side or surface, with one or more additional layers disposed between the implied side or surface and the deposited material.

[0025] Common reference numerals may be used for various elements, devices, apparatuses, etc., such as semiconductor apparatus 206, semiconductor apparatus 204, etc. To distinguish different embodiments, examples, etc., different lower case letters are attached to corresponding reference numerals, such as semiconductor apparatus 206a, 206b, and 206c, etc.

[0026] Figure 1 A schematic top view (top) and a schematic cross-sectional view (bottom) of a three-phase motor drive 100 known in the art are shown.

[0027] The circuit diagram of three phase motor driver is Figure 3 (top), and this circuit diagram can also be applied to Figure 1 A three-phase motor driver 100. For motor driver 100 applications, a commonly used circuit is a three-phase inverter, which may include three MOSFET half-bridges, supplying energy to the motor (only its induction coils are shown and labeled as "Phase A", "Phase B" and "Phase C"). An example of an application for such a motor may be an electric forklift vehicle, whose effective current I RMS For example, up to about 1000A. To handle such high currents, devices may need to be connected in parallel. For an exemplary forklift, up to 28 MOSFETs may be used in parallel, with each individual MOSFET Figure 3(top), resulting in a total of 6x28=168 MOSFETs. Figure 1 In the top view of FIG. 1 , each individual MOSFET in the circuit diagram uses six MOSFETs in parallel, resulting in a total of 36 MOSFETs.

[0028] For such circuits, currently, circuit boards based on insulated metal substrates (IMS) with good thermal characteristics are usually used. Sometimes, printed circuit boards (PCBs) based on FR4 can be used. In order to handle the high current on the board, sometimes, such as Figure 1 Schematically shown in FIG. 1 are copper (Cu) strips 110, 112, 114. However, high currents may generate a lot of heat. The heat that may be generated in the power MOSFET may need to be dissipated to the environment as effectively as possible.

[0029] As in Figure 1 As can be seen in the schematic cross-sectional view (bottom) of FIG. 1 , currently used configurations of motor drive 100 may have at least one electrical "bottleneck" in the dielectric layer of carrier 118 / 124 at a location labeled "Bottleneck 4: 50 μΩ". The labels indicate that the electrical bottleneck corresponds to a portion of circuit 100 having relatively high package and parasitic board resistances and corresponding parasitic inductances. Furthermore, as indicated by the gray arrows, heat flow occurs substantially in only one direction: from packaged chip 120 through conductive chip carrier 122 into carrier 118 / 124.

[0030] In various embodiments, a surface mount device (SMD) package with a heat sink is used. The SMD package with a heat sink can achieve improved bottom side cooling. Alternatively or in addition, top side cooling can be used. As a result, the overall thermal performance of the system can be improved, for example, due to improved heat flow from the SMD to the carrier.

[0031] In various embodiments, the heat sink may be provided as a so-called thermal extension, eg a so-called drain tab.

[0032] exist Figure 3 An exemplary embodiment of a semiconductor device 200 using such an SMD package 204 (or more precisely, a plurality of such SMD packages 204) is shown in FIG. Figure 3 A schematic circuit 300 (top), a schematic top view (middle), and a schematic cross-sectional view (bottom) of a semiconductor device 200 (in this specific example, a three-phase motor driver) according to various embodiments are shown. In the semiconductor device 200, semiconductor chip packages 204 (also referred to as chip packages or simply packages) that are grouped together as semiconductor devices 206 are used.

[0033] exist Figure 2, various exemplary embodiments of a semiconductor device 206 and a semiconductor chip package 204 used in the semiconductor device 206 are shown according to various embodiments. Each chip package 204 may include at least one semiconductor chip 120. The semiconductor chip 120 may have a front side with at least one chip contact. Figure 3 In (bottom), only the leads contacting the chip contacts are shown, without showing the chip contacts themselves. The semiconductor chip 120 may also have a back side opposite to the front side. The back side may form another contact of the semiconductor chip 120, for example, a drain contact. Alternatively, the back side may be electrically insulating and only thermally conductive.

[0034] In various embodiments, the semiconductor device 206 may include a cooling element 208 and a plurality of semiconductor chip packages 204 mounted on the cooling element 208. Each chip package 204 may include an encapsulation 130 encapsulating a semiconductor chip 120, a plurality of contact structures 116 for electrically contacting the semiconductor chip 120 (from the outside of the chip package 204), and at least one cooling structure 202 protruding from the encapsulation 130. The cooling element 208 may be thermally conductively connected to at least one cooling structure 202 of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages 204.

[0035] In various embodiments, at least one cooling structure 202 may be directly connected to the semiconductor chip 120. For example, the semiconductor chip 120 may be mounted with its back side on the cooling structure 202, eg back-bonded (eg soldered, glued or sintered) to the cooling structure 202.

[0036] In various embodiments, the cooling structure 202 may be electrically conductive.The cooling structure 202 may, for example, include or consist of one or more metals, such as aluminum, copper, an aluminum alloy and / or a copper alloy.

[0037] In various embodiments, each of the semiconductor chip packages 204 may form a transistor, eg a MOSFET or an IGBT, or a diode. The semiconductor chip package 204 may be, for example, a power semiconductor device, eg a power transistor or a power diode.

[0038] In various embodiments, eg in case the semiconductor chip package 204 forms a transistor, each of the plurality of contact structures 116 may include at least one control contact structure and at least one controlled contact structure.

[0039] For example, in case a controlled chip contact is formed on the back side of the semiconductor chip 120 and the cooling structure 202 is electrically conductive, the cooling structure 202 may form a further controlled contact structure.

[0040] In various embodiments, at least one cooling structure 202 of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages 204 may be electrically connected by a cooling element 208 .

[0041] Figure 2 Various exemplary embodiments are shown of how this may be achieved if both the cooling structure 202 and the cooling element 208 are electrically conductive and the cooling structure 202 is electrically connected to the cooling element 208 .

[0042] The cooling element 208 may, for example, include or consist of one or more metals, such as aluminum, copper, an aluminum alloy and / or a copper alloy.

[0043] Each of the plurality of semiconductor chip packages 204 may be mounted on a cooling element 208. In various embodiments, the semiconductor chip package 204 may be mounted on the cooling element 208 only through the cooling structure 202, for example, as shown in semiconductor devices 206a, 206d, and 206e. In other embodiments, the semiconductor chip package 204 may be mounted on the cooling element 208 through the cooling structure 202 and the encapsulation body 130, for example, as shown in semiconductor devices 206b and 206c.

[0044] The encapsulation 130 may, for example, include or consist of a molding material or a laminate.

[0045] The plurality of semiconductor chip packages 204 may be surface mounted devices. This means that the semiconductor chip packages 204 may be configured such that their contact structures 116 are attached to a printed circuit board (PCB, see for example Figure 3 , bottom) of an electronic circuit 124 or a surface of a carrier 128 of an insulated metal substrate (IMS) on which the circuit 124 is arranged, rather than having the contact structures protrude through openings in the carrier 128.

[0046] In various embodiments, from Figure 3 As can be seen in the cross-sectional view of FIG, the semiconductor chip package 204 can be (surface) mounted to the carrier 128, and the cooling structure 202 is in thermal and electrical contact with the carrier 128. The electrical contact can lead to the circuit 124. The circuit 124 may include or consist of leads separated by electrically insulating portions 226, such as metal leads.

[0047] In other words, the semiconductor chip package 204 may be (surface) mounted to the carrier 128 so that the corresponding cooling structure 202 may be in electrical contact with the circuit 124, in which case the bottom side of the cooling structure 202 is in electrical contact with the circuit 124, the cooling structure 202 may be a contact structure of the semiconductor chip package 204 and may be exposed on the bottom side of the chip package 204.

[0048] In various embodiments, cooling elements 208 may be mounted to the top side of each cooling structure 202 .

[0049] In various embodiments, a plurality of cooling structures 202 may be provided in each chip package 204. It may be sufficient if only one of the cooling structures 202 of each chip package 204 is connected to the cooling element 208.

[0050] In various embodiments, the thermal connection between the plurality of cooling structures 202 and the cooling element 208 may be formed by welding, gluing, sintering, etc., or by screw connection, or by a combination thereof (eg, screw connection combined with conductive glue). The thermal connection may simultaneously form a conductive connection.

[0051] To achieve the screw connection, the cooling structure 202 (eg, cooling tab) may be provided with an opening, such as a hole 220, such as a threaded hole. The cooling element 208 may be provided with a corresponding opening, such as a hole ( Figure 2 222 as the opening is filled and covered by screw 222).

[0052] like Figure 2 As shown, for example, in semiconductor devices 206a, 206b, 206c, 206d, and 206e, a plurality of semiconductor chip packages 204 may be arranged in at least one row, for example, arranged in a single row (in semiconductor devices 206a, 206b, 206c, and 206d), or arranged in a combination of a first row and a second row. In this context, “arrangement” may be understood to refer to a manner in which the semiconductor chip packages 204 are mounted on the cooling element 208.

[0053] Figure 2 and Figure 3 2 shows an exemplary embodiment in which a combination of two semiconductor devices 206, 206a together forms a semiconductor device 206, 206e, 206f having two rows of semiconductor chip packages 204 and two cooling element portions 208. The cooling element 208 may include a first cooling element portion thermally coupled to the cooling structures 202 of the semiconductor chip packages 204 of the first group and a second cooling element portion thermally coupled to the cooling structures 202 of the semiconductor chip packages 204 of the second group.

[0054] For example, the semiconductor devices 206, 206e, 206f themselves may be considered as semiconductor devices 206, because the semiconductor devices form functional devices, such as one of the semiconductor devices 206a is connected to the high side of the circuit, while another semiconductor device 206a is connected to the low side of the circuit, e.g. Figure 3 300. In the semiconductor device 206e, the two cooling element parts of the cooling element 208 may be integrally formed.

[0055] In various embodiments, all semiconductor chip packages 204 of the first group may be arranged to have the same first orientation. If present, the semiconductor chip packages 204 of the second group may be arranged to have the same second orientation, which may be the same as or different from the first orientation. Figure 2 As shown, for semiconductor device 206e, the first group can be arranged so that the source contact of each chip package 204 is exposed at the bottom ("source-down product"), and the second group can be arranged so that the drain contact of each chip package 204 is exposed at the bottom ("drain-down product").

[0056] In various embodiments, the cooling element 208 may be configured to perform another function in addition to cooling, for example, the cooling element 208 may include a conductive coil.

[0057] In various embodiments, the cooling structure 202 may have any shape as long as it is compatible with the cooling function to be provided for the chip package 204. Figure 2 and Figure 3 In the illustrated embodiment, the cooling structure 202 may be (e.g., rectangular) cooling tabs 202a, 202b, wherein the cooling tab 202a may be provided with an opening 220 for screwing the cooling structure 202 to the cooling element 208, and the cooling tab 202b may be provided without the opening 220. In other embodiments (not shown), the cooling structure 202 may have multiple segments, a three-dimensional structure (e.g., having one or more fins extending from a plane, having a clamp-like structure for clamping on the cooling element 208), or the like.

[0058] In various embodiments, such as Figure 3 As shown, a plurality of semiconductor devices 206 may be integrated into the semiconductor device 200 .

[0059] The semiconductor device 200 may include a carrier 128 including an electronic circuit 124 (conductive lines / traces 124 formed in or on the carrier 128) and a plurality of semiconductor chip packages 206 mounted on the carrier 128. Each of the packages 206 may include: an encapsulation 130 encapsulating a semiconductor chip 120; a plurality of contact structures 116 electrically connecting the semiconductor chip 120 to the electronic circuit 124; and at least one cooling structure 202 protruding from the encapsulation 130; and a cooling element 208 thermally conductively connected to the at least one cooling structure 202 of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages 206.

[0060] like Figure 3 As shown in the cross-sectional view, especially with Figure 1 In contrast, the cooling structure 202 and the cooling element 208 thermally conductively connected thereto may allow an additional heat flow 332 through the cooling structure 202 into the cooling element 208, and the thermal connection between the cooling structure 202 and the carrier 128 may allow another additional heat flow 334 through the cooling structure 202 into the carrier 128. In other words, top-side cooling (heat flow 332) or double-sided cooling (through heat flows 332 and 334) may additionally be achieved.

[0061] In the case where the cooling structures 202 and the cooling elements 208 are electrically conductive, the amount of current that can be conducted through the semiconductor device 200 (in the case of the cooling elements 208) can be increased, particularly in the case where each cooling structure 202 is electrically coupled to the semiconductor chip 120 and the electronic circuit 124 to form another contact structure. Figure 1 and Figure 3 In particular, Figure 1 The "bottleneck 4" of the embodiment can be avoided. The thermal resistance and / or thermal impedance (e.g., junction-to-ambient resistance) can be reduced without requiring additional carrier (e.g., PCB) space. In experiments, even without the additional cooling element 208, the junction-to-carrier thermal resistance R thjc If the cooling element 208 is provided as an additional heat sink, the junction-to-carrier thermal resistance R thjc Even greater than 20% improvement will be obtained.

[0062] Furthermore, power dissipation performance can be improved, thereby increasing power density, and parasitic inductance and resistance can be slightly reduced.

[0063] In particular, in embodiments using source-down and / or drain-down semiconductor devices and using metal (eg, Cu) strips as additional heat sinks, source inductance and board resistance may be improved (one less bottleneck) and power density may be increased.

[0064] The semiconductor device 200 may therefore be suitable for forming a power semiconductor device. This term may also be applied to each chip package 204, which itself may form a power device, such as a (power) MOSFET, a (power) IGBT, or a (power) diode.

[0065] like Figure 3 As shown in the exemplary embodiment of , the semiconductor device 200 can form a half bridge or a part of a half bridge. In other words, the electronic circuit 124 and the plurality of semiconductor chip packages 204 can be connected to include (eg, in parallel) a half bridge. Figure 3 As seen in the schematic circuit 300 on top of , the semiconductor devices may form a three-phase system comprising a plurality of half-bridges, in this case a motor drive. Figure 3 The motor itself is not shown in the middle schematic diagram of , but each of the plurality of semiconductor devices 206 includes a plurality of semiconductor devices 204 which are thermally and electrically connected in groups via a plurality of cooling elements 208 (eg, copper strips). Figure 2 The semiconductor device 206a shown (in each of the groups of semiconductor devices 206a, the semiconductor devices 204 are arranged to have the same orientation, and the cooling element 208 is attached by gluing, welding, sintering, etc.), and the semiconductor device 206g is also used, which is the same as the semiconductor device 206g. Figure 2 The semiconductor device 206e is similar to the semiconductor device 206e, except that the cooling element 208 is attached by gluing, welding, sintering, etc. instead of screw connection. Of course, other embodiments of the semiconductor device 206 can be used in the semiconductor device 200 instead of the embodiment shown. The motor drive can be used in high-power applications, such as in electric forklifts and the like.

[0066] In various embodiments, the electronic circuit 124 and the plurality of semiconductor chip packages 204 may be connected to form or include a full bridge.

[0067] Figure 4 A flow chart 400 of a method of forming a semiconductor device is shown.

[0068] The method may include: mounting a plurality of semiconductor chip packages onto a carrier (in 410), wherein the carrier includes an electronic circuit and each chip package includes an encapsulation body encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip to the electronic circuit, and at least one cooling structure protruding from the encapsulation body; and thermally connecting a cooling element to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages (in 420).

[0069] The mounting of the plurality of semiconductor chip packages may include surface mounting the semiconductor chip packages to a carrier (eg, a PCB or an IMS), for example, by known surface mounting techniques.

[0070] In various embodiments, mounting of the chip packages may be performed such that a first group of semiconductor chip packages may be arranged prior to mounting to form a first row. All semiconductor chip packages of the first group may be arranged to have the same first orientation.

[0071] The cooling element may include a first cooling element portion and may be thermally coupled to the cooling structure of the semiconductor chip packages of the first group via the first cooling element portion.

[0072] Similarly, before mounting, a second group of semiconductor chip packages may be arranged to form a second row. All semiconductor chip packages of the second group may be arranged to have the same second orientation, which may be identical to the first orientation or different from the first orientation.

[0073] The cooling element may include a second cooling element portion which may be thermally coupled to the cooling structure of the semiconductor chip packages of the second group.

[0074] Thermally conductively connecting the cooling element may include welding, gluing or sintering the cooling element to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages. Other known methods suitable for thermally conductively connecting the cooling element to the cooling structure may be used. In various embodiments, the cooling element and the cooling structure may be mechanically connected. For example, the cooling structure may include an opening, and the cooling element may be screwed to the cooling structure. Alternatively, a clamp mechanism may be used.

[0075] Figure 5 A flow chart 500 of a method of forming a semiconductor device is shown.

[0076] The method may include arranging a plurality of semiconductor chip packages (in 510) and mounting the plurality of semiconductor chip packages on a cooling element, wherein each chip package includes an encapsulation body encapsulating a semiconductor chip, a plurality of contact structures for electrically contacting the semiconductor chip, and at least one cooling structure protruding from the encapsulation body, thereby thermally connecting the cooling element to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages, and electrically connecting at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages through the cooling element (in 520).

[0077] Power transistors, which are usually integrated in power applications as transistor outline packages, face a dilemma: on the one hand, cooling can be optimized if one surface is directly connected to the outside world, while on the other hand, a conductive connection may impair electromagnetic compatibility or safety insulation. However, in many cases it is possible to connect one of the potentials, such as the source of the low-side switch (which is usually a low potential anyway), to a heat sink or a different type of heat distribution.

[0078] The usual approach is to electrically insulate the exposed pads of the transistor from the heat sink. This degrades the thermal performance and thus forms a limit to the power density that can be achieved by the (power) transistor.

[0079] In so-called source-down transistor packages, the source contact of the transistor may be exposed at the bottom side / back side of the package.

[0080] Concepts of source-down packaging that already exist in chip technology can be implemented, for example, in the front end, which may require a lot of technical effort. Source-down concepts in the back end may be expensive or require special packaging.

[0081] In various embodiments, an easy-to-implement source-down chip package for a power transistor is provided, which has a nearly standard package outline. The chip package can support the highest electrical performance.

[0082] In various embodiments, a standard profile source-down power package is provided having a gate wire bond on the leadframe side and having a drain clamp.

[0083] In various embodiments, a carrier such as a lead frame may include a die pad (in this case a source pad) to contact the source contact of the transistor chip. A portion of the die pad (e.g., a corner) may be removed (e.g., punched out or etched away) to form a recess to gain space for the gate contact of the transistor chip.

[0084] The chip may be arranged source-down on the die pad, with the source contact electrically and physically contacting the source pad and the gate pad being arranged over the recess.

[0085] A clamp can then be placed on the back side of the chip. The clamp can electrically connect the drain contact (potential) of the chip to the external connector (lead) and can support the chip over most of the chip area, especially over the recess where the gate contact is arranged, in other words, it can support the freely hanging gate pad.

[0086] Electrical connection of, for example, a gate pad to an external connector may be achieved by wire bonding, performed, for example, on the source side of the chip as opposed to the side typically used in prior art transistor packaging. A wire may connect the bottom side of the gate lead to, for example, an external connector.

[0087] A clamp disposed over the drain side of the chip, particularly over a free hanging gate pad, may provide support that may be needed in order to apply a wire to the gate pad (eg, a wire bonding process).

[0088] After the subsequent encapsulation process, the package may resemble a standard transistor outline package, except for the recess that may be revealed by the shape of the interface between the carrier and the encapsulation material.

[0089] Standard power packages with exposed pads that may be suitable for the above modification to form a so-called source-down chip package may include, for example, TO220, TO247, leadless TO, TO263, TO252, TDSON, and QDPAK. In this context, "source down" is to be understood as "source toward the exposed pad" (rather than with respect to the board, or relative to gravity as in the figure). This may result in a configuration for SMD packages such as DDPAK and QDPAK, where the source pad of the "source-down" chip package is arranged so that the source pad faces away from the circuit board.

[0090] FIG. 6A to FIG. 6C A schematic perspective view of a chip package 600 and elements for forming the chip package 600 according to various embodiments is shown. Fig. 7A and Figure 7B 7 and 701 , respectively, visualize a process 700 and 701 of forming a chip package 600 according to various embodiments.

[0091] Figures 5 to 7A The above concept is visualized as a TO220 package in an exemplary manner, and Figure 7B Visualize the above concept as a leadless TDSON package.

[0092] The chip package 600 may include a semiconductor chip 654, such as a transistor chip 654, such as a MOSFET or an IGBT chip. The semiconductor chip 654 may include a first connection pad 654P1 (e.g., a gate pad 654P1) and a second connection pad 654P2 (e.g., a source pad 654P2) on the front side. The semiconductor chip 654 may also include a third connection pad 654P3, such as a drain pad 654P3, on the back side opposite to the front side.

[0093] The chip package 600 may further include a carrier 660 , eg an electrically conductive carrier 660 , eg a leadframe 660 , eg a leadframe 660 including or consisting of copper or any other leadframe material used in the art.

[0094] The carrier 660 may differ from lead frames commonly used in the art in that a recess 660A may be defined by the carrier 660. For example, the carrier 660 may have a cutout in the recessed area 660A in which carrier material may be arranged in prior art carriers. The recess 660A may allow placement of the semiconductor chip 654 as described below.

[0095] The carrier 660 may further include a pad contact region 660P. The pad contact region 660P may be arranged such that it contacts a second connection pad 654P2, such as a source pad 654P2, for example by attaching the second connection pad 654P2 to the pad contact region 660P, such as via welding (e.g., soft soldering or diffusion soldering), gluing, sintering, or any other suitable technique used in the art.

[0096] In various embodiments, for example in a chip package 600 for a higher voltage level, the pad contact area 660P may have a predetermined shape, for example by arranging a groove around the pad contact area 660P in the carrier 660. The groove may be formed, for example, during a stamping process for forming the carrier 660. The groove may increase the insulation distance between the edge of the semiconductor chip 654, which may normally be at the drain potential, and the pad contact area 660P (and possibly the carrier 660 as a whole), which may be at the source potential. In other words, the groove at the source potential may be below the chip edge at the drain potential, so that the increased distance may be beneficial in high voltage applications.

[0097] However, this may require a dedicated design for each chip size.Where high versatility is preferred, such as for low voltage applications, the recess may be omitted and the pad contact area 660P may be defined substantially by the area actually contacted by the second connection pad 654P2.

[0098] The chip package 600 may further include an encapsulation material 656 encapsulating the semiconductor chip 654. The encapsulation material 656 may further at least partially include a carrier 660 and other elements of the chip package 600, for example as described below.

[0099] Multiple external connections 658 can be part of chip package 600, which can extend out of encapsulation material 656, or can be without encapsulation material 656, so as to be able to be electrically conductively contacted with first connection pad 654P1, second connection pad 654P2, and third connection pad 654P3. Multiple external connections 658 can, for example, include first external connection 658_1, second external connection 658_2, and third external connection 658_3. First external connection 658_1 can, for example, be connected to first connection pad 654P1, for example, a gate pad. Second external connection 658_2 can, for example, be connected to second connection pad 654P2, for example, a source pad. Third external connection 658_3 can, for example, be connected to third connection pad 654P3, for example, a drain pad.

[0100] The chip package 600 may further include a conductive clamp 650. The conductive chip may be configured to form a conductive connection between a third connection pad 654P3 (e.g., a drain pad) and a third external connection 658_3, which may, for example, protrude from the encapsulation body 656. The clamp 650 may be attached to the third connection pad 654P3, for example, by welding (e.g., soft soldering or diffusion soldering), gluing, sintering, etc. In various embodiments, the clamp 650 itself may form the third external connection 658_3. The clamp 650 may, for example, be bent to reach the top side of the chip package 600. Thus, after encapsulation, an exposed pad at the drain potential may be provided as the third external connection 658_3.

[0101] In various embodiments, the semiconductor chip 654 may be arranged with its front side facing the carrier 660 , with the first connection pad 654P1 being above the recess 660A, and with the second connection pad 654P2 contacting the pad contact region 660P. Fig. 6A 650 is shown in FIG. 6 (with the clamp 650 already in place), in the two top panels as a top view, in the middle and lower panels on the left as a bottom view, and in Fig. 7A and Figure 7B The top right panel shows a top view.

[0102] The clamp 650 can be arranged over the back side of the semiconductor chip 654 so that it covers the semiconductor chip 654. The clamp 650 can, for example, completely cover the semiconductor chip 654, or the clamp 650 can cover most of the semiconductor chip 654, for example at least 50%, for example at least 60%, for example at least 70%, for example at least 80%, for example at least 90%. In various embodiments, the clamp 650 can be larger than the semiconductor chip 654. In this case, the clamp 650 can extend over one or more edges, or all edges, of the semiconductor chip 654, for example. The portion of the semiconductor chip 654 that should be covered by the clamp 650 is the position where the semiconductor chip 654 extends over the recess 660A. With this arrangement, the clamp 650 can provide support for the semiconductor chip 654 during the attachment of the contact structure 652 (e.g., a wire, such as a lead) to the first connection pad 654P1. This is Fig. 6A , shown as a top view in the two top panels, as a bottom view in the middle and lower panels on the left, and as Fig. 7A and Figure 7B The middle left panel shows a top view.

[0103] The conductive contact structure 652 can conductively connect the first connection pad 654P1 to the first external connection 658_1. The conductive contact structure 652 can be, for example, wire bonded or soldered to the first connection pad 654P1, or by any other suitable technique used in the art, such as any technique commonly used to attach wires to connection pads, including those techniques that may require pressure on the connection pad 654P1, as the clamp 650 can provide sufficient support to avoid damaging the semiconductor chip 654 during the attachment process. This is Fig. 6A , shown as a bottom view in the middle and lower panels on the left, and in Fig. 7A and Figure 7B A bottom view (uponto the inverted partially completed chip package 600) is shown in the lower right panel.

[0104] Subsequently, encapsulation material 656 may be disposed, for example, during a molding process. Encapsulation material 656 may be disposed such that the resulting chip package 600 has an outline similar to or the same as a prior art transistor outline package (e.g., TO220, TO247, leadless TO, or QDPAK). Fig. 6A is shown in the bottom right panel and in Fig. 7A and Figure 7B is shown in the panel at the bottom left.

[0105] In various embodiments, for appropriate wire bonding, the conductive contact structure 652 (e.g., gate lead 652) may be plated on the pad, e.g., on the bottom side of the pad (which may correspond to the front side of the pad in a prior art chip package), using, e.g., nickel (Ni) or silver (Ag). Typical wire materials may include aluminum (Al), copper (Cu), gold (Au), and silver (Ag).

[0106] In various embodiments, the arrangement of the first external connection 658_1, the second external connection 658_2, and the third external connection 658_3 may be any suitable arrangement, such as three pins similar to a prior art package (e.g., a TO220 package), with the gate / drain / source order being the same as in a prior art package (e.g., GDS), and only the exposed pads exposed to the bottom side of the package have been changed to source potential. Other configurations (e.g., GSD for the pins) may be used in various embodiments, as long as, for example, Fig. 7A The exposed pads of the visible bottom side portion of the carrier 660 shown in the bottom left panel are at source potential.

[0107] In various embodiments, the placement of the semiconductor chip 654 and the fixture 650 may not be performed separately, such as Fig. 7A and Figure 7B , but rather is performed in a common process. To this end, the semiconductor chip 654 may first be attached (e.g. soldered) to the fixture 650, or even a plurality of semiconductor chips 654 may first be attached to a plurality of fixtures 650. In various embodiments, a plurality of fixtures 650 may be connected, in other words, a plurality of fixtures 650 may form an integral fixture frame 670. The fixture 650 with the chip 654 (or, respectively, a fixture frame 670 with a plurality of chips 654) may then be arranged on a carrier 660, e.g. a lead frame, so that each of the semiconductor chips 654 and each of the fixtures 650 are arranged as described above, e.g. wherein the second connection pad 654P2 contacts the pad contact area 660P, e.g. is soldered to the pad contact area 660P, and wherein a portion of the fixture 650 and the first connection pad 654P1 are arranged above the recess 660A. This is in Figure 6C As shown in the above. Fig. 6A , Fig. 7A and Figure 7B The subsequent processing is performed as described in the context of .

[0108] In various embodiments, additional connection pads on the semiconductor chip 654 may be connected to additional external connections, for example by wire bonding. Additional connection pads may be arranged above the recess 660A. For example, additional sensing pads and connections to a temperature sensor may be implemented.

[0109] Fig.13 A chip package (eg, as described above in FIG. 6A to FIG. 7B Flowchart 1300 of a method of chip packaging 600) described in the context of.

[0110] The process may include arranging a semiconductor chip comprising a first connecting pad and a second connecting pad on a front side, the front side of the semiconductor chip facing a carrier comprising a pad contact area and a recess, wherein the first connecting pad is arranged above the recess and the second connecting pad is arranged to contact the pad contact area (in 1310).

[0111] The process may also include placing a clamp over the back side of the semiconductor chip to cover the semiconductor chip, where the clamp extends over the recess (in 1320 ).

[0112] The process may also include conductively connecting the first connection pad to a first external connection that is free of encapsulation material or extends beyond the encapsulation material (at 1330).

[0113] exist Figure 1 In the context of , a commonly used circuit for drive applications (eg for electric forklift vehicles) is described and the requirement to dissipate the heat generated in the power MOSFETs of the circuit as effectively as possible and the disadvantages of this solution are discussed.

[0114] In various embodiments, power density for high power drive three-phase inverters may be provided.

[0115] In various embodiments, a "standard" drain-down chip package and a source-down chip package, such as those described above, may be combined to build a half-bridge system. For example, a drain-down transistor outline package (e.g., a TO 220 package) and a source-down transistor outline package (e.g., a TO220 source-down package, such as described above) may be combined to build a half-bridge system. Fig. 7A ) described in the context of can be combined to build a half-bridge system.

[0116] Fig. 8A and Figure 8B Each of them shows a schematic diagram of a semiconductor device 800 (eg a half-bridge system) according to various embodiments, and Fig. 9 A schematic diagram of a three-phase system 900 according to various embodiments is shown. The three-phase system 900 may include three semiconductor devices 800 .

[0117] In various embodiments, the semiconductor device 800 may include a first cooling element 884. The cooling element 884 may include or consist of a high thermal conductivity material, such as a metal, such as a metal commonly used in the art to form the cooling element 884.

[0118] The cooling element 884 may include a contact portion 884C and a portion 884F with an increased surface area, wherein the contact portion 884C may be configured to be contacted by at least one pair of chip packages 880 / 882 and the portion 884F is used to improve heat transfer to the ambient medium. The portion 884F with an increased surface area may, for example, be formed with / formed as a fin, such as Fig. 8A , Figure 8B and Fig. 9 shown.

[0119] The semiconductor device 800 may further include at least one first chip package 880, which may also be referred to as a source-down chip package 880. The source-down chip package 880 may be, for example, the semiconductor chip package 600, as described above. Figures 6A to 7B as described in the context of.

[0120] The source-down chip package 880 may include a first transistor chip (eg, a MOSFET chip), an encapsulation body 880E encapsulating the first transistor chip, and a first cooling structure 880C exposed on a first side of the first chip package 880. The first cooling structure 880C may be conductively connected to a source contact of the first transistor chip.

[0121] Semiconductor device 800 may further include at least one second chip package 882, which may also be referred to as a drain-down chip package 882. Drain-down chip package 882 may be, for example, a standard transistor outline package, such as a standard power package with exposed pads, such as TO220, TO247, leadless TO, or QDPAK.

[0122] The drain-down chip package 882 may include a second transistor chip, an encapsulation body 882E encapsulating the second transistor chip, and a second cooling structure 882C exposed on a first side of the second chip package 882. The second cooling structure 882C may be conductively connected to a drain contact of the second transistor chip.

[0123] In various embodiments, at least one of the at least one first chip package 880 may be mounted on the cooling element 884, and the first cooling structure 880C contacts the first cooling element 884 on a first side, for example a contact portion 884C of the first cooling element 884. Furthermore, at least one of the at least one second chip package 882 may be mounted on the cooling element 884, and the second cooling structure 882C contacts the first cooling element 884 on a second side opposite to the first side, for example a contact portion 884C of the first cooling element 884.

[0124] In various embodiments, the source contact of the source-down chip package 880 and the drain contact of the drain-down chip package 882 may be electrically conductively connected via a cooling element 884. Due to the direct connection of the chip packages 880, 882, respectively, to the cooling element (also referred to as a heat sink) 884, the thermal performance may be significantly improved, since the thermal (and / or electrical) isolation foil, which may be omitted in various embodiments, may generally not be a good thermal conductor (the thermal conductivity may be in the range of 2 W / mK).

[0125] The semiconductor device 800 may be configured as a half-bridge system. Fig. 8A and Figure 8B The exemplary embodiment shown in FIG. 8 can form such a half-bridge system, which can be constructed using a TO220 source-down chip package 880 and a TO220 drain-down chip package 882. In various embodiments, a carrier including an electronic circuit can be provided for forming a half-bridge system. A first cooling element 884 can be mounted on the carrier.

[0126] In various embodiments, two or more chip packages can be easily connected in parallel, for example, if more output power or current is required. Figure 8B 8 shows an exemplary embodiment of three parallel chip packages 880 having at least one first chip package 880 and three parallel chip packages 882 having at least one second chip package 882. The contact portion 884C of the first cooling element 884 may be larger to accommodate the three parallel first chip packages 880 on the first side and the three parallel second chip packages 882 on the second side. Each of the three parallel first chip packages 880 may be mounted on the first side in the same manner as described above, for example, and each of the three parallel second chip packages 882 may be mounted on the second side in the same manner as described above, for example.

[0127] In various embodiments, the semiconductor device 800 may be combined with two similar or identical semiconductor devices 800. Three semiconductor devices 800 together may form a three-phase system 900, such as an inverter 900. Fig. 9 As shown. The high side power line 990 and the low side power line 992 can be part of a circuit in various embodiments, which can be, for example, part of a carrier (not shown). In various embodiments, an expensive insulated metal substrate (IMS) printed circuit board (PCB) is not required because cooling through the motherboard is not required. Alternatively, a standard inexpensive FR4 PCB (without thermal vias) can be used.

[0128] In various embodiments, the phases may be connected by cables directly to one or both of the chip packages 880, 882, respectively. In various embodiments, the phases may be connected by cables to the cooling element 884, to which the chip packages 880, 882 may be electrically and thermally connected.

[0129] In various embodiments, the chip packages 880 , 882 may be electrically isolated from the cooling element 884 , and the low-side and high-side phase nodes of the half-bridge system may be connected by different connection mechanisms, such as by mechanical screws that may be used to connect the phases to the device to be driven.

[0130] In various embodiments, since only one package lead is required for the power current, the effective electrical package resistance of the chip package (eg, TO220 package) 880 may be significantly reduced.

[0131] Furthermore, in various embodiments, thermal performance may be improved by directly connecting the semiconductor packages 880 , 882 to the heat sink 884 .

[0132] In various embodiments, the physical dimensions of the three-phase system 900 (eg, inverter 900) may differ from the physical dimensions of current surface mount device (SMD) based system solutions. While current systems extend primarily in the xy direction of a substantially planar surface, Figure 5 The solution in also uses the z dimension, which may result in reduced space requirements in the xy plane, resulting in a smaller PCB area required, which may reduce system cost (system cost may be proportional to PCB cost).

[0133] Fig. 10A shows a schematic top view of a half-bridge module 1000 according to various embodiments, and Fig. 10B A schematic top view of a half-bridge module 1001 according to various embodiments is shown. Fig.11A shows a schematic cross-sectional view of a transistor package 1014 having a source-down configuration for use in a half-bridge module 1000 , 1001 according to various embodiments, Fig. 11B A schematic cross-sectional view of a transistor package 1012 with a drain-down configuration for use in a half-bridge module 1000 , 1001 is shown according to various embodiments. Fig. 12A shows a schematic diagram of a three-phase system 1200 and elements forming the three-phase system according to various embodiments, and Fig. 12B A schematic diagram of another three-phase system 1200 according to various embodiments is shown. In order to avoid crowding, some structures that may be identified in several figures are not provided with reference numerals. If necessary, the structure can be found in the figure with the corresponding number.

[0134] In various embodiments, the half-bridge module 1000, 1001 may include a carrier 1010 ( Fig. 10A , Fig. 10B and Fig. 12A 1000, 1001), a first source pad 1010S, and a first drain pad 1010D are shown from the top side. The first source pad 1010S and the first drain pad 1010D can be connected by a central part 1010C of the carrier 1010. The central part 1010C can be electrically insulating. The first source pad 1010S and the first drain pad 1010D can be conductive. They can, for example, include or consist of a metal, such as a surface metallization or a metal part included or attached, such as a metal block. The carrier 1010 can, for example, be a small PCB based on FR4 or IMS.

[0135] The half-bridge module 1000, 1001 may further include a first transistor package 1014, the first transistor package 1014 including a first source contact surface 1110S1 exposed at a bottom side of the first transistor package 1014 (see Fig.11A ) and a first drain contact surface 1116S1 exposed at a top side of the first transistor package 1014. The first transistor package 1014 may, for example, include a power MOSFET. Fig.11A The transistor package 1014 shown in the figure is intended to only schematically visualize some characteristics of the first transistor package included in the half-bridge module 1000, 1001, such as the first source contact surface 1110S1 being exposed at the bottom side of the transistor package 1014, the gate contact 1112 also being exposed at the bottom side of the transistor package 1014, and the first drain contact surface 1116S1 being exposed at the opposite top side of the transistor package 1014. The arrangement of the transistor chip 654, the conductive structures 1110, 1116, 1112 and the electrically insulating material 1114 may have any suitable configuration that provides the described characteristics.

[0136] In various embodiments, the first transistor package 1014 may be, for example, as described above in FIG. 6A to FIG. 7B The source-down transistor package 600 is described in the context of FIG. 1 for an embodiment having a fixture 660 exposed at the top of the chip package 600 (eg, a S308 source-down package with drain contacts exposed at the top). In various embodiments, the first transistor package 1014 may be provided by a chip embedding technique.

[0137] The first transistor package 1014 may be mounted to the top side of the carrier 1010, wherein the first source contact surface 1110S1 is in electrical and mechanical contact with the first source pad 1010S. The first transistor package 1014 may be, for example, soldered or glued to the first source pad 1010S with its first source contact surface 1110S1, or attached to the first source pad 1010S by other suitable techniques known in the art.

[0138] The half-bridge module 1000, 1001 may further include a second transistor package 1012, the second transistor package 1012 including a second source contact surface 1110S2 exposed at a top side of the second transistor package 1012 (see Fig. 11B ) and a second drain contact surface 1116S2 exposed at a bottom side of the second transistor package 1012. The second transistor package 1012 may, for example, include a power MOSFET. Fig. 11B The transistor package 1012 shown in the figure is intended to only schematically visualize some characteristics of the second transistor package included in the half-bridge module 1000, 1001, such as the second drain contact surface 1116S2 being exposed at the bottom side of the transistor package 1012, the gate contact 1112 also being exposed at the bottom side of the transistor package 1012, and the second source contact surface 1110S2 being exposed at the opposite top side of the transistor package 1012. The arrangement of the transistor chip 654, the conductive structures 1110, 1116, 1112 and the electrically insulating material 1114 may have any suitable configuration that provides the described characteristics.

[0139] In various embodiments, the second transistor package 1012 may be, for example, a drain-down transistor package with source and drain contact surfaces 1110S2, 1116S2 exposed at opposite main surfaces, such as a PQFN or S308 package with source electrodes exposed at the top. In various embodiments, the second transistor package 1012 may be provided by chip embedding technology.

[0140] The second transistor package 1012 may be mounted to the top side of the carrier 1010, wherein the second drain contact surface 1116S2 is in electrical and mechanical contact with the first drain pad 1010D. The second transistor package 1012 may be, for example, welded or glued to the first drain pad 1010D with its second drain contact surface 1116S2, or attached to the first drain pad 1010D by other suitable techniques known in the art.

[0141] In various embodiments, a portion of the first source pad 1010S may be exposed at the top side at a first end of the carrier 1010, and a portion of the first drain pad 1010D may be exposed at the top side at a second end of the carrier 1010. The second end of the carrier 1010 may be opposite to the first end. They may be at opposite ends of the carrier 1010, for example, along the long axis of the carrier 1010.

[0142] For ease of describing an embodiment of the arrangement of the half-bridge modules 1000, 1001 relative to each other, Fig. 10A , Fig. 10B , Fig. 12A and Fig. 12B 1010. The X and Y directions are indicated in FIG. The Y direction may coincide with a line connecting the first transistor package 1014 and the second transistor package 1012. The X direction may be orthogonal to the Y direction in the plane of the carrier 1010.

[0143] The half-bridge module 1000, 1001 may further include at least one fixing structure 1016, 1018, 1022, 1024 at the first source pad 1010S (fixing structure 1016 or 1024) and / or at the first drain pad 1010D (fixing structure 1018 or 1022). The at least one fixing structure 1016, 1018, 1022, 1024 may be configured to provide or implement mechanical fixing and conductive coupling between the first source pad 1010S and another first source pad 1010S of another adjacent half-bridge module 1000, 1001, and / or to provide or implement mechanical fixing and conductive coupling between the first drain pad 1010D and another first drain pad 1010D of another adjacent half-bridge module 1000, 1001.

[0144] In various embodiments, at least one fixing structure 1016, 1018, 1022, 1024 may be at least one screw hole 1016, 1018 formed in the first source pad (screw hole 1016) and / or in the first drain pad (screw hole 1018). Fig. 10A and Fig. 12A Shown in.

[0145] In various embodiments, at least one fixing structure 1016, 1018, 1022, 1024 may be at least one locking element 1022 and / or at least one locking element 1024, the locking element 1022 being attached to the first source pad 1010S or formed in the first source pad 1010S and configured to be coupled to a corresponding another locking element 1022 of another half-bridge module 1001, and the locking element 1024 being attached to the first drain pad 1010D and configured to be coupled to a corresponding another locking element 1024 of another half-bridge module 1001. Fig. 10B and Fig. 12B Even though the locking elements 1022 and 1024 are only shown to extend from the first source pad 1010S and from the first drain pad 1010D in the direction along the long axis of the carrier 1010, they may alternatively or additionally be arranged to extend from the edge connecting the first drain pad 1010D with the first source pad 1010S, for example to protrude in the direction of the short axis of the carrier 1010. The locking element 1024 may allow coupling of adjacent first source pads 1010S.

[0146] The locking elements 1022, 1024 may, for example, have a comb-like structure, or a jigsaw-type structure, or any other suitable structure that may allow a stable mechanical connection to be established between adjacent half-bridge modules 1001 and provide a conductive connection between adjacent first source pads 1010S (locking elements 1024) and / or between adjacent drain pads 1010D (locking elements 1022).

[0147] Even if according to Fig. 10B and Fig. 12B The locking elements 1022 and 1024 of the various embodiments shown in FIG. 1 have the same structure, but in various embodiments the locking element 1022 may be different from the locking element 1024, for example, so that they are incompatible. Thus, the accidental coupling of the first source pad 1010S of the half-bridge module 1001 to the first drain pad 1010D of the other half-bridge module 1001 can be prevented.

[0148] In other words, two (e.g., identical or substantially identical) half-bridge modules 1000 or two (e.g., identical or substantially identical) half-bridge modules 1001 may be placed adjacent to each other with their top sides facing the same direction. Examples of such arrangements are shown in Fig. 12A and Fig. 12B Shown in.

[0149] In various embodiments, two (or more) half-bridge modules 1000 or two (or more) half-bridge modules 1001 may be placed adjacent to each other in the X direction. In this case, the half-bridge modules 1000 or the half-bridge modules 1001 may be arranged to have the same orientation. Fig. 12A In the case of a half-bridge module 1000 and in Fig. 12B An example is shown in FIG. 1 for a half-bridge module 1001 .

[0150] In this case, the corresponding first source pads 1010S may be adjacent to each other, thereby forming a region or line of the first source pads 1010S. The corresponding first drain pads 1010D may be adjacent to each other, thereby forming a region or line of the first drain pads 1010D. And the central portion 1010C may be adjacent to each other, thereby forming a region or line of the central portion 1010C. The half-bridge modules 1000, 1001 may be arranged to be in direct contact with each other, or (at least for the half-bridge module 1000) with a (e.g., small) gap therebetween. The adjacent arrangement in the X direction may allow a plurality of half-bridge modules 1000 or 1001 to be connected in parallel, respectively, in other words, for the same phase, allowing the available voltage or current for high power applications to be increased.

[0151] In various embodiments, three or more half-bridge modules 1000 or three or more half-bridge modules 1001 may be arranged adjacent to each other in the Y direction.

[0152] In this case, the half-bridge modules 1000 or 1001 may be arranged so that their long axes are aligned and the first source pads 1010S of two adjacent half-bridge modules 1000 or 1001 are arranged adjacent to each other. In this case, the corresponding first source pads 1010S may form a region of first source pads 1010S (and optionally, form a line together with another half-bridge module 1000 or 1001 arranged adjacently in the X direction).

[0153] In addition, the half-bridge modules 1000 or 1001 can be arranged so that their long axes are aligned and the first drain pads 1010D of two adjacent half-bridge modules 1000 or 1001 are arranged adjacent to each other. In this case, the corresponding first drain pads 1010D can form a region of the first drain pads 1010D (and optionally, form a line with another half-bridge module 1000 or 1001 arranged adjacently in the X direction).

[0154] This configuration may allow for easy provision of the three phases of a three-phase system 1200, 1201. More phases may be added by adding further half-bridge modules 1000 or 1001, respectively, in the Y direction.

[0155] Adding more half-bridge modules 1000 or 1001, respectively, in the X direction may allow providing a three (or more) phase system with increased power. Fig. 12A An exemplary configuration of a three-phase system 1200 (eg, an inverter) based on a half-bridge module 1000 is shown. The half-bridge modules 1000 are arranged in a matrix configuration. Fig. 12BAn exemplary configuration of a three-phase system 1201 (eg, inverter) based on half-bridge modules 1001. The half-bridge modules 1001 are arranged in a matrix-like configuration. Due to their modular combination, the half-bridge modules 1000 and 1001 may also be referred to as "power bricks".

[0156] In various embodiments, the first drain contact surface 1116S1 exposed at the top side of the first transistor package 1014 and the second source contact surface 1110S2 exposed at the top side of the second transistor package 1012 may be arranged at the same distance from the top side surface of the carrier 1010. This may allow the first drain contact surface 1116S1 and the second source contact surface 1110S2 to be easily connected by the common conductor element 1020, for example by a common conductor element 1020 having a simple structure (e.g., a flat metal element).

[0157] In various embodiments, the common conductor element 1020 may be arranged to extend in the X direction (e.g., in the direction of the short axis of the carrier 1010) over the edge of the carrier 1010. For example, the length of the common conductor element 1020 may approximately correspond to a multiple (e.g., n times) of the width of the carrier 1010 along its short axis (e.g., in the X direction). This may allow coupling a plurality (e.g., n) of half-bridge modules 1000, e.g., coupling their respective first drain contact surfaces 1116S1 and their respective second source contact surfaces 1110S2 to each other using the common conductor element 1020. For example, a bus bar may be used as the common conductor element 1020, or any other conductive element suitable for high-power applications and having sufficient mechanical stability for connecting the half-bridge modules 1000 may be used as the common conductor element 1020.

[0158] In various embodiments, the common conductor element 1020 may be directly fixed to the first drain contact surface 1116S1 and the second source contact surface 1110S2, for example by welding, gluing or any other suitable technique for forming conductive contacts that fix the common conductor element 1020 to the first drain contact surface 1116S1 and the second source contact surface 1110S2.

[0159] In various embodiments, the carrier 1010 may further include insulating through holes 1021 for fixing the common conductor element 1020 to the half-bridge module 1000, 1001. By fixing the common conductor element 1020 (which may be provided with corresponding through holes) to the carrier 1010, the common conductor element 1020 may be in conductive contact with the first drain contact surface 1116S1 and the second source contact surface 1110S2. Fig. 12A Shown in.

[0160] In various embodiments, the half-bridge modules 1000, 1001 may achieve pure vertical current flow and therefore no current redistribution is required within the packages 1000, 1001. This may significantly reduce package resistance, for example, to the single-digit μΩ range.

[0161] In addition, the common conductor element 1020 that can form the top-side phase bus can improve the th and Z th In other words, since the power MOSFET is cooled from the top side as well as from the bottom side, the thermal performance is improved.

[0162] In various embodiments, the common conductor element 1020 may have two functions: on the one hand, for distributing the current, and on the other hand, for acting as a top-side heat sink.

[0163] In various embodiments, the power density of the half-bridge modules 1000, 1001 (and, therefore, also the three-phase systems 1200, 1201) may also be significantly increased due to lower power loss generation (due to lower package resistance) and better cooling (due to double-sided cooling).

[0164] In various embodiments, in the three-phase system 1200, for example, Fig. 12A As shown, a plurality of half-bridge modules (here: 12) 1000 may be combined. Three common conductor elements 1020 may be provided, each common conductor element 1020 being used for each of the three phases. A first of the common conductor elements 1020 may be arranged to couple a first drain contact surface 1116S1 and a second source contact surface 1110S2 of a first subset (in this case four) of the plurality of half-bridge modules 1000 to provide a first phase. A second of the common conductor elements 1020 may be arranged to couple a first drain contact surface 1116S1 and a second source contact surface 1110S2 of a second subset (in this case four) of the plurality of half-bridge modules 1000 to provide a second phase. A third of the common conductor elements 1020 may be arranged to couple a first drain contact surface 1116S1 and a second source contact surface 1110S2 of a third subset (in this case four) of the plurality of half-bridge modules 1000 to provide a third phase.

[0165] Additional contact bars 1220 may be provided to couple the first drain pads 1010D of adjacent half-bridge modules 1000 to each other (in the X direction and / or in the Y direction). Additional contact bars 1222 may be provided to couple the first source pads 1010S of adjacent half-bridge modules 1000 to each other (in the X direction and / or in the Y direction). The additional contact bars 1220, 1222 may further be used to provide power to the three-phase system 1200.

[0166] exist Fig. 12B In the embodiment of FIG. 1 , different ways of combining half-bridge modules 1001 to form a three-phase system 1201 are shown.

[0167] The width of the common conductor element 1020, which may be part of or attached to each half-bridge module 1001, may approximately correspond to the width of the carrier 1010 along its minor axis (e.g., in the X direction). In other words, the common conductor element 1020 (which may otherwise be the same as described above in Fig. 12A The common conductor element 1020 described in the context of FIG. 1002 and FIG. 1003 ) may not extend to the edge of the carrier 1010. At least one conductor locking element 1026 may be attached to the common conductor element 1020 or formed as a part of the common conductor element 1020. At least one conductor locking element 1026 may be configured to be coupled to a corresponding another conductor locking element 1026 of another adjacent half-bridge module 1001 (or more precisely, a common conductor element 1020). In various embodiments, at least two conductor locking elements 1026 may be provided, which extend over two edges of the carrier 1010 connecting the first end and the second end of the carrier 1010. Fig. 10B and Fig. 12B In the exemplary embodiment shown, four conductor locking elements 1026 are provided per common conductor element 1020 .

[0168] In various embodiments, at least one conductor locking element 1026 may extend over at least one edge of the carrier 1010 connecting the first end and the second end, for example using Fig. 10B and Fig. 12B The comb structure shown, or for example by a jigsaw type structure attached to or formed in the common conductor element 1020, or by any other type of locking element 1026, can be suitable for mechanically coupling adjacent common conductor elements 1020 to each other and for providing a conductive connection between adjacent common conductor elements 1020.

[0169] In various embodiments, the half-bridge modules 1001 can be combined to form a three-phase system 1201, the functionality of which (e.g., with respect to the number of phases and / or power that can be provided) can be similar to the functionality described above in the context of the three-phase system 1200. For example, a number of half-bridge modules 1001 arranged and coupled in the Y direction can define the number of phases that can be provided. The number of half-bridge modules 1001 arranged (and coupled) in parallel in the X direction can define the maximum current / voltage that can be provided by the three-phase system 1201 (or more generally, in the case of more than three phases, a multi-phase system).

[0170] Similar to the three-phase system 1200, further contact strips 1220, 1222 may be provided to supply power to the three-phase system 1201. The further contact strips 1220, 1222 may be attached using locking elements 1024 and 1026, respectively. Corresponding locking elements may be provided on the contact strips 1220, 1222.

[0171] In various embodiments, the three-phase system 1200, 1201 may allow for easy maintenance in the event of a failure of one of the half-bridge modules 1000 or 1001, respectively. In particular, in the case where the half-bridge module 1000 is attached to the common conductor element 1220 and the contact strips 1220, 1222 by screws 1224, or in the case where the half-bridge module 1001 is attached to the common conductor element 1220 and the contact strips 1220, 1222 by locking elements 1226, the individual half-bridge modules 1000 or 1001, respectively, may be easily removed and replaced.

[0172] Various examples are described below:

[0173] Example 1 is a semiconductor device. The semiconductor device may include: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier; wherein each of the chip packages includes an encapsulation body encapsulating a semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip to the electronic circuit, and at least one cooling structure protruding from the encapsulation body; and a cooling element thermally connected to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages.

[0174] In Example 2, the subject matter of Example 1 may further optionally include that each of the plurality of semiconductor chip packages is a surface mount device surface mounted to a carrier.

[0175] In Example 3, the subject matter of Example 1 or 2 may further include that the carrier is a printed circuit board.

[0176] In Example 4, the subject matter of any of the preceding examples may further include: the cooling element being electrically conductive.

[0177] In Example 5, the subject matter of any of the preceding examples may further include: each cooling structure is electrically coupled to the semiconductor chip and the electronic circuit to form another contact structure.

[0178] In Example 6, the subject matter of any of the preceding examples may further include: a plurality of cooling structures being electrically coupled to each other via the cooling element.

[0179] In Example 7, the subject matter of any of the preceding examples may further include that each of the plurality of contact structures includes at least one controlling contact structure and at least one controlled contact structure.

[0180] In Example 8, the subject matter of Example 7 can further include the cooling structure being another controlled contact structure.

[0181] In Example 9, the subject matter of any of the preceding examples may further include: at least one of the plurality of semiconductor chip packages is a power semiconductor device.

[0182] In Example 10, the subject matter of any of the preceding examples may further include that at least one of the plurality of semiconductor chip packages is a MOSFET, an IGBT, or a diode.

[0183] In Example 11, the subject matter of any of the preceding examples may further include: the first group of the plurality of semiconductor chip packages being arranged in a first row.

[0184] In Example 12, the subject matter of Example 11 may further include: all semiconductor chip packages of the first group are arranged to have the same first orientation.

[0185] In Example 13, the subject matter of Example 11 or 12 may further include that the cooling element includes a first cooling element portion thermally coupled to the cooling structure of the first group of semiconductor chip packages.

[0186] In Example 14, the subject matter of any one of Examples 11 to 13 may further include: a second group of the plurality of semiconductor chip packages being arranged in a second row.

[0187] In Example 15, the subject matter of Example 14 may further include: all semiconductor chip packages of the second group are arranged to have the same second orientation, the second orientation being different from the first orientation.

[0188] In Example 16, the subject matter of Example 14 or 15 may further include that the cooling element includes a second cooling element portion thermally coupled to the cooling structure of the second group of semiconductor chip packages.

[0189] In Example 17, the subject matter of Example 16 may further include: the first cooling element portion and the second cooling element portion being integrally formed.

[0190] In Example 18, the subject matter of any of the preceding examples may further include: the cooling element comprising aluminum, copper, an aluminum alloy, and / or a copper alloy.

[0191] In Example 19, the subject matter of any of the preceding examples may further include: the cooling element comprising a conductive coil.

[0192] In Example 20, the subject matter of any of the preceding examples may further include at least one of the encapsulations comprising a molding material or a laminate.

[0193] In Example 21, the subject matter of any of the preceding examples may further include: the cooling element being in direct contact with at least one of the enclosures.

[0194] In Example 22, the subject matter of any of the preceding examples may further include soldering the cooling element to at least one cooling structure of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages.

[0195] In Example 23, the subject matter of any of the preceding examples may further include that the cooling structure includes an opening for screwing the cooling element to the cooling structure.

[0196] In Example 24, the subject matter of any of the preceding examples may further include: the cooling element being screw-connected to the at least one cooling structure of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages.

[0197] In Example 25, the subject matter of any of the preceding examples may further include: the electronic circuit and the plurality of semiconductor chip packages being connected to include parallel half bridges.

[0198] In Example 26, the subject matter of any of the preceding examples may further include: the electronic circuit and the plurality of semiconductor chip packages being connected to include a full bridge.

[0199] Example 27 is a three-phase system comprising or consisting of the semiconductor device of any one of the preceding examples.

[0200] Example 28 is a semiconductor device. The semiconductor device may include: a cooling element, a plurality of semiconductor chip packages mounted on the cooling element, wherein each of the chip packages includes an encapsulation body encapsulating the semiconductor chip, a plurality of contact structures for electrically contacting the semiconductor chip, and at least one cooling structure protruding from the encapsulation body, wherein the cooling element is thermally connected to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages, and wherein at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages is electrically connected via the cooling element.

[0201] In Example 29, the subject matter of Example 28 may further include that each of the plurality of semiconductor chip packages is a surface mount device configured to be surface mounted to a carrier.

[0202] In Example 30, the subject matter of Example 28 or 29 may further include that each of the plurality of contact structures includes at least one controlling contact structure and at least one controlled contact structure.

[0203] In Example 31, the subject matter of any one of Examples 28 to 30 may further include the cooling structure being another controlled contact structure.

[0204] In Example 32, the subject matter of any one of Examples 28 to 31 may further include: at least one of the plurality of semiconductor chip packages is a power semiconductor device.

[0205] In Example 33, the subject matter of any one of Examples 28 to 32 may further include: at least one of the plurality of semiconductor chip packages is a MOSFET, an IGBT, or a diode.

[0206] In Example 34, the subject matter of any one of Examples 28 to 33 may further include: the first group of the plurality of semiconductor chip packages being arranged in a first row.

[0207] In Example 35, the subject matter of Example 34 may further include: all semiconductor chip packages of the first group are arranged to have the same first orientation.

[0208] In Example 36, the subject matter of Example 34 or 35 may further include the cooling element comprising a first cooling element portion thermally coupled to the cooling structure of the first group of semiconductor chip packages.

[0209] In Example 37, the subject matter of any one of Examples 34 to 36 may further include: a second group of the plurality of semiconductor chip packages being arranged in a second row.

[0210] In Example 38, the subject matter of Example 37 may further include: all semiconductor chip packages of the second group are arranged to have the same second orientation, the second orientation being different from the first orientation.

[0211] In Example 39, the subject matter of any one of Examples 34 to 37 may further include that the cooling element includes a second cooling element portion thermally coupled to the cooling structure of the second group of semiconductor chip packages.

[0212] In Example 40, the subject matter of Example 39 may further include: the first cooling element portion and the second cooling element portion being integrally formed.

[0213] In Example 41, the subject matter of any one of Examples 28 to 40 may further include that the cooling element includes aluminum, copper, an aluminum alloy, and / or a copper alloy.

[0214] In Example 42, the subject matter of any one of Examples 28 to 41 may further include that the cooling element includes a conductive coil.

[0215] In Example 43, the subject matter of any one of Examples 28 to 42 may further include: at least one of the encapsulations includes a molding material or a laminate.

[0216] In Example 44, the subject matter of any one of Examples 28 to 43 may further include the cooling element being in thermal contact with at least one of the enclosures.

[0217] In Example 45, the subject matter of any one of Examples 28 to 44 may further include the cooling element being welded or screwed to at least one cooling structure of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages.

[0218] In Example 46, the subject matter of any one of Examples 28 to 45 may further include that the cooling structure includes an opening for screwing the cooling element to the cooling structure.

[0219] Example 47 is a method of forming a semiconductor device. The method may include: mounting a plurality of semiconductor chip packages on a carrier, wherein the carrier includes an electronic circuit, and each of the chip packages includes an encapsulation body encapsulating a semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip to the electronic circuit, and at least one cooling structure protruding from the encapsulation body; and thermally connecting a cooling element to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages.

[0220] In Example 48, the subject matter of Example 47 may further include that the mounting of the plurality of semiconductor chip packages includes surface mounting the semiconductor chip packages to a carrier.

[0221] In Example 49, the subject matter of Example 47 or 48 may further include: the carrier is a printed circuit board.

[0222] In Example 50, the subject matter of any one of Examples 47 to 49 may further include: the cooling element being electrically conductive.

[0223] In Example 51, the subject matter of any one of Examples 47 to 50 may further include: each of the cooling structures is electrically coupled with the semiconductor chip and the electronic circuit to form another contact structure.

[0224] In Example 52, the subject matter of any one of Examples 47 to 51 may further include: the plurality of cooling structures being electrically coupled to each other via the cooling element.

[0225] In Example 53, the subject matter of any one of Examples 47 to 52 may further include that each of the plurality of contact structures includes at least one controlling contact structure and at least one controlled contact structure.

[0226] In Example 54, the subject matter of Example 53 can further include the cooling structure being another controlled contact structure.

[0227] In Example 55, the subject matter of any one of Examples 47 to 54 may further include: at least one of the plurality of semiconductor chip packages is a power semiconductor device.

[0228] In Example 56, the subject matter of any one of Examples 47 to 55 may further include: at least one of the plurality of semiconductor chip packages is a MOSFET, an IGBT, or a diode.

[0229] In Example 57, the subject matter of any one of Examples 47 to 56 may further include, prior to mounting, arranging a first group of the plurality of semiconductor chip packages in a first row.

[0230] In Example 58, the subject matter of Example 57 may further include that the arranging includes arranging all semiconductor chip packages of the first group to have the same first orientation.

[0231] In Example 59, the subject matter of Example 57 or 58 may further include the cooling element comprising a first cooling element portion thermally coupled to the cooling structure of the first group of semiconductor chip packages.

[0232] In Example 60, the subject matter of any one of Examples 57 to 59 may further include, prior to the mounting, arranging a second group of the plurality of semiconductor chip packages in a second row.

[0233] In Example 61, the subject matter of Example 60 may further include that the arranging includes arranging all semiconductor chip packages of the second group to have the same second orientation, the second orientation being different from the first orientation.

[0234] In Example 62, the subject matter of Example 60 or 61 may further include the cooling element comprising a second cooling element portion thermally coupled to the cooling structure of the second group of semiconductor chip packages.

[0235] In Example 63, the subject matter of Example 62 may further include: the first cooling element portion and the second cooling element portion are integrally formed.

[0236] In Example 64, the subject matter of any one of Examples 47 to 63 may further include that the cooling element includes aluminum, copper, an aluminum alloy, and / or a copper alloy.

[0237] In Example 65, the subject matter of any one of Examples 47 to 64 may further include: the cooling element includes a conductive coil.

[0238] In Example 66, the subject matter of any one of Examples 47 to 65 may further include: at least one of the encapsulations includes a molded material or a laminate.

[0239] In Example 67, the subject matter of any one of Examples 47 to 66 can further include placing at least one of the enclosures in direct contact with a cooling element.

[0240] In Example 68, the subject matter of any one of Examples 47 to 67 may further include thermally conductively connecting the cooling element comprises soldering the cooling element to at least one cooling structure of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages.

[0241] In Example 69, the subject matter of any one of Examples 47 to 68 may further include that the cooling structure includes an opening for screwing the cooling element to the cooling structure.

[0242] In Example 70, the subject matter of any one of Examples 47 to 69 may further include thermally conductively connecting the cooling element comprises screwing the cooling element to at least one cooling structure of each of at least two semiconductor chip packages of the plurality of semiconductor chip packages.

[0243] In Example 71, the subject matter of any one of Examples 47 to 70 may further include: the electronic circuit and the plurality of semiconductor chip packages are connected to include parallel half bridges.

[0244] In Example 72, the subject matter of any one of Examples 47 to 71 may further include: the electronic circuit and the plurality of semiconductor chip packages are connected to include a full bridge.

[0245] Example 73 is a method of forming a semiconductor device. The method may include: mounting a plurality of semiconductor chip packages on a cooling element, wherein each of the chip packages includes an encapsulation body encapsulating a semiconductor chip, a plurality of contact structures for electrically contacting the semiconductor chip, and at least one cooling structure protruding from the encapsulation body, so that the cooling element is thermally connected to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages, and at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages is electrically connected through the cooling element.

[0246] In Example 74, the subject matter of Example 73 may further include that each of the plurality of semiconductor chip packages is a surface mount device configured to be surface mounted to a carrier.

[0247] In Example 75, the subject matter of Example 73 or 74 may further include that each of the plurality of contact structures includes at least one controlling contact structure and at least one controlled contact structure.

[0248] In Example 76, the subject matter of any one of Examples 73 to 75 may further include the cooling structure being another controlled contact structure.

[0249] In Example 77, the subject matter of any one of Examples 73 to 76 may further include: at least one of the plurality of semiconductor chip packages is a power semiconductor device.

[0250] In Example 78, the subject matter of any one of Examples 73 to 77 may further include: at least one of the plurality of semiconductor chip packages is a MOSFET, an IGBT, or a diode.

[0251] In Example 79, the subject matter of any one of Examples 73 to 78 may further include, prior to mounting, arranging a first group of the plurality of semiconductor chip packages in a first row.

[0252] In Example 80, the subject matter of Example 79 may further include that the arranging includes arranging all semiconductor chip packages of the first group to have the same first orientation.

[0253] In Example 81, the subject matter of Example 79 or 80 may further include the cooling element comprising a first cooling element portion thermally coupled to the cooling structure of the first group of semiconductor chip packages.

[0254] In Example 82, the subject matter of any one of Examples 79 to 81 may further include, prior to mounting, arranging a second group of the plurality of semiconductor chip packages in a second row.

[0255] In Example 83, the subject matter of Example 82 may further include that the arranging includes arranging all semiconductor chip packages of the second group to have the same second orientation.

[0256] In Example 84, the subject matter of Example 82 or 83 may further include the cooling element comprising a second cooling element portion thermally coupled to the cooling structure of the second group of semiconductor chip packages.

[0257] In Example 85, the subject matter of Example 84 may further include: the first cooling element portion and the second cooling element portion being integrally formed.

[0258] In Example 86, the subject matter of any one of Examples 73 to 85 may further include that the cooling element includes aluminum, copper, an aluminum alloy, and / or a copper alloy.

[0259] In Example 87, the subject matter of any one of Examples 73 to 86 may further include: the cooling element comprising a conductive coil.

[0260] In Example 88, the subject matter of any one of Examples 73 to 87 may further include: at least one of the encapsulations includes a molded material or a laminate.

[0261] In Example 89, the subject matter of any one of Examples 73 to 88 may further include the cooling element being in thermal contact with at least one of the enclosures.

[0262] In Example 90, the subject matter of any one of Examples 73 to 89 may further include: mounting the plurality of semiconductor chip packages on the cooling element includes: welding or screwing the cooling element to at least one cooling structure of each of at least two semiconductor chip packages in the plurality of semiconductor chip packages.

[0263] In Example 91, the subject matter of any one of Examples 73 to 90 may further include that the cooling structure includes an opening for screwing the cooling element to the cooling structure.

[0264] Example 92 is a method of forming a semiconductor device. The method may include mounting the semiconductor device according to any one of Examples 27 to 46 to a carrier including an electronic circuit.

[0265] In Example 93, the subject matter of Example 92 may further include that the mounting includes surface mounting the plurality of semiconductor chip packages to a carrier.

[0266] Example 94 is a chip package. The chip package may include: a semiconductor chip including a first connection pad and a second connection pad on a front side; a carrier including a pad contact area and a recess; an encapsulation material encapsulating the semiconductor chip; a first external connection having no encapsulation material or extending out of the encapsulation material; a conductive clamp; and a contact structure, wherein the semiconductor chip is arranged so that its front side faces the carrier, the first connection pad is above the recess, and the second connection pad contacts the pad contact area, wherein the clamp is arranged on a back side of the semiconductor chip, the clamp covers the semiconductor chip, at the semiconductor chip, the clamp extends above the recess, and wherein the conductive contact structure conductively connects the first connection pad to the first external connection.

[0267] In Example 95, the subject matter of Example 94 may further include the second connection pad being conductively connected to a second external connection that is free of encapsulation material or that extends out of the encapsulation material.

[0268] In Example 96, the subject matter of Example 94 or 95 may further include: the semiconductor chip includes a transistor, and the second connection pad is a source pad of the transistor.

[0269] In Example 97, the subject matter of any one of Examples 94 to 96 may also include: a third connection pad on a back side of the semiconductor chip opposite to the front side, wherein the clamp conductively connects the third connection pad to a third external connection, and the third external connection is free of encapsulation material or extends out of the encapsulation material.

[0270] Example 98 is a semiconductor device. The semiconductor device may include: a first cooling element; at least one first chip package, including a first transistor chip, an encapsulation body encapsulating the first transistor chip, and a first cooling structure exposed on a first side of the first chip package, wherein the first cooling structure is conductively connected to a source contact of the first transistor chip; at least one second chip package, including a second transistor chip, an encapsulation body encapsulating the second transistor chip, and a second cooling structure exposed on a first side of the second chip package, wherein the second cooling structure is conductively connected to a drain contact of the second transistor chip, wherein at least one of the at least one first chip package is mounted on the cooling element, and the first cooling structure contacts the first cooling element on the first side, and wherein at least one of the at least one second chip package is mounted on the cooling element, wherein the second cooling structure contacts the first cooling element on a second side opposite to the first side.

[0271] In Example 99, the subject matter of Example 98 may further include the cooling element, the at least one first chip package mounted on the cooling element, and the at least one second chip package mounted on the cooling element forming a half bridge.

[0272] In Example 100 , the subject matter of Example 99 may further include a carrier including an electronic circuit that may form a portion of the half bridge, wherein the first cooling element is mounted on the carrier.

[0273] Example 101 is a three-phase system. The three-phase system may include three semiconductor devices according to Example 99, and a carrier including an electronic circuit, wherein the three semiconductor devices and the carrier may together be configured as a three-phase system.

[0274] In Example 102, the subject matter of Example 101 may further include: the three-phase system forms an inverter.

[0275] In Example 103 , the subject matter of any one of Examples 98 to 101 may further include that the at least one first chip package is a chip package according to any one of Examples 94 to 97 .

[0276] Example 104 is a half-bridge module. The half-bridge module may include: a carrier having a top side, a first source pad, and a first drain pad; a first transistor package including a first source contact surface exposed at a bottom side of the first transistor package and a first drain contact surface exposed at a top side of the first transistor package, wherein the first transistor package is mounted to the top side of the carrier and the first source contact surface electrically and mechanically contacts the first source pad; a second transistor package including a second source contact surface exposed at a top side of the second transistor package and a second drain contact surface exposed at a bottom side of the second transistor package, wherein the second transistor package is mounted to the top side of the carrier and the second drain contact surface electrically and mechanically contacts the first drain pad, wherein a portion of the first source pad is exposed at the top side at a first end of the carrier, and wherein a portion of the first drain pad is exposed at the top side at a second end of the carrier opposite to the first end.

[0277] In Example 105, the subject matter of Example 104 may further include: at least one fixing structure at the first source pad and / or at the first drain pad, wherein the at least one fixing structure is configured to provide or implement mechanical fixation and conductive coupling between the first source pad and another first source pad of another adjacent half-bridge module, and / or to provide or implement mechanical fixation and conductive coupling between the first drain pad and another first drain pad of another adjacent half-bridge module.

[0278] In Example 106, the subject matter of Example 105 may further include that the at least one fixing structure is at least one screw hole formed in the first source pad and / or the first drain pad.

[0279] In Example 107, the subject matter of Example 105 may further include that the at least one fixing structure is at least one locking element attached to the first source pad and / or the first drain pad and configured to be coupled to a corresponding another locking element of another half-bridge module.

[0280] In Example 108, the subject matter of any one of Examples 104 to 107 may further include that the first drain contact surface exposed at the top side of the first transistor package and the second source contact surface exposed at the top side of the second transistor package are arranged at the same distance from the top side surface of the carrier.

[0281] In Example 109, the subject matter of Example 108 may further include that the carrier includes an insulating through-hole for fixing a common conductor element to the half-bridge module, wherein the common conductor element is to be in conductive contact with the first drain contact surface and the second source contact surface.

[0282] In Example 110, the subject matter of Example 109 may further include a common conductor element.

[0283] In Example 111, the subject matter of Example 110 may further include at least one conductor locking element attached to the common conductor element and configured to couple to a corresponding another conductor locking element of another adjacent half-bridge module.

[0284] In Example 112, the subject matter of Example 111 can further include: at least one conductor locking element extending over at least one edge of the carrier connecting the first end and the second end.

[0285] In Example 113, the subject matter of Example 111 or 112 may further include that the at least one conductor locking element includes two conductor locking elements extending over two edges of the carrier connecting the first end and the second end.

[0286] In Example 114, the subject matter of any one of Examples 104 to 113 may further include: the first transistor package is a chip package according to any one of Examples 94 to 97.

[0287] Example 115 is a three-phase system comprising at least three half-bridge modules according to any one of Examples 104 to 113, wherein the at least three half-bridge modules are coupled to form a three-phase system.

[0288] Example 116 is a three-phase system comprising at least six half-bridge modules according to any one of Examples 104 to 113, wherein a first half-bridge module and a second half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a first phase of the three-phase system, wherein a third half-bridge module and a fourth half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a second phase of the three-phase system, and wherein a fifth half-bridge module and a sixth half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a third phase of the three-phase system, wherein a first drain contact surface and a second source contact surface of each of the first half-bridge module and the second half-bridge module are conductively coupled through a first common conductor element, wherein a first drain contact surface and a second source contact surface of each of the third half-bridge module and the fourth half-bridge module are conductively coupled through a second common conductor element, and wherein a first drain contact surface and a second source contact surface of each of the fifth half-bridge module and the sixth half-bridge module are conductively coupled through a third common conductor element.

[0289] In Example 117, the subject matter of Example 115 or 116 may further include another common conductor element conductively coupled to the first source pad of each of the first half-bridge module, the second half-bridge module, the third half-bridge module, and the fourth half-bridge module.

[0290] In Example 118, the subject matter of any one of Examples 115 to 117 may further include another common conductor element conductively coupled to the first drain pad of each of the third half-bridge module, the fourth half-bridge module, the fifth half-bridge module, and the sixth half-bridge module.

[0291] Example 119 is a method of forming a chip package. The method may include: arranging a semiconductor chip, the semiconductor chip including a first connection pad and a second connection pad on a front side, the front side of the semiconductor chip facing a carrier having a pad contact area and a recess, wherein the first connection pad is arranged above the recess and the second connection pad is arranged to contact the pad contact area; arranging a clamp over a back side of the semiconductor chip, the clamp covering the semiconductor chip, where the clamp extends over the recess; and conductively connecting the first connection pad to a first external connection, the first external connection having no encapsulation material or extending out of the encapsulation material.

[0292] Although the present invention has been particularly shown and described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention is indicated by the appended claims, and is therefore intended to include all changes within the meaning and scope of the equivalents of the claims.

Claims

1. A chip package, comprising: a semiconductor chip comprising a first connection pad and a second connection pad on a front side; a carrier including a pad contact area and a recess; An encapsulation material, which is used to encapsulate the semiconductor chip; a first external connection that is free of or extends beyond the encapsulating material; Conductive fixture; as well as Contact structure; wherein the semiconductor chip is arranged with its front side facing the carrier, wherein the first connection pad is above the recess, and the second connection pad contacts the pad contact area; wherein the clamp is arranged on the back side of the semiconductor chip, covering the semiconductor chip, and at the semiconductor chip, the clamp extends over the recess; and Therein, the contact structure conductively connects the first connection pad to the first external connection.

2. The chip package according to claim 1, in, The second connection pad is conductively connected to a second external connection that is free of or extends out of the encapsulation material.

3. The chip package according to claim 1 or 2, in, The semiconductor chip includes a transistor; and Wherein, the second connection pad is a source pad of the transistor.

4. The chip package according to claim 1 or 2, further comprising: a third connection pad on a back side of the semiconductor chip opposite to the front side; Wherein, the clamp conductively connects the third connection pad to a third external connection, the third external connection being free of the encapsulation material or extending out of the encapsulation material.

5. A semiconductor device comprising: a first cooling element; At least one first chip package, wherein the at least one first chip package is a chip package according to any one of claims 1 to 4, comprising: - a first transistor chip; - an encapsulation body encapsulating the first transistor chip; and - a first cooling structure exposed on a first side of the first chip package; - wherein the first cooling structure is conductively connected to a source contact of the first transistor chip; at least one second chip package, comprising: - a second transistor chip; - an encapsulation body encapsulating the second transistor chip; and - a second cooling structure exposed on the first side of the second chip package; - wherein the second cooling structure is conductively connected to the drain contact of the second transistor chip; wherein at least one of the at least one first chip package is mounted on the cooling element, and the first cooling structure contacts the first cooling element on a first side; and Wherein, at least one of the at least one second chip package is mounted on the cooling element, and the second cooling structure contacts the first cooling element on a second side opposite to the first side.

6. The semiconductor device according to claim 5, in, The cooling element, the at least one first chip package mounted on the cooling element, and the at least one second chip package mounted on the cooling element form a half bridge.

7. The semiconductor device according to claim 6, further comprising: a carrier comprising an electronic circuit forming part of said half-bridge, Wherein, the first cooling element is mounted on the carrier.

8. A three-phase system comprising: The three semiconductor devices according to claim 6; as well as A carrier including an electronic circuit; The three semiconductor devices and the carrier are together configured as the three-phase system.

9. The three-phase system according to claim 8, in, The three-phase system forms an inverter.

10. A half-bridge module, comprising: a carrier comprising a top side, a first source pad, and a first drain pad; a first transistor package, the first transistor package being a chip package according to any one of claims 1 to 4, comprising a first source contact surface exposed at a bottom side of the first transistor package and a first drain contact surface exposed at a top side of the first transistor package, wherein the first transistor package is mounted to the top side of the carrier, wherein the first source contact surface electrically and mechanically contacts the first source pad; a second transistor package comprising a second source contact surface exposed at a top side of the second transistor package and a second drain contact surface exposed at a bottom side of the second transistor package, wherein the second transistor package is mounted to the top side of the carrier, wherein the second drain contact surface electrically and mechanically contacts the first drain pad; wherein a portion of the first source pad is exposed at the top side at the first end of the carrier; and A portion of the first drain pad is exposed at the top side at a second end of the carrier opposite to the first end.

11. The half-bridge module according to claim 10, further comprising: at least one fixing structure at the first source pad and / or the first drain pad; Wherein, the at least one fixing structure is configured to provide or realize mechanical fixation and conductive coupling between the first source pad and another first source pad of the adjacent other half-bridge module, and / or to provide or realize mechanical fixation and conductive coupling between the first drain pad and another first drain pad of the adjacent other half-bridge module.

12. The half-bridge module according to claim 11, in, The at least one fixing structure is at least one screw hole formed in the first source pad and / or the first drain pad.

13. The half-bridge module according to claim 11, in, The at least one fixing structure is at least one locking element attached to the first source pad and / or the first drain pad and configured to be coupled to a corresponding another locking element of the other half-bridge module.

14. The half-bridge module according to any one of claims 10 to 13, in, The first drain contact surface exposed at the top side of the first transistor package and the second source contact surface exposed at the top side of the second transistor package are arranged at the same distance from a top side surface of the carrier.

15. The half-bridge module according to claim 14, in, The carrier comprises insulating through-holes for fixing a common conductor element to the half-bridge module, wherein the common conductor element is in conductive contact with the first drain contact surface and the second source contact surface.

16. The half-bridge module according to claim 15, further comprising: Common conductor element.

17. The half-bridge module according to claim 16, further comprising: At least one conductor locking element is attached to the common conductor element and is configured to be coupled to a corresponding another conductor locking element of another adjacent half-bridge module.

18. The half-bridge module according to claim 17, in, The at least one conductor locking element extends over at least one edge of the carrier connecting the first end and the second end.

19. The half-bridge module according to claim 17 or 18, in, The at least one conductor locking element comprises two conductor locking elements extending over two edges of the carrier connecting the first end and the second end.

20. A three-phase system comprising: At least three half-bridge modules, wherein the at least three half-bridge modules are half-bridge modules according to any one of claims 10 to 19; The at least three half-bridge modules are coupled to form the three-phase system.

21. The three-phase system according to claim 20, comprising: At least six half-bridge modules, wherein the at least six half-bridge modules are half-bridge modules according to any one of claims 10 to 19; wherein a first half-bridge module and a second half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a first phase of the three-phase system; wherein a third half-bridge module and a fourth half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a second phase of the three-phase system; and wherein a fifth half-bridge module and a sixth half-bridge module of the at least six half-bridge modules are coupled in parallel to provide a third phase of the three-phase system; wherein the first drain contact surface and the second source contact surface of each of the first half-bridge module and the second half-bridge module are conductively coupled via a first common conductor element; wherein the first drain contact surface and the second source contact surface of each of the third half-bridge module and the fourth half-bridge module are conductively coupled via a second common conductor element; and Wherein, the first drain contact surface and the second source contact surface of each of the fifth half-bridge module and the sixth half-bridge module are conductively coupled via a third common conductor element.

22. The three-phase system of claim 21, further comprising: Another common conductor element conductively coupled to the first source pad of each of the first half-bridge module, the second half-bridge module, the third half-bridge module, and the fourth half-bridge module.

23. The three-phase system according to claim 21 or 22, further comprising: A further common conductor element is conductively coupled to the first drain pad of each of the third half-bridge module, the fourth half-bridge module, the fifth half-bridge module, and the sixth half-bridge module.

24. A method of forming a chip package, the method comprising: Arranging a semiconductor chip, the semiconductor chip comprising a first connection pad and a second connection pad on a front side, the front side of the semiconductor chip facing a carrier comprising a pad contact area and a recess, wherein the first connection pad is arranged above the recess and the second connection pad is arranged to contact the pad contact area; Arranging a clamp over the back side of the semiconductor chip, the clamp covering the semiconductor chip, where the clamp extends over the recess; and The first connection pad is conductively connected to a first external connection, the first external connection being free of encapsulation material or extending beyond the encapsulation material.

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