Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device includes: a stacked structure including alternately stacked gate structures and first dielectric patterns; a vertical channel penetrating the stacked structure; and a charge storage layer extending from between the vertical channel and the first gate structure to between the vertical channel and the first dielectric pattern. The gate structure includes a first gate structure having a top surface and a bottom surface facing each other and having different widths. The charge storage layer includes a first section between the vertical channel and the first gate structure and a second section between the vertical channel and the first dielectric pattern. The thickness of the first section is greater than the thickness of the second section. One of the width of the top surface of each first gate structure and the width of the bottom surface of each first gate structure is the same as the width of the first dielectric pattern on the first gate structure.

Description

Technical Field

[0001] The inventive concept relates to semiconductor memory devices, and more particularly, to three-dimensional semiconductor memory devices. Background Art

[0002] Recently, semiconductor devices have been highly integrated to meet the demand for high performance and low cost devices. Since the integration of semiconductor devices is an important factor in determining product prices, highly integrated semiconductor devices are increasingly needed. The integration of typical two-dimensional or planar semiconductor devices is mainly determined by the area occupied by the unit memory cell, and is largely affected by the technical level used to form fine patterns. However, the extremely expensive processing equipment required to increase the fineness of the pattern may set practical limitations on improving the integration of two-dimensional or planar semiconductor devices. As a result, there is increasing interest in three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells. Summary of the invention

[0003] Embodiments of the inventive concept provide a three-dimensional semiconductor memory device having improved electrical characteristics.

[0004] An embodiment of the inventive concept provides a three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a stack structure including a plurality of gate structures and a plurality of first dielectric patterns alternately and repeatedly stacked on a substrate, the gate structure including a plurality of first gate structures, each of the first gate structures having a top surface and a bottom surface facing the top surface, and the width of the top surface is different from the width of the bottom surface; a vertical channel penetrating the stack structure on the substrate; and a charge storage layer extending from between the vertical channel and the first gate structure to between the vertical channel and the first dielectric pattern. The charge storage layer includes a first segment between the vertical channel and the first gate structure and a second segment between the vertical channel and the first dielectric pattern. The thickness of the first segment is greater than the thickness of the second segment. One of the width of the top surface and the width of the bottom surface of each first gate structure among the plurality of first gate structures is the same as the width of the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

[0005] Embodiments of the inventive concept also provide a three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a stacked structure including a plurality of gate structures and a plurality of first dielectric patterns alternately and repeatedly stacked on a substrate, the gate structure including a plurality of first gate structures, each of the first gate structures having a top surface and a bottom surface facing the top surface, and the width of the top surface is different from the width of the bottom surface; a vertical channel penetrating the stacked structure on the substrate; and a charge storage structure extending from between the vertical channel and the first gate structure to between the vertical channel and the first dielectric pattern, the charge storage structure including a first charge storage segment between the vertical channel and the first gate structure and a second charge storage segment between the vertical channel and the first dielectric pattern. The thickness of the first charge storage segment is greater than the thickness of the second charge storage segment. One of the width of the top surface and the width of the bottom surface of each first gate structure among the plurality of first gate structures is the same as the width of the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

[0006] Embodiments of the inventive concept also provide a three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a stacked structure, comprising a plurality of gate structures and dielectric patterns alternately and repeatedly stacked on a substrate, the gate structure comprising a plurality of first gate structures, each of the first gate structures having a top surface and a bottom surface facing the top surface, the width of the top surface being different from the width of the bottom surface, the dielectric pattern comprising a plurality of first dielectric patterns adjacent to the plurality of first gate structures; and a vertical channel structure penetrating the stacked structure, the vertical channel structure extending onto a first sidewall of the first gate structure and onto a first sidewall of the first dielectric pattern. The vertical channel structure has a protrusion protruding from the sidewall of the vertical channel structure. The first sidewall of each first gate structure comprises a first recessed region. The protrusion is in the first recessed region. One of the width of the top surface and the width of the bottom surface of each first gate structure among the plurality of first gate structures is the same as the width of the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

[0007] Embodiments of the inventive concept also provide a semiconductor memory device, the semiconductor memory device comprising: a stacked structure including a gate structure and a dielectric structure stacked alternately and repeatedly; a vertical channel penetrating the stacked structure; and a charge storage structure disposed between the vertical channel and the gate structure and between the vertical channel and the dielectric layer. The charge storage structure includes a protrusion extending at an interface between the gate structure and the dielectric structure into a recessed region disposed in a sidewall of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features of the inventive concept will become apparent from the following detailed description made with reference to the accompanying drawings.

[0009] Figure 1A simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is illustrated.

[0010] Figure 2 A plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is shown.

[0011] Figure 3 Shown along Figure 2 , which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0012] Figure 4 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0013] Figure 5 Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0014] Fig. 6A Show Figure 4 FIG. 1 is an enlarged view of a portion B in FIG. 1 , showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0015] Figure 6B Show Figure 4 FIG. 1 is an enlarged view of a portion B in FIG. 1 , showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0016] Figure 7 Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0017] Figure 8 Show Figure 4 FIG. 1 is an enlarged view of a portion B in FIG. 1 , showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0018] Fig. 9 Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0019] Fig.10 Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0020] Fig.11Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0021] Fig.12 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0022] Fig.13 Show Fig.12 An enlarged view of portion A' in FIG.

[0023] Fig.14 Shown along Figure 2 , which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0024] Fig.15 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0025] Fig.16 Shown along Figure 2 , which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0026] Fig.17 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0027] Fig.18 Show Fig.16 Magnified view of portion C in FIG.

[0028] Fig.19 A plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is shown.

[0029] Fig. 20 Shown along Fig.19 A cross-sectional view taken along line III-III' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0030] Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A and Fig.27A Shown along Figure 2, which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0031] Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B and Fig.27B Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0032] Fig. 22C Show Fig. 22B An enlarged view of portion D in FIG. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the inventive concept will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily realize the inventive concept.

[0034] Figure 1 A simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is illustrated.

[0035] Reference Figure 1 , a three-dimensional semiconductor memory device may include a common source line CSL, a plurality of bit lines BL0 to BL2 (ie, bit lines BL0 , BL1 , and BL2 ), and a plurality of cell strings CSTR between the common source line CSL and the bit lines BL0 to BL2 .

[0036] The bit lines BL0 to BL2 may be arranged two-dimensionally, and a plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 to BL2. The cell strings CSTR may thus be arranged two-dimensionally on a common source line CSL or on a substrate.

[0037] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to one of the bit lines BL0 to BL2, and a plurality of memory cell transistors MCT between the ground selection transistor GST and the string selection transistor SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series. In addition, the ground selection line GSL, a plurality of word lines WL0 to WL3 (i.e., WL0, WL1, WL2, and WL3), and a plurality of string selection lines SSL1 and SSL2 (wherein the lines GSL, WL0 to WL3, SSL1, and SSL2 are disposed between the common source line CSL and the bit lines BL0 to BL2) may be used as gates of the ground selection transistor GST, the memory cell transistors MCT, and the string selection transistors SST, respectively.

[0038] Figure 2 A plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is shown. Figure 3 Shown along Figure 2 , which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Figure 4 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Figure 5 Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig. 6A and Figure 6B Show Figure 4 FIG. 1 is an enlarged view of a portion B in FIG. 1 , showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Figure 7 Show Figure 3 FIG. 1 is an enlarged view of a portion A in FIG. 1 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present concept.

[0039] Reference Figure 2 , Figure 3 and Figure 4 , the substrate 100 may include a cell array region CAR and a pad region CR. The substrate 100 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The buffer dielectric layer 50 may be disposed on the top surface of the substrate 100 (or disposed above the top surface of the substrate 100). The buffer dielectric layer 50 may be placed on the cell array region CAR and the pad region CR of the substrate 100. The buffer dielectric layer 50 may include, for example, a thermal oxide layer or a silicon oxide layer.

[0040] The stacked structure ST may be disposed on the cell array region CAR and the pad region CR of the substrate 100. The stacked structure ST may extend along a first direction X on the substrate 100, and may be spaced apart in a second direction Y intersecting the first direction X. The common source region CSR may be disposed in the substrate 100 between the stacked structures ST. The common source region CSR may extend along the first direction X. The common source region CSR may have a conductivity type different from that of the substrate 100.

[0041] Each stacked structure ST may include a dielectric pattern 110 and gate electrodes 120a, 120b, and 120c alternately and repeatedly stacked on the buffer dielectric layer 50. The dielectric pattern 110 may be stacked on the substrate 100 in a third direction Z perpendicular to the top surface of the substrate 100. The dielectric pattern 110 may include, for example, a silicon oxide layer. Each of the gate electrodes 120a, 120b, and 120c may be disposed between the dielectric patterns 110. That is, for example, the gate electrode 120b is disposed between a pair of dielectric patterns 110. The gate electrodes 120a, 120b, and 120c may include a ground selection gate electrode 120a, a string selection gate electrode 120c, and a cell gate electrode 120b between the ground selection gate electrode 120a and the string selection gate electrode 120c. The ground selection gate electrode 120a may be the lowest gate electrode among the gate electrodes 120a, 120b, and 120c, and the string selection gate electrode 120c may be the highest gate electrode among the gate electrodes 120a, 120b, and 120c. Figure 1 The ground selection line GSL shown, the cell gate electrode 120b may be Figure 1 The string selection gate electrode 120c may be located at the word lines WL0 to WL3 shown in FIG. Figure 1 The string selection line SSL is depicted in FIG.

[0042] Each stacked structure ST may have a step structure on the pad region CR of the substrate 100. For example, the stacked structure ST may have a height that decreases as the distance from the cell array region CAR increases. For example, each of the gate electrodes 120a, 120b, and 120c may have a length that decreases as the distance from the substrate 100 increases in the first direction X. In some embodiments, each of the gate electrodes 120a, 120b, and 120c may have a distal end on the pad region CR of the substrate 100. The distal end of the ground selection gate electrode 120a and the distal end of the unit gate electrode 120b may be portions exposed by the immediately overlying unit gate electrode 120b and the immediately overlying string selection gate electrode 120c. The distal end of the string selection gate electrode 120c may be a portion of the string selection gate electrode 120c disposed on the pad region CR.

[0043] Each dielectric pattern 110 may have a length in the first direction X that decreases as the distance from the substrate 100 increases. The length of each dielectric pattern 110 in the first direction X may be substantially the same as the length of an immediately underlying gate electrode among the gate electrodes 120 a, 120 b, and 120 c in the first direction X. Therefore, ends of the gate electrodes 120 a, 120 b, and 120 c may be covered by the immediately overlying dielectric pattern 110 .

[0044] The interlayer dielectric pattern 200 may be formed in a stepped structure covering the stack structure ST and the buffer dielectric layer 50. The interlayer dielectric pattern 200 may expose a top surface of the stack structure ST. The interlayer dielectric pattern 200 may include, for example, a tetraethyl orthosilicate (TEOS) oxide layer.

[0045] The vertical channel structure VS may penetrate the corresponding stacked structure ST on the cell array region CAR of the substrate 100. The vertical channel structure VS may be arranged in a zigzag or straight line along the first direction X. The semiconductor column PI may be disposed between the substrate 100 and the vertical channel structure VS. The semiconductor column PI may be disposed on the top surface of the substrate 100 and may penetrate the ground selection gate electrode 120a. The semiconductor column PI may be electrically connected to the vertical channel structure VS. The semiconductor column PI may be an intrinsic semiconductor or a semiconductor having the same conductivity type as that of the substrate 100. For example, the semiconductor column PI may be a single crystal intrinsic semiconductor or a p-type conductivity semiconductor.

[0046] The gate dielectric layer 60 may be disposed between the ground selection gate electrode 120a and each semiconductor pillar PI. The gate dielectric layer 60 may have sidewalls that are convexly curved in opposite directions. The gate dielectric layer 60 may include, for example, a thermal oxide layer or a silicon oxide layer. Figure 5 The horizontal dielectric layer 170 may be disposed between each vertical channel structure VS and each of the cell selection gate electrode 120b and the string selection gate electrode 120c, and may also be disposed between the gate dielectric layer 60 and the ground selection gate electrode 120a. The horizontal dielectric layer 170 may extend onto the top and bottom surfaces of the gate electrodes 120a, 120b, and 120c. The horizontal dielectric layer 170 may include, for example, a silicon oxide layer (e.g., SiO 2 ) or a high-k dielectric layer (e.g. aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 )).

[0047] In some embodiments, the gate structure may be defined as including a single horizontal dielectric layer 170 and a single gate electrode, the single gate electrode being disposed between dielectric patterns 110 adjacent to each other in the third direction Z. For example, the cell gate structure GS1 may be defined as including a cell gate electrode 120b and a horizontal dielectric layer 170 surrounding the cell gate electrode 120b. The string selection gate structure GS2 may be defined as including a string selection gate electrode 120c and a horizontal dielectric layer 170 surrounding the string selection gate electrode 120c. The ground selection gate structure GS3 may be defined as including a ground selection gate electrode 120a and a horizontal dielectric layer 170 surrounding the ground selection gate electrode 120a.

[0048] Further references Figure 5 , each of the cell gate structure GS1 and the string selection gate structure GS2 may be disposed between dielectric patterns 110 adjacent to each other along a third direction Z. Each of the cell gate structure GS1 and the string selection gate structure GS2 may include a lower portion LP and an upper portion UP. The lower portion LP may be disposed between a pair of upper dielectric patterns 110a and a lower dielectric pattern 110b adjacent to each other along the third direction Z. The upper portion UP may be disposed between the lower portion LP and the upper dielectric pattern 110a located above the lower portion LP among the upper dielectric patterns 110a and the lower dielectric patterns 110b adjacent to each other along the third direction Z. Each of the cell gate structure GS1 and the string selection gate structure GS2 may have a bottom surface 1 and a top surface 3, wherein a width W1 of the bottom surface 1 along the first direction X from an arbitrary line AL (which extends in a direction perpendicular to the top surface of the substrate) is greater than a width W2 of the top surface 3 along the first direction X from the same arbitrary line AL (W1>W2). For example, the width W1 of the lower portion LP at its bottom surface 1 may be greater than the width W2 at the top surface 3 of the upper portion UP (W1>W2). The upper dielectric pattern 110a overlying the cell gate structure GS1 and the string selection gate structure GS2 may have a top surface 5 and a bottom surface 7, and the width W1 of the lower portion LP of the cell gate structure GS1 and the string selection gate structure GS2 at the bottom surface 1 may be substantially the same as the width W3 of the top surface 5 along the first direction X from the same arbitrary line AL (W1=W3). The width W1 of the lower portion LP at the bottom surface 1 may be substantially the same as the width of the lower dielectric pattern 110b below the lower LP. The width W2 of each of the cell gate structure GS1 and the string selection gate structure GS2 at the top surface 3 may be less than the width W3 of the upper dielectric pattern 110a overlying the lower LP at the top surface 5 (W2<W3). The lower portion LP may have a width that remains constant as approaching the upper portion UP from the lower dielectric pattern 110 b , and the upper portion UP may have a width that decreases as approaching the upper dielectric pattern 110 a from the lower portion LP.

[0049] Each of the cell gate electrode 120b and the string selection gate electrode 120c may have a larger width at its bottom surface 1 and may have a smaller width at its top surface 3. For example, each of the cell gate electrode 120b and the string selection gate electrode 120c may include a lower portion A' and an upper portion B'. The lower portion A' may be disposed between the upper dielectric pattern 110a and the lower dielectric pattern 110b adjacent to each other in the third direction Z, and the upper portion B' may be disposed between the lower portion A' and the upper dielectric pattern 110a overlying the lower portion A'. The lower portion A' may have a width at its bottom surface 1 greater than a width at the top surface 3 of the upper portion B'. Each of the lower portion A' and the upper portion B' may have a sidewall adjacent to the charge storage structure 240, and the sidewall of the upper portion B' may form an angle θ with respect to the sidewall of the lower portion A', and the angle θ is an obtuse angle (e.g., 90°<θ<180°). The sidewall of the upper portion B' adjacent to the charge storage structure 240 may be a flat surface substantially without curvature. The sidewall of the lower portion A' may be substantially perpendicular to the top surface of the substrate 100, the sidewall being adjacent to the charge storage structure 240. Alternatively, as Figure 7 As shown, the sidewall of the upper portion B' of each of the cell gate electrode 120b and the string selection gate electrode 120c adjacent to the charge storage structure 240 may have a smoothly curved concave surface, so that the sidewall of the charge storage structure 240 adjacent to the upper portion B' has a smoothly curved convex surface.

[0050] In some embodiments, the vertical channel structure VS may penetrate the cell gate structure GS1 and the string selection gate structure GS2, and may extend from the top surface of the substrate 100 to the first sidewall S1 of the cell gate structure GS1 and the string selection gate structure GS2 and also extend to the first sidewall S1_a of the dielectric pattern 110 other than the lowest dielectric pattern 110. In some embodiments, the first sidewall S1 of the upper portion UP in each of the cell gate structure GS1 and the string selection gate structure GS2 may be recessed from the first sidewall S1_a of the upper dielectric pattern 110a overlying each of the cell gate structure GS1 and the string selection gate structure GS2. Therefore, on the cell array area CAR of the substrate 100, a first recessed region R1 may be provided between the upper dielectric pattern 110a and each of the cell gate structure GS1 and the string selection gate structure GS2. The vertical channel structure VS may have a protrusion PS protruding from its sidewall. The protrusion PS may contact the cell gate structure GS1 and the string selection gate structure GS2. Each protrusion PS may be disposed in the first recessed region R1. For example, the charge storage structure 240 may have a protrusion protruding from its sidewall in contact with the dielectric pattern 110, and the protrusion PS of the vertical channel structure VS may correspond to the protrusion of the charge storage structure 240. Each protrusion of the charge storage structure 240 may be disposed in the first recessed region R1. The top surface of the protrusion PS may be at the same level as the bottom surface 7 of the dielectric pattern 110. Each protrusion PS may be spaced apart from the lower dielectric pattern 110b in the dielectric patterns 110a and 110b adjacent to each other in the third direction Z, and may be in contact with the upper dielectric pattern 110a in the dielectric patterns 110a and 110b adjacent to each other in the third direction Z. In an embodiment of the inventive concept, the charge storage structure 240 may be characterized by including a protrusion PS extending into the first recessed region R1, which is disposed in the sidewalls of the cell gate structure GS1 and the string selection gate structure GS2 at the interface between the gate structures GS1 and GS2 and the dielectric pattern 110a. The charge storage structure 240 may include a first charge storage segment 240A, a second charge storage segment 240B, and a third charge storage segment 240C. The first charge storage segment 240A may be disposed in the first recessed region R1. The first charge storage segment 240A may be disposed between the vertical channel VC and the upper portion UP of each of the cell and string selection gate structures GS1 and GS2. The second charge storage segment 240B may be disposed between the vertical channel VC and each dielectric pattern 110. The third charge storage segment 240C may be disposed between the vertical channel VC and the lower portion LP of each of the cell and string selection gate structures GS1 and GS2. The first charge storage segment 240A may have a thickness W4 greater than the thickness W5 of the second charge storage segment 240B (W4>W5).The thickness W5 of the second charge storage segment 240B may be substantially the same as the thickness W6 of the third charge storage segment 240C (W5=W6). The thickness W4 of the first charge storage segment 240A may increase as approaching the second charge storage segment 240B from the third charge storage segment 240C. In some embodiments, the thickness W4 of the first charge storage segment 240A may be approximately 1.1 to 2 times the thickness W5 of the second charge storage segment 240B. For example, the thickness W4 of the first charge storage segment 240A may be approximately 1.3 to 1.7 times the thickness W5 of the second charge storage segment 240B.

[0051] In some embodiments, the charge storage structure may be formed to have a large thickness on the upper sidewall of the gate electrode. Thus, interference between gate electrodes vertically adjacent to each other may be minimized, and diffusion of trapped charges in the charge storage structure at the corners of certain gate electrodes to the charge storage structure on other gate electrodes vertically adjacent to the certain gate electrodes may also be minimized.

[0052] On the top surface of the substrate 100, the vertical channel structure VS may penetrate the cell gate structure GS1 and the string selection gate structure GS2. Each vertical channel structure VS may include a vertical channel VC and a charge storage structure 240. The vertical channel VC may penetrate the cell gate structure GS1, the string selection gate structure GS2, and the dielectric pattern 110 in the third direction Z. The vertical channel VC may have a hollow tube shape, a cylindrical shape, or a cup shape. The vertical channel VC may include a single layer or multiple layers. The vertical channel VC may include, for example, one or more of a single crystal silicon layer, an organic semiconductor layer, and a carbon nanostructure.

[0053] The charge storage structure 240 may extend between the vertical channel VC and the cell gate structure GS1, between the vertical channel VC and the string selection gate structure GS2, and between the vertical channel VC and the dielectric pattern 110. The bottom surface 7 of the dielectric pattern 110 may have a portion adjacent to the upper portion UP of the corresponding one of the cell and string selection gate structures GS1 and GS2. The bottom surface 7 of the dielectric pattern 110 may also include a portion that is not only spaced apart from the corresponding one of the cell and string selection gate structures GS1 and GS2 but also covered with the charge storage structure 240. The charge storage structure 240 may contact the sidewall of each of the lower portion LP and the upper portion UP. The charge storage structure 240 may have a recess D recessed from its outer wall. The outer wall of the charge storage structure 240 may contact the vertical channel VC. The vertical channel VC may be disposed on the outer wall of the charge storage structure 240 and may be disposed in the recess D. Therefore, the vertical channel VC may have the same profile as the profile of the charge storage structure 240. For example, the recess D may be located at a level measured from the top surface of the substrate 100 between a level of a lower portion LP of each of the cell and string selection gate structures GS1 and GS2 and a level of an upper dielectric pattern 110a overlying an upper portion UP of each of the cell and string selection gate structures GS1 and GS2.

[0054] The charge storage structure 240 may include a tunnel dielectric layer TL, a blocking dielectric layer BLL, and a charge storage layer CTL. The tunnel dielectric layer TL may be disposed adjacent to the vertical channel VC and may surround the inner wall of the vertical channel VC. The blocking dielectric layer BLL may be disposed adjacent to the cell and string selection gate structures GS1 and GS2. The charge storage layer CTL may be disposed between the tunnel dielectric layer TL and the blocking dielectric layer BLL. The tunnel dielectric layer TL may include, for example, a silicon oxide layer or a high-k dielectric layer (e.g., aluminum oxide (AlO)). 2 O 3 ) or hafnium oxide (HfO 2 The blocking dielectric layer BLL may include, for example, a silicon oxide layer or a high-k dielectric layer (eg, aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 )). The charge storage layer CTL may include, for example, a silicon nitride layer.

[0055] In some embodiments, the blocking dielectric layer BLL may be in contact with the first sidewall S1 of the cell and string selection gate structures GS1 and GS2 and in contact with the first sidewall S1_a of the dielectric pattern 110, and may be disposed in the first recessed region R1. The blocking dielectric layer BLL may have a first recess E1 recessed from its outer wall. The outer wall of the blocking dielectric layer BLL may be closer to the vertical channel VC than its inner wall. The charge storage layer CTL may surround the outer wall of the blocking dielectric layer BLL and may be disposed in the first recess E1 of the blocking dielectric layer BLL. The charge storage layer CTL may contact the first recess E1. The charge storage layer CTL may have a second recess E2 recessed from its outer wall. The outer wall of the charge storage layer CTL may be closer to the vertical channel VC than its inner wall. The tunnel dielectric layer TL may surround the outer wall of the charge storage layer CTL and may be disposed in the second recess E2 of the charge storage layer CTL. The tunnel dielectric layer TL may contact the second recess E2. The tunnel dielectric layer TL may have a recess D recessed from an outer wall thereof. The outer sidewall of the tunnel dielectric layer TL may contact the vertical channel VC. The recess D of the tunnel dielectric layer TL may correspond to the recess D of the charge storage structure 240 . Figure 7 Included with Figure 5 A similar structure except for the shape of the sidewall of the upper portion B′ of each of the cell and string selection gate electrodes 120 b and 120 c and the shape of the first recessed region R1 , and the respective shapes of the protrusion PS, the recess D, the first recess E1 , and the second recess E2 .

[0056] In certain embodiments, in reference to Figure 1 In each cell string CSTR described, the ground selection transistor GST may include a ground selection gate electrode 120a of a ground selection gate structure GS3, the string selection transistor SST may include a string selection gate electrode 120c of a string selection gate structure GS2, and the memory cell transistor MCT may include a cell gate electrode 120b of four cell gate structures GS1. In one cell string CSTR, the protrusion PS of the vertical channel structure VS may be disposed on the sidewalls of four cell gate structures GS1 and the sidewall of one string selection gate structure GS2.

[0057] In certain embodiments, in each of adjacent cell strings CSTR penetrating the same stack structure ST, the protrusion PS of the vertical channel structure VS may be disposed on each of the sidewalls of the four cell gate structures GS1 and the sidewall of one string selection gate structure.

[0058] The gap filling layer 250 may be disposed in the inner space surrounded by the vertical channel VC. The gap filling layer 250 may include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The pad 260 may be disposed on the upper portion of the vertical channel VC of the charge storage structure 240 and on the upper portion of the gap filling layer 250. The pad 260 may include a conductive material or a semiconductor material doped with impurities having a conductivity type different from that of the vertical channel VC.

[0059] Further references Fig. 6A , the dummy vertical channel structure DVS may be disposed on the pad region CR of the substrate 100. The dummy vertical channel structure DVS may penetrate the stacked structure ST and the interlayer dielectric pattern 200. When viewed in a plan view, the dummy vertical channel structure DVS may be disposed on the ends of the ground selection gate structure GS3, the cell gate structure GS1, and the string selection gate structure GS2. For example, when viewed in a plan view, the dummy vertical channel structure DVS may be disposed on the edges of the ends of the ground selection gate structure GS3, the cell gate structure GS1, and the string selection gate structure GS2. Each dummy vertical channel structure DVS may include a dummy vertical channel DVC and a dummy charge storage structure D240.

[0060] On the pad region CR of the substrate 100, the dummy vertical channel DVC on the end of the string selection gate structure GS2 may penetrate the cell gate structure GS1, the string selection gate structure GS2, and the dielectric pattern 110. On the pad region CR of the substrate 100, the dummy vertical channel structure DVS on the end of the cell gate structure GS1 may penetrate the cell gate structure GS1, the dielectric pattern 110, and the interlayer dielectric pattern 200. The dummy vertical channel structure DVS on the end of the ground selection gate structure GS3 may penetrate the interlayer dielectric pattern 200. The dummy charge storage structure D240 may be disposed adjacent to the cell gate structure GS1 and the string selection gate structure GS2, and the dummy vertical channel DVC may surround the outer wall of the dummy charge storage structure D240. The dummy charge storage structure D240 may have an inner wall in contact with the cell gate structure GS1 and the string selection gate structure GS2 and in contact with the dielectric pattern 110. The dummy vertical channel DVC may be formed of the same material as that of the vertical channel VC, and the dummy charge storage structure D240 may be formed of the same material as that of the charge storage structure 240 .

[0061] In some embodiments, the dummy vertical channel structure DVS may penetrate the cell gate structure GS1 and the string selection gate structure GS2, and may extend from the top surface of the substrate 100 onto the second sidewall S2 of the cell gate structure GS1 and the string selection gate structure GS2 and also onto the second sidewall S2_a of the dielectric pattern 110. In some embodiments, the second sidewall S2 of the upper portion UP of each of the cell gate structure GS1 and the string selection gate structure GS2 may be recessed from the second sidewall S2_a of the upper dielectric pattern 110a overlying each of the cell gate structure GS1 and the string selection gate structure GS2. Therefore, on the pad region CR of the substrate 100, a second recessed region R2 may be provided between each of the cell gate structure GS1 and the string selection gate structure GS2 and the upper dielectric pattern 110a immediately overlying each of the cell gate structure GS1 and the string selection gate structure GS2. The dummy vertical channel structure DVS may have a dummy protrusion DPS protruding from its inner wall in contact with the dielectric pattern 110. The dummy protrusion DPS may contact the cell gate structure GS1 and the string selection gate structure GS2. Each dummy protrusion DPS may be disposed in the second recessed region R2. For example, the dummy charge storage structure D240 may have a protrusion protruding from its sidewall in contact with the dielectric pattern 110, and the dummy protrusion DPS of the dummy vertical channel structure DVS may correspond to the protrusion of the dummy charge storage structure D240. Each protrusion of the dummy charge storage structure D240 may be disposed in the second recessed region R2.

[0062] In some embodiments, when a sufficient distance is not provided between the dummy vertical channel structures DVS adjacent to each other in the first direction X, or when the width of the dummy vertical channel structure DVS is greater than the width of the vertical channel structure VS, the dummy protrusions DPS of the dummy vertical channel structures DVS adjacent to each other in the first direction X may contact each other. Fig. 6A As shown, the dummy charge storage structures D240 of the dummy vertical channel structures DVS adjacent to each other in the first direction X may contact each other. The portion of the cell gate structure GS1 between the dummy protrusions DPS may be spaced apart from the upper dielectric pattern 110a immediately overlying the portion of the cell gate structure GS1. Figure 6B As shown, the dummy protrusions DPS of the dummy vertical channel structures DVS adjacent to each other in the first direction X may be spaced apart from each other, and an air gap AG may be provided between the dummy protrusions DPS. The air gap AG may be interposed between a portion of the cell gate structure GS1 between the dummy protrusions DPS and an upper dielectric pattern 110a immediately overlying the portion of the cell gate structure GS1.

[0063] In other embodiments, Figure 8As shown, when a sufficient distance is provided between the dummy vertical channel structures DVS adjacent to each other in the first direction X, the dummy protrusions DPS of the dummy vertical channel structures DVS adjacent to each other in the first direction X may be spaced apart from each other. A portion of the cell gate structure GS1 between the dummy protrusions DPS may contact the upper dielectric pattern 110 a immediately overlying the portion of the cell gate structure GS1.

[0064] The dummy vertical channel DVC may have a deposition shape that is the same as that of the vertical channel VC, and the dummy charge storage structure D240 may have a deposition shape that is the same as that of the charge storage structure 240. In addition, like the charge storage structure 240, the dummy charge storage structure D240 may include a blocking dielectric layer BLL, a charge storage layer CTL, and a tunnel dielectric layer TL. The dummy vertical channel DVC and the dummy charge storage structure D240 may have structural characteristics that are the same as those of the vertical channel VC and the charge storage structure 240, respectively. Therefore, the structural description of the vertical channel VC and the charge storage structure 240 may also be applicable to the dummy vertical channel DVC and the dummy charge storage structure D240, and for the sake of brevity, further detailed descriptions of the dummy vertical channel DVC and the dummy charge storage structure D240 may be omitted.

[0065] The dummy semiconductor column DPI may be disposed between the substrate 100 and the dummy vertical channel structure DVS. The dummy semiconductor column DPI may penetrate the ground selection gate structure GS3. The dummy gate dielectric layer D60 may be disposed between the ground selection gate structure GS3 and each dummy semiconductor column DPI. The dummy gap filling layer D250 may be disposed in the inner space surrounded by the dummy vertical channel DVC. The dummy pad D260 may be disposed on the upper portion of the dummy vertical channel DVC, the upper portion of the dummy charge storage structure D240, and the upper portion of the dummy gap filling layer D250.

[0066] The first interlayer dielectric layer 310 may be disposed on the top surface of the stacked structure ST and on the top surface of the interlayer dielectric pattern 200. The first interlayer dielectric layer 310 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0067] The contact structure 340 may be disposed between the stack structures ST adjacent to each other in the second direction Y. The contact structure 340 may extend in the first direction X and may penetrate the first interlayer dielectric layer 310. When viewed in a plan view, the contact structure 340 may have a rectangular or linear shape extending in the first direction X. Alternatively, a plurality of contact structures 340 may be provided, and the plurality of contact structures 340 may be arranged along the common source region CSR in the first direction X. In this case, the plurality of contact structures 340 may have a columnar shape.

[0068] The contact structure 340 may include a spacer 320 and a common source contact 330. The common source contact 330 may be electrically connected to the common source region CSR. The common source contact 330 may include, for example, a metal (e.g., tungsten, copper, or aluminum) or a transition metal (e.g., titanium or tantalum). The spacer 320 may surround the sidewall of the common source contact 330. The spacer 320 may include, for example, a dielectric material such as a silicon oxide layer or a silicon nitride layer.

[0069] The second interlayer dielectric layer 350 may be disposed on the first interlayer dielectric layer 310. The second interlayer dielectric layer 350 may cover a top surface of the first interlayer dielectric layer 310 and a top surface of the contact structure 340. The second interlayer dielectric layer 350 may include, for example, a silicon oxide layer.

[0070] The cell contact plug 410 may be disposed on the pad region CR of the substrate 100. The cell contact plug 410 may be disposed on the ends of the gate structures GS1, GS2, and GS3 of the stacked structure ST. For example, the cell contact plug 410 may directly contact the top surface of the distal end of the gate electrodes 120a, 120b, and 120c. The cell contact plug 410 may include, for example, one or more of a metal (e.g., copper or tungsten) and a metal nitride (e.g., TiN, TaN, or WN).

[0071] The channel contact plug 420 may be provided on the pad 260 disposed on the vertical channel structure VS. The channel contact plug 420 may penetrate the second interlayer dielectric layer 350 and the first interlayer dielectric layer 310, thereby directly contacting the pad 260. The channel contact plug 420 may include, for example, one or more of a metal (e.g., copper or tungsten) and a metal nitride (e.g., TiN, TaN, or WN). In some embodiments, the channel contact plug 420 may not be provided on the dummy pad D260 disposed on the dummy vertical channel structure DVS.

[0072] The connection line 430 may be disposed on the second interlayer dielectric layer 350. The connection line 430 may be electrically connected to the cell contact plug 410.

[0073] The bit lines BL may be disposed on the second interlayer dielectric layer 350 . The bit lines BL may extend in the second direction Y and may cross the stack structure ST. The bit lines BL may be electrically connected to corresponding channel contact plugs 420 .

[0074] Fig. 9 Shows Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig. 9 Included with Figure 5 The following description will focus on the similar structure shown in Figure 5 and Fig. 9 differences between the implementations of

[0075] Reference Fig. 9 The cap pattern 230a may be disposed in the recess D of the charge storage structure 240. The cap pattern 230a may have a sidewall aligned with the outer wall of the charge storage structure 240. The vertical channel VC may extend in the third direction Z along the sidewall of the cap pattern 230a and the outer wall of the charge storage structure 240. The vertical channel VC may have a flat sidewall in contact with the gap filling layer 250. The cap pattern 230a may include, for example, a silicon oxide layer or a high-k dielectric layer (e.g., aluminum oxide (Al2O3)). 2 O 3 ) or hafnium oxide (HfO 2 )). The capping pattern 230a may include the same material as that of the tunnel dielectric layer TL.

[0076] Fig.10 Shows Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig.10 Included with Figure 5 The following description will focus on the similar structure shown in Figure 5 and Fig.10 differences between the implementations of

[0077] Reference Fig.10 , a cap pattern 230b may be disposed in the second recess E2 of the charge storage layer CTL. The cap pattern 230b may have a sidewall aligned with the outer wall of the charge storage layer CTL. The tunnel dielectric layer TL may extend in the third direction Z along the sidewall of the cap pattern 230b and the outer wall of the charge storage layer CTL. The tunnel dielectric layer TL may have a flat sidewall in contact with the vertical channel VC.

[0078] Fig.11 Show Figure 3 An enlarged view of a portion A in FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig.11 Included with Figure 5 The following description will focus on the similar structure shown in Figure 5 and Fig.11 differences between the implementations of

[0079] Reference Fig.11, the bottom surface 7 of the upper dielectric pattern 110a may have a first portion that is covered by the horizontal dielectric layer 170 and is flat relative to the top surface of the substrate 100. The bottom surface 7 of the upper dielectric pattern 110a may also have a second portion that is covered by the charge storage structure 240 and is uneven relative to the top surface of the substrate 100. For example, the second portion of the bottom surface 7 covered by the charge storage structure 240 may have an obtuse angle relative to the first sidewall S1_a of the upper dielectric pattern 110a.

[0080] Fig.12 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig.13 Shows Fig.12 An enlarged view of portion A' in FIG.

[0081] Reference Fig.12 and Fig.13 , a first recessed region R1 may be provided between the lower dielectric pattern 110b and each of the cell gate structure GS1 and the string selection gate structure GS2. The first recessed region R1 may correspond to a region where the first sidewall S1 of each of the cell gate structure GS1 and the string selection gate structure GS2 is recessed from the first sidewall S1_a of the lower dielectric pattern 110b. The first recessed region R1 may partially expose the top surface 8 of the lower dielectric pattern 110b. Each protrusion PS of the vertical channel structure VS may be disposed in the first recessed region R1. The protrusion PS of the vertical channel structure VS may partially cover the top surface 8 of the lower dielectric pattern 110b. In some embodiments, the protrusion PS may have a bottom surface at the same level as that of the top surface 8 of the dielectric pattern 110. Each of the cell gate structure GS1 and the string selection gate structure GS2 may include a lower portion LP and an upper portion UP. The width W1 of the bottom surface 1 of the lower portion LP may be less than the width W2 of the top surface 3 of the upper portion UP (W1<W2). A width W1 of the bottom surface 1 of the lower portion LP may be smaller than a width W8 of the bottom surface 7 of the upper dielectric pattern 110 a ( W1 < W8 ).

[0082] The charge storage structure 240 may include a first charge storage segment 240A, a second charge storage segment 240B, and a third charge storage segment 240C. The first charge storage segment 240A may be disposed between the vertical channel VC and the lower portion LP of each of the cell gate structure GS1 and the string selection gate structure GS2. The second charge storage segment 240B may be disposed between the vertical channel VC and each dielectric pattern 110. The third charge storage segment 240C may be disposed between the vertical channel VC and the upper portion UP of each of the cell gate structure GS1 and the string selection gate structure GS2. The thickness W4 of the first charge storage segment 240A may be greater than the thickness W5 of the second charge storage segment 240B (W4>W5). The thickness W5 of the second charge storage segment 240B may be substantially the same as the thickness W6 of the third charge storage segment 240C (W5=W6). The thickness W4 of the first charge storage segment 240A may increase as it approaches the second charge storage segment 240B from the third charge storage segment 240C.

[0083] Fig.14 Shown along Figure 2 , which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig.15 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0084] refer to Fig.14 and Fig.15 , the vertical channel structure VS, the dummy vertical channel structure DVS, the gap filling layer 250, and the dummy gap filling layer D250 may contact the top surface of the substrate 100. For example, the present embodiment may not include the previously referenced Figure 3 and Figure 4 The semiconductor pillar PI described also does not include a dummy semiconductor pillar DPI. The vertical channel structure VS may have a flat sidewall in contact with the ground selection gate structure GS3. For example, the vertical channel structure VS may not have a protrusion PS in contact with the ground selection gate structure GS3. In addition, the dummy vertical channel structure DVS may not have a dummy protrusion DPS in contact with the ground selection gate structure GS3.

[0085] Fig.16 Shown along Figure 2 , which is a cross-sectional view taken along line II′ of FIG. 1 , shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig.17 Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig.18 Shows Fig.16 Magnified view of portion C in FIG.

[0086] Reference Fig.16 , Fig.17 and Fig.18 , the vertical channel structure VS may have a flat sidewall in contact with the string selection gate structure GS2. Figure 3 and Figure 4 Compared to the described embodiment, the present embodiment may not have the protrusion PS contacting the string selection gate structure GS2. The first sidewall S1 at the upper portion of the string selection gate structure GS2 may be aligned with the first sidewall S1_a of the upper dielectric pattern 110a on the string selection gate structure GS2.

[0087] The charge storage structure 240 may include a fourth charge storage segment 240D between the string selection gate structure GS2 and the vertical channel VC. The fourth charge storage segment 240D may have a larger thickness than the first charge storage segment (see Figure 5 240A) thickness (see Figure 5 W4) small thickness W7.

[0088] Fig.19 A plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is shown. Fig. 20 Shown along Fig.19 A cross-sectional view taken along line III-III' of FIG. 1 shows a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0089] Reference Fig.19 and Fig. 20 , the substrate 100 may be provided with first stack structures ST1 and second stack structures ST2 alternately arranged in the second direction Y. The contact structure 340 may be disposed between the first stack structures ST1 and the second stack structures ST2 extending in the first direction X and adjacent to each other in the second direction Y. The lower substrate 1000 may be disposed under the substrate 100, and the peripheral circuit structure PRS may be disposed between the lower substrate 1000 and the substrate 100. The lower substrate 1000 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate.

[0090] The peripheral circuit structure PRS may include a transistor TR, a peripheral circuit interlayer dielectric layer 10, a wiring pad 13, and a via 15. The transistor TR may be disposed on an active region of the lower substrate 1000. The transistors TR may each include a peripheral gate dielectric layer 40, a peripheral gate electrode 43, and a source / drain region 45. The peripheral circuit interlayer dielectric layer 10 may be disposed on the lower substrate 1000. The peripheral circuit interlayer dielectric layer 10 may cover the transistor TR. The wiring pad 13 and the via 15 may be disposed in the peripheral circuit interlayer dielectric layer 10. The wiring pads 13 located at different levels may be connected to each other by the via 15 interposed therebetween. The transistor TR may be connected to the wiring pad 13 by the via 15.

[0091] The through dielectric pattern TVS may penetrate the contact structure 340 and a pair of first and second stacked structures ST1 and ST2. The through dielectric pattern TVS may be disposed on the cell array region CAR, adjacent to the pad region CR of the substrate 100. The through dielectric pattern TVS may penetrate the substrate 100 and may contact the peripheral circuit structure PRS. The through dielectric pattern TVS may include a dielectric material (e.g., a silicon oxide layer).

[0092] The peripheral contact plug 450 may be disposed in the through dielectric pattern TVS. The peripheral contact plug 450 may contact the wiring pad 13 disposed in the peripheral circuit structure PRS, and may be electrically connected to the transistor TR through the wiring pad 13 and the via 15. The connection line 430 may be disposed on the peripheral contact plug 450. The connection line 430 may extend to the cell contact plug 410. The connection line 430 may electrically connect the peripheral contact plug 450 to the cell contact plug 410.

[0093] FIG. 21A to FIG. 27A Shown along Figure 2 A cross-sectional view taken along line II' of FIG. 1 shows a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. FIG. 21B to FIG. 27B Shown along Figure 2 A cross-sectional view taken along line II-II' of FIG. 1 shows a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Fig. 22C Show Fig. 22B An enlarged view of portion D in FIG.

[0094] Reference Fig.21A and Fig.21B, the substrate 100 may include a cell array region CAR and a pad region CR. A buffer dielectric layer 50 may be formed on the cell array region CAR and the pad region CR of the substrate 100. The buffer dielectric layer 50 may cover the top surface of the substrate 100. A mold structure MS may be formed on the substrate 100. The mold structure MS may be formed by alternately and repeatedly stacking a sacrificial layer 610 and a dielectric layer 620 on the buffer dielectric layer 50. The sacrificial layer 610 may include, for example, a silicon nitride layer. The dielectric layer 620 may be formed of a material having an etching selectivity relative to the sacrificial layer 610. The dielectric layer 620 may include, for example, a silicon oxide layer.

[0095] The mold structure MS may be patterned to have a step structure on the pad region CR of the substrate 100. The patterning of the mold structure MS may include forming a mask pattern (not shown) on the mold structure MS, the mask pattern exposing a portion of the mold structure MS, the portion being formed on the pad region CR of the substrate 100, and then repeatedly performing a process in which the mask pattern is used as an etching mask to etch the dielectric layer 620 and the sacrificial layer 610 and a process in which the width of the mask pattern is reduced to increase the etching target plane area of ​​the dielectric layer 620 and the sacrificial layer 610. The mold structure MS may expose the buffer dielectric layer 50 on the pad region CR of the substrate 100. The dielectric layer 620 may have a distal end whose top surface is exposed on the pad region CR of the substrate 100. The sacrificial layer 610 may have a distal end having a top surface thereof exposed on the pad region CR of the substrate 100. The sacrificial layer 610 may have a distal end having a top surface thereof exposed on the pad region CR of the substrate 100. Figure 2 The length of the dielectric layer 620 in the first direction (in the X direction) may decrease as the distance from the substrate 100 increases, and the length of the dielectric layer 620 in the first direction may decrease as the distance from the substrate 100 increases. A pair of the sacrificial layer 610 and the dielectric layer 620 vertically adjacent to each other may have the same length in the first direction X.

[0096] The interlayer dielectric pattern 200 may be formed to cover the step structure of the mold structure MS and the buffer dielectric layer 50. The interlayer dielectric pattern 200 may expose the top surface of the mold structure MS. The interlayer dielectric pattern 200 may include, for example, a tetraethyl orthosilicate (TEOS) oxide layer.

[0097] refer to Fig.22A and Fig. 22B, the mold structure MS and the buffer dielectric layer 50 may be patterned to form a channel hole CH and a dummy channel hole DCH in the mold structure MS. The channel hole CH may be formed on the cell array region CAR of the substrate 100, and the dummy channel hole DCH may be formed on the pad region CR of the substrate 100. The formation of the channel hole CH and the dummy channel hole DCH may include forming a mask pattern (not shown) on the mold structure MS and the interlayer dielectric pattern 200, and then anisotropically etching the mold structure MS and the interlayer dielectric pattern 200 using the mask pattern as an etching mask. When viewed in a plan view, the channel hole CH and the dummy channel hole DCH may have a circular, elliptical, or polygonal shape.

[0098] For example, the number of deposited layers when forming the dummy channel hole DCH may be greater than the number of deposited layers when forming the channel hole CH, so that the dummy channel hole DCH may be formed to have a width and a depth greater than the width and the depth of the channel hole CH. As another example, the dummy channel hole DCH may be formed to have a width substantially the same as that of the channel hole CH.

[0099] In some embodiments, an etching process may be performed so that the upper sidewall of the sacrificial layer 610 exposed to the channel hole CH may be recessed from the sidewall of the dielectric layer 620 exposed to the channel hole CH. Figure 2 A first recessed region R1 is formed between the sacrificial layer 610 and the dielectric layer 620 adjacent to each other in the third direction Z. In addition, the upper sidewall of the sacrificial layer 610 exposed to the dummy channel hole DCH may be recessed from the sidewall of the dielectric layer 620 exposed to the dummy channel hole DCH. Therefore, a second recessed region R2 may be formed between the sacrificial layer 610 and the dielectric layer 620 adjacent to each other in the third direction Z. The first recessed region R1 and the second recessed region R2 may partially expose the bottom surface of the dielectric layer 620. The first recessed region R1 may be spatially connected to the corresponding channel hole CH, and the second recessed region R2 may be spatially connected to the corresponding dummy channel hole DCH. Etching does not occur on the lower sidewall of the sacrificial layer 610 adjacent to the top surface of the dielectric layer 620. The etching gas may include, for example, CH 2 F 2 , C 4 F 6 , C 4 F 8 and NF 3 One or more of .

[0100] In certain embodiments, Fig. 22CAs shown, during the formation of the channel hole CH and the dummy channel hole DCH, a first byproduct BP1 may be formed on the sidewall of the sacrificial layer 610, and a second byproduct BP2 may be formed on the sidewall of the dielectric layer 620. The first byproduct BP1 may be a layer formed when the etching gas is combined with the etched material separated from the sacrificial layer 610, and the second byproduct BP2 may be a layer formed when the etching gas is combined with the etched material separated from the dielectric layer 620. The second byproduct BP2 may be formed thinner than the first byproduct BP1. The first byproduct BP1 may fully cover the interface between each lower portion of the sacrificial layer 610 and each dielectric layer 620 below the lower portion of the sacrificial layer 610. Therefore, the lower portion of the sacrificial layer 610 may not be etched. On the contrary, because the second byproduct BP2 is formed to have a small thickness on the sidewall of the dielectric layer 620, the etching ions may easily enter the interface between each dielectric layer 620 and each sacrificial layer 610 below the dielectric layer 620. Thus, the first and second recessed regions R1 and R2 may be formed between the sacrificial layer 610 and the lower portion of the dielectric layer 620. After the etching process, the first and second byproducts BP1 and BP2 may be removed.

[0101] In some embodiments, the adhesion between the top surface of the sacrificial layer 610 and the bottom surface of the dielectric layer 620 may be different from the adhesion between the bottom surface of the sacrificial layer 610 and the top surface of the dielectric layer 620. For example, a weak adhesion may be provided between the top surface of the sacrificial layer 610 and the bottom surface of the dielectric layer 620, and a strong adhesion may be provided between the bottom surface of the sacrificial layer 610 and the top surface of the dielectric layer 620. Therefore, the etching gas may enter the interface between the top surface of the sacrificial layer 610 and the bottom surface of the dielectric layer 620, thereby etching the upper portion of the sacrificial layer 610.

[0102] Reference Fig.23A and Fig. 23B , a semiconductor column PI may be formed in the channel hole CH, and a dummy semiconductor column DPI may be formed in the dummy channel hole DCH. The lower portion of the channel hole CH may be filled with the semiconductor column PI, and the lower portion of the dummy channel hole DCH may be filled with the dummy semiconductor column DPI. A selective epitaxial growth process may be adopted to grow the semiconductor column PI and the dummy semiconductor column DPI from the substrate 100 used as a seed crystal exposed to the channel hole CH and the dummy channel hole DCH. The semiconductor column PI and the dummy semiconductor column DPI may include a material whose directivity is the same as that of the substrate 100.

[0103] A charge storage structure 240 may be formed in the channel hole CH, and a dummy charge storage structure D240 may be formed in the dummy channel hole DCH. The charge storage structure 240 may conformally cover the sidewalls of the channel hole CH and the sidewalls of the first recessed region R1, and may partially expose the top surface of the semiconductor pillar PI. The dummy charge storage structure D240 may conformally cover the sidewalls of the dummy channel hole DCH and the sidewalls of the second recessed region R2, and may partially expose the top surface of the dummy semiconductor pillar DPI. The first recessed region R1 may be filled with the charge storage structure 240, and the second recessed region R2 may be filled with the dummy charge storage structure D240. Therefore, the charge storage structure 240 may include a protrusion formed in the first recessed region R1 (see Figure 5 PS), and the dummy charge storage structure D240 may include a dummy protrusion formed in the second recessed region R2 (see Fig. 6A DPS).

[0104] like Figure 5 As shown, each charge storage structure 240 may include a blocking dielectric layer BLL, a charge storage layer CTL, and a tunnel dielectric layer TL sequentially formed on the sidewall of a corresponding one of the channel holes CH. Fig. 6A As shown, each dummy charge storage structure D240 may include a blocking dielectric layer BLL, a charge storage layer CTL, and a tunnel dielectric layer TL sequentially formed on the sidewall of a corresponding one of the dummy channel holes DCH. For example, the blocking dielectric layer BLL may include a silicon oxide layer or a high-k dielectric layer (e.g., Al 2 O 3 or HfO 2 ), the charge storage layer CTL may include a silicon nitride layer, and the tunnel dielectric layer TL may include a silicon oxide layer or a high-k dielectric layer (eg, Al 2 O 3 or HfO 2 ).

[0105] A vertical channel VC may be conformally formed on the charge storage structure 240, and a dummy vertical channel DVC may be conformally formed on the dummy charge storage structure D240. The vertical channel VC may cover the top surface of the semiconductor pillar PI exposed by the charge storage structure 240, and the dummy vertical channel DVC may cover the top surface of the dummy semiconductor pillar DPI exposed by the dummy charge storage structure D240. The vertical channel VC and the dummy vertical channel DVC may be, for example, one of a polysilicon layer, an organic semiconductor layer, and a carbon nanostructure. The vertical channel VC and the dummy vertical channel DVC may be formed by using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0106] The channel hole CH may be filled with a gap filling layer 250, and the dummy channel hole DCH may be filled with a dummy gap filling layer D250. For example, the gap filling layer 250 may fill the inner space surrounded by the vertical channel VC, and the dummy gap filling layer D250 may fill the inner space surrounded by the dummy vertical channel DVC. SOG (i.e., silicon on glass) technology may be used to form the gap filling layer 250 and the dummy gap filling layer D250. The gap filling layer 250 and the dummy gap filling layer D250 may include a dielectric material (e.g., a silicon oxide layer). A pad 260 may be formed on the upper portion of the vertical channel VC, and a dummy pad D260 may be formed on the upper portion of the dummy vertical channel DVC. The pad 260 and the dummy pad D260 may be formed in the following manner: a recessed area is formed by etching the upper portion of the gap filling layer 250 and by etching the upper portion of the dummy gap filling layer D250, and then the recessed area is filled with a conductive material. Alternatively, the pad 260 and the dummy pad D260 may be formed by doping upper portions of the vertical channel VC and the dummy vertical channel DVC with impurities having a conductivity type different from that of the vertical channel VC and the dummy vertical channel DVC.

[0107] refer to Fig.24A and Fig. 24B , the mold structure MS may be anisotropically etched to form a common source trench CTH. The formation of the common source trench CTH may include: forming a first interlayer dielectric layer 310 on the mold structure MS; and then patterning the mold structure MS and the buffer dielectric layer 50 using the first interlayer dielectric layer 310 as an etching mask until the top surface of the substrate 100 is exposed. The common source trench CTH may be formed to be in the first direction (see Figure 2 Then, the common source trench CTH may have a linear or rectangular shape extending in the first direction X. The formation of the common source trench CTH may be formed on the top surface of the substrate 100 in the second direction (see Figure 2 The stacked structures ST may be spaced apart from each other on the buffer dielectric layer 50. Each stacked structure ST may include a sacrificial pattern 610a and a dielectric pattern 110. The sacrificial pattern 610a and the dielectric pattern 110 may be alternately and repeatedly stacked on the buffer dielectric layer 50. The stacked structure ST may have its sidewalls exposed to the common source trench CTH.

[0108] Reference Fig.25A and Fig.25B, the sacrificial pattern 610a exposed to the common source trench CTH may be removed to form a recessed region RR. The sacrificial pattern 610a may be removed by performing a wet etching process and / or an isotropic dry etching process. The recessed region RR may be formed between dielectric patterns 110 vertically adjacent to each other and between the buffer dielectric layer 50 and the lowermost dielectric pattern 110. The etching process may use an etchant including phosphoric acid.

[0109] The recessed region RR may extend horizontally from the common source trench CTH into the gap between the dielectric patterns 110. The recessed region RR may expose the top and bottom surfaces of the dielectric pattern 110, a portion of the sidewall of the charge storage structure 240, a portion of the sidewall of the dummy charge storage structure D240, a portion of the sidewall of the semiconductor pillar PI, and a portion of the sidewall of the dummy semiconductor pillar DPI. The recessed region RR may also expose the protrusion PS of the charge storage structure 240 and the dummy protrusion DPS of the dummy charge storage structure D240.

[0110] A gate dielectric layer 60 may be formed on the exposed sidewalls of the semiconductor pillars PI, and a dummy gate dielectric layer D60 may be formed on the exposed sidewalls of the dummy semiconductor pillars DPI. The gate dielectric layer 60 and the dummy gate dielectric layer D60 may be formed by performing an oxidation process on the sidewalls of the semiconductor pillars PI and the sidewalls of the dummy semiconductor pillars DPI. The gate dielectric layer 60 and the dummy gate dielectric layer D60 may include, for example, a thermal oxide layer or a silicon oxide layer.

[0111] Reference Fig.26A , Fig.26B and Figure 5 , a horizontal dielectric layer 170 may be formed in the recessed region RR (see Figure 5 ). For example, the horizontal dielectric layer 170 may conformally cover the surface of the dielectric pattern 110, the sidewalls of the charge storage structure 240, the sidewalls of the dummy charge storage structure D240, the sidewalls of the gate dielectric layer 60, the sidewalls of the dummy gate dielectric layer D60, and the sidewalls of the first interlayer dielectric layer 310, wherein the surface and the sidewalls are exposed to the recessed region RR. The horizontal dielectric layer 170 may be formed by using a deposition process having excellent step coverage. For example, the horizontal dielectric layer 170 may be formed by using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0112] The gate electrodes 120a, 120b, and 120c may be formed in the recessed region RR. The formation of the gate electrodes 120a, 120b, and 120c may include: forming a metal layer to fill the common source trench CTH and the recessed region RR; and then removing the metal layer formed in the common source trench CTH. The gate electrodes 120a, 120b, and 120c may include, for example, doped silicon, a metal (e.g., tungsten), a metal nitride, a metal silicide, or a combination thereof.

[0113] Reference Fig.27A and Fig.27B , a common source region CSR may be formed in the substrate 100 exposed to the common source trench CTH. An ion implantation process may be performed to form the common source region CSR. The common source region CSR may have a conductivity type different from that of the substrate 100. A contact structure 340 may be formed in the common source trench CTH. The contact structure 340 may include a spacer 320 and a common source contact 330. The spacer 320 may cover the sidewalls of the common source trench CTH. The common source contact 330 may be formed to fill the remaining space of the common source trench CTH in which the spacer 320 is formed.

[0114] Return to reference Figure 3 and Figure 4 , a second interlayer dielectric layer 350 may be formed. The second interlayer dielectric layer 350 may cover the top surface of the first interlayer dielectric layer 310 and the contact structure 340. The second interlayer dielectric layer 350 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A cell contact plug 410 may be formed on the distal ends of the gate electrodes 120a, 120b, and 120c, wherein the distal ends are disposed on the pad region CR of the substrate 100. The cell contact plug 410 may include one or more of a metal (e.g., copper or tungsten) and a metal nitride (e.g., TiN, TaN, or WN). A channel contact plug 420 may be formed on the pad 260. The channel contact plug 420 may penetrate the first interlayer dielectric layer 310 and the second interlayer dielectric layer 350, and may directly contact the pad 260. The channel contact plug 420 may include one or more of a metal (eg, copper or tungsten) and a metal nitride (eg, TiN, TaN, or WN).

[0115] A connection line 430 may be formed on the second interlayer dielectric layer 350. The connection line 430 may be connected to the cell contact plug 410. A bit line BL may be formed on the second interlayer dielectric layer 350. The bit line BL may be electrically connected to the cell contact plug 410. Figure 2 A vertical channel VC is arranged on Y).

[0116] According to some example embodiments of the inventive concepts, it is possible to provide a three-dimensional semiconductor memory device having improved reliability.

[0117] This application claims the priority of Korean Patent Application No. 10-2019-0042159 filed on April 10, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor memory device, comprising: A stack structure comprising a plurality of gate structures and a plurality of first dielectric patterns alternately and repeatedly stacked on a substrate, the gate structure comprising a plurality of first gate structures, each of the first gate structures having a top surface and a bottom surface facing the top surface, and a width of the top surface is different from a width of the bottom surface; A vertical channel on the substrate penetrating the stacked structure; as well as a charge storage layer extending from between the vertical channel and the first gate structure to between the vertical channel and the first dielectric pattern, the charge storage layer comprising a first segment and a third segment between the vertical channel and each of the plurality of first gate structures and a second segment between the vertical channel and the first dielectric pattern, wherein the thickness of the first segment is greater than the thickness of the second segment and the thickness of the third segment, and One of the width of the top surface and the width of the bottom surface of each first gate structure among the plurality of first gate structures is the same as a width of a first dielectric pattern on the top surface of the first gate structure among the plurality of first dielectric patterns.

2. The three-dimensional semiconductor memory device according to claim 1, wherein: Each of the plurality of first gate structures comprises: a first grid portion; and a second gate portion between the first gate portion and the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns, The width of the second gate portion decreases as approaching the first dielectric pattern from the first gate portion.

3. The three-dimensional semiconductor memory device according to claim 1, wherein: The width of the top surface of each first gate structure among the plurality of first gate structures is smaller than the width of the bottom surface of the first gate structure, and The width of the top surface of each first gate structure among the plurality of first gate structures is smaller than a width of a top surface of the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

4. The three-dimensional semiconductor memory device according to claim 1, wherein: The gate structure further includes a second gate structure, wherein the first gate structure and the second gate structure form a single cell string, The first gate structure is a cell gate structure of the single cell string, and The second gate structure is a string selection gate structure of the single cell string.

5. The three-dimensional semiconductor memory device according to claim 1, wherein: each of the plurality of first gate structures comprises a first gate portion and a second gate portion between the first gate portion and the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns, At each first gate structure among the plurality of first gate structures, the charge storage layer has a recess recessed from a sidewall of the charge storage layer, and The recess is located at a level from a top surface of the substrate, the level being between a level of the first dielectric pattern on the first gate structure and a level of the first gate portion.

6. The three-dimensional semiconductor memory device according to claim 1, further comprising: a tunnel dielectric layer between the charge storage layer and the vertical channel; as well as a blocking dielectric layer between the charge storage layer and the first gate structure, Wherein at each first gate structure among the plurality of first gate structures, The blocking dielectric layer has a first cavity recessed from a sidewall of the blocking dielectric layer, The charge storage layer has a second cavity recessed from a sidewall of the charge storage layer, The charge storage layer is in the first cavity, and The tunnel dielectric layer is spaced apart from the second cavity. 7 . The three-dimensional semiconductor memory device according to claim 6 , further comprising a capping pattern between the charge storage layer and the tunnel dielectric layer for each first gate structure among the plurality of first gate structures, the capping pattern being in the second cavity.

8. The three-dimensional semiconductor memory device according to claim 1, wherein The substrate includes a cell array region and a pad region, The stack structure extends from the cell array region to the pad region, and The three-dimensional semiconductor memory device further includes a first dummy vertical structure and a second dummy vertical structure penetrating the stacked structure on the pad region of the substrate, wherein The first dummy vertical structure has a first protrusion protruding from a sidewall of the first dummy vertical structure, The second dummy vertical structure has a second protrusion protruding from a sidewall of the second dummy vertical structure, and The first protrusion of the first dummy vertical structure and the second protrusion of the second dummy vertical structure are in contact with the first gate structure.

9. The three-dimensional semiconductor memory device according to claim 8, wherein: The first protrusion of the first dummy vertical structure contacts the second protrusion of the second dummy vertical structure.

10. The three-dimensional semiconductor memory device according to claim 8, further comprising: each air gap between the first protrusion of the first dummy vertical structure and the second protrusion of the second dummy vertical structure, Wherein, the air gap is interposed between the first dielectric pattern and the first gate structure.

11. The three-dimensional semiconductor memory device according to claim 1, wherein: The plurality of first gate structures are adjacent to each other in a direction perpendicular to a top surface of the substrate.

12. The three-dimensional semiconductor memory device according to claim 1, wherein The charge storage layer surrounds the vertical channel, The gate structure surrounds the charge storage layer, and The shape of the first gate structure is the same on opposite sides of the vertical channel, wherein the width of the top surface of the first gate structure is different from the width of the bottom surface.

13. A three-dimensional semiconductor memory device, comprising: A stack structure comprising a plurality of gate structures and a plurality of first dielectric patterns alternately and repeatedly stacked on a substrate, the gate structure comprising a plurality of first gate structures, each of the first gate structures having a top surface and a bottom surface facing the top surface, and a width of the top surface being different from a width of the bottom surface; a vertical channel on the substrate penetrating the stacked structure; as well as a charge storage structure extending from between the vertical channel and the first gate structure to between the vertical channel and the first dielectric pattern, the charge storage structure comprising a first charge storage segment and a third charge storage segment between the vertical channel and each of the plurality of first gate structures and a second charge storage segment between the vertical channel and the first dielectric pattern, wherein the thickness of the first charge storage segment is greater than the thickness of the second charge storage segment and the thickness of the third charge storage segment, and One of the width of the top surface and the width of the bottom surface of each first gate structure among the plurality of first gate structures is the same as a width of a first dielectric pattern on the top surface of the first gate structure among the plurality of first dielectric patterns.

14. The three-dimensional semiconductor memory device according to claim 13, wherein: The charge storage structure covers a horizontal surface of the first dielectric pattern, the horizontal surface being exposed at a region where the first dielectric pattern is spaced apart from the first gate structure.

15. The three-dimensional semiconductor memory device according to claim 13, wherein: The width of the top surface of each first gate structure among the plurality of first gate structures is smaller than the width of the bottom surface of the first gate structure, and The width of the top surface of each first gate structure among the plurality of first gate structures is smaller than a width of a top surface of the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

16. The three-dimensional semiconductor memory device according to claim 13, wherein: The width of the bottom surface of each first gate structure among the plurality of first gate structures is smaller than the width of the top surface of the first gate structure, and The width of the bottom surface of each first gate structure among the plurality of first gate structures is smaller than a width of a bottom surface of the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

17. The three-dimensional semiconductor memory device according to claim 13, wherein: Each of the plurality of first gate structures includes a first portion and a second portion, the second portion being between the first portion and the first dielectric pattern on the first gate structure among the plurality of first dielectric patterns, At each first gate structure among the plurality of first gate structures, the charge storage structure has a recess recessed from a sidewall of the charge storage structure, and The recess is located at a level from a top surface of the substrate, and the level is between a level of the first dielectric pattern on the first gate structure and a level of the first portion.

18. A three-dimensional semiconductor memory device, comprising: A stacked structure, comprising a plurality of gate structures and dielectric patterns alternately and repeatedly stacked on a substrate, the gate structure comprising a plurality of first gate structures, each of the first gate structures having a top surface and a bottom surface facing the top surface, the width of the top surface being different from the width of the bottom surface, and the dielectric pattern comprising a plurality of first dielectric patterns adjacent to the plurality of first gate structures; as well as a vertical channel structure penetrating the stack structure, the vertical channel structure extending onto a first sidewall of the first gate structure and onto a first sidewall of the first dielectric pattern, wherein the vertical channel structure has a protrusion protruding from a sidewall of the vertical channel structure, The first sidewall of each of the first gate structures includes a first recessed region, The protrusion is in the first recessed area, and One of the width of the top surface and the width of the bottom surface of each first gate structure among the plurality of first gate structures is the same as a width of a first dielectric pattern on the first gate structure among the plurality of first dielectric patterns.

19. The three-dimensional semiconductor memory device according to claim 18, wherein: The protrusion covers a portion of a bottom surface of the first dielectric pattern, the portion of the bottom surface being exposed to a region where the first dielectric pattern is spaced apart from the first gate structure, and The portion of the bottom surface has an obtuse angle with respect to the first sidewall of the first dielectric pattern.

20. The three-dimensional semiconductor memory device according to claim 18, wherein: The substrate includes a cell array region and a pad region, The vertical channel structure is on the cell array region of the substrate, and The three-dimensional semiconductor memory device further includes a dummy vertical channel structure penetrating the stacked structure on the pad region of the substrate. wherein the dummy vertical channel structure extends onto the second sidewall of the first gate structure and onto the second sidewall of the first dielectric pattern, Each of the second sidewalls of the first gate structure includes a second recessed region, The dummy vertical channel structure has a dummy protrusion protruding from a sidewall of the dummy vertical channel structure, and The dummy protrusion is in the second recessed area.

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