Semiconductor storage device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor memory device and a method for manufacturing the same, which includes a substrate; a plurality of buried word lines; and a plurality of storage node plugs. The substrate includes a plurality of active regions and shallow trench isolations. The buried word lines are buried in the substrate, passing through the shallow trench isolation or the active region. The storage node plugs are arranged on the substrate and contact the active region. The storage node plugs include a plurality of first plugs, each including an insulating material and a conductive material stacked in sequence from bottom to top. At least one active region of the semiconductor memory device contacts two first plugs at the same time; alternatively, the semiconductor memory device further includes a storage node pad, which physically contacts at least two first plugs. Therefore, the present invention is conducive to forming a semiconductor memory device with better component reliability.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor storage device and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. A DRAM cell with a recessed gate structure can achieve a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage in the capacitor structure. Therefore, under the current mainstream development trend, it has gradually replaced DRAM cells with only a planar gate structure. Generally speaking, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage device to receive voltage signals from the bit line and word line. However, due to the limitations of process technology, existing DRAM cells with a recessed gate structure still have many defects and need further improvement to effectively enhance the performance and reliability of the related memory devices. Summary of the Invention

[0003] One object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, wherein a plurality of storage node plugs are simultaneously disposed within a dense region of the semiconductor memory device and a plurality of dummy storage node plugs are disposed within an iso region of the semiconductor memory device. This allows for maintaining the same light flux in both regions during the photolithography process, thereby improving the manufacturing yield of the semiconductor memory device. In this manner, the dummy storage node plugs can be formed without adding additional steps, effectively alleviating structural defects that may arise from the aforementioned problems and resulting in a semiconductor memory device with improved component reliability.

[0004] To achieve the above-mentioned objectives, one embodiment of the present invention provides a semiconductor memory device comprising a substrate; a plurality of buried word lines; a plurality of storage node plugs; and a plurality of storage node pads. The substrate comprises a plurality of active regions and shallow trench isolations, wherein the shallow trench isolations surround the active regions. The buried word lines are buried in the substrate, respectively located on the shallow trench isolations or the active regions. The storage node plugs are disposed on the substrate and contact the active regions, and the storage node plugs comprise a plurality of first plugs, wherein each of the first plugs comprises an insulating material and a conductive material stacked sequentially from bottom to top. The storage node pads are disposed on the storage node plugs, and one of the storage node pads physically contacts at least two of the first plugs simultaneously.

[0005] To achieve the above objectives, another embodiment of the present invention provides a semiconductor memory device comprising a substrate; a plurality of buried word lines; and a plurality of storage node plugs. The substrate comprises a plurality of active regions and shallow trench isolations, wherein the shallow trench isolations surround the active regions. The buried word lines are buried in the substrate, respectively located on the shallow trench isolations or the active regions. The storage node plugs are disposed on the substrate and contact the active regions. The storage node plugs comprise a plurality of first plugs, wherein each first plug comprises an insulating material and a conductive material stacked sequentially from bottom to top, and at least one active region simultaneously contacts two first plugs.

[0006] To achieve the above-mentioned purpose, another embodiment of the present invention provides a method for manufacturing a semiconductor memory device, which includes the following steps. First, a substrate is provided, wherein the substrate includes a plurality of active areas and shallow trench isolations, and the shallow trench isolations surround the active areas. Next, a plurality of buried word lines are formed in the substrate, buried in the substrate, and respectively located on the shallow trench isolations or the active areas. Then, a plurality of storage node plugs are formed on the substrate and contact the active areas, wherein the storage node plugs include a plurality of first plugs, wherein each of the first plugs includes an insulating material and a conductive material stacked in sequence from bottom to top. Then, a plurality of storage node pads are formed on the storage node plugs, wherein one of the storage node pads physically contacts at least two of the first plugs at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 8 A schematic diagram illustrating a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention is shown;

[0008] Figure 1 is a schematic cross-sectional view of the semiconductor memory device of the present invention after forming an insulating layer;

[0009] Figure 2 is a cross-sectional schematic diagram of the semiconductor memory device of the present invention after the etching process;

[0010] Figure 3 is a schematic cross-sectional view of the semiconductor memory device of the present invention after forming insulating sidewalls;

[0011] Figure 4 is a cross-sectional schematic diagram of the semiconductor memory device of the present invention after the epitaxial growth process;

[0012] Figure 5 is a schematic cross-sectional view of the semiconductor storage device of the present invention after a mask layer is formed;

[0013] Figure 6 is a cross-sectional schematic diagram of the semiconductor storage device of the present invention after forming a storage node pad;

[0014] Figure 7 is a schematic cross-sectional view of the semiconductor memory device of the present invention after forming an insulating material layer; and

[0015] Figure 8 It is a cross-sectional schematic diagram of the semiconductor memory device of the present invention after the etching back process is performed.

[0016] Figure 9 FIG. 4 is a schematic diagram illustrating a manufacturing process of a semiconductor memory device according to a second embodiment of the present invention.

[0017] Figure 10 FIG. 4 is a schematic diagram illustrating a manufacturing process of a semiconductor memory device according to a third embodiment of the present invention.

[0018] The description of the accompanying drawings is as follows:

[0019] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into and become a part of this specification. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and are provided for illustration and drawing convenience only. Relative dimensions and proportions are subject to change based on actual conditions. The same symbols in different embodiments represent corresponding or similar features.

[0020] 100, 300, 400 semiconductor storage devices

[0021] 110 substrate

[0022] 110A Storage Area

[0023] 110B surrounding areas

[0024] 120 Shallow Trench Isolation

[0025] 130, 131, 133 active areas

[0026] 140 Gate structure

[0027] 141 Ditch

[0028] 142 dielectric layer

[0029] 143 Gate dielectric layer

[0030] 144 gate

[0031] 145 cap layer

[0032] 147 dielectric layer

[0033] 150 Insulation layer

[0034] 150a, 350a etched surface

[0035] 151, 153, 155 openings

[0036] 152, 154 openings

[0037] 161, 163, 165 Insulation sidewalls

[0038] 170 mask layer

[0039] 181 epitaxial layer

[0040] 190 conductive material layer

[0041] 191, 192 conductive layer

[0042] 193, 195 conductive pads

[0043] 200 mask layer

[0044] 201, 203 mask pattern

[0045] 213, 313 First plug

[0046] 215, 415 Second plug

[0047] 211 Third Plug

[0048] 220 insulation material layer

[0049] 221, 223 insulation layer

[0050] 310 air gap

[0051] 310a top surface

[0052] 492 conductive layer

[0053] P1 first spacing

[0054] P2 Second spacing

[0055] P3 third spacing DETAILED DESCRIPTION

[0056] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present invention.

[0057] Please refer to Figures 1 to 8 , which is a schematic diagram of the manufacturing process of the semiconductor memory device 100 according to the first embodiment of the present invention. Figure 1As shown, the semiconductor memory device 100 includes, for example, a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate. The substrate 110 further includes a memory region 110A having a relatively high density of components and a peripheral region 110B having a relatively low density of components. Preferably, the peripheral region 110B is disposed on at least one side of the memory region 110A. For example, from a top view (not shown), the peripheral region 110B may entirely surround the outside of the memory region 110A, but the present invention is not limited thereto.

[0058] For example Figure 1 As shown, at least one shallow trench isolation (STI) 120 is formed in the substrate 110 to define a plurality of active areas 130 in the substrate 110. In this way, the shallow trench isolation 120 can be arranged around the active areas 130. The active areas 130 further include an active area 131 formed in the storage area 110A and an active area 133 formed in the peripheral area 110B and adjacent to the storage area 110A. Preferably, the active areas 131 and 133 have different extension lengths, and the active area 133 can have a relatively larger extension length, but the present invention is not limited thereto. In one embodiment, the shallow trench isolation 120 is formed by, for example, first forming a plurality of trenches (not shown) in the storage area 110A and the peripheral area 110B of the substrate 110 using an etching method, then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride, etc.), and forming the required shallow trench isolation 120 after a planarization process, but the present invention is not limited thereto.

[0059] Furthermore, a plurality of buried gate structures 140 are formed within the substrate 110. These structures include a dielectric layer 142, a gate dielectric layer 143, a gate 144, and a capping layer 145 stacked sequentially from bottom to top. The capping layer 145 of each gate structure 140 may have a surface flush with the top surface of the substrate 110, allowing each gate structure 140 to function as a buried wordline (WL) of the semiconductor memory device 100 to receive or transmit voltage signals from each memory cell (not shown). In one embodiment, the manufacturing method of the gate structure 140 includes but is not limited to the following steps: first, a plurality of trenches 141 are formed in the substrate 110, then, a dielectric layer 142 covering the entire surface of each trench 141, a gate dielectric layer 143 covering the lower half of each trench 141, and a gate 144 filling the lower half of each trench 141 are sequentially formed, and after etching back part of the gate 144 and the gate dielectric layer 143, a cap layer 145 filling the upper half of each trench 141 is formed, but the present invention is not limited thereto. It should be noted that the gate structures 140 formed in the memory region 110A are, for example, arranged in sequence according to the same first pitch P1 and are interleaved with the active region 131 and the shallow trench isolation 120 located in the memory region 110A. The gate structures 140 formed in the peripheral region 110B are arranged in sequence according to a relatively larger second pitch P2 (the second pitch P2 is larger than the first pitch P1) and are interleaved with the active region 133 and the shallow trench isolation 120 located in the peripheral region 110B.

[0060] Although the drawings of this embodiment do not specifically illustrate the specific extension directions of the active regions 130 (active regions 131 and 133) and gate structures 140, those skilled in the art will readily understand that, from a top view (not shown), the active regions 131 and 133 extend parallel to each other along a first direction (not shown) and are arranged in an array within the memory region 110A and the peripheral region 110B. The gate structures 140 extend parallel to each other along a second direction (not shown), passing through the active regions 131 and 133 and the shallow trench isolation 120 within the memory region 110A and the peripheral region 110B. The second direction, for example, intersects but is not perpendicular to the first direction. Furthermore, in one embodiment, the active region 133 may further include a first portion (not shown) extending along the second direction and a second portion (not shown) extending along a third direction (not shown) perpendicular to the second direction, forming an overall rectangular frame or other suitable shape surrounding the active region 131. In this way, the first portion and the second portion of the active area 133 can form a protection structure to prevent the active area 131 in the storage region 110A from structural collapse or damage.

[0061] Next, bit line contact plugs (BLC, not shown) are formed in the substrate 110. A plurality of bit lines (BL, not shown), a dielectric layer 147, and an insulating layer 150 filling the spaces between the bit lines are also formed on the substrate 110. The bit lines, for example, extend parallel to each other and spaced apart along the third direction, intersecting with the buried word lines (i.e., gate structures 140) and active areas 131 within the memory region 110A. The bit line contact plugs may be integrally formed with the bit lines and directly contact the active areas 131 to receive or transmit voltage signals from the memory cells. In one embodiment, each of the bit lines includes, for example, a semiconductor layer (e.g., including polysilicon, not shown), a barrier layer (e.g., including titanium and / or titanium nitride, not shown), a conductive layer (e.g., including a low-resistivity metal such as tungsten, aluminum, or copper), and a cap layer (e.g., including silicon oxide, silicon nitride, or silicon oxynitride, not shown) stacked in sequence. The dielectric layer 147 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO, not shown) structure, and the insulating layer 150 includes, for example, an insulating material such as silicon oxide or silicon oxynitride, but is not limited thereto.

[0062] like Figure 2 As shown, a mask layer (not shown) is formed on the insulating layer 150. An etching process, such as a dry etching process, is performed using the mask layer to form a plurality of openings 151, 153, and 155 that penetrate the insulating layer 150 and the dielectric layer 147. The openings 151, 153, and 155 are sequentially arranged, for example, at the same third pitch P3. Preferably, the third pitch P3 is equal to the first pitch P1 and smaller than the second pitch P2, but is not limited thereto. Specifically, because the openings 151 formed in the memory region 110A and the gate structures 140 have substantially the same spacing (the third pitch P3 is equal to the first pitch P1), each opening 151 in the memory region 110A can be precisely aligned with each gate structure 140 in the substrate 110, such that the capping layer 145 of the gate structure 140 is exposed through each opening 151.

[0063] On the other hand, since the gate structures 140 formed in the peripheral region 110B have a relatively large arrangement pitch (the second pitch P2), the openings 153 and 155 in the peripheral region 110B are not completely aligned with the gate structures 140 in the peripheral region 110B. For example, only a portion of the openings 153 can completely expose the capping layer 145 of the gate structure 140, while the remaining openings 153 and 155 can only expose a portion of the active region 133 surface, or a portion of the gate structure 140 surface, or the shallow trench isolation 120. In addition, since the material of the insulating layer 150 may have the same or a relatively smaller etching selectivity with the shallow trench isolation 120, and a relatively larger etching selectivity with the cap layer 145 of the gate structure 140, each opening 155 may further penetrate the surface of the shallow trench isolation 120 and extend into a portion of the shallow trench isolation 120, especially extending downward into the shallow trench isolation 120 in the peripheral area 110B, but each opening 151, 153 may stop at the surface of the cap layer 145 or the active area 133, as shown in FIG. Figure 2 In other words, the formation of each opening 155 is caused by over-etching in the etching process, and the etching degree of each opening 155 is different from each other, so that bottom surfaces with different heights can be formed.

[0064] like Figure 3 As shown, deposition and etch-back processes are sequentially performed on substrate 110 to form a plurality of insulating sidewalls 161, 163, and 165 that respectively fill openings 151, 153, and 155. These sidewalls are arranged, for example, along the third direction between the bit lines. The insulating sidewalls 161 formed in storage region 110A contact the capping layer 145 of each gate structure 140, while the insulating sidewalls 163 and 165 formed in peripheral region 110B may contact the surface of active region 133 or shallow trench isolation 120. It is worth noting that the present invention controls the parameters such as the size of the opening, the spacing between the openings, the etching time, and the position of the openings in the peripheral region 110B, so that each insulating sidewall 165 formed in the peripheral region 110B further extends into a portion of the shallow trench isolation 120, thereby increasing the aspect ratio of the opening and increasing the difficulty of etching the opening and backfilling the insulating material, so that the insulating sidewalls 165 have bottom surfaces of different heights, such as Figure 3 shown.

[0065] like Figure 4As shown, a mask layer 170 is formed on the insulating layer 150 and the insulating sidewalls 161, 163, and 165, covering the insulating layer 150 and the insulating sidewalls 163 and 165 in the peripheral region 110B. This completely exposes the insulating layer 150 and the insulating sidewalls 161 in the storage region 110A, and partially exposes the insulating sidewalls 163 adjacent to the storage region 110A and the insulating layer 150 on both sides thereof. An etching process, such as a wet etching process, is then performed with the mask layer 170 covering the insulating layer 150. This completely removes the insulating layer 150 and the dielectric layer 147 in the storage region 110A, forming a plurality of openings 152 to expose the surface of the active region 131. Simultaneously, the insulating layer 150 on both sides of the insulating sidewalls 163 adjacent to the storage region 110A is partially removed, forming a plurality of openings 154. Then, a selective epitaxial growth (SEG) process is performed again with the mask layer 170 covering the active region 131 to form a plurality of epitaxial layers 181 on the exposed surface of the active region 131. The mask layer 170 is then removed. In one embodiment, the epitaxial layers 181 include a conductive material such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), but the present invention is not limited thereto.

[0066] It should be noted that due to the difference in component concentration in the storage area 110A and the peripheral area 110B, the present invention can further control the size of the opening 154, the spacing and size of the insulating sidewalls 163 and 165, the etching time and other conditions to prevent incomplete etching from occurring in the peripheral area 110B adjacent to the storage area 110A due to the micro loading effect during the etching process. In this way, the insulating sidewalls 163 adjacent to the storage area 110A and the insulating layers 150 on both sides thereof can often only be partially removed, and the surface of the active area 133 below cannot be exposed, and an epitaxial layer cannot be formed in the selective epitaxial process. Moreover, due to the different etching degrees of the etching process, the remaining insulating layers 150 on both sides of the insulating sidewalls 163 may also have top surfaces of different heights, and at the same time form an uneven etched surface 150a, such as Figure 4 shown.

[0067] like Figure 5As shown, a deposition process is performed on substrate 110 to form a conductive material layer 190, which fills each opening 152, 154 and further covers the insulating sidewalls 161, 163, 165 and the top surface of insulating layer 150. In one embodiment, conductive material layer 190 includes, but is not limited to, a conductive material such as tungsten, titanium, aluminum, or copper. In one embodiment, a barrier layer (not shown) may be optionally formed before forming conductive material layer 190. The barrier layer may include, but is not limited to, materials such as titanium / titanium nitride (TiN) or tantalum (Ta) / tantalum nitride (TaN). Then, a mask layer 200 is formed on conductive material layer 190, including a plurality of mask patterns 201, 203. Specifically, the mask patterns 201 formed in the storage region 110A have relatively small widths and spacings and are aligned with the conductive material layer 190 filling each opening 152, while the mask patterns 203 formed in the peripheral region 110B have relatively large widths and spacings to mitigate the difference in pattern concentration between the storage region 110A and the peripheral region 110B, so that each mask pattern 203 can simultaneously cover the conductive material layer 190 filling all openings 154, or simultaneously cover more than one insulating sidewall 165 and the insulating layer 150 on both sides thereof, such as Figure 5 shown.

[0068] An etching process, such as a dry etching process, is performed with the aid of the mask layer 200 to pattern the conductive material layer 190 covering the insulating sidewalls 161, 163, 165 and the top surface of the insulating layer 150, exposing the insulating sidewalls 161, 163, 165 and the top surface of the insulating layer 150 below. The insulating sidewalls 161, 163, 165 and the insulating layer 150 exposed from the mask layer 200 are then removed, and finally, the mask layer 200 is removed. Figure 6 As shown, conductive layers 191 and 192 can be formed in the openings 152 and 154, respectively, and a plurality of conductive pads 193 and 195 can be formed above the conductive layers 191 and 192. It should be noted that the conductive layer 191 and the conductive pads 193 formed in the memory region 110A are sequentially stacked above the epitaxial layer 181. Since the conductive layer 191 and the epitaxial layer 181 both include conductive materials, they can together form a third plug 211. The third plug 211 has a top surface higher than the insulating sidewalls 161. It is in physical contact with the conductive pads 193 above it, and is located between the adjacent insulating sidewalls 161 and the buried word line (gate structure 140), and is in physical contact with the active region 131 below. Thus, the third plug 211 can be electrically connected to the transistor element (not shown) in the active region 131 through the epitaxial layer 181 thereunder, and electrically connected to the subsequently formed capacitor element (not shown) through the conductive pad 193 thereover.

[0069] On the other hand, each conductive layer 192 formed in the peripheral region 110B is stacked on the etched surface 150a of the insulating layer 150, and is composed of an insulating material (insulating layer 150) and a conductive material (conductive layer 192) stacked in sequence between adjacent insulating sidewalls 163 to form a first plug 213 to physically contact the active area 133 below. The first plug 213 has a top surface that is the same as or higher than the insulating sidewall 163, wherein part of the first plug 213 is not completely located between the adjacent buried word lines, and even partially overlaps the buried word line in the direction perpendicular to the substrate 110. In this way, not only can the first plug 213 not be electrically connected to the transistor element in the active area 133, but at least two first plugs 213 are in physical contact with the same conductive pad 195 at the same time, and can serve as a dummy plug. In this embodiment, all the first plugs 213 are physically connected to the same conductive pad 195 at the same time as an implementation mode, such as Figure 6 In addition, the remaining conductive pads 195 formed in the peripheral region 110B are simultaneously in physical contact with the plurality of insulating sidewalls 165 and / or the insulating layer 150 above the shallow trench isolation 120, so that the insulating layer 150 located above the shallow trench isolation 120 and between adjacent insulating sidewalls 165 can also form a plurality of second plugs 215. The second plugs 215 can serve as dummy plugs, such as Figure 6 shown.

[0070] like Figure 7 As shown, a deposition process is performed on the substrate 110 to form an insulating material layer 220, which conformally covers the top surfaces of the conductive pads 193 and 195, completely filling the space between the conductive pads 193, and partially filling the space between the conductive pads 195. In one embodiment, the insulating material layer 220 includes an insulating material such as silicon nitride or silicon carbonitride, and preferably includes the same insulating material as the insulating sidewalls 161, 163, and 165, but is not limited thereto.

[0071] Then, if Figure 8 As shown, an etch-back process is performed to remove the insulating material layer 220 covering the top surfaces of the conductive pads 193 and 195, thereby forming an insulating layer 221 between the conductive pads 193 and an insulating layer 223 between the conductive pads 195. The top surface of the insulating layer 221 formed in the storage region 110A can be flush with the top surfaces of the conductive pads 193 and 195 and directly contact the underlying insulating sidewalls 161. The top surface of the insulating layer 223 formed in the peripheral region 110B is not flush with the top surfaces of the conductive pads 195, but has a relatively lower, recessed top surface and can also directly contact the underlying insulating sidewalls 163 and 165. Thus, the semiconductor memory device 100 according to the first embodiment of the present invention is completed.

[0072] According to the first embodiment of the present invention, a semiconductor memory device 100 includes a buried wordline (i.e., gate structure 140) embedded in a substrate 110, and plugs 211, 213, 215 and insulating sidewalls 161, 163, 165 disposed on the substrate 110. The insulating sidewalls 161, 163, 165 and the plugs 211, 213, 215 are alternately disposed on the substrate 110. It should be noted that the plugs 211, 213, 215 serve as storage node contacts (SNCs) of the semiconductor memory device 100, physically contacting the underlying active regions 131, 133. The conductive pads 193, 195 serve as storage node pads (SN pads) of the semiconductor memory device 100, disposed on and connected to the storage node plugs, respectively. In detail, each third plug 211 is composed of an epitaxial layer 181 (including a conductive material) and a conductive layer 191 (including a conductive material) stacked in sequence to electrically connect the transistor component in the substrate 110, and further electrically connect to the capacitor component through the conductive pad 193 above it, thereby forming the smallest storage unit of the semiconductor memory device 100 to receive or transmit the required signal.

[0073] The first plug 213 is composed of an insulating layer 150 (including an insulating material) and a conductive layer 192 (including a conductive material) stacked in sequence, and the second plug 215 is completely composed of the insulating layer 150 (including an insulating material). Two or more first plugs 213 are in contact with the active area 133 and / or the storage node pad (conductive pad 195) at the same time, and the second plug 215 is in direct contact with the shallow trench isolation 120. Therefore, neither the first plug 213 nor the second plug 215 can be electrically connected to any of the transistor components and serves as a dummy plug. In other words, the manufacturing method of the present invention takes advantage of the manufacturing problems of micro-loading effect or incomplete etching that are easily generated during the etching manufacturing process due to the difference in component density between the storage region 110A and the peripheral region 110B of the semiconductor memory device 100, and more simply forms multiple dummy storage node plugs in the peripheral region 110B. In this way, the dummy storage node plugs can be formed without adding additional operation steps. At the same time, the manufacturing problems caused by the lower component density in the peripheral region 110B can be improved, thereby improving the manufacturing yield of the semiconductor memory device 100.

[0074] Furthermore, it should be noted that each insulating sidewall 161 is disposed above each gate structure 140. However, the gate structures 140 in the peripheral region 110B have a relatively large spacing (second spacing P2), so that the insulating sidewall 163 cannot be completely disposed above the gate structure 140, but can only be disposed on the active area 133, or can only partially overlap the underlying gate structure 140. This configuration improves the process tolerance or process window of the components in the peripheral region 110B. It also prevents negative impacts on the overall structure of the semiconductor memory device caused by micro-loading effects or etching defects caused by differences in component density during the manufacturing process of the components in the peripheral region 110B. This helps achieve more optimized structural integrity and device performance.

[0075] However, those skilled in the art will readily appreciate that, provided they meet actual product requirements, the semiconductor memory device and its fabrication process of the present invention may have other aspects or be achieved through other means, and are not limited to the aforementioned. The following further describes other embodiments or variations of the semiconductor memory device and its fabrication process of the present invention. To simplify the description, the following description primarily details the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with identical reference numerals to facilitate cross-reference between the various embodiments.

[0076] Please refer to Figure 9 FIG. 1 is a schematic diagram illustrating a method for fabricating a semiconductor memory device 300 according to a second embodiment of the present invention. The fabrication steps of the semiconductor memory device 300 according to this embodiment are substantially the same as those of the semiconductor memory device 100 according to the first embodiment, and are not described in detail herein. The main difference between this embodiment and the first embodiment is that, in this embodiment, after the epitaxial layer 181 is formed (as in the first embodiment), Figure 4 As shown in FIG. 1 ), another etching process, such as a wet etching process, is performed to further remove the insulating layer 150 adjacent to the storage region 110A to expose the underlying dielectric layer 147. Then, subsequent processes are performed in sequence, as in the first embodiment described above. Figures 5 to 8 Thus, the semiconductor memory device 300 according to the second embodiment of the present invention is completed.

[0077] It should be noted that, in this embodiment, due to the difference in the density of components in the storage area 110A and the peripheral area 110B, the deposition process of the conductive material layer 190 (as in the first embodiment) is performed. Figure 5As shown in FIG. 1 , the problem of incomplete hole filling may occur in the peripheral area 110B adjacent to the storage area 110A, thereby forming an air gap 310. The air gap 310 may have top surfaces of different heights, or even form an uneven top surface 310a, such as Figure 9 As shown. Thus, each conductive layer 192 formed in the peripheral region 110B is stacked on the air gap 310, and the sequentially stacked air gap 310 (comprising an insulating material) and conductive layer 192 (comprising a conductive material) together form a first plug 313. However, in another embodiment, a plug (not shown) comprising the sequentially stacked insulating layer 150, the air gap, and the conductive layer 192 may also be formed in the peripheral region 110B adjacent to the storage region 110A. In this embodiment, two or more first plugs 313 also simultaneously contact the active region 133 and / or the storage node pad (conductive pad 195), but are not electrically connected to any of the transistor devices, serving as dummy plugs. Thus, the fabrication method of the present invention can form dummy storage node plugs without adding additional steps. It can also alleviate various fabrication issues arising from the lower device density in the peripheral region 110B, thereby improving the fabrication yield of the semiconductor memory device 300.

[0078] Please refer to Figure 10 , which is a schematic diagram illustrating a method for manufacturing a semiconductor memory device 400 according to a third embodiment of the present invention. The steps for manufacturing the semiconductor memory device 400 in this embodiment are substantially the same as those for manufacturing the semiconductor memory device 100 in the first embodiment, and are not described in detail here. The main difference between this embodiment and the first embodiment is that in this embodiment, the etching process of the insulating layer 150 is performed by covering with another mask layer (not shown) (as in the first embodiment). Figure 4 As shown), the insulating layer 150 in the storage area 110A is completely removed, the insulating layer 150 on both sides of the insulating sidewall 163 is partially removed, and the insulating layer 150 on both sides of the insulating sidewall 165 is partially removed. Then, the subsequent manufacturing process is carried out in sequence, as in the first embodiment described above. Figures 5 to 8 As shown, the epitaxial layer 181 and other components are formed. Thus, the semiconductor memory device 400 according to the third embodiment of the present invention is completed.

[0079] It should be noted that in this embodiment, due to the difference in component density in the storage area 110A and the peripheral area 110B, and by controlling the opening size, the opening spacing, or the etching time, the insulating layer 150 is not completely etched, resulting in top surfaces of different heights and uneven etching surfaces 350a. Figure 10As shown. In this way, the conductive layers 492 subsequently formed in the peripheral region 110B are stacked on the etched surface 350a of the insulating layer 150, and the sequentially stacked insulating layer 150 (including insulating material) and the conductive layer 492 (including conductive material) together form a plurality of second plugs 415, which directly contact the shallow trench isolation 120 below. In addition, two or more second plugs 415 can also contact the storage node pad at the same time, and cannot be electrically connected to any component, and serve as dummy plugs, such as Figure 10 Thus, the manufacturing method of the present invention can also form dummy storage node plugs without adding additional operation steps, and can also improve various manufacturing problems derived from the low density of components in the peripheral area 110B, thereby improving the manufacturing yield of the semiconductor memory device 400.

[0080] In general, the semiconductor memory device of the present invention is to respectively set a plurality of storage node plugs and dummy storage node plugs in the dense area and the loose area where the difference in component density is relatively large, so that the same light flux can be maintained in each area during the photolithography manufacturing process, which is beneficial to improving the manufacturing yield of the semiconductor memory device. At the same time, the manufacturing process of the dummy storage node plug is to take advantage of the manufacturing problems such as micro-load effect or incomplete etching that are easily derived in the etching manufacturing process due to the difference in component density between the dense area and the loose area. In this way, the dummy storage node plug can be formed without adding additional operation steps. Therefore, the manufacturing method of the semiconductor memory device of the present invention can form a semiconductor memory device with better component reliability, so that it can achieve more optimized device performance.

[0081] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that include: A substrate, wherein the substrate includes a plurality of active areas isolated by shallow trenches; a plurality of buried word lines, buried in the substrate and passing through the shallow trench isolation or the active area; a plurality of insulating sidewalls, disposed on the substrate, with a portion of the insulating sidewalls being located directly above the buried word line; A plurality of storage node plugs are disposed on the substrate and contact the active region, wherein the storage node plugs include a plurality of first plugs, wherein each of the first plugs includes an insulating material and a conductive material stacked sequentially from bottom to top; as well as A plurality of storage node pads are disposed on the storage node plugs, and one of the storage node pads physically contacts at least two of the first plugs simultaneously.

2. The semiconductor memory device according to claim 1, wherein The first plug partially overlaps the buried word line in a direction perpendicular to the substrate.

3. The semiconductor memory device according to claim 1, wherein The insulating material includes silicon oxide or air.

4. The semiconductor memory device according to claim 1, wherein The insulating material disposed in the first plug has top surfaces with different heights.

5. The semiconductor memory device according to claim 1, wherein The insulating material in each of the first plugs has an uneven etched surface.

6. The semiconductor memory device according to claim 1, wherein The insulating sidewalls and the storage node plugs are alternately arranged.

7. The semiconductor memory device according to claim 6, wherein Part of the insulating sidewalls extends into part of the shallow trench isolation and has bottom surfaces of different heights.

8. The semiconductor memory device according to claim 6, wherein The insulating sidewalls are separated from each other and have the same third spacing. The buried word lines are separated from each other and have a first spacing and a second spacing. The third spacing is equal to the first spacing, and the second spacing is greater than the first spacing.

9. The semiconductor memory device according to claim 1, wherein The storage node plug further includes a plurality of second plugs, each of which includes an insulating material and a conductive material stacked sequentially from bottom to top and directly contacts the shallow trench isolation, wherein the insulating material in the second plug has top surfaces of different heights.

10. The semiconductor memory device according to claim 1, wherein At least one of the active regions contacts two of the first plugs simultaneously.

11. A semiconductor memory device, characterized in that include: A substrate, wherein the substrate includes a plurality of active areas isolated by shallow trenches; a plurality of buried word lines, buried in the substrate and passing through the shallow trench isolation or the active area; as well as a plurality of insulating sidewalls, disposed on the substrate, with a portion of the insulating sidewalls being located directly above the buried word line; A plurality of storage node plugs are arranged on the substrate and contact the active area. The storage node plugs include a plurality of first plugs, wherein each of the first plugs includes an insulating material and a conductive material stacked in sequence from bottom to top, and at least one of the active areas contacts two of the first plugs at the same time.

12. The semiconductor memory device according to claim 11, wherein The at least one active region is arranged circumferentially outside the remaining active regions.

13. The semiconductor memory device according to claim 11, wherein The storage node plug further includes a plurality of second plugs, each of which includes an insulating material and a conductive material stacked sequentially from bottom to top and directly contacts the shallow trench isolation, wherein the insulating material in the second plug has top surfaces of different heights.

14. The semiconductor memory device according to claim 11, wherein The first plug partially overlaps the buried word line in a direction perpendicular to the substrate.

15. The semiconductor memory device according to claim 11, wherein The insulating material in the first plug has top surfaces of different heights, and the insulating material includes silicon oxide or air.

16. The semiconductor memory device according to claim 11, wherein The insulating sidewalls and the storage node plugs are alternately arranged.

17. The semiconductor memory device according to claim 16, wherein The top surface of the insulating sidewall is flush with the top surface of the conductive material of each first plug.

18. The semiconductor memory device according to claim 16, wherein Part of the insulating sidewalls extends into part of the shallow trench isolation and has bottom surfaces of different heights.

19. A method for manufacturing a semiconductor memory device, characterized in that include: Providing a substrate, wherein the substrate includes a plurality of active areas and shallow trench isolations, wherein the shallow trench isolations surround the active areas; forming a plurality of buried word lines in the substrate, the buried word lines being buried in the substrate and respectively located on the shallow trench isolation or the active area; forming a plurality of insulating sidewalls on the substrate, wherein a portion of the insulating sidewalls is located directly above the buried word line; forming a plurality of storage node plugs on the substrate and contacting the active region, wherein the storage node plugs include a plurality of first plugs, wherein each of the first plugs includes an insulating material and a conductive material stacked sequentially from bottom to top; as well as A plurality of storage node pads are formed on the storage node plugs, wherein one of the storage node pads physically contacts at least two of the first plugs simultaneously.

20. The method for manufacturing a semiconductor memory device according to claim 19, wherein The storage node plug further includes a plurality of second plugs. Each of the second plugs includes an insulating material and a conductive material stacked in sequence from bottom to top and directly contacts the shallow trench isolation.

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