Semiconductor storage device and state transition detection circuit and method for terminal resistor thereof

Abstract

The present disclosure provides a semiconductor memory device and a state transition detection circuit and method for its terminal resistor. The semiconductor memory device includes 1st to Mth input and output terminals for signals to be detected, and the state transition detection circuit includes: an i-th logic detection circuit for receiving a control logic signal of the i-th signal to be detected, performing a logical operation on the control logic signal of the terminal resistor of the i-th signal to be detected to generate an i-th detection result signal; a j-th detection mode control circuit, which is connected to the j-th input and output terminal of the signal to be detected and the i-th logic detection circuit, for receiving a mode detection control signal, and when the mode detection control signal is at a first level, outputting the i-th detection result signal through the j-th input and output terminal of the signal to be detected to determine the conversion state of the terminal resistor of the i-th signal to be detected; i and j are different. The time of the state switching of the terminal resistor can be accurately determined to the clock cycle level.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor memory device and a state transition detection circuit and method thereof for terminal resistors. Background Art

[0002] In related technologies, the on-die termination (ODT) state of the data signal (Data, DQ) changes during read / write operations and various command switching, triggering a dynamic ODT transition. This ODT transition, including the switching of the ODT termination resistance (represented in this disclosure as RTT, but not limited to this), is critical to high-speed signal quality and affects its integrity.

[0003] Existing methods for testing ODT state transitions on silicon wafers (chips after tapeout) have limitations and cannot accurately determine the timing of ODT state transitions to the clock cycle level. Therefore, how to test ODT state transitions on silicon wafers while ensuring high-speed performance is a pressing technical challenge.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure aims to provide a semiconductor memory device and a circuit and method for detecting a state transition of a terminal resistor thereof, which can accurately detect the timing of the state transition of the terminal resistor to the clock cycle level.

[0006] An embodiment of the present disclosure provides a state transition detection circuit for a terminal resistor in a semiconductor memory device, wherein the semiconductor memory device includes 1st to Mth input and output terminals for signals to be detected, and the state transition detection circuit includes: an i-th logic detection circuit, for receiving a control logic signal of the terminal resistor of the i-th signal to be detected, and performing a logical operation on the control logic signal of the terminal resistor of the i-th signal to be detected to generate an i-th detection result signal; a j-th detection mode control circuit, whose output end is connected to the j-th input and output terminal of the signal to be detected, and whose input end is connected to the output end of the i-th logic detection circuit, for receiving a mode detection control signal, and when the mode detection control signal is at a first level, outputting the i-th detection result signal through the j-th input and output terminal of the signal to be detected to determine the conversion state of the terminal resistor of the i-th signal to be detected; wherein M is an integer greater than 1, i and j are both integers greater than or equal to 1 and less than or equal to M, and i and j are different.

[0007] An embodiment of the present disclosure also provides a state transition detection method for a terminal resistor in a semiconductor storage device, wherein the semiconductor storage device includes 1st to Mth input and output terminals for signals to be detected, and the method includes: receiving a control logic signal of the terminal resistor of the i-th signal to be detected, performing a logical operation on the control logic signal of the terminal resistor of the i-th signal to be detected to generate an i-th detection result signal; receiving a mode detection control signal, and when the mode detection control signal is at a first level, outputting the i-th detection result signal through the j-th input and output terminal of the signal to be detected to determine the conversion state of the terminal resistor of the i-th signal to be detected; wherein M is an integer greater than 1, i and j are both integers greater than or equal to 1 and less than or equal to M, and i and j are different.

[0008] An embodiment of the present disclosure further provides a semiconductor memory device, comprising a state transition detection circuit for a terminal resistor in the semiconductor memory device according to any embodiment of the present disclosure.

[0009] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0011] Figure 1 The present invention is a schematic diagram of a state transition detection circuit for a terminal resistor in a semiconductor memory device according to an exemplary embodiment of the present invention.

[0012] Figure 2 FIG. 4 is a schematic diagram of the structure of a state transition detection circuit of a terminal resistor in a semiconductor memory device according to another exemplary embodiment of the present disclosure.

[0013] Figure 3 FIG. 1 is a schematic diagram of the structure of an i-th logic detection circuit according to an exemplary embodiment of the present disclosure.

[0014] Figure 4 FIG. 1 is a schematic diagram of the structure of a j-th detection mode control circuit according to an exemplary embodiment of the present disclosure.

[0015] Figure 5 1 is a schematic diagram of the structure of the first to eighth detection mode control circuits in the state transition detection circuit of the terminal resistor in the semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0016] Figure 6 FIG. 4 is a timing diagram of relevant signals in the fourth state detection logic unit in an exemplary embodiment of the present disclosure.

[0017] Figure 7 1 is a schematic diagram of state transition of selecting the output terminal resistances of the first to fourth signal-to-be-detected input and output terminals corresponding to the lower 4 bits of the signal-to-be-detected according to an exemplary embodiment of the present disclosure.

[0018] Figure 8 1 is a schematic diagram of state transition of output terminal resistances of the fifth to eighth signal-to-be-detected input and output terminals corresponding to the upper 4 bits of the signal-to-be-detected according to an exemplary embodiment of the present disclosure.

[0019] Figure 9 The present invention is a flowchart illustrating a method for detecting a state transition of a terminal resistor in a semiconductor memory device according to an exemplary embodiment of the present invention.

[0020] Figure 10 FIG. 1 is a schematic diagram of the structure of a semiconductor memory device in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The accompanying drawings are only schematic illustrations of the present disclosure. The same reference numerals in the drawings represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The state transition detection circuit of the terminal resistor in the semiconductor storage device provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0022] The semiconductor memory device in the embodiments of the present disclosure may be a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM). For example, the semiconductor memory device may be a dual data rate synchronous dynamic random access memory (DDR SDRAM) or a low power dual data rate synchronous dynamic random access memory (LPDDR SDRAM). For example, the semiconductor memory device may be DDR3, DDR4, DDR5, DDR6, etc. However, the present disclosure does not limit the form of the semiconductor memory device.

[0023] Figure 1 The following is a schematic diagram of the structure of a state transition detection circuit for a terminal resistor in a semiconductor memory device, according to an exemplary embodiment of the present disclosure. The semiconductor memory device may include first through Mth input and output terminals for signals to be detected. M is an integer greater than 1 and may be either an even or odd number. However, for ease of presentation, this disclosure assumes that M is an even number. For example, M may be 8 or 16. In the following embodiments, M = 8 is used as an example, but this disclosure is not limited thereto.

[0024] It is understood that the signal to be detected can be a high-speed signal in a semiconductor memory device. For example, the signal to be detected can be any one of a DQ, a data strobe signal (DQS), a data mask signal (DM), and a termination data strobe signal (TDQS). In the following embodiments, the signal to be detected is DQ for example, but the present disclosure is not limited to this. The M-bit signal to be detected can include the 1st to 8th signals to be detected, and DQ(i-1) can be used to represent the i-th signal to be detected (i is an integer greater than or equal to 1 and less than or equal to M. When M=8, i can be any integer between 1 and 8), but the present disclosure is not limited to this. Among them, the 1st to Mth signals to be detected can be signals transmitted by the 1st to Mth input and output terminals of the signal to be detected in the semiconductor memory device (such as the 1st to Mth data signals). For example, the i-th signal to be detected can refer to the signal transmitted by the i-th input and output terminal of the signal to be detected (such as the i-th data signal). The 1st to Mth input and output terminals for signals to be detected may be represented by DQ 0 to DQ 7, and correspondingly, the i-th input and output terminal for signals to be detected may be represented by DQ i, but the present disclosure is not limited to this representation.

[0025] In some possible implementations, a different termination resistor may be set for each bit of the signal to be detected in the semiconductor memory device. For example, a termination resistor ODT(i-1) is set for the i-th bit of the signal to be detected DQ(i-1), and a termination resistor ODT(j-1) is set for the j-th bit of the signal to be detected DQ(j-1), where j is an integer greater than or equal to 1 and less than or equal to M, and j is not equal to i.

[0026] It can be understood that the ODT in the DRAM can have four working states: ODT_WR (if ODT_WR is enabled, the RTT_WR resistor is used as ODT during write operations, regardless of the state of the ODT pin), ODT_Norm (if ODT_WR is not used and ODT_Norm is enabled, then when ODT is high, the RTT_Norm resistor is used as ODT), ODT_Park (after ODT_Park is enabled, when ODTdisable, ODT_WR and ODT_Norm are not effective, when ODT is low, the RTT_PARK resistor is used as ODT) and ODTdisable (that is, no ODT). The ODT in each working state may include multiple resistance RTTs. For example, the RTT value in the ODT_WR working state can include 80 ohms, 120 ohms, 240 ohms and high impedance. In the embodiment of the present disclosure, each resistance in each working state can be regarded as a state of the terminal resistor, and the state transition detection circuit of the terminal resistor in the embodiment of the present disclosure is used to detect the change of the resistance RTT at the bottom layer. Of course, each of the four working states can also be regarded as a state. Correspondingly, the state conversion detection circuit of the terminal resistor in the embodiment of the present disclosure is used to detect the switching between the four working states.

[0027] like Figure 1 As shown, the state transition detection circuit 10 of the terminal resistor in the semiconductor memory device may include: an i-th logic detection circuit 101 and a j-th detection mode control circuit 102 .

[0028] The i-th logic detection circuit 101 can be used to receive the control logic signal of the terminal resistor of the i-th signal to be detected (represented by ODT_C_i), perform logical operation on the control logic signal ODT_C_i of the terminal resistor of the i-th signal to be detected, and generate the i-th detection result signal DQ[i-1].

[0029] The j-th detection mode control circuit 102 has an output end that can be connected to the j-th signal to be detected input / output terminal DQ j-1, and an input end that can be connected to the output end of the i-th logic detection circuit 101. The j-th detection mode control circuit 102 can be used to receive a mode detection control signal (represented by TM_ODT_lowbytes_output). When the mode detection control signal TM_ODT_lowbytes_output is at a first level, the i-th detection result signal DQ[i-1] is output through the j-th signal to be detected input / output terminal DQ j-1 to determine the conversion state of the terminal resistance ODT(i-1) of the i-th signal to be detected.

[0030] In an embodiment of the present disclosure, when M is 8, the state transition detection circuit 10 of the terminal resistor may include the first logic detection circuit to the eighth logic detection circuit, and the first to eighth bit detection result signals (which can be respectively represented as DQ[0] to DQ[7]) can be obtained respectively through the first logic detection circuit to the eighth logic detection circuit. The state transition detection circuit 10 of the terminal resistor may also include the first to eighth detection mode control circuits, and the output ends of the first logic detection circuit to the eighth logic detection circuit are cross-connected with the input ends of the first to eighth detection mode control circuits (corresponding to i and j being any two different numbers between 1 and 8, for example, i is 1 and j is 5, and for another example, i is 1 and j is 2). In this way, the first bit detection result signal DQ[0] to the eighth bit detection result signal DQ[7] can be transmitted to different detection mode control circuits respectively.

[0031] For example, the output ends of the 1st to 4th logic detection circuits are respectively connected to the input ends of the 5th to 8th detection mode control circuits, and the output ends of the 5th to 8th logic detection circuits are respectively connected to the 1st to 4th detection mode control circuits, that is, the 5th to-be-detected signal input / output terminal DQ4 to the 8th to-be-detected signal input / output terminal DQ7 can be used to output the 1st-bit detection result signal DQ[0] to the 4th-bit detection result signal DQ[3], respectively, and the 1st to-be-detected signal input / output terminal DQ0 to the 4th to-be-detected signal input / output terminal DQ3 can be used to output the 5th-bit detection result signal DQ[4] to the 8th-bit detection result signal DQ[7], respectively.

[0032] For another example, the output ends of the first logic detection circuit, the third logic detection circuit, the fifth logic detection circuit, and the seventh logic detection circuit are respectively connected to the input ends of the second detection mode control circuit, the fourth detection mode control circuit, the sixth detection mode control circuit, and the eighth logic detection circuit, and the output ends of the second logic detection circuit, the fourth logic detection circuit, the sixth logic detection circuit, and the eighth logic detection circuit are respectively connected to the input ends of the first detection mode control circuit, the third detection mode control circuit, the fifth detection mode control circuit, and the seventh logic detection circuit, that is, the second to-be-detected signal input / output terminal DQ1, the fourth to-be-detected signal input / output terminal DQ3, the sixth to-be-detected signal input / output terminal DQ5, and the eighth to-be-detected signal input / output terminal DQ7 can be used to output the first-bit detection result signal DQ[0], the third-bit detection result signal DQ[2], the fifth-bit detection result signal DQ[4], and the seventh-bit detection result signal DQ[6], respectively, and the first to-be-detected signal input / output terminal DQ0, the third to-be-detected signal input / output terminal DQ 2. The fifth detection signal input / output terminal DQ4 and the seventh detection signal input / output terminal DQ6 can be used to output the second-bit detection result signal DQ[1], the fourth-bit detection result signal DQ[3], the sixth-bit detection result signal DQ[5] and the eighth-bit detection result signal DQ[7], respectively.

[0033] Here, the first level may be a level when the mode detection control signal TM_ODT_lowbytes_output is valid. For example, when the mode detection control signal TM_ODT_lowbytes_output is valid at a high level, the first level may refer to a logic high level "1". When the mode detection control signal TM_ODT_lowbytes_output is valid at a low level, the first level may refer to a logic low level "0".

[0034] It is understood that the j-th detection mode control circuit may include first to third input terminals, wherein the first input terminal may be a control input terminal for receiving the mode detection control signal TM_ODT_lowbytes_output, the second input terminal may be connected to the output terminal of the i-th logic detection circuit 101 for receiving the i-th detection result signal DQ[i-1], and the third input terminal may be connected to the j-th to-be-detected signal DQ(j-1). The output terminal of the j-th detection mode control circuit 102 may be connected to the j-th to-be-detected signal input / output terminal DQ j-1.

[0035] In some embodiments, the mode detection control signal TM_ODT_lowbytes_output can be used to control the jth detection mode control circuit 102 to select outputting the i-th detection result signal DQ[i-1] or the j-th detection signal DQ(j-1) through the j-th detection signal input / output terminal DQj-1.

[0036] In one possible embodiment, the control logic signal ODT_C_i of the terminal resistance of the i-th signal to be detected may include an n-bit i-th sub-control logic signal, where n is an integer greater than or equal to 1. The n-bit i-th sub-control logic signal can be used to control multiple state switching modes, for example, switching from 34 ohms in the ODT_Park working state to 40 ohms in the ODT_Norm working state. The following example uses the control logic signal of the terminal resistance of each signal to be detected including 4 sub-control logic signals (represented by ODTTR0, ODTTR1, ODTTR2 and ODTTR3, respectively), but the present disclosure is not limited to this.

[0037] Among them, the ODTTR0, ODTTR1, ODTTR2 and ODTTR3 sub-control logic signals are signals inherent in the semiconductor memory device for controlling the state change of the terminal resistance ODT (i-1) of the i-th signal to be detected. The specific state change combination of the ODTTR0, ODTTR1, ODTTR2 and ODTTR3 sub-control logic signals can indicate how the terminal resistance of the i-th signal to be detected switches from one state to another, for example, how to change from 34 ohms in the ODT_Park working state to 40 ohms in the ODT_Norm working state. In the embodiment of the present disclosure, the ODTTR0, ODTTR1, ODTTR2 and ODTTR3 sub-control logic signals can be obtained as input signals of the state transition detection circuit of the terminal resistance, and after a series of logic (for example, performing an OR operation on the n-bit state change sub-pulse signals generated by the ODTTR0, ODTTR1, ODTTR2 and ODTTR3 sub-control logic signals), it is output from the j-th signal to be detected input and output terminal.

[0038] In some embodiments of the present disclosure, a logical operation is performed on the control logic signal of the terminal resistance of the i-th signal to be detected to generate the i-th detection result signal. The same first logical operation may be performed on each i-th sub-control logic signal of the i-th sub-control logic signals ODTTR0, ODTTR1, ODTTR2 and ODTTR3, and then a second logical operation is performed on the first logical operation result of each control logic signal to obtain the second logical operation result, and finally the i-th detection result signal is generated through the second logical operation result.

[0039] In the disclosed embodiment, a control logic signal for the terminal resistance of the i-th signal to be detected is received by an i-th logic detection circuit, a logical operation is performed on the control logic signal for the terminal resistance of the i-th signal to be detected to generate an i-th detection result signal, a mode detection control signal is received by a j-th detection mode control circuit, and when the mode detection control signal is at a first level, the i-th detection result signal is output through the j-th signal to be detected input / output terminal to determine the conversion state of the terminal resistance of the i-th signal to be detected. Since the control logic signal for the i-th signal to be detected is the original control signal for controlling the selection of the terminal resistance value within the semiconductor memory device, it directly reflects the conversion logic of the terminal resistance of the i-th signal to be detected. Thus, the i-th detection result signal generated by the logical operation on the control logic signal of the i-th signal to be detected also reflects the conversion logic of the terminal resistance. At the same time, since the i-th detection result signal is output through the j-th signal to be detected input and output terminal, the conversion state of the terminal resistance of the i-th signal to be detected can be directly obtained through the j-th signal to be detected input and output terminal, and since the control logic signal of the terminal resistance of the i-th signal to be detected and the i-th detection result signal output from the j-th signal to be detected input and output terminal are both at the clock cycle level, the detection time of the state switching of the terminal resistance can be accurately achieved to the clock cycle level.

[0040] In the embodiments of the present disclosure, reference Figure 2 As shown, the state transition detection circuit 10 of the terminal resistor in the semiconductor memory device may further include a j-th logic detection circuit 103 and an i-th detection mode control circuit 104 .

[0041] The j-th logic detection circuit 103 can be used to receive the control logic signal of the terminal resistor of the j-th signal to be detected (denoted by ODT_C_j in this disclosure), and perform logical operation on the control logic signal ODT_C_j of the terminal resistor of the j-th signal to be detected to generate the j-th detection result signal DQ[j-1].

[0042] Here, the structure of the jth logic detection circuit 103 can be exactly the same as that of the ith logic detection circuit 101, and the only difference is that it receives control logic signals of terminal resistors of different bits of signals to be detected and generates corresponding detection result signals of different bits.

[0043] The jth detection mode control circuit 102 may be configured to output the jth to-be-detected signal DQ(j−1) through the jth to-be-detected signal input / output terminal DQ j−1 when the mode detection control signal TM_ODT_lowbytes_output is at the second level.

[0044] It can be understood that the second level may be opposite to the first level. When the first level represents a logic high level “1”, the second level represents a low level logic “0”, and vice versa.

[0045] The i-th detection mode control circuit 104 is connected to the i-th signal to be detected input / output terminal DQ i-1 and the j-th logic detection circuit 103. The i-th detection mode control circuit 104 can be configured to receive a mode detection control inverted signal (represented by TM_ODT_lowbytes_outputB). When the mode detection control inverted signal TM_ODT_lowbytes_outputB is at a first level, the j-th detection result signal DQ[j-1] is output through the i-th signal to be detected input / output terminal DQ i-1 to determine the conversion state of the terminal resistance of the j-th signal to be detected. When the mode detection control inverted signal TM_ODT_lowbytes_outputB is at a second level, the i-th signal to be detected DQ(i-1) is output through the i-th signal to be detected input / output terminal DQi-1.

[0046] The mode detection control inverted signal TM_ODT_lowbytes_outputB and the mode detection control signal TM_ODT_lowbytes_output are inverted signals of each other. For example, when the mode detection control signal TM_ODT_lowbytes_output is at the first level, the mode detection control inverted signal TM_ODT_lowbytes_outputB is at the second level, and vice versa.

[0047] In some embodiments of the present disclosure, similar to the j-th detection mode control circuit 102, the output end of the i-th detection mode control circuit 104 is connected to the i-th detection signal input and output terminal DQ i-1, and the input end of the i-th detection mode control circuit 104 is connected to the output end of the j-th logic detection circuit 103 to receive the j-th detection result signal DQ[j-1].

[0048] In the disclosed embodiment, a control logic signal of the terminal resistance of the j-th signal to be detected is received by the j-th logic detection circuit, a logical operation is performed on the control logic signal of the terminal resistance of the j-th signal to be detected to generate a j-th detection result signal, and a mode detection control inverting signal is received by the i-th detection mode control circuit. When the mode detection control inverting signal is at a first level, the j-th detection result signal is output through the i-th signal to be detected input / output terminal to determine the conversion state of the terminal resistance of the j-th signal to be detected, and when the mode detection control inverting signal is at a second level, the i-th signal to be detected is output through the i-th signal to be detected input / output terminal. Therefore, when the mode detection control inverting signal is at a first level, the conversion state of the terminal resistance of the j-th signal to be detected can be directly obtained through the i-th signal to be detected input / output terminal.

[0049] Figure 3 FIG. 1 is a schematic diagram showing the structure of the i-th logic detection circuit according to an exemplary embodiment of the present disclosure. Figure 3 As shown, the i-th logic detection circuit 101 may include an i-th state logic conversion circuit 31 and an i-th trigger 32 .

[0050] Among them, the i-th state logic conversion circuit 31 can be used to receive the control logic signal ODT_C_i of the terminal resistor of the i-th signal to be detected, perform logic conversion on the control logic signal ODT_C_i of the terminal resistor of the i-th signal to be detected, and output the i-th state change pulse signal (represented by change_pulse_i) to the i-th trigger 32.

[0051] The i-th flip-flop 32 may be configured to receive and generate an i-th detection result signal DQ[i-1] according to the i-th state change pulse signal change_pulse_i.

[0052] In the embodiment of the present disclosure, the control logic signal of the terminal resistance of the i-th signal to be detected is received and logically converted by the i-th state logic conversion circuit to output the i-th state change pulse signal to the i-th trigger. The i-th trigger receives and generates the i-th detection signal based on the i-th state change pulse signal. In this way, the obtained i-th detection signal can reflect the conversion logic of the terminal resistance of the i-th signal to be detected in real time, which is conducive to determining the conversion state of the terminal resistance of the i-th signal to be detected in real time according to the input and output terminals of the j-th signal to be detected.

[0053] In some embodiments of the present disclosure, reference Figure 3 As shown, the control logic signal ODT_C_i of the terminal resistor of the i-th signal to be detected may include the n-th i-th sub-control logic signal, and the i-th state logic conversion circuit 31 may include the k-th i-th state detection logic unit and the i-th superimposing unit 315 . Figure 3In the example, the control logic signal ODT_C_i for the terminal resistor of the i-th signal to be detected includes four i-th sub-control logic signals, that is, the i-th state logic conversion circuit 31 may include a first i-th state detection logic unit 311, a second i-th state detection logic unit 312, and a third i-th state detection logic unit 313 to a fourth i-th state detection logic unit 314. Here, n is an integer greater than or equal to 1, and k is an integer greater than or equal to 1 and less than or equal to n.

[0054] The kth i-th state detection logic unit may be configured to receive the kth i-th sub-control logic signal and generate the kth i-th state change sub-pulse signal according to the kth i-th sub-control logic signal.

[0055] The i-th superimposing unit 315 may be configured to superimpose the 1st to nth i-th state change sub-pulse signals to obtain the i-th state change pulse signal change_pulse_i.

[0056] In the embodiment of the present disclosure, the kth i-th sub-control logic signal is received by the kth i-th state detection logic unit, and the kth i-th state change sub-pulse signal is generated according to the kth i-th sub-control logic signal. The 1st to nth i-th state change sub-pulse signals are superimposed by the i-th superposition unit to obtain the i-th state change pulse signal. This is conducive to determining the i-th detection result signal based on the i-th state change pulse signal.

[0057] In some embodiments of the present disclosure, continue to refer to Figure 3 Taking n=4 as an example, the 4 i-th sub-control logic signals can be the 1-th i-th sub-control logic signal (corresponding to ODTTR0) to the 4-th i-th sub-control logic signal (corresponding to ODTTR3), and the k-th i-th state detection logic unit can be used to receive the k-th i-th sub-control logic signal, generate the k-th i-th state change sub-pulse signal including at least one pulse when the k-th i-th sub-control logic signal changes, and generate the k-th i-th state change sub-pulse signal not including a pulse when the k-th i-th sub-control logic signal does not change; k is any integer from 1 to 4.

[0058] It can be understood that each time the k-th i-th sub-control logic signal changes, the k-th i-th state detection logic unit will correspondingly generate a pulse.

[0059] The i-th superimposing unit 315 may be configured to superimpose the 1st to 4th i-th state change sub-pulse signals to obtain the i-th state change pulse signal change_pulse_i.

[0060] In the embodiment of the present disclosure, the kth i-th sub-control logic signal is received by the kth i-th state detection logic unit, and when the kth i-th sub-control logic signal changes, a kth i-th state change sub-pulse signal including at least one pulse is generated, and when the kth i-th sub-control logic signal does not change, a kth i-th state change sub-pulse signal not containing a pulse is generated. The i-th state change pulse signal is obtained by superimposing the 1st to 4th i-th state change sub-pulse signals. This is conducive to determining the i-th detection result signal based on the i-th state change pulse signal.

[0061] In some embodiments of the present disclosure, continue to refer to Figure 3 As shown, the k-th i-th state detection logic unit may include a plurality of buffers 316 and an XOR gate 317 .

[0062] The plurality of buffers 316 may be configured to delay the kth ith sub-control logic signal (eg, the 1st ith sub-control logic signal) to obtain a delayed kth ith sub-control logic signal.

[0063] The XOR gate 317 may be configured to receive and generate a kth i-th state change sub-pulse signal according to the kth i-th sub-control logic control signal and the delayed kth i-th sub-control logic control signal.

[0064] It can be understood that the components and structures of the 1st i-th state detection logic unit to the 4th i-th state detection logic unit can be the same.

[0065] In an embodiment of the present disclosure, the kth ith sub-control logic signal is delayed through multiple buffers to obtain the delayed kth ith sub-control logic signal, which is received through an XOR gate and generated according to the kth ith sub-control logic control signal and the delayed kth ith sub-control logic control signal. This can be used to obtain the ith state change pulse signal, which is conducive to determining the ith detection result signal based on the ith state change pulse signal.

[0066] In some embodiments of the present disclosure, the i-th superimposing unit 315 may include an OR gate circuit, which may be configured to receive and perform logical OR processing on the 1st i-th state change pulse change_pulse_i1 to the nth i-th state change pulse change_pulse_in to generate the i-th state change pulse signal change_pulse_i.

[0067] In some possible implementations, the OR gate circuit can be implemented as an OR gate with n input terminals or as an OR gate with n-1 two input terminals, which is not specifically limited here. For example, for an OR gate circuit when n=4, the OR gate circuit can be further described with reference to Figure 3, the OR gate circuit may include a first OR gate 3151 , a second OR gate 3152 and a third OR gate 3153 .

[0068] The first OR gate 3151 can be used to receive and generate a first OR output signal (denoted by change_pulse_io1) according to the first i-th state change sub-pulse signal (denoted by change_pulse_i1) and the second i-th state change sub-pulse signal (denoted by change_pulse_i2).

[0069] The second OR gate 3152 can be used to receive and generate a second OR output signal (denoted by change_pulse_io2) according to the 3rd i-th state change sub-pulse signal (denoted by change_pulse_i3) and the 4th i-th state change sub-pulse signal (denoted by change_pulse_i4).

[0070] The third OR gate 3153 may be configured to receive and generate an i-th state change pulse signal change_pulse_i according to the first OR output signal change_pulse_io1 and the second OR output signal change_pulse_io2 .

[0071] In the disclosed embodiments, an OR gate circuit can receive and perform a logical OR operation on the first i-th state transition pulse to the n-th i-th state transition pulse to generate an i-th state change pulse signal. Thus, an i-th state change pulse signal including pulses corresponding to all ODT state changes can be obtained. It should be noted that the disclosed embodiment does not limit the number of OR gates included in the OR gate circuit or the connection method of the OR gates; as long as the first i-th state transition pulse to the n-th i-th state transition pulse can be logically ORed, the signal can be used.

[0072] Figure 4 2 is a schematic diagram of the structure of the j-th detection mode control circuit and the i-th detection mode control circuit according to an exemplary embodiment of the present disclosure.

[0073] like Figure 4 As shown, the j-th detection mode control circuit 102 may include a first AND gate 1021 and a first selector 1022 .

[0074] The first AND gate 1021 can be used to receive and generate a first selection signal (represented by sel_1) having the same level as the mode detection control signal TM_ODT_lowbytes_output according to the terminal resistance conversion output enable signal TM_ODT_Transition_en and the mode detection control signal TM_ODT_lowbytes_output when the terminal resistance conversion output enable signal TM_ODT_Transition_en is at the first level.

[0075] It can be understood that both the terminal resistance conversion output enable signal TM_ODT_Transition_en and the mode detection control signal TM_ODT_lowbytes_output can be implemented through the test mode. Among them, the terminal resistance conversion output enable signal TM_ODT_Transition_en can be the main control signal (preferred signal) of the j-th detection mode control circuit 102, which can be used to enable (determine whether to turn on) the j-th detection mode control circuit 102 to transmit the conversion state of ODT. And it is a high-level active signal, that is, when it is at the first level (the first level by default), the j-th detection mode control circuit 102 is enabled or turned on, and the j-th detection mode control circuit 102 is determined according to the mode detection control signal TM_ODT_lowbytes_output to output the i-th detection result signal DQ[i-1] or the j-th signal to be detected (j-th data signal) DQ(j-1).

[0076] The first input terminal and the second input terminal of the first selector 1022 are respectively used to receive the j-th signal to be detected DQ(j-1) and the i-th detection result signal DQ[i-1], and its control terminal is connected to the output terminal of the first AND gate 1021 for receiving the first selection signal sel_1. Its output terminal is used to output the i-th detection result signal DQ[i-1] through the j-th signal to be detected input and output terminal DQ j-1 when the first selection signal sel_1 is the first level.

[0077] It can be understood that when the first selection signal sel_1 is at the second level, the output end of the first selector 1022 outputs the j-th detection signal DQ(j-1) through the j-th detection signal input and output terminal DQ j-1.

[0078] Continue to refer Figure 4As shown, the i-th detection mode control circuit 104 may include a second AND gate 1041 and a second selector 1042. The second AND gate 1041 can be used to receive the terminal resistance conversion output enable signal TM_ODT_Transition_en and the mode detection control inverted signal TM_ODT_lowbytes_outputB. When the terminal resistance conversion output enable signal TM_ODT_Transition_en is at a first level, a second selection signal (represented by sel_2) having the same level as the mode detection control inverted signal TM_ODT_lowbytes_outputB is generated.

[0079] The first input terminal and the second input terminal of the second selector 1042 are respectively used to receive the i-th signal to be detected DQ(i-1) and the j-th detection result signal DQ[j-1], and its control terminal is connected to the output terminal of the second AND gate 1041 for receiving the second selection signal sel_2. Its output terminal is used to output the j-th detection result signal DQ[j-1] through the i-th signal to be detected input and output terminal DQ i-1 when the second selection signal sel_2 is the first level.

[0080] It is understood that when the terminal resistance conversion output enable signal TM_ODT_Transition_en is at the first level, the first selection signal sel_1 and the second selection signal sel_2 are inverted signals. For example, if the mode detection control signal TM_ODT_lowbytes_output is at the first level, the mode detection control inverted signal TM_ODT_lowbytes_outputB is at the second level, the first selection signal is at the first level, and the second selection signal is at the second level.

[0081] In some embodiments of the present disclosure, a terminal resistance conversion output enable signal and a mode detection control signal are received by a first AND gate. When the terminal resistance conversion output enable signal is at a first level, a first selection signal having the same level as the mode detection control signal is generated. The j-th signal to be detected and the i-th detection result signal are respectively received by the first input terminal and the second input terminal of the first selector. The control terminal receives the first selection signal, and the output terminal outputs the i-th detection result signal through the j-th signal to be detected input and output terminal when the first selection signal is at the first level. The mode detection control signal TM_ODT_lowbytes_output is used to determine whether the j-th detection mode control circuit outputs the i-th detection result signal DQ[i-1] or the i-th detection mode control circuit outputs the j-th signal to be detected (j-th data signal) DQ(j-1). In this way, the terminal resistance conversion output enable signal and the mode detection control signal can be used to determine which terminals of the 1st to M-th signal to be detected input and output terminals are used to output the signal to be detected and which terminals are used to output the detection result signal.

[0082] In some possible implementations, assuming M=8, the state transition detection circuit of the terminal resistor in the semiconductor memory device may include the 1st logic detection circuit to the 8th logic detection circuit, and the 1st detection mode control circuit to the 8th detection mode control circuit. The circuit structures of the 1st detection mode control circuit to the 8th detection mode control circuit may be the same. Each detection mode control circuit may include an AND gate and a selector. Each AND gate (including 4 AND gates) in the 1st to the 4th detection mode control circuits may receive the mode detection control signal TM_ODT_lowbytes_output, and each AND gate (including 4 AND gates) in the 5th to the 8th detection mode control circuits may receive the mode detection control inverted signal TM_ODT_lowbytes_outputB. In this way, the 1st to the 4th detection mode control circuits may share the first AND gate 1021 (in other embodiments, each detection mode control circuit may have its own AND gate) to simultaneously control the outputs of the 1st to-be-detected signal input / output terminal DQ 0 to the 4th to-be-detected signal input / output terminal DQ 3 through the first selection signal sel_1. The fifth to eighth detection mode control circuits may share the second AND gate to simultaneously control the outputs of the fifth to eighth to-be-detected signal input / output terminals DQ4 to DQ7 through the second selection signal sel_2.

[0083] Figure 5 1 is a schematic diagram of the structure of the first to eighth detection mode control circuits in the state transition detection circuit of the terminal resistor in the semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0084] like Figure 5As shown, the first to fourth detection mode control circuits in the first to eighth detection mode control circuits 50 (corresponding to j=1, 2, 3 and 4 respectively) share the first AND gate 501 (which can be used as the first AND gate 1021 mentioned above), and respectively include a first data selector 502 (the first selector 1022 when j=1), a second data selector 503 (the first selector 1022 when j=2), a third data selector 504 (the first selector 1022 when j=3) and a fourth data selector 505 (the first selector 1022 when j=4). 1022), the 5th to 8th detection mode control circuits (corresponding to i=5, 6, 7 and 8 respectively) share the second AND gate 511 (which can be used as the above-mentioned second AND gate 2041), and respectively include the 5th data selector 512 (the second selector 1042 when i=5), the 6th data selector 513 (the second selector 1042 when i=6), the 7th data selector 514 (the second selector 1042 when i=7), the 8th data selector 515 (the second selector 1042 when i=8) and the inverter 516.

[0085] The first input terminal 5011 and the second input terminal 5012 of the first AND gate 501 can respectively receive the terminal resistance conversion output enable signal TM_ODT_Transition_en and the mode detection control signal TM_ODT_lowbytes_output, and the output terminal is used to output the first selection signal sel_1.

[0086] The control terminals of the first data selector 502 , the second data selector 503 , the third data selector 504 and the fourth data selector 505 are all connected to the output terminal of the first AND gate 501 for receiving the first selection signal sel_1 .

[0087] The first input terminal and the second input terminal of the first data selector 502 are respectively used to receive the first-bit signal to be detected DQ(0) (obtained through the original channel of the first-bit signal to be detected DQ(0)) and the fifth-bit detection result signal DQ[4] (connected to the output terminal of the fifth logic detection circuit to obtain the conversion state of the ODT of the fifth-bit signal to be detected DQ(4)), and the output terminal is connected to the first-bit signal to be detected input and output terminal DQ 0.

[0088] The first input terminal and the second input terminal of the second data selector 503 are respectively used to receive the second-bit signal to be detected DQ(1) (obtained through the original channel of the second-bit signal to be detected DQ(1)) and the sixth-bit detection result signal DQ[5] (connected to the output terminal of the sixth logic detection circuit to obtain the conversion state of the ODT of the sixth-bit signal to be detected DQ(5)), and the output terminal is connected to the second-bit signal to be detected input and output terminal DQ 1.

[0089] The first input terminal and the second input terminal of the third data selector 504 are respectively used to receive the third-bit signal to be detected DQ(2) (obtained through the original channel of the third-bit signal to be detected DQ(2)) and the seventh-bit detection result signal DQ[6] (connected to the output terminal of the seventh logic detection circuit to obtain the conversion state of the ODT of the seventh-bit signal to be detected DQ(6)), and the output terminal is connected to the third-bit signal to be detected input and output terminal DQ 2.

[0090] The first input terminal and the second input terminal of the fourth data selector 505 are respectively used to receive the fourth-bit signal to be detected DQ(3) (obtained through the original channel of the fourth-bit signal to be detected DQ(3)) and the eighth-bit detection result signal DQ[7] (connected to the output terminal of the eighth logic detection circuit to obtain the conversion state of the ODT of the eighth-bit signal to be detected DQ(7)), and its output terminal is connected to the fourth signal to be detected input and output terminal DQ 3.

[0091] The input end of the inverter 516 receives the mode detection control signal TM_ODT_lowbytes_output, and the output end outputs the mode detection control inverted signal TM_ODT_lowbytes_outputB to the second input end 5112 of the second AND gate 511. The first input end 5111 of the second AND gate 511 can receive the terminal resistance conversion output enable signal TM_ODT_Transition_en, and the output end is used to output the second selection signal sel_2.

[0092] The control terminals of the fifth data selector 512 , the sixth data selector 513 , the seventh data selector 514 and the eighth data selector 515 are all connected to the output terminal of the second AND gate 511 .

[0093] The first input terminal and the second input terminal of the fifth data selector 512 are respectively used to receive the fifth-bit signal to be detected DQ(4) (obtained through the original channel of the fifth-bit signal to be detected DQ(4)) and the first-bit detection result signal DQ[0] (connected to the output terminal of the first logic detection circuit to obtain the conversion state of the ODT of the first-bit signal to be detected DQ(0)), and the output terminal is connected to the fifth-bit signal to be detected input and output terminal DQ 4.

[0094] The first input terminal and the second input terminal of the sixth data selector 513 are respectively used to receive the sixth-bit signal to be detected DQ(5) (obtained through the original channel of the sixth-bit signal to be detected DQ(5)) and the second-bit detection result signal DQ[1] (connected to the output terminal of the second logic detection circuit to obtain the conversion state of the ODT of the second-bit signal to be detected DQ(1)), and the output terminal is connected to the sixth-bit signal to be detected input and output terminal DQ 5.

[0095] The first input terminal and the second input terminal of the 7th data selector 514 are respectively used to receive the 7th signal to be detected DQ(6) (obtained through the original channel of the 7th signal to be detected DQ(6)) and the 3rd detection result signal DQ[2] (connected to the output terminal of the 3rd logic detection circuit to obtain the conversion state of the ODT of the 3rd signal to be detected DQ(2)), and the output terminal is connected to the 7th signal to be detected input and output terminal DQ 6.

[0096] The first input terminal and the second input terminal of the 8th data selector 515 are respectively used to receive the 8th signal to be detected DQ(7) (obtained through the original channel of the 8th signal to be detected DQ(7)) and the 4th detection result signal DQ[3] (connected to the output terminal of the 4th logic detection circuit to obtain the conversion state of the ODT of the 4th signal to be detected DQ(4)), and its output terminal is connected to the 8th signal to be detected input and output terminal DQ 7.

[0097] pass Figure 5It can be seen that after the terminal resistance conversion output enable signal TM_ODT_Transition_en is enabled (at the first level), the conversion state of the output terminal resistance of the signal input and output port to be detected is adopted. And when the mode detection control signal TM_ODT_lowbytes_output (at the first level) is valid, the first data selector 502 to the fourth data selector 505 all output the detection result signal of the corresponding bit to the corresponding signal input and output terminal to be detected (the first data selector 502 outputs the 5th bit detection result signal DQ[4] to the first signal input and output terminal DQ 0 to be detected, the second data selector 503 outputs the 6th bit detection result signal DQ[5] to the second signal input and output terminal DQ 1 to be detected, the third data selector 504 outputs the 7th bit detection result signal DQ[6] to the third signal input and output terminal DQ 2 to be detected, and the fourth data selector 505 outputs the 8th bit detection result signal DQ[7] to the fourth signal input and output terminal DQ 3), when the mode detection control inverting signal TM_ODT_lowbytes_outputB is invalid (at the second level), the 5th data selector 512 to the 8th data selector 515 all output the corresponding bit of the to-be-detected signal (data signal) to the corresponding to-be-detected signal input / output terminal (the 5th data selector 512 outputs the 5th bit to-be-detected signal (5th bit data signal) DQ(4) to the 5th to-be-detected signal input / output terminal DQ 4, the 6th data selector 513 outputs the 6th bit to-be-detected signal (6th bit data signal) DQ(5) to the 6th to-be-detected signal input / output terminal DQ 5, the 7th data selector 514 outputs the 7th bit to-be-detected signal (7th bit data signal) DQ(6) to the 7th to-be-detected signal input / output terminal DQ 6, and the 8th data selector 515 outputs the 8th bit to-be-detected signal (8th bit data signal) DQ(7) to the 8th to-be-detected signal input / output terminal DQ 7).

[0098] When the mode detection control signal TM_ODT_lowbytes_output is invalid (at the second level), the first data selector 502 to the fourth data selector 505 all output the corresponding bit of the to-be-detected signal (data signal) to the corresponding to-be-detected signal input / output terminal (the first data selector 502 outputs the first bit of the to-be-detected signal DQ(0) to the first to-be-detected signal input / output terminal DQ 0, the second data selector 503 outputs the second bit of the to-be-detected signal DQ(1) to the second to-be-detected signal input / output terminal DQ 1, the third data selector 504 outputs the third bit of the to-be-detected signal DQ(2) to the third to-be-detected signal input / output terminal DQ 2, and the fourth data selector 505 outputs the fourth bit of the to-be-detected signal DQ(3) to the fourth to-be-detected signal input / output terminal DQ 3), when the mode detection control inverting signal TM_ODT_lowbytes_outputB is valid (at the first level), the 5th data selector 512 to the 8th data selector 515 all output the detection result signal of the corresponding bit to the corresponding input and output terminal of the signal to be detected (the 5th data selector 512 outputs the 1st bit detection result signal DQ[0] to the 5th signal to be detected input and output terminal DQ4, the 6th data selector 513 outputs the 2nd bit detection result signal DQ[1] to the 6th signal to be detected input and output terminal DQ5, the 7th data selector 514 outputs the 3rd bit detection result signal DQ[2] to the 7th signal to be detected input and output terminal DQ6, and the 8th data selector 515 outputs the 4th bit detection result signal DQ[3] to the 8th signal to be detected input and output terminal DQ7).

[0099] Figure 6 1 is a timing diagram of relevant signals in the 4th i-th state detection logic unit in an exemplary embodiment of the present disclosure.

[0100] like Figure 6 As shown, reference Figure 3 601 may represent the timing of the 4th i-th sub-control logic signal ODTTR3. 602 may represent the timing of the 4th i-th sub-control logic signal ODTTR3 after delay. 603 may represent the timing of the i-th state change pulse signal change_pluse_i. 604 may represent the timing of the 1st detection result signal DQ[0].

[0101] Assuming that there is a high-level pulse at 601, 602 delays the high-level pulse at 601, and this delay is generated by multiple buffers 316. 603 can be the timing obtained by performing an XOR operation on 601 and 602. 604 can be the timing obtained by inputting 603 into the i-th flip-flop (e.g., a D flip-flop).

[0102] It is understandable that Figure 6Only how the 4th i-th state detection logic unit (including the 4th i-th sub-control logic signal ODTTR3 and the delayed 4th i-th sub-control logic signal ODTTR3) generates the 4th i-th state change sub-pulse signal change_pluse_i4 is shown. The manner in which the 1st i-th state detection logic unit to the 3rd i-th state detection logic unit (including the 1st i-th sub-control logic signal ODTTR0 to the 3rd i-th sub-control logic signal ODTTR2 and the delayed 1st i-th sub-control logic signal ODTTR0 to the 3rd i-th sub-control logic signal ODTTR2) generate the 1st i-th state change sub-pulse change_pluse_i1 to the 3rd i-th state change pulse signal change_pluse_i3 is exactly the same (refer to Figure 3 , the circuit structures of the i-th state detection logic units from the 1st to the 4th bits are exactly the same).

[0103] pass Figure 6 It can be seen that the 1st to 4th i-th state detection logic units can generate different 1st i-th state change sub-pulses change_pluse_i1 to 4th i-th state change sub-pulse signals change_pluse_i4. Therefore, the i-th superposition unit 315 including the first OR gate 3151, the second OR gate 3152 and the third OR gate 3153 is required to superimpose the 1st i-th state change sub-pulses change_pluse_i1 to the 4th i-th state change sub-pulse signals change_pluse_i4 to obtain the i-th state change pulse signal change_pluse_i.

[0104] Figure 7 1 is a schematic diagram of state transition of selecting the output terminal resistances of the first to fourth signal-to-be-detected input and output terminals corresponding to the lower 4 bits of the signal-to-be-detected according to an exemplary embodiment of the present disclosure. Figure 7 The terminal resistance status detection circuit includes the 1st to 8th logic detection circuits and Figure 5 The 1st to 8th mode detection control circuits are shown.

[0105] like Figure 7 As shown, the clock signal CK_c is the inverted signal of the clock signal CK_t, and the two form a differential clock signal to achieve the rising edge and the falling edge (for example Figure 7The ODT signal represents the timing of the ODT. Assume that the ODT signal changes state at time t4, for example, from RTT_PARK (the default termination resistor value when ODT is driven low) to the resistance value corresponding to ODT being driven high, and then changes back to RTT_PARK at time t13. Here, the resistance value corresponding to ODT being driven high can correspond to the dynamic random access memory (DRAM) drive state. The tADC(min), tADC(avg), and tADC(max) signals represent the timing of the ODT signal when the minimum, average, and maximum RTT change time jitter values ​​are changed when the ODT resistance value is changed.

[0106] Among them, the TM_ODT_Transition_en signal can represent the timing of the terminal resistance conversion output enable signal, and the TM_ODT_lowbytes_output signal can represent the timing of the mode detection control signal. It can be seen that at the first moment, the TM_ODT_Transition_en signal and the TM_ODT_lowbytes_output signal both change from a low level to a high level, and then remain at a high level. The TM_ODT_Transition_en signal changes at the first moment, from a low level to a high level, and then remains at a high level, indicating that the i-th logic detection circuit 101 is enabled to work at the first moment, and then the i-th logic detection circuit 101 is always in an enabled working state. The TM_ODT_lowbytes_output signal changes at the first moment from a low level to a high level, and then remains at a high level. The mode detection control inverting signal TM_ODT_lowbytes_outputB changes from a high level to a low level at the first moment, and then remains at a low level. Combined with Figure 5It can be seen that, starting from the first moment, the first data selector 502 has been outputting the fifth-bit detection result signal DQ[4] to the first signal to be detected input and output terminal DQ 0, the second data selector 503 has been outputting the sixth-bit detection result signal DQ[5] to the second signal to be detected input and output terminal DQ 1, the third data selector 504 has been outputting the seventh-bit detection result signal DQ[6] to the third signal to be detected input and output terminal DQ 2, the fourth data selector 505 has been outputting the eighth-bit detection result signal DQ[7] to the fourth signal to be detected input and output terminal DQ 3, the fifth data selector 512 has been outputting the fifth-bit signal to be detected (fifth-bit data signal) DQ(4) to the fifth signal to be detected input and output terminal DQ 4, and the sixth data selector 513 has been outputting the sixth-bit signal to be detected (sixth-bit data signal) DQ(5) to the sixth signal to be detected input and output terminal DQ 5, the 7th data selector 514 always outputs the 7th signal to be detected (7th data signal) DQ(6) to the 7th signal to be detected input / output terminal DQ 6, and the 8th data selector 515 always outputs the 8th signal to be detected (8th data signal) DQ(7) to the 8th signal to be detected input / output terminal DQ 7, that is, the 1st signal to be detected input / output terminal DQ 0 to the 4th signal to be detected input / output terminal DQ 3 are used as the output ends of the state conversion of the terminal resistor, corresponding to Figure 7 In the timing of the DQ 0 signal to the DQ 3 signal, the fifth to-be-detected signal input and output terminal DQ 5 to the eighth to-be-detected signal input and output terminal DQ 7 are used as the output ends of the data signal, corresponding to the timing of the DQ 7:4 signals respectively.

[0107] pass Figure 7 It can be seen that the fifth-bit detection result signal DQ[4] to the eighth-bit detection result signal DQ[7] can be obtained respectively through the first to-be-detected input / output terminal DQ0 to the fourth to-be-detected input / output terminal DQ3, and then the conversion states of the terminal resistor ODT(4) of the fifth-bit to-be-detected signal to the terminal resistor ODT(7) of the eighth-bit to-be-detected signal are determined.

[0108] Figure 8 1 is a schematic diagram of state transition of output terminal resistances of the fifth to eighth signal-to-be-detected input and output terminals corresponding to the upper 4 bits of the signal-to-be-detected according to an exemplary embodiment of the present disclosure. Figure 7 The terminal resistance status detection circuit includes the 1st to 8th logic detection circuits and Figure 5 The 1st to 8th mode detection control circuits are shown.

[0109] like Figure 8 shown, and Figure 7 compared to, Figure 8The TM_ODT_Transition_en signal in the first moment changes from low level to high level, but the TM_ODT_lowbytes_output signal remains at a low level, and the mode detection control inverting signal TM_ODT_lowbytes_outputB remains at a high level. Figure 5 It can be seen that, starting from the first moment, the first data selector 502 has been outputting the first-bit signal to be detected DQ(0) to the first-bit signal to be detected input / output terminal DQ 0, the second data selector 503 has been outputting the second-bit signal to be detected DQ(1) to the second-bit signal to be detected input / output terminal DQ 1, the third data selector 504 has been outputting the third-bit signal to be detected DQ(2) to the third-bit signal to be detected input / output terminal DQ 2, the fourth data selector 505 has been outputting the fourth-bit signal to be detected DQ(3) to the fourth-bit signal to be detected input / output terminal DQ 3, the fifth data selector 512 has been outputting the first-bit detection result signal DQ[0] to the fifth-bit detection result signal input / output terminal DQ 4, and the sixth data selector 513 has been outputting the second-bit detection result signal DQ[1] to the sixth-bit detection result signal input / output terminal DQ 5, the 7th data selector 514 always outputs the 3rd bit detection result signal DQ[2] to the 7th to-be-detected signal input / output terminal DQ6, and the 8th data selector 515 always outputs the 4th bit detection result signal DQ[3] to the 8th to-be-detected signal input / output terminal DQ7, that is, the 5th to-be-detected signal input / output terminal DQ4 to the 8th to-be-detected signal input / output terminal DQ7 are used as the output ends of the state conversion of the terminal resistor, corresponding to Figure 8 In the timing of the DQ 4 signal to the DQ 7 signal, the first to-be-detected signal input and output terminal DQ 0 to the fourth to-be-detected signal input and output terminal DQ 3 serve as output ends of the data signal, corresponding to the timing of the DQ 3:0 signals respectively.

[0110] pass Figure 8 It can be seen that the first-bit detection result signal DQ[0] to the fourth-bit detection result signal DQ[3] can be obtained respectively through the fifth-bit detection signal input / output terminal DQ4 to the eighth-bit detection signal input / output terminal DQ7, thereby determining the conversion state of the terminal resistance ODT(0) of the first-bit detection signal to the terminal resistance ODT(3) of the fourth-bit detection signal.

[0111] On the basis of the above disclosed embodiments, the present disclosed embodiments further provide a method for detecting state transition of a terminal resistor in a semiconductor memory device.

[0112] Figure 9The present invention is a flowchart illustrating a method for detecting a state transition of a terminal resistor in a semiconductor memory device according to an exemplary embodiment of the present invention. The semiconductor memory device may include first to Mth signal input and output terminals to be detected, where M is an integer greater than 1.

[0113] like Figure 9 As shown, the state transition detection method of the terminal resistor in the semiconductor memory device may include the following steps:

[0114] Step S901: receiving a control logic signal of a terminal resistor of an i-th signal to be detected, performing a logic operation on the control logic signal of the terminal resistor of the i-th signal to be detected, and generating an i-th detection result signal.

[0115] Step S902: receiving a mode detection control signal, and when the mode detection control signal is at a first level, outputting the i-th detection result signal through the j-th to-be-detected signal input / output terminal to determine the conversion state of the terminal resistance of the i-th to-be-detected signal.

[0116] Wherein, i and j are both integers greater than or equal to 1 and less than or equal to M, and i and j are different.

[0117] Figure 9 For other contents of the embodiment, reference may be made to the above embodiment.

[0118] Figure 10 FIG. 1 is a schematic diagram of the structure of a semiconductor memory device in an exemplary embodiment of the present disclosure.

[0119] like Figure 10 As shown, the semiconductor memory device 1000 in the embodiment of the present disclosure may include the state transition detection circuit 10 of the terminal resistor in the semiconductor memory device described above.

[0120] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A state transition detection circuit for a terminal resistor in a semiconductor memory device, characterized in that: The semiconductor memory device includes first to Mth input and output terminals for signals to be detected, and the state transition detection circuit includes: an i-th logic detection circuit, configured to receive a control logic signal of a terminal resistor of an i-th signal to be detected, and perform a logic operation on the control logic signal of the terminal resistor of the i-th signal to be detected to generate an i-th detection result signal; a j-th detection mode control circuit, connected to the j-th signal to be detected input / output terminal and the i-th logic detection circuit, configured to receive a mode detection control signal, and output the i-th detection result signal through the j-th signal to be detected input / output terminal when the mode detection control signal is at a first level, so as to determine a conversion state of a terminal resistance of the i-th signal to be detected; Wherein, M is an integer greater than 1, i and j are both integers greater than or equal to 1 and less than or equal to M, and i and j are different.

2. The circuit according to claim 1, wherein Also includes: a j-th logic detection circuit, configured to receive a control logic signal of a terminal resistor of a j-th signal to be detected, and perform a logic operation on the control logic signal of the terminal resistor of the j-th signal to be detected to generate a j-th detection result signal; an i-th detection mode control circuit, which is respectively connected to the i-th signal to be detected input and output terminal and the j-th logic detection circuit, and is used to receive a mode detection control inverted signal, and when the mode detection control inverted signal is at the first level, output the j-th detection result signal through the i-th signal to be detected input and output terminal to determine the conversion state of the terminal resistance of the j-th signal to be detected; and when the mode detection control inverted signal is at the second level, output the i-th signal to be detected through the i-th signal to be detected input and output terminal; Among them, the mode detection control inverting signal and the mode detection control signal are inverted signals of each other; the j-th detection mode control circuit is also used to output the j-th signal to be detected through the j-th signal to be detected input and output terminal when the mode detection control signal is the second level.

3. The circuit according to claim 1, wherein The i-th logic detection circuit includes: The i-th state logic conversion circuit is used to receive the control logic signal of the terminal resistor of the i-th signal to be detected, perform logic conversion on the control logic signal of the terminal resistor of the i-th signal to be detected, and output an i-th state change pulse signal to the i-th trigger; The i-th trigger is used to receive and generate the i-th detection result signal according to the i-th state change pulse signal.

4. The circuit according to claim 3, wherein: The control logic signal of the terminal resistor of the i-th signal to be detected includes an n-bit i-th sub-control logic signal, and the i-th state logic conversion circuit includes: a k-th i-th state detection logic unit, the k-th i-th state detection logic unit being configured to receive the k-th i-th sub-control logic signal and generate a k-th i-th state change sub-pulse signal according to the k-th i-th sub-control logic signal; an i-th superimposing unit, configured to superimpose the i-th state change sub-pulse signals from the 1st to the nth positions to obtain the i-th state change pulse signal; Here, n is an integer greater than or equal to 1, and k is an integer greater than or equal to 1 and less than or equal to n.

5. The circuit according to claim 4, wherein The k-th i-th state detection logic unit includes: a plurality of buffers, configured to delay the k-th ith sub-control logic signal to obtain a delayed k-th ith sub-control logic signal; An exclusive OR gate is used to receive and generate the kth i-th state change sub-pulse signal according to the kth i-th sub-control logic control signal and the delayed kth i-th sub-control logic control signal.

6. The circuit according to claim 5, wherein: The i-th superimposing unit includes: The OR gate circuit is used to receive and perform logic OR processing on the 1st to nth i-th state change sub-pulse signals to generate the i-th state change pulse signal.

7. The circuit according to claim 1, wherein: The j-th detection mode control circuit includes: a first AND gate, configured to receive a terminal resistance conversion output enable signal and the mode detection control signal, and generate a first selection signal having the same level as the mode detection control signal when the terminal resistance conversion output enable signal is at a first level; A first selector, wherein the first input terminal and the second input terminal are respectively used to receive the j-th signal to be detected and the i-th detection result signal, the control terminal is connected to the output terminal of the first AND gate, and is used to receive the first selection signal, and the output terminal is used to output the i-th detection result signal through the j-th signal to be detected input and output terminal when the first selection signal is at the first level.

8. The circuit according to any one of claims 1 to 7, characterized in that The signal to be detected includes at least one of the following: a data signal DQ, a data strobe signal DQS, a data mask signal DM, and a terminal data strobe signal TDQS.

9. A method for detecting state transition of a terminal resistor in a semiconductor memory device, characterized in that: The semiconductor memory device includes first to Mth input and output terminals for signals to be detected, and the method includes: receiving a control logic signal of a terminal resistor of an i-th signal to be detected, performing a logic operation on the control logic signal of the terminal resistor of the i-th signal to be detected to generate an i-th detection result signal; receiving a mode detection control signal, and outputting the i-th detection result signal through the j-th to-be-detected signal input / output terminal when the mode detection control signal is at a first level, so as to determine a conversion state of a terminal resistance of the i-th to-be-detected signal; Wherein, M is an integer greater than 1, i and j are both integers greater than or equal to 1 and less than or equal to M, and i and j are different.

10. A semiconductor memory device, characterized in that: A state transition detection circuit comprising a terminal resistor in a semiconductor memory device according to any one of claims 1 to 8.

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