Suspicious Activity Monitoring Storage System

Abstract

The subject application relates to a suspicious activity monitoring memory system. The duration of memory device operation exceeding operating parameters can be tracked via intentional degradation of transistors. One or more signals generated by the intentional degradation of the transistors can be used to generate alarms and / or otherwise used in memory device control circuits and / or systems.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and in particular, to a memory device having a data recording mechanism. Background Art

[0002] Semiconductor devices (e.g., processors, memory systems, etc.) may include semiconductor circuits for storing and / or processing information. An example semiconductor device is a memory device. The memory device may include a volatile memory device, a non-volatile memory device, or a combination device. Memory devices such as dynamic random access memory (DRAM) may use electrical energy to store and / or access data. For example, the memory device may include a DDR random access memory (RAM) device that uses a double data rate (DDR) interface connection scheme (e.g., DDR4, DDR5) for high-speed data transfer.

[0003] In order to facilitate the collection of data regarding utilization and real-world operating parameters of semiconductor devices, it is helpful to use a data logger in a memory device to monitor and record such data during use for subsequent retrieval. This data can be used for diagnostic operations, to collect demographic data to improve understanding of the conditions and / or environments in which the product can be used, etc. However, data logging in volatile memory devices is challenging. Summary of the invention

[0004] According to one aspect of the subject application, an apparatus is provided. The apparatus includes: a first recording circuit configured to track a first duration that a circuit experiences a first operating condition via a first performance degradation; and a first detector circuit configured to generate a first alarm at least in part by comparing an output from the first recording circuit to a first alarm reference voltage.

[0005] According to another aspect of the subject application, a method is provided. The method includes: applying a stress voltage to a gate of a transistor for a duration; outputting a drain voltage of the transistor to a sensitivity detector, wherein an amplitude of the drain voltage is adjusted in response to the duration; determining whether the drain voltage is greater than or equal to a reference alarm voltage; and generating an alarm signal in response to determining that the drain voltage is greater than or equal to the reference alarm voltage.

[0006] According to yet another aspect of the subject application, a system is provided. The system includes: a memory device configured to be operated beyond a first operating parameter; a recording circuit configured to track a duration that the memory device is operated beyond the first operating parameter; and a sensitivity detector configured to determine whether to generate an alarm based at least in part on a comparison of an output from the recording circuit with a first alarm reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be better understood by reading the following detailed description and referring to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a memory device according to an embodiment of the present disclosure;

[0009] Figure 2 is a block diagram of a suspicious activity detection block according to an embodiment of the present disclosure;

[0010] Figure 3 According to the second embodiment of the present disclosure Figure 2 A block diagram of an instance of a suspicious activity detection block;

[0011] Figure 4 is a method for operating according to the second embodiment of the present disclosure Figure 3 Flowchart of the suspicious activity detection block;

[0012] Figure 5 According to the third embodiment of the present disclosure Figure 2 a block diagram of a second instance of a suspicious activity detection block; and

[0013] Figure 6 According to the fourth embodiment of the present disclosure Figure 2 A block diagram of a third instance of a suspicious activity detection block. DETAILED DESCRIPTION

[0014] As an alternative to non-volatile memory-based data loggers, it may be possible to store relevant operational data in a less power and space-efficient manner. For example, if the desired type of operational data relates to the duration over which an operational parameter has been experienced (e.g., how many hours has the device been operating within a particular operating temperature range), a data logging circuit that exploits time-dependent changes in material properties may be used. One such data logging circuit involves a complementary metal oxide semiconductor (CMOS) device (e.g., a p-channel CMOS (PMOS) device or an n-channel (NMOS) device) circuit that experiences material degradation that is proportional to the time over which a known voltage is applied to its gate. By utilizing such a CMOS degradation-based data logging circuit to measure the duration over which a device has been experiencing different operational parameters, a large amount of valuable operational data may be obtained with a small investment in circuit space and power.

[0015] As described in more detail below, the technology disclosed herein relates to electronic systems, including memory devices, systems having memory devices, and related methods for storing condition and / or usage information thereof. An electronic system (e.g., a dynamic random access memory (DRAM) device) may include a degradation-based storage circuit (e.g., a CMOS degradation-based data logger) configured to collect and store information about the duration that the electronic system experiences different operating characteristics (e.g., device modes) and / or environmental conditions (e.g., device operating temperature).

[0016] The degradation-based storage circuit can be used as a low-cost embedded data logger to record various information related to the end-user's utilization of the electronic device / system. The recorded usage information (e.g., duration of experience with different temperature ranges, operating modes, asserted signals, addresses utilized, etc.) can be used to diagnose operation, improve usage models, revise design specifications, etc.

[0017] In some embodiments, the degradation-based storage circuits may each include a trigger circuit corresponding to a desired parameter or parameter combination for which the duration is measured to couple a predetermined voltage to the gate of the CMOS device to cause degradation for the duration that the target condition or standard is active. By degrading the corresponding CMOS device each time one or more target conditions occur during operation of the electronic device / system, the cumulative degradation of the CMOS device (which may be measured by a circuit that measures the trigger voltage of the CMOS device) may be used to determine the cumulative duration that the corresponding trigger condition is active.

[0018] Because the potential degradation of a single CMOS device is not infinite, various embodiments may provide various connection topologies for coupling multiple CMOS devices to one or more trigger circuits (e.g., spare transistors) so that a depleted or defective CMOS device can be replaced with a new, not yet degraded CMOS device. This may allow monitoring to continue for longer periods of time than a single CMOS would allow (e.g., the operating time period of one transistor). Examples of these various embodiments, as well as other information related to degradation-based monitoring techniques and / or descriptions related to specific sensing circuit systems generally described herein, are discussed in co-pending and commonly assigned U.S. patent application Ser. No. 16 / 138,900, filed on Sep. 21, 2018, and entitled “A SEMICONDUCTOR DEVICE WITH A DATA-RECORDING MECHANISM” (e.g., reference 1 to the accompanying drawings). Figure 3 ). This application is incorporated herein by reference in its entirety.

[0019] Because the cumulative degradation of the CMOS device is predictable, the output from the recording circuit (e.g., a circuit that outputs and / or determines a trigger voltage of the CMOS device and / or a circuit that outputs and / or determines a signal corresponding to material degradation proportional to the duration of application of a stress voltage to the circuit (such as a CMOS device)) can be determined to correspond to different alarm levels and can therefore be used in a larger control system and / or monitoring system. In this way, the recording circuit output can be provided to a sensitivity detector within a detection block to generate an alarm signal based on a reference voltage within the detection block that defines when the alarm signal is generated. It should be noted that in addition to the specific examples described herein, any number of recording circuits, outputs, sensitivity detectors, detection blocks, and generated alarms can be used in any suitable combination with each other. The described alarm system can benefit from each of the benefits provided to the electronic device / system (e.g., the operation of the electronic device / system) and can therefore provide an improved monitoring and / or detection circuit in at least the manner described above and at least relative to current monitoring and detection technology.

[0020] In view of the foregoing, Figure 1 1 is a block diagram of an electronic device (e.g., a semiconductor memory device such as a DRAM device). Memory device 10 may include an array of memory cells, such as memory array 12. Memory array 12 may include memory banks (e.g., Figure 10-15 in the example of ). Each memory bank may include a word line (WL), a bit line (BL), and memory cells arranged at the intersection of the word line and the bit line. The memory cell may include any of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, etc. Selection of the word line may be performed by a row decoder 14, and selection of the bit line may be performed by a column decoder 16. A sense amplifier (SAMP) may be provided for the corresponding bit line and may be connected to at least one corresponding local input / output (I / O) line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that may operate as a switch. The memory array 12 may also include plate lines and corresponding circuitry for managing the operation of the plate lines.

[0021] The memory device 10 may use external terminals including a command terminal and an address terminal coupled to a command bus and an address bus to receive a command signal (CMD) and an address signal (ADDR), respectively. The memory device 10 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals (CK and CKF), a data clock terminal for receiving data clock signals (WCK and WCKF), data terminals (DQ, RDQS, DBI, and DMI), and power supply terminals (VDD, VSS, VDDQ, and VSSQ).

[0022] The command terminal and the address terminal may be supplied with an address signal and a memory bank address signal from the outside. The address signal and the memory bank address signal supplied to the address terminal may be transmitted to the address decoder 18 through the command address input circuit 22. The address decoder 18 may receive the address signal and supply a decoded row address signal (XADD) to the row decoder 14 and a decoded column address signal (YADD) to the column decoder 16. The address decoder 18 may also receive a memory bank address signal (BADD) and supply the memory bank address signal to both the row decoder 14 and the column decoder 16.

[0023] A command signal (CMD), an address signal (ADDR), and a chip select signal (CS) may be supplied to the command terminal and the address terminal from the memory controller. The command signal may represent various memory commands (e.g., including access commands, which may include read commands and / or write commands) from the memory controller. The chip select signal may be used to select the memory device 10 to respond to the commands and addresses provided to the command terminals and the address terminals. When a valid chip select signal is provided to the memory device 10, the commands and addresses may be decoded and memory operations may be performed. The command signal may be provided to the command decoder 20 as an internal command signal (ICMD) through the command address input circuit 22. The command decoder 20 may include a circuit for decoding the internal command signal to generate various internal signals and commands (such as row command signals for selecting word lines and column command signals for selecting bit lines) for performing memory operations. The internal command signal may also include output and input activation commands, such as clock control commands (CMDCK). Command decoder 20 may further include one or more registers for tracking various counts or values ​​(eg, a count of refresh commands received by memory device 10 and / or self-refresh operations performed by memory device 10).

[0024] When a read command is issued and the row address and column address are supplied with the read command in time, read data is read from the memory cell specified by the row address and column address in the memory array 12. The read command may be received by the command decoder 20, which may provide an internal command to the I / O circuit 26 so that the read data may be output from the data terminal through the read / write amplifier 28 and the I / O circuit 26 according to the clock signal. The read data may be programmed in the memory device 10 (such as the mode register ( Figure 1 The read latency information may be defined in terms of a clock cycle of a clock signal (CK). For example, the read latency information may be a number of clock cycles of a clock signal (e.g., CK) after a read command is received by the memory device 10 when associated read data is provided.

[0025] When a write command is issued and the write command is supplied for the row address and the column address in time, the write data may be supplied to the data terminal according to the clock signals (e.g., WCK and WCKF). The write command may be received by the command decoder 20, which may provide an internal command to the I / O circuit 26, so that the write data is received by the data receiver in the I / O circuit 26 and supplied to the memory array 12 through the I / O circuit 26 and the read / write amplifier 28. The write data may be written to the memory cell specified by the row address and the column address. The write data may be supplied to the data terminal at a time defined by the write latency (WL) information. The write latency information may be programmed in the memory device 10, such as in a mode register ( Figure 1 The write latency information may be defined in terms of a clock cycle of the clock signal (CK). For example, the write latency information may be a number of clock cycles of the clock signal (CK) after a write command is received by the memory device 10 when associated write data is received.

[0026] The power supply terminals may be provided with power supply potentials (VDD and VSS). These power supply potentials (VDD and VSS) may be supplied to the internal voltage generator circuit 30. The internal voltage generator circuit 30 may generate various internal potentials (VPP, VOD, VARY, VPERI, etc.) based on the power supply potentials (VDD and VSS). The internal potential (VPP) may be used in the row decoder 14, the internal potentials (VOD and VARY) may be used in the sense amplifiers included in the memory array 12, and the internal potential (VPERI) may be used in many other circuit blocks.

[0027] A power supply potential (VDDQ) may also be provided for the power supply terminal. The power supply potential (VDDQ) may be supplied to the I / O circuit 26 together with the power supply potential (VSS). In an embodiment of the present technology, the power supply potential (VDDQ) may be the same potential as the power supply potential (VDD). In another embodiment of the present technology, the power supply potential (VDDQ) may be a potential different from the power supply potential (VDD). However, a dedicated power supply potential (VDDQ) may be used for the I / O circuit 26 so that the power supply noise generated by the I / O circuit 26 does not propagate to other circuit blocks.

[0028] An external clock signal and a complementary external clock signal can be supplied to the clock terminal and the data clock terminal. The external clock signal (CK, CKF, WCK and WCKF) can be supplied to the clock input circuit 32. Some clock signals (CK and CKF, WCK and WCKF) can be complementary. The complementary clock signal can have opposite clock levels and change between opposite clock levels at the same time. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal changes from a low clock level to a high clock level, the complementary clock signal changes from a high clock level to a low clock level, and when the clock signal changes from a high clock level to a low clock level, the complementary clock signal changes from a low clock level to a high clock level.

[0029] The input buffer included in the clock input circuit 32 can receive an external clock signal. For example, when enabled by a signal (CKE) from the command decoder 20, the input buffer can receive clock signals (CK, CKF, WCK, and WCKF). The clock input circuit 32 can receive an external clock signal to generate an internal clock signal (ICLK). The internal clock signal can be supplied to the internal clock circuit 34. The internal clock circuit 34 can provide various phase and frequency controlled internal clock signals based on the received internal clock signal and the clock enable signal (CKE) from the command address input circuit 22. For example, the internal clock circuit 34 can include a clock path (CK) that receives the internal clock signal and provides various clock signals to the command decoder 20. Figure 1 10). The internal clock circuit 34 may further provide an input / output (I / O) clock signal. The I / O clock signal used as a timing signal may be supplied to the I / O circuit 26 for determining the output timing of read data and the input timing of write data. The I / O clock signal may be provided at multiple clock frequencies so that data may be output from and / or input to the memory device 10 at different data rates. When high memory speeds are desired, higher clock frequencies may be desirable. When lower power consumption is desired, lower clock frequencies may be desirable. The internal clock signal may also be supplied to the timing generator 36 and used to generate various internal clock signals.

[0030] The memory device 10 can be coupled to any suitable electronic device that uses at least a portion of the memory for temporary and / or permanent storage of information as a host device. For example, the host device can include a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or at least a portion of a processing circuit system, such as a central processing unit, a coprocessor, a dedicated memory controller, etc. The host device can sometimes be a networking device (e.g., a switch, a router) or a digital image, audio and / or video recorder, a vehicle, an appliance, a toy, or any of a variety of other products. In one embodiment, the host device can be directly connected to the memory device 10, but in other embodiments, the host device can be indirectly connected to the memory device 10 (e.g., through a networking connection or through communication with an intermediate device).

[0031] The memory device 10 may include a data logging circuit 38 (data logger) for logging data from one or more sensors 40 and / or from other components of the device (e.g., address command input circuit 22, one or more decoders of decoders 14 / 16 / 18 / 20). The data logging circuit 38 may include a complementary metal oxide semiconductor (CMOS) device (e.g., a p-channel CMOS (PMOS) device or an n-channel (NMOS) device) configured to degrade according to target usage information (e.g., negative bias temperature instability-based (NBTI-based) degradation and / or carrier hot channel-based (CHC-based) degradation). In this way, the data logging circuit 38 is a network of sensors, measurement circuit systems, and logging circuit systems. The memory device 10 may further adjust and / or change the amount of degradation that occurs each time to compensate for other factors or conditions that affect the degradation (e.g., operating temperature). In some embodiments, the memory device 10 may adjust the amount of degradation by adjusting the stress voltage used to degrade the CMOS. In some embodiments, the memory device 10 may adjust the duty cycle by adjusting the stress input used to degrade the CMOS. Despite Figure 1 1 and 2, respectively, the memory device 10 is shown as a separate functional block, but the memory device 10 may include the data logging circuit 38 within any other components described above, such as the command address input circuit 22, the I / O circuit 26, etc. Moreover, the memory device 10 may include other connections for the data logging circuit 38. For example, the data logging circuit 38 may be coupled to other circuits, such as the address command input circuit 22, one or more decoders of the decoders 14 / 16 / 18 / 20, etc., to include trigger conditions from the circuits.

[0032] In view of the foregoing, the data logging circuit 38 may generally be referred to as a logging circuit that receives suspicious activity (SA) signals from one or more sensors 40. Although described in terms of SA detection and general preventative operations, it should be understood that the data logging circuit 38 may log and / or track outputs from the sensors 40 for a variety of applications and / or purposes and may use any of the variations of the logging and / or tracking parameters described above.

[0033] This relationship can be found in Figure 2 Summarize in. Figure 2 is a block diagram of a suspicious activity (SA) detection block 50 . Figure 2 An example of the SA detection block 50 includes a recording circuit 52 and a detection circuit system 54. The recording circuit 52 can be any suitable data recording (logging) and / or recording (recording) circuit system suitable for use with a memory device (e.g., memory device 10). The detection circuit system 54 can detect whether a specific input or a specific operating condition of the memory device 10 and / or the memory array 12 is at a suitable level to generate an alarm. The specific input can include and / or be associated with row hammer parameters, access parameters, temperature parameters, voltage load parameters, current load parameters, stress parameters, etc. In this way, the detection circuit system 54 can include detectors with different sensitivities for detecting different alarm levels or urgency. For example, the detection circuit system 54 includes a high sensitivity detector 56A, a medium sensitivity detector 56B, and a low sensitivity detector 56C, each of which is capable of outputting a separate alarm corresponding to the corresponding urgency of the input signal.

[0034] A suspicious activity (SA) signal may be received via recording circuitry 52. ​​In response to receiving the SA signal, recording circuitry 52 may record one or more parameters about the signal and vary its output to detection circuitry 54 based at least in part on the one or more parameters as recorded over time. Detection circuitry 54 may receive the output from recording circuitry 52 and determine whether the value of the output is suitably high to activate one of its alarms.

[0035] Figure 3 An example of the SA detection block 50 is shown in FIG. Figure 3 is a block diagram of a first example SA detection block 50A. The SA detection block 50A includes an example of a recording circuit 52A that uses at least some of the data recording circuits 38 to record one or more parameters associated with the SA signal. As depicted, the SA signal actuates a switch 70 within the recording circuit 52A. The switch 70 can be any suitable device that is actuated in response to a control signal. Therefore, the parameter of the SA signal recorded by this example of the recording circuit 52A is the duration of the SA signal being enabled (e.g., the logic of the circuit system is high and / or "1").

[0036] When switch 70 is actuated, stress voltage 72 is applied to the gate of transistor 74. Once the SA signal is disabled (e.g., the logic of the circuit system is low and / or "0"), switch 70 returns to its zero state and stops applying stress voltage 72 to the gate of transistor 74. Therefore, the gate of transistor 74 receives stress voltage 72 for the duration that the SA signal is enabled.

[0037] It should be noted that although transistor 74 is depicted as a single transistor, transistor 74 may have any suitable components that may degrade by a predictable amount. For example, transistor 74 may represent a CMOS-based degradation sensor that includes one or more PMOS and / or NMOS devices. Furthermore, in some embodiments, transistor 74 may include one or more PMOS devices and / or NMOS devices. When transistor 74 is a PMOS device, transistor 74 may degrade according to NBTI, and the gate of the PMOS device may be coupled to stress voltage 72 and / or intermediate logic (and / or components) between the PMOS device and stress voltage 72, such as switch 70. Additionally, the drain of the PMOS device may be coupled to detection circuitry 54, to a resistor to ground, to a feedback line to the intermediate logic and / or components, etc. When transistor 74 is an NMOS device, transistor 74 may degrade according to CHC. In these cases, the gate of the NMOS device can be coupled to the stress voltage 72 and / or intermediate logic (and / or components) between the NMOS device and the stress voltage 72, the drain can be coupled to the stress voltage 72, and the source can be coupled to the detection circuit system 54, to a resistor to ground, to a feedback line to the intermediate logic and / or components, etc.

[0038] Additionally, in some embodiments, transistor 74 may include an NMOS device and degrade according to channel induced secondary electron generation (CHISEL). In this case, the gate of the NMOS device may be directly coupled to the drain, wherein both the gate and the drain are directly coupled to the stress voltage. The source of the NMOS device may be coupled to a relatively large resistor, thereby allowing a relatively large drain-to-body voltage (e.g., a high electric field). However, because the large resistor is coupled to the source, the current used to degrade the NMOS device remains relatively small, thereby enabling power consumption to remain relatively low during degradation.

[0039] In each of these described examples, transistor 74 can degrade a predictable amount based at least in part on the amount of time that stress voltage 72 is received via the gate. The output from transistor 74 (e.g., voltage output from the drain and / or source of transistor 74) can generally change based at least in part on the amount of degradation that transistor 74 cumulatively experiences while the drive voltage (V) (e.g., reference arrow 76) remains substantially constant. Thus, a particular sensitivity detector 56D of the detection circuit system 54 can use the output from transistor 74 to determine whether an alarm is generated in response to when the SA signal has been enabled over time. For example, sensitivity detector 56D can include a comparison circuit (e.g., comparator 84) that compares the output from transistor 74 to a reference value (e.g., reference voltage 86, a suitable reference current) to determine whether the output from transistor 74 is large enough to activate an alarm.

[0040] When suspicious activity occurs for longer than a suitable amount of time, the generated alarm can be used to notify an operator. The suitable amount can be defined by the sensitivity detector 56D and / or the reference value. In this way, the alarm output from the comparator 84 can be used to drive an alarm circuit, can be used as a signal to initiate notification of an operator, can be received by a control system and / or control circuit that changes the operation of the memory device 10 in response to the alarm, etc.

[0041] Figure 4 1 is a flow chart of a method 100 for operating the SA detection block 50. In general, the method 100 includes the SA detection block receiving a suspicious activity (SA) signal (box 102), applying a stress voltage (box 104), outputting an analog voltage to a sensitivity detector based at least in part on the duration of the total time that the stress voltage was previously applied to the transistor (box 106), comparing the output voltage with at least one reference voltage (box 108), generating an alarm in response to the result of the comparison (box 110), and performing preventive and / or precautionary operations in response to the alarm (box 112). It should be understood that although the specific operations of the method 100 are described in a specific order, these operations can be performed in any suitable order. In addition, although the method 100 is described as being performed by the SA detection block 50, it should be understood that any suitable system and / or circuit system (e.g., a circuit combined with a control system) can perform the described operations.

[0042] At block 102, the SA detection block 50 may receive a suspicious activity (SA) signal. The SA detection block 50 may receive the SA signal at the recording circuit 52. In response to receiving the SA signal, the SA detection block 50 may apply a stress voltage 72 to the transistor, such as at least to a gate (e.g., a gate contact) of the transistor 74, at block 104. Applying the stress voltage 72 may degrade the transistor 74 by a predictable amount.

[0043] At block 106, the analog output voltage from recording circuit 52 (eg, the voltage output from transistor 74) may be transmitted to sensitivity detector 56. The voltage value of the output voltage may be based at least in part on the accumulated duration of previous application of stress voltage 72 to transistor 74.

[0044] At block 108, the SA detection block 50 may compare the output voltage to at least one reference voltage 86. The SA detection block 50 may use the sensitivity detector 56 (including the comparator 84) to compare at least the output voltage to the reference voltage 86. The reference voltage 86 may be selected to correspond to an amount of degradation corresponding to a particular duration of application of the stress voltage 72 to the transistor 74. In this way, the sensitivity detector 56 may provide an alert, generate an alert, produce an alert, trigger an alert, etc. when the output voltage exceeds the relatively low reference voltage 86 in situations where a short duration (of application of the stress voltage) warrants an alert or monitoring, and may provide an alert, generate an alert, produce an alert, trigger an alert, etc. when the output voltage exceeds the relatively high reference voltage 86 in situations where a long duration (of application of the stress voltage) warrants an alert or monitoring.

[0045] At box 110, the SA detection block 50 may generate an alarm in response to the result of the comparison at box 108. The alarm may be a voltage signal from the comparator 84 indicating that the output voltage from the recording circuit 52 is greater than the reference voltage 86. The alarm may be output from the comparator 84 and received by a control system inside the memory device 10 (e.g., inside the DRAM) and / or outside the memory device 10 (e.g., outside the DRAM). The control system may perform preventive operations in response to receiving the alarm. The control system inside the memory device 10 may respond to the alarm by changing one or more operations of the memory device 10. However, the control system outside the memory device 10 may respond to the alarm by performing one or more external operations relative to the memory device 10. For example, the control system may set additional alarms (e.g., audible alarms, visual alarms, etc.) for processing by an operator. The control system may additionally or alternatively perform additional computing actions, such as generating an email notification, a pop-up notification, or an alarm generated by a computer in other ways to be presented to the operator through a graphical user interface (GUI). Additionally, the control system may respond by tracking alarms over time and using this information to monitor system or network-wide behavior such that alarms between different storage devices 10 may be correlated and / or compared to improve monitoring of the network.

[0046] At block 112, the SA detection block 50 may sometimes perform preventive or precautionary operations in response to an alarm. In these cases, the SA detection block 50 may include a response circuit (not shown in the diagram of the SA detection block 50). The operation of the response circuit may reduce the likelihood that the memory device 10 is operated to exceed the first operating parameter. The SA detection block 50 via the response circuit may perform different operations in response to different alarms, and any suitable combination of alarms and operations may be used in the systems and methods described herein.

[0047] Additionally, in response to determining that recording circuit 52 has operated long enough to experience degradation or otherwise operate undesirably, some instances of SA detection block 50 can reset recording circuit 52. Recording circuit 52 can be reset by reversing degradation of transistor 74, replacing transistor 74 with a fresh and / or new transistor, etc.

[0048] In view of the foregoing, Figure 5 is a block diagram of a second example of SA detection block 50, namely SA detection block 50C. In some cases, any suitable configuration of recording circuit 52 may be used with detection circuit system 54. Detection circuit system 54 may have any suitable number of sensitivity detectors 56. For example, detection circuit system 54 may have two or more sensitivity detectors 56.

[0049] In this depicted example, the SA detection block 50C shares a recording circuit 52 between two sensitivity detectors 56. Each sensitivity detector 56 can monitor a different parameter to be exceeded. For example, the first sensitivity detector 56E can compare the output voltage with a first reference voltage 86 indicating that a stress voltage (e.g., stress voltage 72 or other suitable stress voltage) has been applied for a duration exceeding half of the recording period, while the second sensitivity detector 56F can compare the output voltage with a second reference voltage 86 indicating that the stress voltage 72 has been applied for 75% of the recording period. In this example, the stress voltage 72 is applied in response to performing a row hammering operation on the memory device 10. The row hammering operation can include detecting that the same row address of the memory device 10 is repeatedly accessed for a specific duration. In this way, the SA signal can be transmitted in response to detecting a specific row addressing suspicious activity, which can be used to intentionally degrade the transistor 74 to capture the duration of the specific row addressing occurrence. Further, reference voltage 86 may correspond to a voltage level indicative of an output voltage corresponding to an expected output voltage of transistor 74 that has been intentionally degraded for a specific duration (e.g., 75% of a sensing period or sensing duration). Thus, SA detection block 50C may monitor for specific row hammering behavior that exceeds a specific duration.

[0050] Using a similar approach, other parameters corresponding to suspicious activity may be tracked over time by the SA detection block 50. For example, a memory device 10 operating at a temperature greater than the maximum recommended operating temperature for at least a duration greater than half of the sensing duration (e.g., greater than or equal to 50% of the sensing duration) may indicate suspicious activity and may be desired to be monitored. It should be noted that the sensing duration may be any suitable defined amount of time, including the total operating time of the memory device 10 or any suitable component of the memory device 10. As another example, a memory device 10 operating at a voltage greater than the maximum recommended operating voltage for at least a duration greater than half of the sensing duration (e.g., greater than or equal to 50% of the sensing duration) may indicate suspicious activity and may be desired to be monitored.

[0051] Figure 6is a block diagram of a third example of the SA detection block 50, namely, an SA detection block 50D. The SA detection block 50D may include any number of recording circuits 52 (52A, 52B, ..., 52C) and any number of sensitivity detectors (56A1, 56B1, 56C1, 56A2, ..., 56C3) within the detection circuit system 54 corresponding to the recording circuits 52. In this way, various parameters may be utilized as enable inputs to the recording circuits 52 to relate a stress voltage (e.g., stress voltage 72 or other suitable stress voltage) to a duration of using a particular operation or correspondingly operating the memory device 10 in other ways.

[0052] For example, the SA signal may be generated at least in part by a pre-thresholding operation and / or other conversion operation (e.g., implementing two or more conditions before allowing the SA signal to be generated). In this way, the SA signal may correspond to an over-temperature condition, wherein the presence of the SA signal may indicate that a threshold temperature has been exceeded for a particular length of time that the memory device 10 is allowed to operate at the temperature during operation (allowing the temperature to be monitored even though a direct sensed output of the threshold temperature may not be suitable for transmission to the recording circuit 52). In the described example, the over-temperature condition is monitored while the counting circuit system tracks the duration of the memory device 10 operating at the over-temperature, so that when the memory device 10 operates at the over-temperature for too long (e.g., defined by a threshold amount of duration), the instance of the occurrence of the described specific operation may initiate the generation of the SA signal and the transmission of the SA signal to the recording circuit 52.

[0053] The sensitivity detector 56 can output respective alarms. When multiple sensitivity detectors 56 are used, the alarms outputted can correspond to different alarm intensities (e.g., low, medium, high, etc.), which can correspond to different operations, or to different signal transmission techniques for indicating the existence of an alarm condition to an operator. For example, a low alarm can at least partially energize a light indicator, while a high alarm can at least partially energize a light indicator and another light indicator and / or emit an audible alarm, etc. In addition, in some embodiments, the alarm intensity can be used to initiate the generation of an email notification, a pop-up notification, or otherwise a computer-generated alarm to be presented to an operator through a graphical user interface (GUI). These previously described responses can be alarm responses outside the DRAM. In some cases, the alarm response can include changing the operation inside the DRAM. For example, adjusting voltage, adjusting timing delays, etc.

[0054] In some embodiments, the sensitivity detector 56 may use a reference voltage 86 that is defined relative to other voltages and / or other reference voltages 86. In this way, the first sensitivity detector 56 may use a reference voltage 86 that is at least twice the value of the voltage of the second sensitivity detector 56, a reference voltage 86 that is 1.5 times the value of the voltage of the second sensitivity detector 56, or any suitable combination of reference voltages. Because the rate at which the transistor 74 degrades is not linear with time, the reference voltage 86 may be adjusted to account for nonlinearity (e.g., the reference voltages 86 may not be exact multiples of each other). Additionally, in some embodiments, a high sensitivity detector 56 may output an alarm associated with a higher priority than an alarm generated by a low sensitivity detector 56. The relative priorities between the alarms may change the manner in which a control system that receives the alarm adjusts the operation of the memory device 10 in response to the alarm.

[0055] Therefore, the technical effects of the present disclosure include facilitating improved monitoring operations of memory devices to prevent undesired operations and / or unauthorized accesses of memory devices. These technologies describe systems and methods for monitoring the operation of memory devices by recording circuits that utilize the cumulative degradation performance of semiconductor devices. As described, it is discussed herein that CMOS devices are used for these monitoring operations. However, any suitable semiconductor device that can be utilized in cumulative degradation operations can be used in these systems and methods for monitoring memory devices. The output from the recording circuit can have a value that is proportional to or otherwise related to the cumulative degradation experienced by the semiconductor device. In this way, the recording circuit output can be provided to a sensitivity detector to monitor the operation of the memory device and generate an alarm signal when warranted. The alarm system described can benefit from each benefit provided to an electronic device / system (e.g., the operation of the electronic device / system) and can therefore provide an improved monitoring and / or detection circuit at least in the above manner and at least relative to current monitoring and detection technologies.

[0056] The above specific embodiments have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the specific forms disclosed, but to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0057] In this manner, in the above examples, the memory device is described in the context of a DRAM device. However, in addition to or in place of a DRAM device, a memory device configured according to other embodiments of the present technology may include other types of suitable storage media, such as devices incorporating NAND-based and / or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase change storage media, ferroelectric storage media, etc.

[0058] The technology presented and claimed herein is cited and applied to material objects and specific examples of a practical nature that significantly improve the art and are therefore not abstract, intangible, or purely theoretical. Further, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] ... [function]" or "steps for [performing] ... [function]," such elements are intended to be interpreted under 35 U.S.C. § 112(f). However, for any claim containing elements designated in any other manner, such elements are intended not to be interpreted under 35 U.S.C. § 112(f).

Claims

1. A semiconductor device comprising: a first recording circuit configured to track a first duration of time that the circuit is subjected to a first operating condition, wherein a first performance degradation is tracked by the first recording circuit in response to operation of the circuit under the first operating condition, thereby allowing a stress voltage to be applied to a transistor gate, and wherein the first operating condition corresponds to an input associated with a row hammer parameter, an access parameter, a temperature parameter, a voltage load parameter, a current load parameter, a stress parameter, or any combination thereof; as well as A first detector circuit is configured to generate a first alarm at least in part by comparing an output from the first recording circuit to a first alarm reference voltage. 2 . The semiconductor device of claim 1 , wherein the first detector circuit is configured to be coupled to a control system. 3 . The semiconductor device according to claim 2 , wherein the control system performs a preventive operation in response to receiving the first alarm. 4 . The semiconductor device of claim 1 , comprising a second detector circuit configured to generate a second alarm at least in part by comparing the output from the first recording circuit with a second alarm reference voltage. 5 . The semiconductor device according to claim 4 , wherein the second alarm reference voltage is at least twice as large as the first alarm reference voltage.

6. The semiconductor device of claim 1, comprising a plurality of further spare transistors for tracking the duration in response to the circuit operating under the first operating condition for an operating time period longer than one transistor. 7 . The semiconductor device of claim 1 , comprising a second recording circuit configured to track a second duration that the circuit is subjected to a second operating condition, wherein the second operating condition causes a second performance degradation of the transistor. 8 . The semiconductor device according to claim 7 , wherein the first recording circuit and the second recording circuit are configured to output respective voltage values ​​to the first detector circuit.

9. A method for operating a semiconductor device, comprising: applying a stress voltage to the gate of the transistor for a duration of time when the suspicious activity signal is enabled; outputting a drain voltage of the transistor to a sensitivity detector, wherein an amplitude of the drain voltage is adjusted in response to the duration; determining whether the drain voltage is greater than or equal to a reference alarm voltage; as well as An alarm signal is generated in response to determining that the drain voltage is greater than or equal to the reference alarm voltage.

10. The method of claim 9, comprising performing a preventive action in response to the alarm signal.

11. The method of claim 9, wherein the stress voltage is configured to be applied in response to a switch closing, wherein the switch is configured to close in response to receiving a suspicious activity signal. 12 . The method of claim 9 , wherein the amplitude of the drain voltage increases in proportion to the duration. 13 . The method of claim 9 , comprising generating a higher priority alarm signal in response to determining that the drain voltage is greater than or equal to a reference alarm voltage that is greater than the reference alarm voltage.

14. A memory system comprising: a memory device configured to be operated beyond a first operating parameter; a logging circuit configured to track a duration that the memory device is operated beyond the first operating parameter, wherein the first operating parameter comprises a row hammer parameter, an access parameter, a temperature parameter, a voltage load parameter, a current load parameter, a stress parameter, or any combination thereof; as well as A sensitivity detector is configured to determine whether to generate an alarm based at least in part on a comparison of an output from the recording circuit and a first alarm reference voltage.

15. The memory system of claim 14, comprising a control system communicatively coupled to the sensitivity detector, wherein the control system performs a preventative action in response to receiving the alert.

16. The memory system of claim 15, wherein the control system is configured to alter operation of the memory device to reduce the likelihood that the memory device will be operated beyond the first operating parameter.

17. The memory system of claim 15, comprising: further recording circuitry configured to track a duration that the memory device is operated beyond a second operating parameter; as well as A further sensitivity detector is configured to determine whether to generate a further alarm based at least in part on a comparison of further outputs from the further recording circuit.

18. The memory system of claim 17, wherein the control system is configured to perform an additional preventative operation in response to receiving the additional alert, wherein the preventative operation is not the same operation as the additional preventative operation.

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