Controller, operation method thereof, and memory system including the controller

Abstract

A controller and an operation method thereof and a memory system including the controller are disclosed. The controller includes a controller for controlling a non-volatile memory device according to a request from a host having a host memory. The controller includes: an address unit configured to divide an area of ​​the host memory allocated as a host memory buffer (HMB) to generate a plurality of sub-HMB areas, determine index values ​​of the plurality of sub-HMB areas, and generate an HMB mapping table by mapping a virtual address to the index value; and a memory control module configured to access at least one of the plurality of sub-HMB areas based on the HMB mapping table. The virtual address can be set to a continuous value with respect to the plurality of sub-HMB areas.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Application No. 10-2019-0044455, filed on April 16, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments relate generally to semiconductor devices, and more particularly to a controller and an operating method thereof, and a memory system including the controller. Background Art

[0004] In recent years, the paradigm of computer environments has changed to ubiquitous computing where computer systems can be used anywhere, anytime. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has increased rapidly. Typically, such portable electronic devices use a memory system that employs a memory device. The memory system can be used to store data used in the portable electronic device.

[0005] A memory system using a memory device does not have a mechanical drive unit and therefore exhibits good stability and durability, fast information access rate, and low power consumption. Such a memory system may include a universal serial bus (USB) memory device, a memory card with various interfaces, a universal flash memory (UFS) device, a solid-state drive (SSD), etc. Summary of the invention

[0006] Embodiments are provided for techniques capable of improving the performance of a memory system that uses host memory.

[0007] In an embodiment of the present disclosure, a controller for controlling a nonvolatile memory device according to a request from a host having a host memory, the controller may include: an address unit configured to divide an area of ​​the host memory allocated as a host memory buffer (HMB) to generate a plurality of sub-HMB areas, determine index values ​​of the plurality of sub-HMB areas, and generate an HMB mapping table by mapping a virtual address to the index value; and a memory control module configured to access at least one of the plurality of sub-HMB areas based on the HMB mapping table. The virtual address may be set to a continuous value with respect to the plurality of sub-HMB areas.

[0008] In an embodiment of the present disclosure, an operation method of a controller for controlling a nonvolatile memory device according to a request from a host having a host memory may include: dividing an area of ​​the host memory allocated as a host memory buffer (HMB) to generate a plurality of sub-HMB areas; determining index values ​​for addresses of the plurality of sub-HMB areas; and generating an HMB mapping table by mapping a virtual address to the determined index value. The virtual address may be set to a continuous value with respect to the plurality of sub-HMB areas.

[0009] In an embodiment of the present disclosure, a memory system including a nonvolatile memory device and a controller, the controller being configured to control the nonvolatile memory device according to a request from a host having a host memory. The controller can divide an area of ​​the host memory allocated as a host memory buffer (HMB) to generate a plurality of sub-HMB areas, determine offset values ​​for addresses of the plurality of sub-HMB areas, and generate an HMB mapping table by mapping a virtual address to the offset value.

[0010] According to an embodiment of the present disclosure, the performance of a memory system using a host memory may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above-mentioned aspects and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0013] Figure 2 and Figure 3 is a diagram for describing an operating method of a memory system according to an embodiment of the present disclosure;

[0014] Figure 4 and Figure 5 is a diagram for describing an operating method of a memory system according to an embodiment of the present disclosure;

[0015] Figure 6 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the present disclosure;

[0016] Figure 7 is a diagram illustrating an embodiment according to the present disclosure Figure 6 A diagram of the configuration of the controller shown;

[0017] Figure 8 is a diagram illustrating a data processing system including a memory system according to an embodiment of the present disclosure;

[0018] Fig. 9is a diagram illustrating a data processing system including a memory system according to an embodiment of the present disclosure;

[0019] Fig.10 is a diagram illustrating a network system including a memory system according to an embodiment of the present disclosure; and

[0020] Fig.11 is a block diagram illustrating a nonvolatile memory device included in a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are simplified schematic diagrams of various embodiments of the present invention. Thus, in order to avoid obscuring the present disclosure, well-known elements that are not necessary for understanding the present invention may be omitted. Therefore, the described embodiments should not be interpreted as being limited to the specific configurations illustrated herein, but may include differences in configurations that do not depart from the spirit and scope of the present invention as defined by the appended claims.

[0022] Furthermore, although only a few embodiments of the present invention have been described, those skilled in the art will appreciate that many other embodiments and modifications thereof may be made without departing from the scope and spirit of the present invention.

[0023] Figure 1 is a diagram illustrating a memory system 10 according to an embodiment of the present disclosure.

[0024] refer to Figure 1 The memory system 10 may store data to be accessed by a host 20 such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), an in-vehicle infotainment system, etc. The host 20 may include a host memory 21 .

[0025] The memory system 10 may form various types of storage devices according to an interface protocol coupled to the host 20. For example, the memory system 10 may be configured by one of various types of storage devices such as a solid state drive (SSD); multimedia cards in the form of MMC, eMMC, RS-MMC, and micro-MMC; secure digital cards in the form of SD, mini-SD, and micro-SD; a universal serial bus (USB) storage device; a universal flash memory (UFS) device; a personal computer memory card international association (PCMCIA) card type storage device; a peripheral component interconnect (PCI) card type storage device; a PCI-Express (PCI-E) card type storage device; a compact flash (CF) card; a smart media card; a memory stick, etc.

[0026] The memory system 10 may be implemented as one of various types of packages such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0027] The memory system 10 may include a nonvolatile memory device 100 and a controller 200 .

[0028] The nonvolatile memory device 100 may operate as a storage medium of the memory system 10. The nonvolatile memory device 100 may be implemented as one of various nonvolatile memory devices such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magnetoresistive (TMR) layer, a phase change random access memory (PRAM) using a chalcogenide alloy, and a resistive random access memory (ReRAM) using a transition metal compound, according to the type of memory cells constituting the nonvolatile memory device.

[0029] Although already Figure 1 The memory system 10 is illustrated in FIG. 1 to include a single nonvolatile memory device 100 , but the memory system 10 may include a plurality of nonvolatile memory devices 100 .

[0030] The nonvolatile memory device 100 may include a memory cell array 110 (see Fig.11 ), the memory cell array 110 includes a plurality of memory cells MC arranged in a region where a plurality of word lines WL1 to WLm and a plurality of bit lines BL1 to BLn cross each other. The memory cell array 110 may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of pages.

[0031] For example, each memory cell in the memory cell array may be a single-level cell (SLC) capable of storing a single bit of data (e.g., 1-bit data) or a multi-level cell (MLC) capable of storing 2 or more bits of data. An MLC may store 2 bits of data, 3 bits of data, 4 bits of data, and the like. Typically, a memory cell capable of storing 2 bits of data may be referred to as an MLC, a memory cell capable of storing 3 bits of data may be referred to as a three-level cell (TLC), and a memory cell capable of storing 4 bits of data may be referred to as a quad-level cell (QLC). However, for the sake of clarity, in the disclosed embodiments, memory cells storing 2 or more bits of data may be collectively referred to as MLCs.

[0032] The memory cell array 110 may include at least one or more memory cells of SLC and MLC types. The memory cell array 110 may include memory cells arranged in a two-dimensional (2D) (eg, horizontal) structure or memory cells arranged in a 3D (eg, vertical) structure. Fig.11 The nonvolatile memory device 100 is described in detail.

[0033] The controller 200 may include a host interface 210, a processor 220, a memory 230, a memory interface 240, a memory control module 250, and an address unit 260. The controller 200 may control the overall operation of the memory system 10 by driving the firmware or software loaded into the memory 230. The controller 200 may decode and drive code-based instructions or algorithms such as firmware or software. The controller 200 may be implemented using hardware or a combination of hardware and software.

[0034] Although not in Figure 1 2 , but the controller 200 may further include, for example, other well-known circuits such as an error correction code (ECC) engine that generates parity by performing ECC encoding on write data provided from the host 20 and uses the parity to perform ECC decoding on read data read from the nonvolatile memory device 100. All elements included in the controller 200 may be coupled to each other through an internal bus generally indicated by a double arrow.

[0035] The host interface 210 may interface the memory system 10 with the host 20 according to the protocol of the host 20. For example, the host interface 210 may communicate with the host 20 through any one of the USB protocol, the UFS protocol, the MMC protocol, the Parallel Advanced Technology Attachment (PATA) protocol, the Serial Advanced Technology Attachment (SATA) protocol, the Small Computer System Interface (SCSI) protocol, the Serial Attached SCSI (SAS) protocol, the PCI protocol, and the PCI-E protocol. The host interface 210 may be coupled to the host 20 through a host channel. Through the host channel, the host 20 may transmit a command (or request or instruction) CMD, an address ADRR to the memory system 10, and send / receive data DATA to / from the memory system 10.

[0036] The processor 220 may include a microcontroller unit (MCU) and / or a central processing unit (CPU). The processor 220 may process a request sent from the host 20. In order to process the request sent from the host 20, the processor 220 may drive a code-based instruction or algorithm (e.g., firmware) loaded into the memory 230 and control internal functional blocks (such as the host interface 210, the memory 230, the memory interface 240, and the non-volatile memory device 100).

[0037] The processor 220 may generate a control signal for controlling the operation of the nonvolatile memory device 100 based on a request transmitted from the host 20 , and provide the generated control signal to the nonvolatile memory device 100 through the memory interface 240 .

[0038] The memory 230 may include a random access memory (RAM) such as a dynamic random access memory (DRAM) and a static random access memory (SRAM). The memory 230 may store firmware driven by the processor 220. The memory 230 may also store data (e.g., metadata) required to drive the firmware. For example, the memory 230 may operate as a working memory of the processor 220.

[0039] In an embodiment, the memory 230 may include areas for various purposes (such as an area for storing a flash translation layer (FTL), an area used as a command queue (CMDQ) for queuing commands corresponding to requests provided from the host 20, an area used as a write data buffer to temporarily store write data, an area used as a read data buffer to temporarily store read data, and an area used as a mapping cache buffer to cache mapping data).

[0040] The memory interface 240 may control the nonvolatile memory device 100 under the control of the processor 220. The memory interface 240 may also be referred to as a memory controller. The memory interface 240 may provide a control signal to the nonvolatile memory device 100 through a channel CH. The control signal may include a command, an address, an operation control signal, etc. for controlling the nonvolatile memory device 100. The memory interface 240 may provide data stored in a data buffer to the nonvolatile memory device 100 or store data transmitted from the nonvolatile memory device 100 in the data buffer.

[0041] The memory control module 250 may access the memory 230 and the host memory 21 according to a command from the processor 220 to perform data processing.

[0042] For example, when the access address included in the command from the processor 220 is the address of the memory 230, the memory control module 250 can process the data by accessing the memory 230. In addition, when the access address included in the command from the processor 220 is the address of the host memory 21, the memory control module 250 can process the data by accessing the host memory 21.

[0043] The address of the host memory 21 included in the command from the processor 220 may be a virtual address of a host memory buffer (HMB) mapping table managed by the address unit 260. For example, the memory control module 250 may convert the virtual address into the address of the host memory 21 through the address unit 260, and then access the host memory 21 based on the address of the host memory.

[0044] The address unit 260 may convert the virtual address into the address of the host memory 21 so that the memory control module 250 may access the host memory 21. The address unit 260 may be operably disposed between the memory control module 250 and the host interface 210. Figure 5 In an embodiment, the address unit 260 may be physically located between the memory control module 250 and the host interface 210, such as Figure 5 shown.

[0045] Figure 1 The configuration of the controller in FIG. 20 is illustrated only as an example, and the controller 200 may be implemented to include other components in addition to the components included in the controller 200 .

[0046] Figure 2 and Figure 3 Is a description Figure 1 A diagram of a method of operation of the memory system 10 is shown.

[0047] refer to Figure 2 In step S210, the host 20 may allocate a portion of the host memory 21 to be used by the memory system 10. Hereinafter, the allocated host memory region may be referred to as an HMB. For example, the HMB may represent a portion of the host memory 21 that is set by the host 20 to allow the controller to access the host memory 21. Figure 3 As shown in (a), the host 20 may allocate part of host memory regions Region_2, Region_4, Region_6, Region_8, and Region_10 (hereinafter referred to as HMB_0, HMB_1, HMB_2, HMB_3, and HMB_4) among host memory regions Region_0 to Region_11 included in the host memory 21 as HMB regions.

[0048] In an embodiment, the allocated host memory areas (ie, HMB areas) may have different sizes from each other. Figure 3 As shown in (a), the HMB areas HMB_0 and HMB_1 may have sizes different from each other.

[0049] In an embodiment, the allocated host memory area may be arranged non-contiguously. Figure 3 As shown in (a), the unallocated host memory region Region_3 may be arranged between the allocated host memory regions HMB_0 and HMB_1.

[0050] In step S220, the memory system 10 may divide the HMB into preset sizes, such as Figure 3 As shown in (b) in the figure. Figure 3 As shown in (b), the address unit 260 may generate a plurality of sub host memory areas sub_0 to sub_10 (ie, sub HMB areas) by dividing the HMB including the HMB areas HMB_0 to HMB_4 by a preset size.

[0051] In an embodiment, the preset size may correspond to a unit of data processed by the controller 200 .

[0052] In step S230, the memory system 10 may specify (or determine) index values ​​for the plurality of sub-host memory regions sub_0 to sub_10 (i.e., sub-HMB regions). For example, the address unit 260 may specify index values ​​for the physical addresses of the plurality of sub-host memory regions sub_0 to sub_10 based on the base address, such as Figure 3 As shown in (b).

[0053] In an embodiment, the base address may be the address of an HMB area (e.g., HMB_0) having a minimum physical address value among multiple HMB areas HMB_0 to HMB_4 constituting the HMB, or the address of a sub-host memory area (e.g., sub_0) having a minimum physical address value among multiple sub-host memory areas sub_0 to sub_10 (i.e., sub-HMB areas).

[0054] At step S240, the memory system 10 may specify virtual addresses for the plurality of sub-host memory regions sub_0 to sub_10. The address unit 260 may assign offset indexes to the plurality of sub-host memory regions sub_0 to sub_10 in ascending index order. For example, Figure 3 As shown in (c), the address unit 260 may assign offset indexes to a plurality of sub-host memory areas sub_0 to sub_10 from a sub-host memory area having a lowest index value (e.g., sub_0) to a sub-host memory area having a highest index value (e.g., sub_10) among the plurality of sub-host memory areas.

[0055] In an embodiment, the virtual addresses of the plurality of sub-host memory areas sub_0 to sub_10 may be linear addresses which are consecutively allocated addresses.

[0056] At step S250, the memory system 10 may generate an HMB mapping table. For example, the address unit 260 may generate an HMB mapping table in which the index values ​​and virtual addresses of the plurality of sub-host memory regions sub_0 to sub_10 are mapped, such as Figure 3 Even when the host 20 can allocate the host memory area of ​​the host memory 21 (as the HMB area constituting the HMB) discontinuously to the memory system 10, the memory control module 250 can access the HMB using the virtual addresses (i.e., linear addresses) sequentially mapped to the multiple sub-host memory areas in the HMB mapping table, and thus the memory control module 250 can recognize that the HMB exists as a separate memory (such as a single SRAM).

[0057] In an embodiment, the address unit 260 may store the generated HMB mapping table.

[0058] Figure 4 and Figure 5 Is a description Figure 1 A diagram of a method of operation of the memory system 10 is shown.

[0059] refer to Figure 4 In step S410, the memory system 10 may receive a data processing command. For example, the controller 200 may receive a command for a data processing operation (such as data read, data write, etc.) from the host 20.

[0060] In step S420, the memory system 10 may determine whether to access the host memory 21 included in the host 20 or the memory 230 included in the controller 200. For example, the controller 200 may determine whether the address of the memory area to be accessed is the address of the HMB or the address of the memory 230. That is, when the address of the memory area is a virtual address included in the HMB mapping table, the controller 200 may determine that the HMB is to be accessed.

[0061] At step S430, when the address of the memory area is a virtual address (ie, in the case of "yes" at step S420), the memory system 10 may convert the virtual address into a physical address of the host memory 21. For example, Figure 5As shown, the memory control module 250 may send an access request including a target virtual address (e.g., virtual address 3) among a plurality of virtual addresses to the address unit 260 for data processing (①). The address unit 260 may change the target virtual address (e.g., virtual address 3) included in the access request to a target index value (e.g., index 4) based on the HMB mapping table, the target index value being the index value mapped to the target virtual address (②). The address unit 260 may ultimately convert the virtual address mapped to index 4 into a physical address of the host memory 21. For example, the address unit 260 may determine an address in which the address value corresponding to index 4 is added to the physical address of the sub-HMB area sub_0 as the physical address of the host memory 21 to be accessed by the controller 200.

[0062] In step S440, the memory system 10 may access the host memory 21. For example, Figure 5 As shown, when the address of the memory area to be accessed for data processing is the address of the HMB, the memory control module 250 can access (i.e., store data therein or read stored data therefrom) a sub-HMB area (e.g., sub_4) (③) within the address of the host memory 21 that corresponds to the target offset value.

[0063] At step S450, in the case of “No” at step S420, the memory system 10 may access the memory 230 of the controller 200. For example, when the address of the memory area to be accessed for data processing is the address of the memory 230 of the controller 200, the memory control module 250 may access the memory 230 of the controller 200 (e.g., store data in the memory 230 or read the stored data from the memory 230).

[0064] Therefore, even when some of the multiple host memory areas included in the host memory 21 are discontinuously allocated as HMB areas, the memory system 10 can manage the HMB using an HMB mapping table in which a virtual address is mapped as a linear address to the discontinuously allocated host memory area, and thus the linearity of the address used to access the host memory 21 can be ensured.

[0065] Figure 6 2 is a block diagram illustrating a data processing system 2000 including a solid state drive (SSD) 2200 according to an embodiment of the present disclosure. Figure 6 , the data processing system 2000 may include a host 2100 and an SSD 2200 .

[0066] The SSD 2200 may include a controller 2210 , a buffer memory 2220 , nonvolatile memory devices 2231 to 223 n , a power supply 2240 , a signal connector 2250 , and a power connector 2260 .

[0067] The controller 2210 may control the overall operation of the SSD 2200 .

[0068] The buffer memory 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 223n. In addition, the buffer memory 2220 may temporarily store data read out from the nonvolatile memory devices 2231 to 223n. According to the control of the controller 2210, the data temporarily stored in the buffer memory 2220 may be transmitted to the host 2100 or the nonvolatile memory devices 2231 to 223n.

[0069] The nonvolatile memory devices 2231 to 223n may be used as storage media of the SSD 2200. The nonvolatile memory devices 2231 to 223n may be coupled to the controller 2210 through a plurality of channels CH1 to CHn, respectively. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to one channel may be coupled to the same signal bus and data bus.

[0070] The power supply 2240 may provide the power PWR input through the power connector 2260 to the inside of the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. The auxiliary power supply 2241 may provide power to allow the SSD 2200 to terminate normally when a sudden power outage (SPO) occurs. The auxiliary power supply 2241 may include a large-capacity capacitor capable of charging the power PWR.

[0071] The controller 2210 may exchange a signal SGL with the host 2100 through the signal connector 2250. The signal SGL may include a command, an address, data, etc. The signal connector 2250 may be configured by various types of connectors according to an interface scheme between the host 2100 and the SSD 2200.

[0072] Figure 7 The diagram is as follows Figure 6 A block diagram of the controller 2210 is shown. Figure 7 , the controller 2210 may include a host interface (H / I) unit 2211, a control unit 2212, a random access memory (RAM) 2213, an error correction code (ECC) unit 2214, and a memory interface (M / I) 2215 unit.

[0073] The host interface unit 2211 may provide a connection between the host 2100 and the SSD 2200 according to a protocol of the host 2100. For example, the host interface unit 2211 may communicate with the host 2100 through any one of SD, USB, MMC, embedded MMC (eMMC), PCMCIA, PATA, SATA, SCSI, SAS, PCI, PCI-E, and UFS protocols. In addition, the host interface unit 2211 may perform a disk emulation function, supporting the host 2100 to recognize the SSD 2200 as a general memory system, such as a hard disk drive (HDD).

[0074] The control unit 2212 may analyze and process a signal SGL input from the host 2100. The control unit 2212 may control operations of internal functional blocks according to firmware or software for driving the SSD 2200. The random access memory 2213 may be used as a working memory for driving such firmware or software.

[0075] The ECC unit 2214 may generate parity data of data to be transmitted to the nonvolatile memory devices 2231 to 223n. The generated parity data may be stored in the nonvolatile memory devices 2231 to 223n together with the data. The ECC unit 2214 may detect an error of the data read out from the nonvolatile memory devices 2231 to 223n based on the parity data. When the detected error is within a correctable range, the ECC unit 2214 may correct the detected error.

[0076] The memory interface unit 2215 may provide control signals such as commands and addresses to the nonvolatile memory devices 2231 to 223n according to the control of the control unit 2212. The memory interface unit 2215 may exchange data with the nonvolatile memory devices 2231 to 223n according to the control of the control unit 2212. For example, the memory interface unit 2215 may provide data stored in the buffer memory 2220 to the nonvolatile memory devices 2231 to 223n, or provide data read out from the nonvolatile memory devices 2231 to 223n to the buffer memory 2220.

[0077] Figure 8 is a diagram illustrating a data processing system 3000 including a memory system 3200 according to an embodiment of the present disclosure. Figure 8 , the data processing system 3000 may include a host 3100 and a memory system 3200 .

[0078] The host 3100 may be configured in the form of a board such as a printed circuit board. Figure 8 , but the host 3100 may include internal functional blocks for performing the functions of the host.

[0079] The host 3100 may include a connection terminal 3110 such as a socket, a slot, or a connector. The memory system 3200 may be mounted on the connection terminal 3110 .

[0080] The memory system 3200 may be configured in the form of a board such as a printed circuit board. The memory system 3200 may be a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory 3220, nonvolatile memory devices 3231 and 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0081] The controller 3210 may control the overall operation of the memory system 3200. The controller 3210 may be configured to Figure 7 The controller 2210 shown in FIG. 2 is configured in the same manner.

[0082] The buffer memory 3220 may temporarily store data to be stored in the nonvolatile memory devices 3231 and 3232. In addition, the buffer memory 3220 may temporarily store data read out from the nonvolatile memory devices 3231 and 3232. The data temporarily stored in the buffer memory 3220 may be transmitted to the host 3100 or the nonvolatile memory devices 3231 and 3232 according to the control of the controller 3210.

[0083] The nonvolatile memory devices 3231 and 3232 may be used as storage media of the memory system 3200 .

[0084] The PMIC 3240 may provide power input through the connection terminal 3250 to the inside of the memory system 3200. The PMIC 3240 may manage power of the memory system 3200 according to the control of the controller 3210.

[0085] The connection terminal 3250 may be coupled to the connection terminal 3110 of the host 3100. Through the connection terminal 3250, signals such as commands, addresses, and data, and power may be transmitted between the host 3100 and the memory system 3200. The connection terminal 3250 may be configured as various types according to an interface scheme between the host 3100 and the memory system 3200. The connection terminal 3250 may be provided on either side of the memory system 3200.

[0086] Fig. 9 4 is a block diagram illustrating a data processing system 4000 including a memory system 4200 according to an embodiment of the present disclosure. Fig. 9 , the data processing system 4000 may include a host 4100 and a memory system 4200 .

[0087] The host 4100 may be configured in the form of a board such as a printed circuit board (PCB). Fig. 9 Although not shown in the figure, the host 4100 may include internal functional blocks for performing the functions of the host.

[0088] The memory system 4200 may be configured in the form of a surface mount type package. The memory system 4200 may be mounted on the host 4100 through solder balls 4250. The memory system 4200 may include a controller 4230, a buffer memory 4220, and a nonvolatile memory device 4210.

[0089] The controller 4230 may control the overall operation of the memory system 4200. The controller 4230 may be configured to Figure 7 The controller 2210 shown in FIG. 2 is configured in the same manner.

[0090] The buffer memory 4220 may temporarily store data to be stored in the nonvolatile memory device 4210. In addition, the buffer memory 4220 may temporarily store data read out from the nonvolatile memory device 4210. The data temporarily stored in the buffer memory 4220 may be transmitted to the host 4100 or the nonvolatile memory device 4210 according to the control of the controller 4230.

[0091] The nonvolatile memory device 4210 may be used as a storage medium of the memory system 4200 .

[0092] Fig.10 is a diagram illustrating a network system 5000 including a memory system 5200 according to an embodiment of the present disclosure. Fig.10 , the network system 5000 may include a server system 5300 and a plurality of client systems 5410 to 5430 coupled to each other through a network 5500 .

[0093] The server system 5300 may serve data in response to requests from the plurality of client systems 5410 to 5430. For example, the server system 5300 may store data provided from the plurality of client systems 5410 to 5430. The server system 5300 may provide data to the plurality of client systems 5410 to 5430.

[0094] The server system 5300 may include a host 5100 and a memory system 5200. The memory system 5200 may be composed of Figure 1 The memory system 10 shown, Figure 6 The memory system 2200 shown, Figure 8 The memory system 3200 or Fig. 9 Memory system 4200 configuration is shown.

[0095] Fig.11 yes Figure 1 A detailed diagram of a nonvolatile memory device 100 included in the memory system 10 is shown. Fig.11 , the nonvolatile memory device 100 may include a memory cell array 110 , a row decoder 120 , a data read / write (R / W) block 130 , a column decoder 140 , a voltage generator 150 , and control logic 160 .

[0096] The memory cell array 110 may include memory cells MC arranged in regions where word lines WL1 to WLm and bit lines BL1 to BLn cross each other.

[0097] The row decoder 120 may be coupled to the memory cell array 110 through the word lines WL1 to WLm. The row decoder 120 may operate according to the control of the control logic 160. The row decoder 120 may decode an address provided from an external device (not shown). The row decoder 120 may select and drive the word lines WL1 to WLm based on the decoding result. For example, the row decoder 120 may provide a word line voltage provided from the voltage generator 150 to the word lines WL1 to WLm.

[0098] The data read / write block 130 may be coupled to the memory cell array 110 through the bit lines BL1 to BLn. The data read / write block 130 may include read / write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn. The data read / write block 130 may operate according to the control of the control logic 160. The data read / write block 130 may operate as a write driver or a sense amplifier according to the operation mode. For example, the data read / write block 130 may be used as a write driver for storing data provided from an external device in the memory cell array 110 in a write operation. In another example, the data read / write block 130 may be used as a sense amplifier for reading data from the memory cell array 110 in a read operation.

[0099] The column decoder 140 may operate according to the control of the control logic 160. The column decoder 140 may decode an address provided from an external device. The column decoder 140 may couple a data input / output line (or a data input / output buffer) with read / write circuits RW1 to RWn of the data read / write block 130 corresponding to the bit lines BL1 to BLn, respectively, based on the decoding result.

[0100] The voltage generator 150 may generate a voltage used in an internal operation of the nonvolatile memory device 100. The voltage generated by the voltage generator 150 may be applied to the memory cells MC of the memory cell array 110. For example, the program voltage generated in a program operation may be applied to the word line of the memory cell on which the program operation is to be performed. In another example, the erase voltage generated in an erase operation may be applied to the well region of the memory cell on which the erase operation is to be performed. In yet another example, the read voltage generated in a read operation may be applied to the word line of the memory cell on which the read operation is to be performed.

[0101] The control logic 160 may control the overall operation of the nonvolatile memory device 100 based on a control signal provided from an external device. For example, the control logic 160 may control the operation of the nonvolatile memory device 100, such as read, write, and erase operations of the nonvolatile memory device 100.

[0102] The above embodiments of the present invention are intended to illustrate rather than limit the present invention. Various alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any particular type of semiconductor device. In view of this disclosure, other additions, reductions or modifications are obvious and are intended to fall within the scope of the appended claims.

Claims

1. A controller for controlling a non-volatile memory device according to a request from a host having a host memory, the controller comprising: an address unit configured to divide an area of ​​the host memory allocated as a host memory buffer HMB to generate a plurality of sub-HMB areas, determine index values ​​of the plurality of sub-HMB areas, and generate an HMB mapping table by mapping a virtual address to the index value; as well as a memory control module configured to access at least one of the plurality of sub-HMB areas based on the HMB mapping table, wherein the virtual addresses are set to consecutive values ​​with respect to the plurality of sub-HMB areas, wherein the HMB is an area set by the host to allow the controller to use the host memory, and The index value of each of the sub-HMB areas is configured to specify a physical address of each of the sub-HMB areas. 2 . The controller of claim 1 , wherein the address unit determines the index value based on the physical address of the sub-HMB area corresponding to a minimum address value among the physical addresses of the plurality of sub-HMB areas. 3 . The controller according to claim 1 , wherein the address unit maps the virtual addresses to the index values ​​sequentially in ascending order from a minimum index value among the index values.

4. The controller according to claim 1, wherein when the memory control module requests to access the host memory using a virtual address, the address unit converts the virtual address into an index value mapped to the virtual address based on the HMB mapping table, and determines the physical address of the host memory according to the converted index value. 5 . The controller according to claim 1 , wherein the address unit divides a plurality of areas of the host memory by a unit of data processed in the controller. 6 . The controller according to claim 1 , wherein the plurality of regions allocated as the HMB include at least one region having a size different from sizes of other regions. 7 . The controller according to claim 1 , wherein a physical address of at least one sub-HMB area among the plurality of sub-HMB areas is not continuous with physical addresses of other sub-HMB areas.

8. An operating method of a controller for controlling a non-volatile memory device according to a request from a host having a host memory, the method comprising: Dividing a region of the host memory allocated as a host memory buffer HMB to generate a plurality of sub-HMB regions; determining index values ​​for addresses of the plurality of sub-HMB regions; and Generate an HMB mapping table by mapping the virtual address to the determined index value, wherein the virtual addresses are set to consecutive values ​​with respect to the plurality of sub-HMB areas, wherein the HMB is an area set by the host to allow the controller to use the host memory, and The index value of each of the sub-HMB areas is configured to specify a physical address of each of the sub-HMB areas.

9. The operating method according to claim 8, wherein determining the index value comprises: The index value is determined based on the physical address of the sub-HMB area corresponding to a minimum address value among the physical addresses of the plurality of sub-HMB areas.

10. The operating method according to claim 8, wherein generating the HMB mapping table comprises: The virtual addresses are sequentially mapped to the index values ​​in ascending order from a minimum index value among the index values.

11. The operating method according to claim 8, further comprising: Based on the HMB mapping table, convert the virtual address into an index value mapped to the virtual address; as well as The physical address of the host memory is accessed according to the converted index value. 12 . The operating method according to claim 8 , wherein the plurality of areas of the host memory are divided by a unit of data processed in the controller. 13 . The operating method according to claim 8 , wherein the plurality of areas allocated as the HMB include at least one area having a size different from sizes of other areas. 14 . The operating method according to claim 8 , wherein a physical address of at least one sub-HMB area among the plurality of sub-HMB areas is not continuous with physical addresses of other sub-HMB areas.

15. A memory system comprising: a non-volatile memory device; as well as a controller configured to control the nonvolatile memory device according to a request from a host having a host memory, wherein the controller divides an area of ​​the host memory allocated as a host memory buffer HMB to generate a plurality of sub-HMB areas, determines offset values ​​for addresses of the plurality of sub-HMB areas, and generates an HMB mapping table by mapping a virtual address to the offset value, wherein the HMB is an area set by the host to allow the controller to use the host memory, and The offset value of each of the sub-HMB areas is configured to specify a physical address of each of the sub-HMB areas. 16 . The memory system of claim 15 , wherein the controller accesses at least one of the plurality of sub-HMB areas by converting at least one target virtual address among the virtual addresses into an offset value mapped to the target virtual address based on the HMB mapping table.

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