Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, which relate to the field of wafer packaging and testing technology. The semiconductor device comprises: a substrate; a dielectric layer located on a side surface away from the substrate; a pad located on the dielectric layer; and a barrier formed on the pad so as to divide the pad into a welding pad and a test pad. By forming a barrier on the pad layer to divide the pad layer into a welding pad and a test pad, the area damaged by the probe and the welding pad will not affect each other, thereby improving the yield and stability of the chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, semiconductor devices are increasingly used in production and life. Semiconductor devices, such as chips, usually require pads to be designed to achieve external connections. However, the pads and external connecting wires often have unstable connections, which affects the electrical connection between the pads and other external semiconductor components and reduces the yield and stability of semiconductor devices.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, which can at least to some extent overcome the technical problem of instability of the semiconductor device caused by the limitations and defects of the related art.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0006] substrate;

[0007] A dielectric layer, located on one side of the substrate;

[0008] A pad, located on a surface of the dielectric layer away from the substrate;

[0009] The barrier protrudes from the surface of the pad away from the substrate, thereby dividing the pad into a welding pad and a testing pad.

[0010] In an embodiment, the dielectric layer comprises a second through hole communicating with the pad, and the barrier is located above the second through hole.

[0011] In an embodiment, there is a void in the filling material of the second through hole.

[0012] In an embodiment, the second through hole has a width of 0.1-0.3 um and a depth of 0.25-0.65 um, and a ratio of the depth to the width of the second through hole is >2:1.

[0013] In an embodiment, the barrier is rectangular or elliptical, the width of the barrier is 1 um to 20 um, the length of the barrier is 50 um to 80 um, and the height of the barrier is 100 nm to 6 um.

[0014] In an embodiment, the substrate includes a wiring layer, the wiring layer includes soldering wires, and the soldering wires are connected to the soldering pads through conductive pillars passing through the dielectric layer.

[0015] In an embodiment, the pad structure further includes a protection layer located on a side of the dielectric layer away from the substrate and exposing the pad.

[0016] In an embodiment, the material of the protective layer is one or more combinations of polyimide and tetraethyl orthosilicate.

[0017] In an embodiment, the pad structure further includes a passivation layer located between the protection layer and the dielectric layer.

[0018] In an embodiment, the material of the pad, the barrier and the filling material in the second through hole are the same, and the material of the pad is one of copper, aluminum, tungsten, titanium, gold, silver or an alloy of the above materials.

[0019] According to another aspect of the present disclosure, there is also provided a method for manufacturing a semiconductor device, comprising:

[0020] providing a substrate;

[0021] forming a dielectric layer on the substrate;

[0022] forming a second through hole in the dielectric layer by etching;

[0023] A pad layer is formed on the dielectric layer, and a barrier is formed above the second through hole, so that the pad layer is divided into a welding pad and a test pad by the barrier.

[0024] In an embodiment, forming a second through hole in the dielectric layer by etching comprises:

[0025] forming a photoresist layer on a surface of the dielectric layer away from the substrate;

[0026] Expose through a mask plate to transfer the pattern of the mask plate to the photoresist layer;

[0027] Developing the photoresist layer so that the region where the second through hole is to be opened is exposed;

[0028] Etching to form the second through hole in the area where the second through hole is to be opened;

[0029] The photoresist layer is removed.

[0030] In an embodiment, forming a pad layer on the dielectric layer and forming a barrier above the second through hole includes: forming a pad layer on the dielectric layer by physical vapor deposition, forming a gap when filling the second through hole during the physical vapor deposition process, and forming the barrier above the second through hole.

[0031] In one embodiment, the method further comprises:

[0032] forming a passivation layer on the pad and the dielectric layer;

[0033] depositing a protective layer on the passivation layer;

[0034] exposing and developing the protective layer to expose the passivation layer on the pad;

[0035] The exposed passivation layer is removed by etching to expose the pad.

[0036] In an embodiment, the passivation layer is a pad silicon oxide layer or a pad silicon nitride layer, and the material of the protection layer is a combination of one or more of polyimide and tetraethyl orthosilicate (TEOS).

[0037] By forming a barrier on the pad layer to divide the pad layer into welding pads and test pads, the mutual influence between the area damaged by the probe and the welding pad is avoided, thereby improving the stability of the chip.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0040] Figure 1 A cross-sectional view showing a semiconductor device in the related art;

[0041] Figure 2 A cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure;

[0042] Figure 3 A diagram showing the effect of using a semiconductor device according to an embodiment of the present disclosure;

[0043] Figure 4 A cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure;

[0044] Figure 5A A flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0045] Figure 5B A flow chart showing a method of forming a second through hole by a mask-photolithography process in one embodiment of the present disclosure;

[0046] Figure 6A-6J A cross-sectional view showing various stages in a method for manufacturing a semiconductor device according to another embodiment of the present disclosure;

[0047] Figure 7 A top view of a semiconductor device in one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted.

[0050] In related technologies, such as Figure 1 As shown, the pad 04 on the semiconductor device is usually used as a test pad for contacting with a test probe and as a welding pad for connecting with a conductive connection line 01. However, when the semiconductor device is tested, the contact between the test probe and the pad 04 is likely to cause damage 02 to the pad 04, such as scratches or dust. These pad damages 02 are likely to cause an unreliable connection between the pad 04 and the conductive connection line 01, and the conductive connection line 01 (i.e., the package bonding wire) is likely to fall off, affecting the electrical connection between the semiconductor device and other external semiconductor components, and reducing the yield and stability of the semiconductor device.

[0051] In an embodiment of the present disclosure, a semiconductor device including a pad structure is provided, such as Figure 2 As shown, the semiconductor device includes a substrate 301, a dielectric layer 302 located on one side of the substrate 301; pads 308 and 309 located on the surface of the dielectric layer 302 away from the substrate 301; and a barrier 307 protruding from the surface of the pad away from the substrate 301 so as to divide the pad into a welding pad 308 and a test pad 309.

[0052] In the pad structure in the above embodiment, the welding pad 308 is used to connect to the conductive connecting line 01, and the test pad 309 is used to contact the test probe. The welding pad 308 and the test pad 309 are isolated by the barrier 307. Therefore, even if the test pad 309 is damaged when contacting the test probe 02, it will not affect the welding pad 308, so that the welding pad 308 can be effectively connected to the conductive connecting line 01, thereby improving the yield and stability of the semiconductor device.

[0053] like Figure 2 As shown, the substrate 301 may include a dielectric layer 3011 and a wiring layer 3012. The wiring layer 3012 may be disposed between the dielectric layer 3011 and the dielectric layer 302.

[0054] The material of the dielectric layer 3011 can be selected and determined according to the design requirements of the semiconductor device, and can be an organic insulating material, an inorganic insulating material, or a mixed material of an organic insulating material and an inorganic insulating material. For example, in one embodiment, the material of the dielectric layer 3011 can be one of silicon oxide, silicon nitride, and silicon oxynitride, or any combination thereof. It is understood that the dielectric layer 3011 can be a single insulating material layer, or can be formed by stacking multiple layers of different insulating materials.

[0055] like Figure 2 As shown, the wiring layer 3012 may include a welding wire 3031, and the welding wire 3031 may be connected to the welding pad 308 for connecting the semiconductor device to an external circuit. The orthographic projection of the welding pad 308 on the wiring layer 3012 may at least partially overlap with the welding wire 3031, and the welding pad 308 and the welding wire 3031 may be connected via the first conductive column 304 passing through the dielectric layer 302.

[0056] When preparing the first conductive pillar 304, a first through hole may be formed in the dielectric layer 302, and the first through hole may expose the surface of the welding wire 3031; and then when forming the welding pad 308, the material used to form the welding pad 308 is filled in the first through hole to form the first conductive pillar 304. The first conductive pillar 304 can not only realize the connection between the welding pad 308 and the welding wire 3031, but also realize the support of the welding pad 308, and when the conductive connection wire 01 is bonded or welded to the welding pad 308, the support force of the welding pad 308 is effectively improved, thereby improving the yield rate of the semiconductor device.

[0057] The material of the dielectric layer 302 can be selected and determined according to the design requirements of the semiconductor device, and can be an organic insulating material or an inorganic insulating material. For example, in one embodiment, the material of the dielectric layer 302 can be one of silicon oxide, silicon nitride and silicon oxynitride or any combination thereof. It is understood that the dielectric layer 302 can be a single insulating material layer or a plurality of different insulating material layers stacked together.

[0058] like Figure 2 As shown, the wiring layer 3012 may further include a test wiring 3032. In one embodiment, the test wiring 3032 and the test pad 309 are separated by the dielectric layer 302, and a second conductive column 305 is disposed therebetween, and the second conductive column 305 is not connected to the test wiring 3032. When preparing the second conductive column 305, a second through hole is first formed in the dielectric layer 302, and the second through hole does not expose the surface of the test wiring 3032; then, when forming the test pad 309, the material used to form the test pad 309 is filled in the second through hole to form the second conductive column 305.

[0059] In another embodiment, Figure 4 As shown, the test wiring 3032 and the test pad 309 are separated by the dielectric layer 302, and the two are connected by the second conductive column 305. When preparing the second conductive column 305, a second through hole is first formed in the dielectric layer 302, and the second through hole exposes the surface of the test wiring 3032; then when forming the test pad 309, the material used to form the test pad 309 can be filled in the second through hole to form the second conductive column 305. The second conductive column 305 can not only realize the connection between the test pad 309 and the test wiring 3032, but also realize the support of the test pad 309 and the welding pad 308.

[0060] The barrier 307 protrudes from the surface of the pad away from the substrate 301, thereby dividing the pad into a welding pad 308 and a test pad 309. In one embodiment, the barrier 307 is located above the second through hole. The barrier can be rectangular or elliptical. In one embodiment, the width of the barrier is 1um to 20um, the length of the barrier is 50um to 80um, and the height of the barrier is 100nm to 6um. For example, the width of the barrier can be 2um, 5um, 7um, 10um, 15um or 18um, the length of the barrier can be 60um or 70um, and the height of the barrier can be 300nm, 500nm, 800nm, 1um, 3um or 5um.

[0061] like Figure 3As shown, when the test probe 03 moves to the edge of the test pad 309, it will be blocked by the side wall of the barrier 307, so that the test probe 03 can only move within the test pad 309 area, so that the damage 02 will only occur within the test pad 309 area. Therefore, this can reduce the possibility of the test probe 03 mistakenly entering the welding pad 308 when the surface of the test pad 309 deviates, reduce the damage to the welding pad 308, ensure the structural integrity of the welding pad 308, and improve the yield and stability of semiconductor device packaging.

[0062] The pad may be rectangular with an aspect ratio of 1:1 to 2:1. In one embodiment, the pad is square. Accordingly, the welding pad 308 and the test pad 309 divided by the barrier 307 may also be rectangular, for example, the welding pad 308 and the test pad 309 are square. The material of the pad may be one of copper, aluminum, tungsten, titanium, gold, silver, or an alloy of the above materials. In one embodiment, the material of the welding pad 308, the test pad 309, and the barrier 307 is the same as the filling material in the second through hole.

[0063] In one embodiment, the semiconductor device further includes a protective layer 311, which is located on a side of the dielectric layer 302 away from the substrate 301 and exposes the pad, wherein the material of the protective layer 311 can be a combination of one or more of polyimide and tetraethyl orthosilicate. Figure 2 As shown, the semiconductor device further includes a passivation layer 310 located between the protection layer 311 and the dielectric layer 302. The passivation layer may be a pad silicon oxide layer or a pad silicon nitride layer. The passivation layer may be one layer or multiple layers.

[0064] The method for forming the semiconductor device is described below with reference to the accompanying drawings.

[0065] Figure 5A A flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0066] like Figure 5A As shown, in step S502, a substrate is provided.

[0067] The substrate may include a dielectric layer and a wiring layer, and the wiring layer and the dielectric layer may be one layer or more layers.

[0068] Step S504: forming a dielectric layer on the substrate.

[0069] In a specific implementation, the dielectric layer can be formed by chemical vapor deposition, atomic layer deposition, and the like. It is understandable that the dielectric layer can be a layer of insulating material, or can be a plurality of layers of the same or different insulating materials stacked together. The material of the dielectric layer can be selected and determined according to the design requirements of the semiconductor device, and can be an organic insulating material or an inorganic insulating material. In an exemplary embodiment of the present disclosure, the material of the dielectric layer can be one or more of silicon oxide, silicon nitride, amorphous silicon, or silicon oxynitride.

[0070] Step S506: forming a second through hole in the dielectric layer by etching.

[0071] The second through hole can be formed in the dielectric layer by a mask-photolithography process, and the etching can be dry etching or wet etching. In one embodiment, the width of the second through hole is 0.1-0.3um, the depth is 0.25-0.65um, and the ratio of the depth to the width of the second through hole is >2:1. For example, the width of the second through hole is 0.2um, the depth is 0.5um, and the ratio of the depth to the width of the second through hole is 2.5:1.

[0072] Step S508 , forming a pad layer on the dielectric layer, and forming a barrier above the second through hole, so that the pad layer is divided into a welding pad and a test pad by the barrier.

[0073] In one embodiment, a pad layer located on the dielectric layer can be formed by physical vapor deposition, and the material forming the pad layer can be filled in the second through hole. When the width of the second through hole is small, the filling material in the second through hole forms a void, thereby forming a barrier above the pad layer and at a position corresponding to the second through hole. In one embodiment, the barrier is rectangular or elliptical, the width of the barrier is 1um to 20um, the length of the barrier is 50um to 80um, and the height of the barrier is 100nm to 6um. The material of the pad layer can be one of copper, aluminum, tungsten, titanium, gold, silver, or an alloy of the above materials. In another embodiment, the pad layer and the barrier located on the dielectric layer can be formed by electroplating.

[0074] In the above embodiment, a barrier is formed on the pad layer, thereby dividing the pad layer into a welding pad and a test pad, so that the area damaged by the probe and the welding pad will not affect each other, thereby improving the yield and stability of the chip without incurring additional costs. The barrier is naturally formed during the process of filling the second through hole in the dielectric layer, does not require a separate process, is low in cost, and is easy to implement.

[0075] Figure 5B A flow chart of forming a second through hole by a mask-photolithography process in one embodiment of the present disclosure is shown.

[0076] like Figure 5B As shown, the mask lithography process may include:

[0077] Step S5601, forming a photoresist layer on the surface of the dielectric layer;

[0078] Step S5602, performing exposure through a corresponding mask plate to transfer the pattern of the mask plate to the photoresist layer;

[0079] Step S5603, exposing the photoresist layer through development to expose the area where the second through hole is to be opened, and the second through hole is located in the pad area;

[0080] Step S5604, forming a second through hole by etching, wherein the etching may be dry etching, wet etching or plasma etching;

[0081] Step S5605, removing the photoresist layer to obtain a second through-hole structure.

[0082] Figures 6A-6J Cross-sectional views showing various stages in a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0083] like Fig. 6A As shown, a substrate 301 and a dielectric layer 302 formed on the substrate 301 are provided. The substrate 301 includes a wiring layer, and the wiring layer includes a welding wiring 3031 and a test wiring 3032.

[0084] like Figure 6B As shown, a photoresist layer 320 is formed on the dielectric layer 302, and a through-hole pattern is photolithographically processed, and exposure and development are performed through a corresponding mask plate to transfer the pattern of the mask plate to the dielectric layer.

[0085] like Figure 6C-1 As shown, the first through hole 304 and the second through hole 305 are formed by etching, and the photoresist 320 is removed. The first through hole 304 is connected to the welding wiring 3031, while the second through hole 305 is not connected to the test wiring 3032. By etching, the opening portion not covered and protected by the photoresist is removed to form the first through hole 304 and the second through hole 305. The etching method can be dry etching, wet etching or plasma etching. In another embodiment of the present disclosure, as shown in FIG. Figure 6C-2 As shown, the first through hole 304 is connected to the welding wire 3031 , and the second through hole 305 is connected to the test wire 3032 .

[0086] like Fig.6DAs shown, the pad layer is formed by physical vapor deposition or electroplating, and during the deposition process, metal materials such as copper, aluminum, tungsten, etc. fill the first through hole 304 and the second through hole 305. Since the second through hole 305 is narrow, it is sealed in advance during the deposition process to generate a void, and a barrier 307 is formed on the pad layer; the pad layer is divided into a welding pad 308 and a test pad 309 by the barrier 307.

[0087] like Fig. 6E As shown, a photoresist layer 322 is formed on the pad layer and the barrier 307 .

[0088] like Fig. 6F As shown, the pad pattern is photolithographically processed on the photoresist layer 322. Exposure and development are performed through a corresponding mask plate to remove the photoresist outside the pad area.

[0089] like Figure 6G As shown, the pad layer material in the area outside the pad area is removed by etching, and the material in the pad area is retained because of the photoresist coverage.

[0090] like Figure 6H As shown, a passivation layer 310 is formed on the dielectric layer 302, the pads 308, 309 and the barrier 307. The passivation layer 310 may be one or more layers, and the material of the passivation layer 310 may be silicon oxide or silicon nitride. In one embodiment, the passivation layer includes a layer of silicon nitride and a layer of silicon oxide.

[0091] like Fig.6I As shown, a protective layer 311 is formed on the passivation layer 310, and the protective layer 311 is exposed, developed and etched to expose the passivation layer 310 on the pad area. The method for forming the protective layer can be chemical vapor deposition, atomic layer deposition, etc. The material of the protective layer can be one or more combinations of materials such as polyimide (polyimide), tetraethyl orthosilicate (TEOS), etc.

[0092] like Figure 6J As shown, the exposed passivation layer 310 is removed by etching, thereby exposing the pad areas 308, 309 and the barrier 307 for testing and connecting wires.

[0093] It should be noted that during the deposition process, there may be a slight depression in the pad layer above the first through hole 305. In one embodiment, the top of the barrier 307 is in the shape of a crater.

[0094] In the above embodiment, the second through hole is generated in the process of forming the first through hole for connecting the wiring. The characteristics of the second through hole are used to naturally generate a barrier when generating the pad layer. No additional process steps are required and no additional costs are incurred, which has good advantages and effects.

[0095] A semiconductor device formed by a semiconductor manufacturing method similar to the above is Figure 6J As shown, the semiconductor device includes a substrate 301, a dielectric layer 302, which is located on a side surface away from the substrate 301; there are a first through hole 304 and a second through hole 305 in the dielectric layer, and the first through hole 304 is connected to the welding wiring 3031; a pad located on the dielectric layer 302, the first through hole 304 and the second through hole 305 are filled with pad material, wherein the filling material filled in the second through hole 305 has a gap 306; a barrier 307 is formed above the second through hole 305 on the pad to divide the pad into a welding pad 308 and a test pad 309.

[0096] In the above embodiment, a barrier is formed on the pad layer to divide the pad into a welding pad and a test pad, so that the area damaged by the probe and the welding pad will not affect each other, thereby improving the yield and stability of the chip.

[0097] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc., which shall all be considered as part of the present disclosure.

[0098] The present disclosure also provides a semiconductor device, comprising any one of the pad structures described in the above pad structure implementations. The semiconductor device may be a memory, a processor or other semiconductor integrated circuit devices.

[0099] The pad structure adopted by the semiconductor device of the embodiment of the present disclosure is the same as the pad structure in the embodiment of the above-mentioned pad structure, and therefore has the same beneficial effects, which will not be described in detail here.

[0100] Figure 7 FIG. 2 shows a top view of a semiconductor device in one embodiment of the present disclosure. Figure 7As shown, the top view of the pad area 308, 309 is rectangular, and a protective layer 311 is formed on the outside. The barrier 307 is formed in the pad area, dividing the pad area into two parts 308 and 309, which are used as a welding pad and a test pad, respectively. In one embodiment, the barrier is rectangular or elliptical. In one embodiment, the width of the barrier is 1um to 20um, the length is 50um to 80um, and the height of the barrier is 100nm to 6um. In one embodiment, the pad is rectangular with an aspect ratio of 1:1 to 2:1. In one embodiment, the pad is square. In one embodiment, the barrier 307 divides the pad into the same area of ​​the welding pad 308 and the test pad 309. In another embodiment, the area of ​​the welding pad 308 is larger than the area of ​​the test pad 309. The specific area size of the welding pad 308 and the test pad 309 is set according to the requirements of the wire bonding, and the present disclosure does not limit this.

[0101] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A dielectric layer, located on one side of the substrate; A pad, located on a surface of the dielectric layer away from the substrate; A barrier protrudes from the surface of the pad away from the substrate to divide the pad into a welding pad and a test pad; The dielectric layer includes a second through hole communicating with the pad, the barrier is located above the second through hole, and the second through hole is filled with a filling material.

2. The semiconductor device according to claim 1, wherein: The filling material of the second through hole forms a gap, and a second conductive column is formed in the second through hole.

3. The semiconductor device according to claim 1 or 2, characterized in that: The second through hole has a width of 0.1-0.3 um and a depth of 0.25-0.65 um, and a ratio of the depth to the width of the second through hole is >2:

1.

4. The semiconductor device according to claim 1, wherein: The barrier is rectangular or elliptical, the width of the barrier is 1um~20um, the length of the barrier is 50um~80um, and the height of the barrier is 100nm~6um.

5. The semiconductor device according to claim 1 or 4, characterized in that: The substrate includes a wiring layer including soldering wires connected to the soldering pads via conductive pillars passing through the dielectric layer.

6. The semiconductor device according to claim 5, characterized in that A protection layer is also included, which is located on a side of the dielectric layer away from the substrate and exposes the pad.

7. The semiconductor device according to claim 6, characterized in that The material of the protective layer is one or more combinations of polyimide and tetraethyl orthosilicate.

8. The semiconductor device according to claim 6, characterized in that Also included is a passivation layer located between the protection layer and the dielectric layer.

9. The semiconductor device according to claim 2, characterized in that The materials of the pad and the barrier are the same as the filling material in the second through hole. The material of the pad is one of copper, aluminum, tungsten, titanium, gold, silver or an alloy of the above materials.

10. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate; forming a second through hole in the dielectric layer by etching; A pad layer is formed on the dielectric layer, and a barrier is formed above the second through hole, so that the pad layer is divided into a welding pad and a test pad by the barrier.

11. The method according to claim 10, characterized in that Forming a second through hole in the dielectric layer by etching comprises: forming a photoresist layer on a surface of the dielectric layer away from the substrate; Expose through a mask plate to transfer the pattern of the mask plate to the photoresist layer; Developing the photoresist layer so that the region where the second through hole is to be opened is exposed; Etching to form the second through hole in the area where the second through hole is to be formed; The photoresist layer is removed.

12. The method according to claim 10, characterized in that Forming a pad layer on the dielectric layer and forming a barrier over the second through hole comprises: A pad layer is formed on the dielectric layer by physical vapor deposition, a gap is formed when the second through hole is filled in the physical vapor deposition process, and the barrier is formed above the second through hole.

13. The method according to claim 10, characterized in that Also includes: forming a passivation layer on the pad and the dielectric layer; depositing a protective layer on the passivation layer; exposing and developing the protective layer to expose the passivation layer on the pad; The exposed passivation layer is removed by etching to expose the pad.

14. The method according to claim 13, characterized in that The passivation layer is a pad silicon oxide layer or a pad silicon nitride layer, and the material of the protection layer is a combination of one or more of polyimide and tetraethyl orthosilicate.

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