Display device

Abstract

The present disclosure relates to a display device, the display device comprising: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels and a common voltage line disposed in the display area; and a driving voltage line connected to each of the plurality of pixels, wherein, in a plan view, a subset of the plurality of pixels overlaps with the common voltage line in the display area, and the external common voltage line and the common voltage line are connected to each other.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0045420, filed with the Korean Intellectual Property Office on April 18, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that connects a common voltage line in a non-display area inside a display area. Background Art

[0004] A display device displays an image. Recently, emissive display devices have attracted attention as self-emissive displays.

[0005] Emissive display devices have self-luminous characteristics and, unlike liquid crystal displays, do not require a separate light source, so the thickness and weight of the emissive display device can be reduced. In addition, emissive display devices exhibit high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0006] Generally, an emissive display device may include: a substrate; a plurality of thin film transistors disposed on the substrate; a plurality of insulating layers disposed between wirings constituting the thin film transistors; and a light-emitting element connected to the thin film transistor. An organic light-emitting element may be an example of the light-emitting element.

[0007] On the other hand, as the bezels of display devices become thinner, a user's line of sight becomes fixed or converges on an image (or the screen of the display device). In recent years, a full-surface display technology has been developed to eliminate the bezels on the front surface of a display device and display an image on the entire front surface of the display device.

[0008] The above information disclosed in this background section is only for enhancing the understanding of the background of the present disclosure, and thus, the above information may include information that does not constitute prior art known to those of ordinary skill in the art. Summary of the Invention

[0009] The present disclosure provides a display device for preventing a common voltage drop and minimizing a right bezel / left bezel.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels and a common voltage line disposed in the display area; and a driving voltage line connected to each of the plurality of pixels, wherein, in a plan view, a subset of the plurality of pixels overlaps with the common voltage line in the display area, and the external common voltage line and the common voltage line are connected to each other.

[0011] The driving voltage line may be indirectly connected to the subset of the plurality of pixels via a driving voltage connection line.

[0012] The external common voltage line may be disposed to surround four edges of the display area.

[0013] The common voltage line may further include a lateral common voltage line and a longitudinal common voltage line.

[0014] The external common voltage line may be divided via the display area.

[0015] The display device may further include an external initialization voltage line and an external driving voltage line disposed in the non-display area, and each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may have a multi-layer structure.

[0016] Each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may include a plurality of separated parts, and each of the plurality of parts may be connected to each other by a connection member.

[0017] The connection member may be disposed on the same layer as a gate line, a data line, or a pixel electrode in the display area.

[0018] The connection member may include a first connection member disposed on the same layer as the gate line and a second connection member disposed on the same layer as the pixel electrode, and the first connection member and the second connection member may overlap with each other in a plan view.

[0019] The display area may further include a driving voltage connection line disposed in the display area and crossing the driving voltage line, and a width of the driving voltage connection line may be reduced at a portion where the common voltage line and the driving voltage connection line overlap.

[0020] The driving voltage connection line, the driving voltage line, and the common voltage line may be disposed on different layers from each other, and the driving voltage connection line may be disposed closer to the substrate than the driving voltage line and the common voltage line.

[0021] The display device may further include a common electrode in contact with the external common voltage line in the non-display area.

[0022] A display device according to another exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels disposed in the display area; a driving voltage line connected to each of the plurality of pixels; and a plurality of common voltage lines disposed in the display area, wherein the external common voltage line and the plurality of common voltage lines are connected to each other.

[0023] The external common voltage line may be disposed to surround four edges of the display area.

[0024] The plurality of common voltage lines and the driving voltage line may be disposed on the same layer.

[0025] Each of the plurality of common voltage lines may further include a horizontal common voltage line and a vertical common voltage line.

[0026] The plurality of common voltage lines may be disposed farther from the substrate than the driving voltage line, and an insulating layer may be disposed between the plurality of common voltage lines and the driving voltage line.

[0027] The external common voltage line may be disposed to be divided by the display area.

[0028] The display device may further include an external initialization voltage line and an external driving voltage line disposed in the non-display area, and each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may have a multi-layer structure.

[0029] Each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may include a plurality of separated parts, and each of the plurality of parts may be connected to each other by a connection member.

[0030] The connection member may be disposed on the same layer as a gate line, a data line, or a pixel electrode in the display area.

[0031] The display device may further include a driving voltage connection line disposed in the display area and crossing the driving voltage line, and a width of the driving voltage connection line may be reduced at an overlapping portion of the common voltage line and the driving voltage connection line.

[0032] According to an exemplary embodiment, by connecting an external common voltage line in a non-display area to a common voltage line in a display area, a decrease in the common voltage can be prevented, and the right and left borders of the display device can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a view showing a display device according to an exemplary embodiment of the present disclosure.

[0034] Figure 2 is a view showing a display device according to another exemplary embodiment.

[0035] Figure 3 is a view showing a display device according to another exemplary embodiment.

[0036] Figure 4 is a view showing a display device according to another exemplary embodiment.

[0037] Figure 5 is a view showing a display device according to another exemplary embodiment.

[0038] Figure 6 is a view showing a display device according to another exemplary embodiment.

[0039] Figure 7 is a view schematically showing the arrangement shape of drive voltage connection lines, drive voltage lines, and common voltage lines in a display area of a display device according to an exemplary embodiment.

[0040] Figures 8 to 10 are views schematically showing the arrangement shapes of drive voltage connection lines, drive voltage lines, and common voltage lines in a display area of a display device according to another exemplary embodiment, respectively.

[0041] Figure 11 is a view showing a wiring connection structure between a display area and a non-display area in a display device according to an exemplary embodiment of the present disclosure.

[0042] Figure 12 and Figure 13 are views showing a wiring connection structure between a display area and a non-display area in a display device according to another exemplary embodiment.

[0043] Figure 14 is a view of an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment.

[0044] Figure 15 is a layout diagram of a pixel area of a display device according to an exemplary embodiment.

[0045] Figure 16 is a cross-sectional view taken along line XVI-XVI' Figure 15 shown in Figure 15 .

[0046] Figure 17 is a layout view of a pixel region of a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0047] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. As will be recognized by those skilled in the art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0048] The drawings and the accompanying description are to be considered illustrative in nature and not restrictive. Throughout the specification, like reference numerals refer to like elements.

[0049] In addition, in the drawings, for better understanding and ease of description, the dimensions and thicknesses of each element are arbitrarily shown, and the present disclosure is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, zones, etc. are exaggerated for clarity, better understanding, and ease of description.

[0050] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element, or there can be one or more intervening elements therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Further, in the specification, the words "on" or "above" mean being located on or below the target portion, and do not necessarily mean being on the upper side of the target portion based on the direction of gravity.

[0051] Also, unless explicitly described to the contrary, the words "comprise" and variations such as "comprising" or "containing" will be understood to imply the inclusion of the stated elements without excluding any other elements.

[0052] In addition, throughout the specification, the phrase "in a plane" means observing the target portion from the top, and the phrase "in a cross-section" means a cross-section formed by vertically cutting the target portion from the side.

[0053] Now, a display device according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1 is a view showing a display device according to an exemplary embodiment of the present disclosure. Referring to Figure 1 , the display device includes a display area DA and a non-display area NDA.

[0055] A plurality of pixels PX1, PX2, and PX3 are provided in the display area, and the driving voltage line 172 is connected to each pixel and applies a driving voltage VDD to the pixel. A driving voltage connection line 172c that intersects the driving voltage line 172 is provided in the display area DA. The driving voltage connection line 172c intersects the driving voltage line 172 and is connected to the driving voltage line 172 at the intersection point. Therefore, the driving voltage transmitted to the driving voltage line 172 can be transmitted to adjacent pixels via the driving voltage connection line 172c. The driving voltage connection line 172c can be provided on a layer different from the layer of the driving voltage line 172.

[0056] For convenience, Figure 1 only a partial view of the pixels PX1, PX2, and PX3, the driving voltage line 172, and the driving voltage connection line 172c is shown.

[0057] An external driving voltage line 1720 is provided in the non-display area NDA. The external driving voltage line 1720 may include a first driving voltage line 1720a and a second driving voltage line 1720b that are separated from each other via the display area DA. The first driving voltage line 1720a and the second driving voltage line 1720b may not be connected to each other in the non-display area NDA and may be connected to the driving voltage line 172 in the display area DA.

[0058] An external common voltage line 7410 is provided in the non-display area NDA. The external common voltage line 7410 may include a first common voltage line 7410a and a second common voltage line 7410b that are separated from each other. The first common voltage line 7410a and the second common voltage line 7410b may be separated from each other via the display area DA and may be connected to each other through a common voltage line 741 provided in the display area DA.

[0059] Referring to Figure 1 , one of the driving voltage lines 172 connected to the plurality of pixels PX1, PX2, and PX3 may be replaced with a common voltage line 741. Therefore, the first common voltage line 7410a and the second common voltage line 7410b that are spaced apart from each other via the display area DA can be connected to each other via the common voltage line 741.

[0060] Therefore, when the first common voltage line 7410a and the second common voltage line 7410b are connected by the common voltage line 741 in the display area DA, the problem of voltage drop during the transmission period of the common voltage VSS can be solved. In addition, since the first common voltage line 7410a and the second common voltage line 7410b are not provided at the edge of the display area DA, the left non-display area NDA and the right non-display area NDA can be minimized.

[0061] In other words, when the external common voltage line 7410 is set to surround all four edges of the display area DA, a voltage drop occurs during the transmission of the common voltage VSS. Additionally, since the external common voltage line 7410 should be set on the left non-display area NDA and the right non-display area NDA located outside the left and right edges of the display area DA, it may not be possible to remove the left non-display area NDA and the right non-display area NDA.

[0062] However, as Figure 1 shown, when the external common voltage lines 7410 are set to be separated from each other via the display area DA and connected to each other by the common voltage line 741 disposed in the display area DA, the problem of common voltage reduction can be prevented, and the left non-display area NDA and the right non-display area NDA can be removed, thereby minimizing the bezel or even completely removing the bezels at least on the right and left sides of the display device.

[0063] The common electrode 270 (also referred to as the second electrode herein) is in contact with the external common voltage line 7410 to receive the common voltage VSS. As Figure 1 shown, among the driving voltage lines 172 connected to the plurality of pixels PX1, PX2, and PX3, the driving voltage line 172 connected to the pixel PX3 is replaced with the common voltage line 741. However, the driving voltage lines 172 are connected by the driving voltage connection lines 172c in the display area DA, so that all the pixels PX1, PX2, and PX3 can receive the driving voltage VDD.

[0064] Table 1 below shows the long range uniformity (LRU), voltage drop, and reduction in panel power consumption of the display device according to the Figure 1 exemplary embodiment. Table 2 shows the LRU, voltage drop, and reduction in panel power consumption of a comparative display device in which the common voltage line 741 is not disposed in the display area DA and the external common voltage line 7410 surrounds all four edges of the display area DA.

[0065] (Table 1)

[0066] Item Result LRU (%) 81.25 VDD Drop (V) 0.22 VSS Drop (V) 2.16 Reduction in Panel Power Consumption 19.2％

[0067] (Table 2)

[0068] Item Result LRU (%) 79.24 VDD Drop (V) 0.18 VSS Drop (V) 4.09

[0069] Compare Table 1 and Table 2. When the external common voltage line 7410 is not provided on the right and left sides of the display area DA and the external common voltage line 7410 is connected through the common voltage line 741 inside the display area DA, the reduction amount of the common voltage is low. By connecting the external common voltage line 7410 through the common voltage line 741 in the display area DA, the common voltage drop can be reduced, and the LRU can be improved.

[0070] Figure 2 is a view showing a display device according to another exemplary embodiment. Referring to Figure 2 , except for the shape of the external common voltage line 7410 and the points where the external common voltage line 7410 surrounds the four edges of the display area DA, this display device is the same as Figure 1 's display device. The detailed description of the same components is omitted. In Figure 2 's case, similar to Figure 1 , the common voltage line 741 provided in the display area DA is connected to the external common voltage line 7410. Therefore, a voltage drop during the transmission of the common voltage VSS can be prevented.

[0071] Figure 3 is a view showing a display device according to another exemplary embodiment. Referring to Figure 3 , except that the common voltage line 741 provided in the display area DA includes a horizontal common voltage line 741b and a vertical common voltage line 741a, this display device is the same as Figure 2 's display device. The detailed description of the same components is omitted. That is, this display device has a grid structure, and the common voltage line 741 of this grid structure includes a horizontal common voltage line 741b and a vertical common voltage line 741a. In this case, a reduction in the common voltage VSS can be effectively prevented, and the common voltage VSS can be uniformly transmitted through the common voltage line 741 having a grid structure.

[0072] Figures 4 to 6 are views respectively showing a display device according to another exemplary embodiment. Referring to Figure 4 , the common voltage line 741 is provided in the display area DA. However, different from the display device shown in Figure 1 , the common voltage line 741 is provided separately from the driving voltage lines 172 respectively connected to the pixels PX1, PX2, and PX3. Other configurations are the same as those shown in Figure 1 , and the detailed description of the same configurations is omitted. That is, if there is enough space in the display area DA to separately provide the common voltage line 741, the common voltage line 741 can be separately formed without removing the existing driving voltage lines 172.

[0073] In addition to forming the common voltage line 741 separately without removing the driving voltage line 172 in the display area DA, Figure 5 is also the same as Figure 2 . A detailed description of the same constituent elements is omitted.

[0074] In addition to forming the common voltage line 741 separately without removing the driving voltage line 172 in the display area DA, Figure 6 is the same as Figure 3 . A detailed description of the same constituent elements is omitted.

[0075] In Figures 1 to 6 , the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 can be respectively disposed in different layers so as to be separated from each other. Although the driving voltage connection line 172c and the driving voltage line 172 can be disposed in different layers from each other, the driving voltage connection line 172c and the driving voltage line 172 are connected through a contact hole so as to uniformly transmit the driving voltage VDD.

[0076] Figure 7 Schematically shows the arrangement shapes of the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 in the display area DA. In Figure 7 , PX1, PX2, and PX3 represent pixels connected to respective connection wirings among one or more connection wirings.

[0077] Referring to Figure 7 , the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 are respectively disposed on different layers. For example, the driving voltage connection line 172c can be disposed on the bottommost layer such that the driving voltage connection line 172c is closest to the substrate of the display device, followed by the driving voltage line 172 and the common voltage line 741. However, the present disclosure is not limited thereto, and they can be disposed in a different stacking order. In some embodiments, the driving voltage line 172 and the common voltage line 741 can be disposed on the same layer.

[0078] Referring to Figure 7 , the width of the driving voltage connection line 172c overlapping with the common voltage line 741 can be narrower than the width of the driving voltage connection line 172c overlapping with the driving voltage line 172. Therefore, the risk of short circuit between the common voltage line 741 and the driving voltage connection line 172c can be reduced. The driving voltage connection line 172c and the driving voltage line 172 are connected to each other through the contact hole 28.

[0079] Figure 8Schematically shows the arrangement shape of the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 in the display area DA of a display device according to another exemplary embodiment. Refer to Figure 8 , the common voltage line 741 includes a horizontal common voltage line 741b and a vertical common voltage line 741a. Except that the common voltage line 741 includes a horizontal common voltage line 741b and a vertical common voltage line 741a, this display device is the same as the display device according to Figure 7 the exemplary embodiment of. The detailed description of the same constituent elements is omitted.

[0080] The horizontal common voltage line 741a and the vertical common voltage line 741b can be provided on the same layer and connected to each other. That is, the common voltage line 741 can have a grid shape including the horizontal common voltage line 741b and the vertical common voltage line 741a. In this case, the common voltage line 741 can be provided on a layer different from the layer of the driving voltage line 172, and an insulating layer can be provided between the common voltage line 741 and the driving voltage line 172. In one embodiment, the driving voltage line 172 can be provided closer to the substrate than the common voltage line 741.

[0081] Figure 9 Schematically shows the arrangement shape of the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 in the display area DA of a display device according to another exemplary embodiment. Refer to Figure 9 , except that the common voltage line 741 is provided outside the pixels PX1, PX2, and PX3, this display device is the same as Figure 7 the exemplary embodiment of. The detailed description of the same constituent elements is omitted. Since the common driving voltage line 741 is provided outside the pixels PX1, PX2, and PX3, the common voltage line 741 is provided without removing the existing driving voltage line 172. That is, each driving voltage line 172 is connected to the respective pixels among the pixels PX1, PX2, and PX3, and the common voltage line 741 is separately provided in each empty area between the pixels. The common voltage line 741 can be provided on the same layer as the driving voltage line 172.

[0082] Figure 10 Schematically shows the arrangement shape of the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 in the display area DA of a display device according to another exemplary embodiment. Refer to Figure 10 , the common voltage line 741 includes a horizontal common voltage line 741b and a vertical common voltage line 741a. Except that the common voltage line 741 includes a horizontal common voltage line 741b and a vertical common voltage line 741a, this display device is the same as the display device according to Figure 9is the same as the display device of the exemplary embodiment. A detailed description of the same constituent elements is omitted.

[0083] The horizontal common voltage line 741b and the vertical common voltage line 741a may be disposed on the same layer and connected to each other. That is, the common voltage line 741 may have a mesh shape including the horizontal common voltage line 741a and the vertical common voltage line 741b.

[0084] The common voltage line 741 may be disposed on the driving voltage line 172. The common voltage line 741 may be disposed farther from the substrate than the driving voltage line 172, and an insulating layer may be disposed between the driving voltage line 172 and the common voltage line 741.

[0085] Next, various methods of connecting wirings in the display area DA and the non-display area NDA will be described with reference to the drawings.

[0086] Figure 11 A wiring connection structure between the display area DA and the non-display area NDA in a display device according to an exemplary embodiment of the present disclosure is shown. In Figures 11 to 13 order to better understand and facilitate the description, the voltage transmitted from each wiring is described with respect to the wiring.

[0087] Referring to Figure 11 , the display device includes an external common voltage line 7410, an external initialization voltage line 1270, and an external driving voltage line 1720 disposed in the non-display area NDA.

[0088] The external common voltage line 7410 includes a first common voltage line 7410a, a second common voltage line 7410b, a third common voltage line 7410c, and a fourth common voltage line 7410d that are separated from each other. The external common voltage line 7410 may be formed of multiple layers including at least a first layer and a second layer. In Figure 11 order, the first layer and the second layer are shown in different patterns. The second common voltage line 7410b, the third common voltage line 7410c, and the fourth common voltage line 7410d may include the first layer and the second layer, and the first common voltage line 7410a may include only the first layer.

[0089] In this case, the first layer may be the same layer as the first source / drain layer of the display area DA, and the second layer may be the same layer as the second source / drain layer of the display area DA.

[0090] The first common voltage line 7410a, the second common voltage line 7410b, the third common voltage line 7410c, and the fourth common voltage line 7410d are connected to each other through the first connection member 7415, the second connection member 7416, and the contact holes 14 and 15. The first connection member 7415 may be disposed in the same layer as the layer in which the pixel electrodes in the display area DA are provided. The first connection member 7415 may be connected to the second connection member 7416 through the contact hole 15, and the second connection member 7416 may be connected to the external common voltage line 7410a through the contact hole 14. The second connection member 7416 may be disposed in the same layer as the second source / drain layer of the display area DA.

[0091] In addition, the first common voltage line 7410a disposed close to the display area DA is connected to the common voltage line 741 provided in the display area DA through the connection member 7417. The first common voltage line 7410a and the connection member 7417 may be connected through the contact hole 18. The connection member 7417 may be disposed in the same layer as the second source / drain layer.

[0092] The external initialization voltage line 1270 partially protrudes, and a part of the protruding area includes the second layer. That is, the external initialization voltage line 1270 may include a first layer that is in the same layer as the first source / drain layer of the display area DA and a second layer that is in the same layer as the second source / drain layer of the display area DA.

[0093] The external initialization voltage line 1270 is connected to the initialization voltage line 127 inside the display area DA through the connection member 1275. The connection member 1275 may be disposed in the same layer as the second source / drain layer. The connection member 1275 may be connected to the external initialization voltage line 1270 via the contact hole 27. The second layer of the connection member 1275 may also be connected to the first layer through the contact hole 28.

[0094] The external driving voltage line 1720 may include a first layer that is in the same layer as the first source / drain layer of the display area DA and a second layer that is in the same layer as the second source / drain layer of the display area DA. A part of the second layer extends into the display area DA to be connected to the driving voltage line 172 of the display area DA.

[0095] Next, refer to Figure 12 Describe a display device according to another exemplary embodiment of the present disclosure. Refer to Figure 12, the external initialization voltage line 1270 is set closer to the display area DA than the external common voltage line 7410. The external initialization voltage line 1270 is connected to the connection member 1275 through the contact hole 27 and is connected to the initialization voltage line 127 inside the display area DA through the connection member 1275. The connection member 1275 may be disposed in the same layer as the first source / drain layer of the display area DA. The external initialization voltage line 1270 may be connected to the outside via the connection members 1276, 1277, and 1278. The connection member 1276 and the connection member 1278 may be disposed in the same layer as the connection member 1275, and the connection member 1277 may be disposed in the same layer as the pixel electrode in the display area DA. The connection member 1277 may be connected to the connection member 1276 and the connection member 1278 respectively through the contact hole 25. The connection member 1276 is also connected to the external initialization voltage line 1270 via the contact hole 28.

[0096] The external common voltage line 7410 is connected to the connection member 7417 through the contact hole 14. The external common voltage line 7410 is connected to the common voltage line 741 of the display area DA through the connection member 7417. The external common voltage line 7410 is disposed in the same layer as the first source / drain layer of the display area DA. A part of the external common voltage line 7410 includes a second layer, and the second layer is disposed in the same layer as the second source / drain layer of the display area DA. The first layer and the second layer may be connected to each other through the contact hole 15.

[0097] Next, the external driving voltage line 1720 is described. The external driving voltage line 1720 includes a first layer in the same layer as the first source / drain layer of the display area DA and a second layer in the same layer as the second source / drain layer of the display area DA. Each part of the first layer of the external driving voltage line 1720 is separated from each other, but is connected to each other through the second layer. A part of the second layer extends to be connected to the driving voltage line 172 of the display area DA to transmit the driving voltage VDD.

[0098] Next, refer to Figure 13 Describe a display device according to another exemplary embodiment of the present disclosure. Refer to Figure 13 , the external driving voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 are formed in a single layer. Each of the external driving voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 is disposed in a direction parallel to the edge of the display area DA.

[0099] In addition, the island-shaped external drive voltage line 1721, the external common voltage line 7411, and the external initialization voltage line 1271 are respectively connected to the island-shaped external drive voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 through the connection member 7711. The connection member 7711 is connected to each wiring through the contact hole 17. The connection member 7711 may be disposed in the same layer as the layer in which the pixel electrodes in the display area DA are provided.

[0100] In addition, the island-shaped external drive voltage line 1721, the external common voltage line 7411, and the external initialization voltage line 1271 are respectively connected to the island-shaped external drive voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 through the connection member 7712. Each connection member 7712 is connected to the wiring through the contact hole 12. The connection member 7712 may be disposed in the same layer as the gate conductor layer in the display area DA.

[0101] The island-shaped wiring and the line-shaped wiring may be connected by two connection members overlapping each other. That is, the wirings separated from each other are connected by the connection member 7712 and the connection member 7711. The connection member 7712 is disposed in the same layer as the gate conductor layer in the display area DA, and the connection member 7711 is disposed in the same layer as the layer in which the pixel electrodes in the display area DA are provided.

[0102] Figures 11 to 13 This is only an example, and Figures 1 to 9 the wiring connection structure of the display device shown in Figures 11 to 13 is not limited to the

[0103] Next, with reference to Figures 14 to 16 the pixel structure of the display area DA will be described. Figure 14 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment.

[0104] With reference to Figure 14 , the pixel PX of the display device includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, a light-emitting diode LED, and a plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741.

[0105] The display device includes a display area in which an image is displayed, and the pixels PX are arranged in various forms in the display area.

[0106] A plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, two switching transistors, and compensation transistors T4, T5, T6, and T7 for operating a light-emitting diode LED. The two switching transistors are connected to a scan line 151 and include a second transistor T2 and a third transistor T3. These compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0107] A plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a scan line 151, a previous scan line 152, a light-emission control line 153, a bypass control line 158, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may correspond to a part of the previous scan line 152 or may be electrically connected thereto.

[0108] The scan line 151 is connected to a gate electrode G2 of the second transistor T2 and a gate electrode G3 of the third transistor T3 and transmits a scan signal Sn. The previous scan line 152 is connected to a gate electrode G4 of the fourth transistor T4 and transmits a previous scan signal Sn-1 applied to a pixel PX provided in a previous stage. The light-emission control line 153 is connected to a light-emission controller (not shown) and transmits a light-emission control signal EM to a gate electrode G5 of the fifth transistor T5 and a gate electrode G6 of the sixth transistor T6, and controls the time when the light-emitting diode LED emits light. The bypass control line 158 transmits a bypass signal GB to a gate electrode G7 of the seventh transistor T7.

[0109] The data line 171 is a wiring for transmitting a data voltage Dm generated from a data driver (not shown), and the brightness of the light-emitting diode LED (also referred to as a light-emitting element) varies according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD (also referred to as VDD, as Figure 1 shown). When the fourth transistor T4 is turned on, the initialization voltage line 127 transmits an initialization voltage Vint (i.e., VINT, as Figure 11 , Figure 12 and Figure 13 shown), and the initialization voltage Vint initializes the voltage applied to a gate electrode G1 of the driving transistor T1. The common voltage line 741 applies a common voltage ELVSS (also referred to as VSS, as Figure 1 shown). The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 may be constant voltages.

[0110] The driving transistor T1 adjusts the amount of the driving current Id output from the driving transistor T1 according to the data voltage Dm. The driving current Id is applied to the light-emitting diode LED to control the brightness of the light-emitting diode LED according to the data voltage Dm. For this purpose, the first electrode S1 of the driving transistor T1 is set to receive the driving voltage ELVDD. The first electrode S1 is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2 so that when the second transistor T2 is turned on, the data voltage Dm is also applied to the first electrode S1. The second electrode D1 (output electrode) of the driving transistor T1 is set to output the driving current Id toward the light-emitting diode LED. The second electrode D1 of the driving transistor T1 is connected to the light-emitting diode LED via the sixth transistor T6. On the other hand, the gate electrode G1 of the driving transistor T1 is connected to the second storage electrode E2 of the storage capacitor Cst. Therefore, the voltage applied to the gate electrode G1 of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the driving current Id output from the driving transistor T1 changes accordingly.

[0111] The second transistor T2 receives the data voltage Dm into the pixel PX. The gate electrode G2 of the second transistor T2 is connected to the scan line 151, the first electrode S2 of the second transistor T2 is connected to the data line 171, and the second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0112] The third transistor T3 causes the compensation voltage (the sum of the data voltage Dm and the threshold voltage Vth of the driving transistor T1) to be transmitted to the second storage electrode E2 of the storage capacitor Cst, and the data voltage Dm of the compensation voltage changes through the driving transistor T1. The gate electrode G3 of the third transistor T3 is connected to the scan line 151, the first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. When the third transistor T3 is turned on according to the scan signal Sn transmitted through the scan line 151, the gate electrode G1 and the second electrode D1 of the driving transistor T1 are connected in a diode manner, and the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst are connected.

[0113] The fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 of the fourth transistor T4 is connected to the previous scan line 152, the first electrode S4 of the fourth transistor T4 is connected to the initialization voltage line 127, and the second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous scan signal Sn-1 transmitted through the previous scan line 152. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint has a low voltage value, thereby serving as a voltage that can turn on the driving transistor T1.

[0114] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 of the fifth transistor T5 is connected to the light emission control line 153, the first electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0115] The sixth transistor T6 is used to transmit the driving current Id output from the driving transistor T1 to the light emitting diode LED. The gate electrode G6 of the sixth transistor T6 is connected to the light emission control line 153, the first electrode S6 of the sixth transistor T6 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D6 of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0116] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EM transmitted through the light emission control line 153. When the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (i.e., the voltage of the second storage electrode E2 of the storage capacitor Cst). The driving current Id flows to the light emitting diode LED through the sixth transistor T6. As the current I led flows through the light emitting diode LED, the light emitting diode LED emits light.

[0117] The seventh transistor T7 is responsible for initializing the anode of the light-emitting diode LED. The gate electrode G7 of the seventh transistor T7 is connected to the bypass control line 158, the first electrode S7 of the seventh transistor T7 is connected to the anode of the light-emitting diode LED, and the second electrode D7 of the seventh transistor T7 is connected to the initialization voltage line 127. According to one embodiment, the bypass control line 158 may be connected to the previous scan line 152. In this case, the bypass signal GB is applied with a signal having the same timing as the previous scan signal Sn-1. In another embodiment, the bypass control line 158 may not be connected to the previous scan line 152 and may transmit a signal different from the previous scan signal Sn-1. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the light-emitting diode LED to put the light-emitting diode LED in an initialization state.

[0118] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. Accordingly, the voltage charged across the second storage electrode E2 and the first storage electrode E1 at the storage capacitor Cst determines the voltage applied to the gate electrode G1 of the driving transistor T1. The second storage electrode E2 of the storage capacitor Cst receives the data voltage Dm through the second electrode D3 of the third transistor T3, or receives the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0119] On the other hand, the anode of the light-emitting diode LED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and the cathode of the light-emitting diode LED is connected to the common voltage line 741 that transmits the common voltage ELVSS.

[0120] In Figure 14 the exemplary embodiment, the pixel PX includes seven transistors T1 to T7 and one capacitor Cst, but the present disclosure is not limited thereto, and the number of transistors, the number of capacitors, and their connections may be changed without departing from the scope of the present disclosure.

[0121] Figure 15 is a layout diagram of a pixel region of a display device according to an exemplary embodiment, and Figure 16 is along Figure 15 the line XVI-XVI' of the cross-sectional view taken.

[0122] Refer to Figure 15, a display device according to an exemplary embodiment includes a scan line 151 that extends in a first direction DR1 and transmits a scan signal Sn, a previous scan line 152 that transmits a previous scan signal Sn-1, a light emission control line 153 that transmits a light emission control signal EM, and an initialization voltage line 127 that transmits an initialization voltage Vint. A bypass signal GB may be transmitted through the previous scan line 152.

[0123] The display device includes a data line 171 that extends in a second direction DR2 orthogonal to the first direction DR1 and transmits a data voltage Dm, and a common voltage line 741 that transmits a common voltage ELVSS. Figure 15 and Figure 16 The first pixel PX1 shown in corresponds to a pixel in which the driving voltage line 172 is replaced with Figures 1 to 3 the common voltage line 741 in. Figure 15 The driving voltage line 172 connected to the second pixel PX2 shown in is not replaced with the common voltage line 741, and a conventional driving voltage line 172 is provided. Hereinafter, the first pixel PX1 will be described in comparison with the second pixel PX2.

[0124] The display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting diode LED.

[0125] Each channel of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is provided in the semiconductor layer 130. At least some of the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are also provided in the semiconductor layer 130. The semiconductor layer 130 ( Figure 15 the shaded portion in) may be formed to be bent into various shapes. The semiconductor layer 130 may include a polycrystalline semiconductor such as polycrystalline silicon or an oxide semiconductor.

[0126] The semiconductor layer 130 includes a channel doped with an N-type impurity or a P-type impurity, and a first doping region and a second doping region located on respective sides of the channel and having a higher doping concentration than the channel. The first doping region and the second doping region may correspond to the first electrode and the second electrode of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7, respectively. If one of the first doping region and the second doping region is a source region, the other doping region may be a drain region. Additionally, in the semiconductor layer 130, a region (e.g., a channel) between the first electrode and the second electrode of different transistors may be doped such that the source electrode of one transistor and the drain electrode of another transistor can be electrically connected to each other.

[0127] Each channel of transistors T1, T2, T3, T4, T5, T6, and T7 overlaps with the gate electrode of each of the transistors T1, T2, T3, T4, T5, T6, and T7 and is disposed between the first electrode and the second electrode of each of the transistors T1, T2, T3, T4, T5, T6, and T7. The multiple transistors T1, T2, T3, T4, T5, T6, and T7 may have substantially the same stacked structure. Hereinafter, the driving transistor T1 will be mainly described in detail, and the remaining transistors T2 to T7 will be schematically described.

[0128] The driving transistor T1 includes a channel, a first gate electrode 155 ( Figure 14 the gate electrode G1 shown in), a first electrode S1, and a second electrode D1. In a plan view, the channel of the driving transistor T1 disposed between the first electrode S1 and the second electrode D1 overlaps with the first gate electrode 155. As Figure 15 shown, the channel is curved to form a longer channel length within a limited area. When the length of the channel becomes longer, the driving range of the gate voltage Vg applied to the first gate electrode 155 of the driving transistor T1 widens, and the driving current Id continuously increases according to the gate voltage Vg. Therefore, by changing the magnitude of the gate voltage Vg, the gray scale of the light emitted by the light emitting diode LED can be more precisely controlled, and the display quality of the display device can be improved. In addition, since the channel extends in several directions instead of one direction, the influence due to directionality is canceled in the manufacturing process, thereby reducing the influence of process dispersion. Therefore, it is possible to prevent deterioration of image quality such as spot defects (for example, uneven brightness occurring according to pixels even when the same data voltage Dm is applied) due to the characteristics of the driving transistor T1, and the characteristics of the driving transistor T1 may change according to the region of the display device due to process dispersion. The shape of the channel is not limited to the shown Ω shape, and the channel may have various shapes.

[0129] The first gate electrode 155 overlaps with the channel in a plan view. The first electrode S1 and the second electrode D2 are located on opposite sides of the channel. The extended portion of the storage line 126 is isolated and located on the first gate electrode 155. The extended portion of the storage line 126 overlaps with the first gate electrode 155 in a plan view, and a second gate insulating layer is located therebetween to form a storage capacitor Cst. The extended portion of the storage line 126 corresponds to the first storage electrode E1 of the storage capacitor Cst, and the first gate electrode 155 may correspond to Figure 14The second storage electrode E2 of the storage capacitor Cst shown in []. An extension of the storage line 126 is provided with an opening 56 such that the first gate electrode 155 can be connected to the first data connection member 71. In the opening 56, the upper surface of the first gate electrode 155 and the first data connection member 71 are electrically connected through the opening 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the first gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0130] The gate electrode G2 of the second transistor T2 can correspond to a part of the scanning line 151. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 of the second transistor T2 can be provided on the semiconductor layer 130.

[0131] The third transistor T3 can be formed by two transistors adjacent to each other. In the Figure 15 pixel PX shown in [], the third transistor T3 is shown as having a first part extending to the left and a second part extending downward with respect to the folded part of the semiconductor layer 130. Each of these two parts functions as the third transistor T3 and has a structure in which the first electrode S3 of one of the two transistors is connected to the second electrode D3 of the other transistor. The gate electrodes of the two transistors can correspond to a part of the scanning line 151 or a part protruding upward from the scanning line 151. Such a structure can be called a double-gate structure and functions to prevent leakage current. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through the contact hole 63.

[0132] The fourth transistor T4 includes two fourth transistors formed at the meeting point of the previous scanning line 152 and the semiconductor layer 130. The gate electrode G4 of the fourth transistor T4 can correspond to a part of the previous scanning line 152. There is a structure in which the first electrode S4 of one of the two transistors is connected to the second electrode D4 of the other transistor. Similar to the third transistor T3, the fourth transistor T4 has a double-gate structure that can prevent leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0133] As described above, the third transistor T3 and the fourth transistor T4 have a double-gate structure, so the electron movement path of their channels is blocked in the cutoff state, effectively preventing leakage current.

[0134] The gate electrode G5 of the fifth transistor T5 may correspond to a part of the light emission control line 153. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 77, and the second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0135] Since the driving voltage line 172 connected to the pixel is replaced by the common voltage line 741, the first pixel PX1 receives the driving voltage ELVDD from the adjacent pixel PX2 through the driving voltage connection line 172c of the driving voltage line 172 connected to the adjacent pixel PX2.

[0136] However, in the second pixel PX2, the common voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67, and the second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0137] The gate electrode G6 of the sixth transistor T6 may correspond to a part of the light emission control line 153. The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69, and the first electrode S6 of the sixth transistor T6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0138] The gate electrode G7 of the seventh transistor T7 may correspond to a part of the previous scan line 152. The first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and the second electrode D7 of the seventh transistor T7 is connected to the first electrode S4 of the fourth transistor T4.

[0139] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 that overlap each other via the second gate insulating layer 142. The second storage electrode E2 of the storage capacitor Cst may correspond to the first gate electrode 155 of the driving transistor T1, and the first storage electrode E1 of the storage capacitor Cst may correspond to an extended portion of the storage line 126. Here, the second gate insulating layer 142 may be formed of a dielectric material, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the first gate electrode 155 of the driving transistor T1 as the second storage electrode E2 of the storage capacitor Cst, a space for forming the storage capacitor Cst can be ensured in the space narrowed due to the channel of the driving transistor T1 that occupies a large area within the pixel PX.

[0140] The first storage electrode E1 of the first pixel PX1 receives a driving voltage ELVDD through the driving voltage connection line 172c. Accordingly, the storage capacitor Cst stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage connection line 172c and the gate voltage Vg of the first gate electrode 155.

[0141] However, the driving voltage line 172 is connected to the first storage electrode E1 of the second pixel PX2 through the contact hole 68. Accordingly, the storage capacitor Cst of the second pixel PX2 stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage line 172 and the gate voltage Vg of the first gate electrode 155.

[0142] The second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64. The first electrode (e.g., Figure 16 191 shown in) is connected to the third data connection member 73 through the contact hole 81. The first electrode may be a pixel electrode of the pixel PX.

[0143] The parasitic capacitor control pattern 79 may be formed between the double gate electrodes of the third transistor T3. There will be a parasitic capacitor inside the pixel PX, and if the voltage applied to the parasitic capacitor changes, the image quality characteristics of the display device will deteriorate. In Figure 15 the first pixel PX1 shown in, the common voltage line 741 is provided instead of the driving voltage line 172, and thus, the driving voltage line 172 and the parasitic capacitor control pattern 79 are connected. However, in the second pixel PX2, the parasitic capacitor control pattern 79 and the driving voltage line 172 are connected through the contact hole 66. Accordingly, deterioration of the image quality characteristics can be prevented by applying the driving voltage ELVDD having a constant DC voltage to the parasitic capacitor. The parasitic capacitor control pattern 79 may be provided in a region different from the Figure 15 region shown in. The parasitic capacitor control pattern 79 may be applied with a voltage other than the driving voltage ELVDD.

[0144] One terminal of the first data connection member 71 is connected to the first gate electrode 155 of the driving transistor T1 through the contact hole 61, and the other terminal of the first data connection member 71 is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0145] One terminal of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the other terminal of the second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64.

[0146] The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 via the contact hole 69.

[0147] Hereinafter, in addition to referring to Figure 15 , also referring to Figure 16 The cross-sectional structure of the display device according to an exemplary embodiment will be described in a stacked order.

[0148] The display device according to an exemplary embodiment includes a first substrate 110.

[0149] The first substrate 110 may include a plastic layer and a barrier layer. In some embodiments, the plastic layer and the barrier layer may be alternately stacked.

[0150] The plastic layer may include one selected from the group consisting of polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyaryl compound, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone), and any combination thereof.

[0151] The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide. The barrier layer may include an inorganic material, but is not limited thereto.

[0152] A buffer layer 112 is provided on the first substrate 110, and an additional barrier layer 111 may be provided between the buffer layer 112 and the first substrate 110. The buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide or an organic insulating material such as polyimide acryl.

[0153] A semiconductor layer 130 including the channels, first electrodes, and second electrodes of each of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 is provided on the buffer layer 112.

[0154] A first gate insulating layer 141 is provided on the semiconductor layer 130 to cover the semiconductor layer 130. A first gate conductor layer including a first gate electrode 155, a scan line 151, a previous scan line 152, and a light emission control line 153 is provided on the first gate insulating layer 141.

[0155] A second gate insulating layer 142 is provided on the first gate conductor layer to cover the first gate conductor layer. The first gate insulating layer 141 and the second gate insulating layer 142 may include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide and an organic insulating material.

[0156] A second gate conductor layer including a storage line 126, an initialization voltage line 127, and a parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142.

[0157] An interlayer insulating layer 160 is disposed on the second gate conductor layer to cover the second gate conductor layer. The interlayer insulating layer 160 may include inorganic insulating materials such as silicon nitride, silicon oxide, and aluminum oxide, and may include an organic insulating material.

[0158] A data conductor layer including a data line 171, a driving voltage line 172, a first data connection member 71, a second data connection member 72, and a third data connection member 73 is disposed on the interlayer insulating layer 160. The first data connection member 71 may be connected to the first gate electrode 155 through a contact hole 61.

[0159] A passivation layer 180 is disposed on the data conductor layer to cover the data conductor layer. The passivation layer 180 may be a planarization layer and may include an organic insulating material or an inorganic insulating material.

[0160] A first electrode 191 is disposed on the passivation layer 180. The first electrode 191 is connected to the third data connection member 73 through a contact hole 81 formed in the passivation layer 180.

[0161] A separation layer 350 is disposed on the passivation layer 180 and the first electrode 191. The separation layer 350 has an opening 351 overlapping the first electrode 191. An emission layer 370 is disposed in the opening 351. A second electrode 270 is disposed on the emission layer 370 and the separation layer 350. The first electrode 191, the emission layer 370, and the second electrode 270 may form a light-emitting diode (light-emitting element) LED. The first electrode 191 may be a pixel electrode, and the second electrode 270 may be a common electrode.

[0162] According to an exemplary embodiment, the pixel electrode may be an anode as a hole injection electrode, and the common electrode may be a cathode as an electron injection electrode. Conversely, the pixel electrode may be a cathode, and the common electrode may be an anode. When holes and electrons are injected from the pixel electrode and the common electrode into the emission layer 370, excitons formed by the combination of holes and electrons are emitted when transitioning from an excited state to a ground state.

[0163] An encapsulation layer 400 for protecting the light-emitting element LED is disposed on the second electrode 270. As Figure 16 shown, the encapsulation layer 400 may be in contact with the second electrode 270, or according to another exemplary embodiment, the encapsulation layer 400 may be spaced apart from the second electrode 270.

[0164] The encapsulation layer 400 may be a thin film encapsulation layer in which an inorganic film and an organic film are stacked, and may include three layers including an inorganic film, an organic film, and an inorganic film. According to an exemplary embodiment, a cover layer and / or a functional layer may be disposed between the second electrode 270 and the encapsulation layer 400.

[0165] Figure 17 is a layout diagram of a pixel region of a display device according to an exemplary embodiment. Referring to Figure 17 , the display device includes a plurality of signal lines 127, 151, 152, 153, 171, 172, and 741. The plurality of signal lines 127, 151, 152, 153, 171, 172, and 741 may include scan lines 151 disposed in a first direction DR1, previous scan lines 152, light emission control lines 153, data lines 171 disposed in a second direction DR2, driving voltage lines 172, initialization voltage lines 127, and common voltage lines 741.

[0166] The display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst.

[0167] Each channel of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 is disposed in the semiconductor layer 130. At least a part of the first electrode and the second electrode of the plurality of transistors T1, T2, T3, T4, T5, and T6 may be disposed in the semiconductor layer 130.

[0168] Each of the plurality of signal lines 127, 151, 152, 153, 171, 172, and 741 and the semiconductor layer 130 are connected through a plurality of contact holes 82, 83, 84, 85, 86, 87, and 88.

[0169] Each transistor and the plurality of signal lines 127, 151, 152, 153, 171, 172, and 741 are similar to the corresponding transistors and signal lines shown in Figure 15 , and detailed descriptions of the same constituent elements are omitted.

[0170] Referring back to Figure 17 , the common voltage line 741 is disposed outside the regions of the pixels PX1, PX2, and PX3. Referring to the display device shown in Figure 15 , the driving voltage line 172 of some of the pixels PX1 is replaced with a common voltage line 741, and the corresponding pixels PX1 receive a driving voltage ELVDD from adjacent pixels through driving voltage connection lines 172c.

[0171] Returning to the reference Figure 17In the display device shown, the common voltage line 741 is separately provided outside the regions of the pixels PX1, PX2, and PX3. Accordingly, the common voltage line 741 can be provided without removing any of the conventional drive voltage lines 172 in the pixels PX1, PX2, and PX3.

[0172] That is, Figure 15 corresponding to the Figures 1 to 3 , Figure 7 and Figure 8 exemplary embodiments, and Figure 17 corresponding to the Figures 4 to 6 , Figure 9 and Figure 10 exemplary embodiments.

[0173] Figure 17 Differing from Figure 15 is also that the initialization voltage line 127 is provided in the second direction DR2 instead of in the first direction DR1. The initialization voltage line 127 can also be provided in a region between adjacent pixels PX1, PX2, and PX3.

[0174] Although the present disclosure has been described in connection with embodiments currently regarded as practical exemplary embodiments, it will be understood that the present disclosure is not limited to the exemplary embodiments. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the present disclosure.

Claims

1. A display device, wherein, The display device includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels disposed in the display area; a common voltage line disposed in the display area; a driving voltage line connected to each of the plurality of pixels; and a driving voltage connection line disposed in the display area and intersecting the driving voltage line, wherein, in a plan view, a subset of the plurality of pixels overlaps with the common voltage line in the display area, the external common voltage line and the common voltage line are connected to each other, and the width of the driving voltage connection line is reduced at an overlapping portion of the common voltage line and the driving voltage connection line.

2. The display device according to claim 1, wherein, The driving voltage line is indirectly connected to the subset of the plurality of pixels via the driving voltage connection line.

3. The display device according to claim 1, wherein, The external common voltage line is disposed to surround four edges of the display area.

4. The display device according to claim 1, wherein, The common voltage line further includes a lateral common voltage line and a longitudinal common voltage line.

5. The display device according to claim 1, wherein, The external common voltage line is divided via the display area.

6. A display device, wherein, The display device includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels disposed in the display area; a driving voltage line connected to each of the plurality of pixels; a plurality of common voltage lines disposed in the display area; and a driving voltage connection line disposed in the display area and intersecting the driving voltage line, wherein the external common voltage line and the plurality of common voltage lines are connected to each other, and the width of the driving voltage connection line is reduced at an overlapping portion of the common voltage line and the driving voltage connection line.

7. The display device according to claim 6, wherein, The external common voltage line is disposed to surround four edges of the display area.

8. The display device according to claim 6, wherein, The plurality of common voltage lines and the driving voltage line are disposed on the same layer.

9. The display device according to claim 7, wherein, Each of the plurality of common voltage lines further includes a lateral common voltage line and a longitudinal common voltage line, wherein, the plurality of common voltage lines are disposed farther from the substrate than the driving voltage line, and an insulating layer is disposed between the plurality of common voltage lines and the driving voltage line.

10. The display device according to claim 6, wherein, The external common voltage line is divided via the display area.

Images