Semiconductor devices

Abstract

The present invention provides a semiconductor device for improving the dynamic characteristics of a semiconductor device. The semiconductor device comprises: a transistor having a plurality of gate structures; and a diode portion having a cathode region on the lower surface of a semiconductor substrate, each gate structure having: a gate groove portion; an emitter region of a first conductivity type, which is disposed between the upper surface of the semiconductor substrate and a drift region in contact with the gate groove portion and has a higher doping concentration than the drift region; and a base region of a second conductivity type, which is disposed between the emitter region and the drift region in contact with the gate groove portion, wherein, in a plan view, a first threshold value of a gate structure portion closest to the cathode region is lower by more than 0.1 V and less than 1 V than a second threshold value of a gate structure portion farthest from the cathode region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device in which a transistor such as an insulated gate bipolar transistor (IGBT) and a diode such as a freewheeling diode (FWD) are provided on the same substrate (for example, refer to Patent Documents 1 to 6).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-41601

[0006] Patent Document 2: Japanese Patent Application Publication No. 2011-216825

[0007] Patent Document 3: Japanese Patent Application Publication No. 2015-118991

[0008] Patent Document 4: Japanese Patent Application Publication No. 2015-185742

[0009] Patent Document 5: Japanese Patent Application Publication No. 2018-6648

[0010] Patent Document 6: Japanese Patent Application Publication No. 2018-120990 Summary of the invention

[0011] Technical issues

[0012] In a semiconductor device, it is preferable to improve dynamic characteristics such as snapback.

[0013] Technical Solution

[0014] In order to solve the above-mentioned problems, a semiconductor device having a semiconductor substrate with a drift region of a first conductivity type is provided. The semiconductor device may have a transistor portion having a plurality of gate structures on the upper surface of the semiconductor substrate. The semiconductor device may have a diode portion, wherein the diode portion has a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on the lower surface of the semiconductor substrate. Each gate structure may have a gate groove portion arranged in a manner to reach the drift region from the upper surface of the semiconductor substrate. Each gate structure may have an emitter region of a first conductivity type having a doping concentration higher than that of the drift region and arranged in contact with the gate groove portion between the upper surface of the semiconductor substrate and the drift region. Each gate structure may have a base region of a second conductivity type arranged in contact with the gate groove portion between the emitter region and the drift region. In a plan view, the first threshold of the gate structure portion closest to the cathode region may be lower by more than 0.1V and less than 1V than the second threshold of the gate structure portion farthest from the cathode region.

[0015] In a plan view, the gate structure having the first threshold value may be provided in parallel with an end side of the cathode region.

[0016] The gate groove portion may be arranged in a manner having a long side in a direction parallel to the end side of the cathode region. The transistor portion may have a gate structure portion, and may have a plurality of gate mesas portions arranged along the long side of the gate groove portion. A gate mesas portion closest to the cathode region among the plurality of gate mesas portions may be provided with a gate structure portion having a first threshold value.

[0017] The gate groove portion may have a gate conductive portion. The gate groove portion may have a gate insulating film disposed between the gate conductive portion and the semiconductor substrate. The film thickness of the gate insulating film in the gate groove portion of the gate structure portion having the first threshold may be smaller than the film thickness of the gate insulating film in the gate groove portion of the gate structure portion having the second threshold.

[0018] The doping concentration of the base region of the gate structure portion having the first threshold may be lower than the doping concentration of the base region of the gate structure portion having the second threshold.

[0019] A channel density of the gate mesa portion having the first threshold may be higher than a channel density of the gate mesa portion having the second threshold.

[0020] The gate mesa portion may have an emitter region and a contact region of the second conductivity type having a doping concentration higher than that of the base region on the upper surface of the semiconductor substrate. An area ratio of the contact region at the upper surface of the gate mesa portion having a first threshold to the emitter region may be smaller than an area ratio of the contact region at the upper surface of the gate mesa portion having a second threshold to the emitter region.

[0021] The transistor portion may include a gate groove portion and a dummy groove portion. The density of the dummy groove portion in the proximity region of the transistor portion in contact with the cathode region in a top view may be less than the density of the dummy groove portion in the central region of the region farthest from the cathode region. The gate structure portion having the first threshold may be provided in the proximity region.

[0022] The diode part may have an upper surface side lifetime control region on the upper surface side of the semiconductor substrate, where the lifetime of carriers is lower than the lifetime of carriers in other regions. The upper surface side lifetime control region may be arranged in a manner extending to a proximity region of the transistor part in contact with the cathode region in a top view. The gate structure part having the first threshold may be arranged in the proximity region.

[0023] The cathode region may have a long side in a plan view. The gate structure having the first threshold may be disposed at a position opposite to the center of the long side of the cathode region, and may not be disposed at a position opposite to both ends of the long side. The gate trench may intersect with the long side of the cathode region in a plan view.

[0024] The semiconductor device may include an interlayer insulating film disposed above the upper surface of the semiconductor substrate and having a contact hole. The semiconductor device may include an emitter electrode disposed above the interlayer insulating film and in contact with the semiconductor substrate through the contact hole. On the upper surface of the semiconductor substrate, the gate groove portion may extend along a predetermined extension direction. In the extension direction, a contact hole having a long side in a direction different from the extension direction may be arranged between the gate structure portion having the first threshold and the end edge of the semiconductor substrate.

[0025] The first threshold value may be lower than the second threshold value by 0.1 V or more and 0.5 V or less.

[0026] It should be noted that the above invention summary does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0028] Figure 2 yes Figure 1 Magnified view of area A in FIG.

[0029] Figure 3 It is shown Figure 2 A diagram showing an example of the bb cross section in FIG.

[0030] Figure 4A 1 is a diagram showing an example of arrangement of the first gate structure 46 - 1 in a plan view.

[0031] Figure 4B1 is a diagram showing another example of arrangement of the first gate structure 46 - 1 in a plan view.

[0032] Figure 5 This is a diagram for explaining an example of the first gate structure 46 - 1 .

[0033] Figure 6 This is a diagram for explaining another example of the first gate structure 46 - 1 .

[0034] Figure 7 1 is a diagram showing an example of arrangement of doped regions on the upper surface of the mesa portion 60 .

[0035] Figure 8 1 is a diagram showing an example of arrangement of the groove portions on the upper surface of the transistor portion 70 .

[0036] Fig. 9 It is a diagram showing another example of the bb cross section.

[0037] Fig.10 1 is an example showing the relationship between the dose of impurities and the amount of decrease ΔVth in the threshold voltage of the first gate structure 46 - 1 .

[0038] Fig.11 This is a diagram for explaining the snapback phenomenon.

[0039] Fig.12 4 is a diagram showing the relationship between the amount of decrease ΔVth in the threshold voltage of the first gate structure 46 - 1 and the dynamic characteristics of the semiconductor device 100 .

[0040] Fig.13 2 is a diagram showing a configuration example of the upper surface of the semiconductor device 100 .

[0041] Fig.14 1 is a diagram showing an example of arrangement of the cathode region 82 on the upper surface of the active portion 120 .

[0042] Explanation of symbols

[0043] 10···semiconductor substrate, 11···well region, 12···emitter region, 14···base region, 15···contact region, 16···accumulation region, 18···drift region, 20···buffer region, 21···upper surface, 22···collector region, 23···lower surface, 24···collector, 29···straight line portion, 30···dummy groove portion, 31···front end portion, 32···dummy insulating film, 34···dummy conductive portion, 38···interlayer insulating film, 39···straight line portion, 40···gate groove portion, 41···front end portion, 42···gate insulating film, 44···gate conductive portion, 46···gate structure portion, 46-1···first Gate structure portion, 46-2···second gate structure portion, 52···emitter electrode, 54···contact hole, 56···contact hole, 60, 61···mesa portion, 70···transistor portion, 71···proximity region, 73···central region, 80···diode portion, 81···extension region, 82···cathode region, 83···intersection portion, 84···connection portion, 85···long side, 90···edge terminal structure portion, 92···upper surface side lifetime control region, 100···semiconductor device, 102···end side, 112···gate pad, 120···active portion, 130···peripheral gate wiring, 131···active side gate wiring DETAILED DESCRIPTION

[0044] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0045] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is actually installed.

[0046] In this specification, there are cases where the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes only specify the relative positions of the components, and do not limit specific directions. For example, the Z-axis is not limited to represent the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the positive and negative are not recorded but the Z-axis direction is recorded, it means a direction parallel to the +Z-axis and the -Z-axis. In addition, in this specification, the situation of observing from the +Z-axis direction is sometimes referred to as a top view.

[0047] In this specification, when the terms "same" or "equal" are used, this may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0048] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. The conductivity type of each doped region may be of opposite polarity. In addition, when described as P+ type or N+ type in this specification, it means that the doping concentration is higher than the doping concentration of P-type or N-type, and when described as P-type or N-type, it means that the doping concentration is lower than the doping concentration of P-type or N-type. In addition, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than the doping concentration of P+ type or N+ type.

[0049] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors is sometimes used as doping concentration. This concentration difference can be measured using the voltage-capacitance measurement method (CV method). In addition, the carrier concentration measured using the expansion resistance measurement method (SR) is used as the doping concentration. In addition, in the case where the doping concentration distribution has a peak, the peak value can be used as the doping concentration of the region. In the case where the doping concentration of the region where the donor or acceptor exists is roughly uniform, the average value of the doping concentration can be used as the doping concentration of the region. In addition, in this specification, the concentration of the dopant refers to the concentration of the donor and the acceptor respectively.

[0050] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 In FIG. 1 , only some components of the semiconductor device 100 are shown, and some components are omitted.

[0051] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has an edge 102 when viewed from above. In this specification, when simply referred to as viewed from above, it means observing from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edge 102 facing each other when viewed from above. Figure 1 In the embodiment, the X-axis and the Y-axis are parallel to any end side 102. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0052] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. An emitter electrode is provided above the active portion 120, but Figure 1 Omitted in .

[0053] The active region 120 includes a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a FWD. Figure 1 In FIG. 1 , a region where the transistor portion 70 is disposed is marked with a symbol “I”, and a region where the diode portion 80 is disposed is marked with a symbol “F”. The transistor portion 70 and the diode portion 80 are arranged in a predetermined direction (in Figure 1 The transistor portion 70 and the diode portion 80 may be arranged in parallel alternately along the X-axis direction. In this specification, the direction perpendicular to the arrangement direction in a plan view is sometimes referred to as the extension reverse direction (in the X-axis direction). Figure 1 The transistor portion 70 and the diode portion 80 may each have a long side in the extending direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The long side direction of the transistor portion 70 and the diode portion 80 may be the same as or different from the long side direction of the groove portion described later.

[0054] The diode portion 80 has an N+ type cathode region in the region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region overlapping with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a P+ type collector region may be provided in a region other than the cathode region. In this specification, an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0055] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. In addition to the gate pad 112, the semiconductor device 100 may also have an anode pad, a cathode pad, and a current detection pad. Each pad is arranged near the end 102. The vicinity of the end 102 refers to the area between the end 102 and the emitter electrode when viewed from above. When the semiconductor device 100 is actually installed, each pad is connected to an external circuit via wiring such as a cable.

[0056] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of a gate trench portion of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 to the gate trench portion. Figure 1 In the figure, the gate wiring is shaded with diagonal lines.

[0057] The gate wiring of this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is arranged between the active portion 120 and the edge 102 of the semiconductor substrate 10 in a plan view. The peripheral gate wiring 130 of this example surrounds the active portion 120 in a plan view. The area surrounded by the peripheral gate wiring 130 in a plan view can be set as the active portion 120. In addition, the peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 can be a metal wiring including aluminum or the like.

[0058] The active side gate wiring 131 is provided in the active portion 120. By providing the active side gate wiring 131 in the active portion 120, it is possible to reduce the variation in the wiring length from the gate pad 112 to each region of the semiconductor substrate 10, in other words, it is possible to reduce the variation in the delay and attenuation of the voltage applied to each region.

[0059] The active-side gate wiring 131 is connected to the gate trench portion of the active portion 120. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0060] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. The active-side gate wiring 131 of this example is provided to extend in the X-axis direction so as to cross the active portion 120 from one peripheral gate wiring 130 to the other peripheral gate wiring 130 at approximately the center in the Y-axis direction.

[0061] In addition, the semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detection portion (not shown) which simulates the operation of a transistor portion provided in the active portion 120 .

[0062] The semiconductor device 100 of this example includes an edge termination structure 90 between the peripheral gate wiring 130 and the edge 102. The edge termination structure 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has, for example, a guard ring, a field plate, a surface electric field reduction, or a structure obtained by combining them. The guard ring, the field plate, the surface electric field reduction, or a structure obtained by combining them can be provided in a ring shape surrounding the active portion 120.

[0063] Figure 2 yes Figure 1 1 is an enlarged view of region A. Region A is a region including the transistor portion 70, the diode portion 80, and the active-side gate wiring 131. In the region where the active portion 120 is adjacent to the peripheral gate wiring 130, the peripheral gate wiring 130 may be arranged instead of the active-side gate wiring 131.

[0064] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15. The gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15 are provided inside the upper surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131. The emitter electrode 52 and the active-side gate wiring 131 are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0065] Although an interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, Figure 2 In this example, the interlayer insulating film is provided with a contact hole 54 that penetrates the interlayer insulating film. Figure 2 In FIG. 1 , each contact hole 54 is shaded with diagonal lines.

[0066] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the trench portion 30 through the contact hole provided in the interlayer insulating film. The emitter electrode 52 can be connected to the dummy conductive portion of the dummy trench portion 30 at the front end of the dummy trench portion 30 in the Y-axis direction.

[0067] The active side gate wiring 131 is connected to the gate groove portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 can be connected to the gate conductive portion of the gate groove portion 40 at the front end portion 41 of the gate groove portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy groove portion 30.

[0068] The emitter electrode 52 is formed of a material including metal. Figure 2, the range in which the emitter electrode 52 is provided is shown. For example, at least a portion of the emitter electrode 52 may be formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed of titanium and / or a titanium compound, etc., in the lower layer of the region formed of aluminum, etc. Further, in the contact hole, there may be a plug formed by embedding tungsten, etc. in a manner that contacts the barrier metal and aluminum, etc.

[0069] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend with a predetermined width in a range not overlapping with the active side gate wiring 131. The well region 11 of this example is provided so as to be separated from the active side gate wiring 131 with respect to the end in the Y-axis direction of the contact hole 54. The well region 11 is a region of the second conductivity type having a higher doping concentration than the doping concentration of the base region 14. The base region 14 of this example is of the P- type, and the well region 11 is of the P+ type.

[0070] The transistor section 70 and the diode section 80 each have a plurality of groove sections arranged along the arrangement direction. In the transistor section 70 of this example, one or more gate groove sections 40 and one or more dummy groove sections 30 are alternately arranged along the arrangement direction. In the diode section 80 of this example, a plurality of dummy groove sections 30 are arranged along the arrangement direction. In the diode section 80 of this example, no gate groove section 40 is provided.

[0071] The gate trench portion 40 of this example may include two straight line portions 39 extending in an extending direction perpendicular to the arrangement direction (portions forming a straight groove along the extending direction) and a front end portion 41 connecting the two straight line portions 39 . Figure 2 The extension direction is the Y-axis direction.

[0072] Preferably, at least a portion of the tip portion 41 is curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39 .

[0073] In the transistor portion 70, the dummy trench portion 30 is provided between the straight line portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the straight line portions 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a straight line shape extending in the extending direction, or may have a straight line portion 29 and a front end portion 31 similarly to the gate trench portion 40. Figure 2 The semiconductor device 100 shown includes both a linear dummy trench portion 30 having no front end portion 31 and a dummy trench portion 30 having a front end portion 31. In this specification, each linear portion of each trench portion may be treated as one trench portion.

[0074] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a plan view. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. Thus, the electric field concentration at the bottom of each trench portion can be alleviated.

[0075] A mesa portion is provided between each groove portion in the arrangement direction. The mesa portion refers to an area clamped by the groove portion inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the groove portion. The mesa portion of this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the groove portion. In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when only the mesa portion is referred to, it refers to the mesa portion 60 and the mesa portion 61 in general.

[0076] The mesa portion 60 in the mesa portion 60 that contacts the gate trench portion 40 and has the emitter region 12 is referred to as a gate mesa portion. In this example, the mesa portion 60 of the transistor portion 70 is the entire gate mesa portion. In other examples, the transistor portion 70 may have a dummy mesa portion that is not in contact with the gate trench portion 40 or has no emitter region 12.

[0077] A base region 14 is provided in each mesa portion. A region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 and located closest to the active-side gate wiring 131 is referred to as a base region 14-e. Figure 2 In the figure, although the base region 14-e is shown to be arranged at the end of one side in the extension direction of each mesa portion, the base region 14-e is also arranged at the end of the other side of each mesa portion. In each mesa portion, the area sandwiched by the base region 14-e in a plan view can be provided with at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 can be arranged between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0078] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0079] The contact regions 15 and emitter regions 12 in the mesa portion 60 are arranged from the groove portion on one side in the X-axis direction to the groove portion on the other side. As an example, the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the extending direction of the groove portion (Y-axis direction).

[0080] In other examples, the contact region 15 and the emitter region 12 of the mesa portion 60 may be arranged in strips along the extending direction of the groove portion (Y-axis direction). For example, the emitter region 12 is arranged in the region contacting the groove portion, and the contact region 15 is arranged in the region sandwiched by the emitter region 12.

[0081] The emitter region 12 is not provided in the mesa portion 61 of the diode portion 80. The base region 14 and the contact region 15 may be provided on the upper surface of the mesa portion 61. The contact region 15 may be provided in contact with each base region 14-e in the region sandwiched by the base region 14-e on the upper surface of the mesa portion 61. The base region 14 may be provided in the region sandwiched by the contact region 15 on the upper surface of the mesa portion 61. The base region 14 may be arranged in the entire region sandwiched by the contact region 15.

[0082] In the transistor portion 70, a buffer zone may be provided in a region in contact with the diode portion 80. The mesa portion of the buffer zone is a dummy mesa portion having the same structure as the mesa portion 61 of the diode portion 80. The collector region 22 is provided on the lower surface of the dummy mesa portion of the buffer zone. By providing the buffer zone, the cathode region 82 can be configured separately from the gate mesa portion, and the flow of carriers between the gate mesa portion and the cathode region 82 can be suppressed.

[0083] The mesa portion of the buffer region may have a contact region 15 on the upper surface of the semiconductor substrate 10 instead of at least a part of the base region 14 of the diode portion 80. The area of ​​the contact region 15 on the upper surface of the mesa portion of the buffer region is larger than the area of ​​the contact region 15 on the upper surface of one mesa portion 60. Thus, when the transistor portion 70 is turned off, it becomes easy to extract carriers such as holes to the emitter electrode side.

[0084] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched by the base region 14-e. The contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the mesa portion 60 in the arrangement direction (X-axis direction).

[0085] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. In the lower surface of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. Figure 2In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0086] Figure 3 It is shown Figure 2 FIG. bb section is an example of a cross section of FIG. bb section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section. The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film including at least one of a silicate glass film to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with Figure 2 The contact hole 54 described in FIG.

[0087] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0088] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in the transistor portion 70 and the diode portion 80, respectively.

[0089] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially provided from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0090] The emitter region 12 is disposed between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate groove portion 40. The emitter region 12 may be in contact with the groove portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18.

[0091] The base region 14 is provided between the emitter region 12 and the drift region 18. The base region 14 of this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the groove portions on both sides of the mesa portion 60.

[0092] The accumulation region 16 is provided below the base region 14. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved and the on-state voltage can be reduced. The accumulation region 16 can be provided in a manner covering the entire lower surface of the base region 14 in each mesa portion 60.

[0093] The mesa portion 61 of the diode portion 80 is provided with a P-type base region 14 in contact with the upper surface 21 of the semiconductor substrate 10. The drift region 18 is provided below the base region 14. The reservoir region 16 may be provided below the base region 14 in the mesa portion 61.

[0094] In each transistor portion 70 and diode portion 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82. The buffer region 20 may have a plurality of peaks or a single peak in the doping concentration distribution in the depth direction.

[0095] In transistor section 70, P+ type collector region 22 is provided below buffer region 20. In diode section 80, N+ type cathode region 82 is provided below buffer region 20. Collector region 22 and cathode region 82 are exposed on lower surface 23 of semiconductor substrate 10 and connected to collector electrode 24.

[0096] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least any one of the emitter region 12, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these doped regions and reaches the drift region 18. The groove portion penetrating the doped region is not limited to being manufactured in the order of forming the groove portion after forming the doped region. Forming a doped region between the groove portions after forming the groove portion is also included in the groove portion penetrating the doped region.

[0097] As described above, the gate trench portion 40 and the dummy trench portion 30 are provided in the transistor portion 70. The dummy trench portion 30 is provided in the diode portion 80, but the gate trench portion 40 is not provided.

[0098] In this example, the boundary between the transistor portion 70 and the diode portion 80 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22. Figure 3 In the example of FIG. 1 , the dummy trench portion 30 is arranged at the end of the transistor portion 70 in the X-axis direction.

[0099] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position further inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0100] The gate conductive portion 44 can be set longer than the base region 14 in the depth direction. The gate groove portion 40 of the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed on the surface layer of the interface contacting the gate groove portion 40 in the base region 14.

[0101] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0102] The gate trench 40 and the dummy trench 30 of this example are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces convex downward (curved in cross section).

[0103] In this specification, the combination of the gate trench portion 40, the emitter region 12 in contact with the gate trench portion 40, and the base region 14 in contact with the gate trench portion 40 is referred to as a gate structure portion 46. The gate structure portion 46 may include only the portion of the emitter region 12 and the base region 14 of the mesa portion 60 in contact with the gate trench portion 40.

[0104] The transistor portion 70 has a plurality of gate structures 46 arranged in parallel in the X-axis direction. Each gate structure 46 has a threshold value corresponding to the characteristics of each component. The threshold value refers to a voltage at which a channel is formed in the base region 14 and the gate structure is turned on when the gate voltage is gradually increased. The threshold value is determined by, for example, the doping concentration of the base region 14.

[0105] The semiconductor device 100 has gate structures 46 with different thresholds. In this example, the semiconductor device 100 has one or more second gate structures 46-2 with a second threshold and one or more first gate structures 46-1 with a first threshold lower than the second threshold. The first threshold is lower than the second threshold by 0.1V or more and 1V or less.

[0106] In this example, the gate structure 46 closest to the cathode region in a plan view is the first gate structure 46-1 having the first threshold. The plurality of gate structures 46 selected in sequence starting from the gate structure 46 closest to the cathode region 82 may be the first gate structure 46-1. That is, the transistor portion 70 has the first gate structure 46-1 at the boundary portion with the diode portion 80. Figure 3 In the example of , the two gate structures 46 that are closest to the cathode region 82 are the first gate structures 46 - 1 . In this example, the distance from the cathode region 82 refers to the distance in the X-axis direction.

[0107] In addition, the gate structure 46 which is farthest from the cathode region 82 is the second gate structure 46-2 having the second threshold value. All gate structures 46 other than the first gate structure 46-1 may be the second gate structure 46-2.

[0108] At the boundary portion between the transistor portion 70 and the diode portion 80, an NPN transistor is formed by the emitter region 12, the base region 14, and the cathode region 82. Therefore, even if a collector-emitter voltage is applied to turn on the transistor portion 70, the current increases linearly relative to the applied voltage at the boundary portion. If the applied voltage reaches a voltage exceeding the built-in voltage of the PN junction near the collector region 22, a conductivity modulation state is achieved. In particular, if the width of the transistor portion 70 in the X-axis direction is miniaturized, the proportion of the boundary portion increases, and the proportion of the current flowing in the NPN transistor increases. Therefore, the transistor portion 70 does not become conductive until the applied voltage becomes a high voltage, resulting in a snapback phenomenon in which the voltage decreases sharply and the current increases sharply when the transistor becomes conductive. In addition, even if the snapback phenomenon does not occur, the on-state voltage increases and the conduction loss increases due to the obstruction of conductivity modulation.

[0109] According to the semiconductor device 100 of this example, the first gate structure 46-1 with a low threshold is arranged at the boundary portion between the transistor portion 70 and the diode portion 80. When the transistor portion 70 is turned on, the first gate structure 46-1 with a low threshold becomes turned on earlier than the second gate structure 46-2. Therefore, at the boundary portion, electrons are supplied early from the first gate structure 46-1, so that the PN junction near the collector region 22 is operated early. Therefore, conductivity modulation can be promoted. In addition, the snapback phenomenon can be suppressed.

[0110] Figure 4A 4 is a diagram showing an example of the arrangement of the first gate structure 46-1 in a plan view. Figure 4A , the vicinity of the boundary between the transistor portion 70 and the diode portion 80 is shown in an enlarged manner. In a plan view, the cathode region 82 may be a rectangular shape having long sides in the Y-axis direction. In this example, the long side 83 of the end sides of the cathode region 82 is shown. In addition, the positions of the two ends of the cathode region 82 in the Y-axis direction are set to Yb1 and Yb2, and the central position is set to Yc. In addition, the positions of the two ends of the contact hole 54 in the Y-axis direction are set to Yh1 and Yh2.

[0111] In a top view, the first gate structure portion 46-1 can be arranged parallel to the end edge of the cathode region 82. In this example, the first gate structure portion 46-1 is arranged parallel to the long side 83 of the cathode region 82. The direction in which the first gate structure portion 46-1 is arranged is the direction in which the gate groove portion 40 has a long side. In addition, the gate table portion (the table portion 60 in this example) is arranged along the long side direction of the gate groove portion 40. That is, the long side direction of the gate table portion is the same direction as the long side direction of the gate groove portion 40. The direction in which the gate groove portion 40 has a long side is the direction in which the straight portion 39 of the gate groove portion 40 extends. Figure 4A The direction of the Y-axis is shown in FIG. 1. It should be noted that the region where the contact region 15 in contact with the emitter region 12 along the Y-axis direction is provided is also included in the first gate structure portion 46-1.

[0112] As described above, the first gate structure portion 46-1 is provided in one or more gate mesa portions that are closest to the cathode region 82 among the plurality of gate mesa portions (the mesa portion 60 in this example). The first gate structure portion 46-1 in this example can be provided over two or more emitter regions 12 that are periodically arranged in the Y-axis direction. The first gate structure portion 46-1 can be provided in a range including the central position Yc in the Y-axis direction. The first gate structure portion 46-1 can be provided in a range wider than the cathode region 82 in the Y-axis direction. That is, the first gate structure portion 46-1 can be provided in a position that is further outward than the end positions Yb1 and Yb2 of the cathode region 82 in the Y-axis direction. The outer side refers to the side away from the central position Yc. The first gate structure portion 46-1 can be provided in a position that is further inward than the end positions Yh1 and Yh2 of the contact hole 54 in the Y-axis direction. The inner side refers to the side close to the central position Yc. The first gate structure 46-1 may be provided to a position further outward than the end positions Yh1 and Yh2 of the contact hole 54 in the Y-axis direction. The first gate structure 46-1 may be provided over all emitter regions 12 of the gate mesa portion. The first gate structure 46-1 may be provided over all contact regions 15 of the gate mesa portion. The first gate structure 46-1 may be provided over the entire range of the mesa portion 60 in the Y-axis direction.

[0113] Figure 4B : is a diagram showing other configuration examples of the first gate structure 46-1 when viewed from above. The first gate structure 46-1 of this example is arranged at a position opposite to the central position Yc of the cathode region 82 in the X-axis direction. That is, the first gate structure 46-1 is arranged in the range including the central position Yc in the Y-axis direction. Among them, the first gate structure 46-1 of this example is not arranged at a position opposite to the end positions Yb1 and Yb2 of the long side 83 of the cathode region 82 in the X-axis direction. That is, the first gate structure 46-1 is arranged in the range between the end positions Yb1 and Yb2 in the Y-axis direction. The first gate structure 46-1 may not be arranged in the outermost emitter region 12 in the emitter region 12 arranged between the end positions Yb1 and Yb2 in the Y-axis direction.

[0114] The second gate structure 46-2 may be provided in the area other than the first gate structure 46-1 in the mesa portion 60. The second gate structure 46-2 may be provided at a position further inside than the end positions Yh1 and Yh2 of the contact hole 54 in the Y-axis direction. The second gate structure 46-2 may be provided at a position further outside than the end positions Yh1 and Yh2 of the contact hole 54 in the Y-axis direction.

[0115] If the threshold of the gate structure 46 is low, avalanche breakdown is likely to occur on the lower surface 23 side of the semiconductor substrate 10. In the active portion 120, carriers sometimes flow in from the outside of the active portion 120. Therefore, avalanche breakdown is more likely to occur at the end of the active portion 120. In this regard, by not providing the first gate structure 46-1 on the outer portion of the mesa portion 60, avalanche breakdown in this portion can be suppressed. On the other hand, by providing the first gate structure 46-1 in the central portion of the mesa portion 60, conductivity modulation can be promoted.

[0116] Figure 5 This is a diagram illustrating an example of the first gate structure 46-1. The film thickness T1 of the gate insulating film 42 of the first gate structure 46-1 of this example is smaller than the film thickness T2 of the gate insulating film 42 of the second gate structure 46-2. As the film thickness of the gate insulating film 42, the film thickness in the X-axis direction at the central position of the gate groove portion 40 in the depth direction (Z-axis direction) can be used. The film thickness T1 can be set within a range of less than the thickness of the film thickness T2 and greater than about 80% of the film thickness T2, preferably 99% to 84% of the film thickness T2. As a result, the first threshold of the first gate structure 46-1 becomes smaller than the second threshold of the second gate structure 46-2.

[0117] By forming the gate insulating film 42 of the first gate structure 46-1 and the gate insulating film 42 of the second gate structure 46-2 in different processes and conditions, the film thickness of each gate insulating film 42 can be made different. Figure 4B As shown, in the case where the first gate structure 46 - 1 and the second gate structure 46 - 2 are provided in the one straight line portion 39 of the gate trench portion 40 , the film thickness of the gate insulating film 42 in the one straight line portion 39 may vary.

[0118] Figure 6 This is a diagram for explaining another example of the first gate structure 46-1. Figure 6 In the embodiment of the present invention, as a P-type, the doping concentration of the base region 14 of the second gate structure 46-2 is lower than that of the base region 14 of the second gate structure 46-2. The doping concentration of the base region 14 of the first gate structure 46-1 can be set within a range of about 70% of the doping concentration of the base region 14 of the second gate structure 46-2 and lower than that of the base region 14 of the second gate structure 46-2. Thus, the first threshold of the first gate structure 46-1 becomes smaller than the second threshold of the second gate structure 46-2.

[0119] By forming the base region 14 of the first gate structure 46-1 and the base region 14 of the second gate structure 46-2 in different processes and conditions, the doping concentrations of the base regions 14 can be made different. Figure 4B As shown, in the case where one straight line portion 39 of the gate trench portion 40 is provided with the first gate structure portion 46 - 1 and the second gate structure portion 46 - 2 , the doping concentration of the base region 14 in one mesa portion 60 may vary.

[0120] It should be noted that the doping concentration of at least one base region 14 of the diode portion 80 may be the same as the doping concentration of the base region 14 of the first gate structure portion 46-1. The doping concentration of the base region 14 of one or more mesa portions 61 selected sequentially from, for example, the mesa portion 61 closest to the transistor portion 70 among the mesa portions 61 of the diode portion 80 may be the same as the doping concentration of the base region 14 of the first gate structure portion 46-1.

[0121] Figure 7 : is a diagram showing an example of the configuration of the doping region on the upper surface of the mesa portion 60. In this example, a region in the transistor portion 70 whose distance from the diode portion 80 in the X-axis direction is within a predetermined value is set as a proximity region 71. In addition, the central position of the transistor portion 70 in the X-axis direction is set as Xc, and the region of the transistor portion 70 including the central position Xc is set as a central region 73. The central position Xc is the position farthest from the diode portion 80. A plurality of mesa portions 60 may be included in the proximity region 71. The gate structure portion 46 included in the proximity region 71 is set as a first gate structure portion 46-1, and the gate structure portion 46 such as the central region 73 other than the proximity region 71 is set as a second gate structure portion 46-2.

[0122] In this example, the channel density of the gate mesa portion (in this example, the mesa portion 60) in the proximity region 71 is higher than the channel density of the gate mesa portion in the central region 73. The channel density refers to the ratio of the channels included in a unit area when viewed from above. In this example, the ratio of the area of ​​the emitter region 12 included in the mesa portion 60 to the area excluding the emitter region 12 can be set as the channel density. The area of ​​the emitter region 12 of the mesa portion 60 in the proximity region 71 is set to S1, the area of ​​the area excluding the emitter region 12 (in this example, the contact area 15) is set to S2, the area of ​​the emitter region 12 of the mesa portion 60 in the central region 73 is set to S3, and the area of ​​the area excluding the emitter region 12 is set to S4.

[0123] In this example, the area ratio S1 / (S1+S2) may be higher than the area ratio S3 / (S3+S4). The area ratio S1 / (S1+S2) may be 1.5 times or more than the area ratio S3 / (S3+S4), or may be 2 times or more. The higher the channel density (in this example, the area ratio S1 / (S1+S2)), the smaller the threshold of the gate structure 46 becomes. Thus, the first threshold of the first gate structure 46-1 included in the proximity region 71 becomes smaller than the second threshold of the second gate structure 46-2 included in the central region 73, etc.

[0124] In addition, the ratio of the length of the emitter region 12 included in the mesa portion 60 to the length of the region other than the emitter region 12 in the Y-axis direction can be set as the channel density. The length of the emitter region 12 of the mesa portion 60 in the proximity region 71 is set to L1, the length of the region other than the emitter region 12 (in this example, the contact region 15) is set to L2, the length of the emitter region 12 of the mesa portion 60 in the central region 73 is set to L3, and the length of the region other than the emitter region 12 is set to L4. The channel density L1 / (L1+L2) is higher than the channel density L3 / (L3+L4). The channel density L1 / (L1+L2) can be more than 1.5 times the channel density L3 / (L3+L4), or more than 2 times.

[0125] Figure 8 1 is a diagram showing an example of the arrangement of the groove portion on the upper surface of the transistor portion 70. The transistor portion 70 of this example is also Figure 7 Similarly, the example of has a proximity region 71 and a central region 73 , and the channel density of the proximity region 71 is higher than the channel density of the central region 73 .

[0126] In this example, the density of the dummy groove portions 30 in the proximity region 71 is lower than the density of the dummy groove portions 30 in the central region 73. That is, the density of the gate groove portions 40 in the proximity region 71 is higher than the density of the gate groove portions 40 in the central region 73. The density of the groove portions is the number of groove portions included in a unit width in the X-axis direction. In this example, the straight line portion of each groove portion is set as one groove portion. Figure 8 In the example, in the region other than the proximity region 71, the gate trench portions 40 and the dummy trench portions 30 are alternately arranged along the X-axis direction. In contrast, in the proximity region 71, two or more gate trench portions 40 are continuously arranged along the X-axis direction. Thus, the first threshold of the first gate structure portion 46-1 included in the proximity region 71 becomes smaller than the second threshold of the second gate structure portion 46-2 included in the central region 73 and the like.

[0127] Fig. 9 FIG. 1 is a diagram showing another example of the cross section taken along line bb. Figure 3In addition to the structure of the semiconductor device 100 shown in FIG. 1 , the semiconductor device 100 further includes an upper surface side lifetime control region 92. Figure 3 The semiconductor device 100 shown is the same. In this example, the semiconductor device 100 also has a proximity region 71 .

[0128] The upper surface side lifetime control region 92 is a region formed by injecting impurities such as light ions from the upper surface 21 side of the semiconductor substrate 10. The impurities are, for example, hydrogen ions such as helium ions or protons. In the upper surface side lifetime control region 92, crystal defects are formed by injecting impurities, and the carrier lifetime is lower than that in other regions due to the crystal defects.

[0129] exist Fig. 9 In the figure, a cross mark is used to indicate the peak position of the distribution of crystal defects and carrier lifetime in the depth direction. The distribution has a slope relative to the lower surface 23 side and the upper surface 21 side starting from the cross mark. In the case of impurities being injected from the upper surface 21 side, crystal defects are also formed in the impurity passing region. Therefore, the slope of the distribution of crystal defects and carrier lifetime on the upper surface 21 side is gentler than the slope of the distribution of crystal defects and carrier lifetime on the lower surface 23 side. By the inclination of the slope of the distribution, it is possible to determine whether an upper surface side lifetime control region 92 is formed by injecting impurities from the upper surface 21 side. The upper surface side lifetime control region 92 can be set at a position closer to the upper surface 21 side than the center in the depth direction of the semiconductor substrate 10.

[0130] The diode unit 80 has an upper surface side lifetime control region 92. The upper surface side lifetime control region 92 may be provided over the entire range in the X-axis direction of the diode unit 80. By providing the upper surface side lifetime control region 92 in the diode unit 80, the reverse recovery time of the diode unit 80 can be shortened, and the reverse recovery loss can be reduced.

[0131] The upper surface side lifetime control region 92 is provided so as to extend to the proximity region 71 of the transistor portion 70. That is, the upper surface side lifetime control region 92 is provided continuously from the diode portion 80 to the proximity region 71. In this example, in the transistor portion 70, the region where the upper surface side lifetime control region 92 is provided is set as the proximity region 71.

[0132] As described above, if impurities are injected from the upper surface 21 side of the semiconductor substrate 10, crystal defects are also formed in the impurity passage area. Therefore, crystal defects are also formed in the portion of the base region 14 near the region 71 that functions as a channel. If the crystal defect density in the channel portion increases, the threshold of the gate structure 46 decreases. As a result, the first threshold of the first gate structure 46-1 included in the close region 71 becomes smaller than the second threshold of the second gate structure 46-2 included in other regions. It should be noted that the upper surface side lifetime control region 92 is not limited to impurity injection from the upper surface side, and highly accelerated light element ion injection or the like can also be implemented from the lower surface side to the vicinity of the groove. Even in this case, the influence of the foot of the peak can be utilized to make the first threshold of the gate structure 46-1 smaller than the second threshold of the second gate structure 46-2 included in other regions. It should be noted that in FIG. 4A to FIG. 9 Each example described in the above may be combined with other examples. Three or more examples may also be combined.

[0133] Fig.10 An example of the dose of impurities implanted to form the upper surface lifetime control region 92 and the decrease in the threshold voltage ΔVth of the first gate structure 46-1 is shown. The decrease ΔVth corresponds to the difference between the second threshold and the first threshold. In this example, the impurities are helium ions. Fig.10 In FIG. 1 , the solid line portion is a measured value, and the dotted line portion is a calculated value. In the example where the upper surface side lifetime control region 92 is not provided, the threshold value of the gate structure portion 46 is 6V or more and 6.5V or less.

[0134] In this example, 20V is applied between the emitter and the collector, and the gate voltage is gradually increased from 0V, and the gate voltage when a current of 1 / 1000 of the rated current flows is measured as a threshold. It should be noted that although the current flowing through the entire semiconductor device 100 is measured, as described above, the first gate structure 46-1 with a low threshold value starts to flow current earlier than other regions. Therefore, the gate voltage when a current of 1 / 1000 of the rated current flows can be regarded as the threshold voltage of the first gate structure 46-1.

[0135] like Fig.10 As shown, the first threshold of the first gate structure 46-1 can be controlled by the dose of the impurity. It should be noted that the decrease amount ΔVth of the threshold voltage also varies depending on the range of the impurity (the depth position of the upper surface side lifetime control region 92).

[0136] Fig.11 This is a diagram for explaining the snapback phenomenon. Fig.11The collector current Ic is shown when the emitter-collector voltage Vce is gradually increased. In a normal waveform without snapback, if the voltage Vce starts to increase, current flows mainly through the NPN transistor. If the voltage Vce is further increased, the transistor unit 70 operates as an IGBT by conductivity modulation. In contrast, if snapback occurs, the transistor unit 70 is not in the on state until the voltage Vce becomes high voltage, and the current increases sharply when the transistor unit 70 is in the on state.

[0137] Fig.12 4 is a diagram showing the relationship between the drop amount ΔVth of the threshold voltage of the first gate structure 46 - 1 and the dynamic characteristics of the semiconductor device 100 . Fig.12 In the embodiment, whether the snapback suppression effect is produced and whether the semiconductor device 100 is stably operated are evaluated as the dynamic characteristics of the semiconductor device 100. The case where the snapback suppression effect is produced is indicated by a circle mark. In addition, the case where the semiconductor device 100 is stably operated is indicated by a circle mark, the case where the operation becomes unstable but the semiconductor device 100 is not destroyed is indicated by a triangle mark, and the case where the semiconductor device 100 is likely to be destroyed is indicated by a cross mark.

[0138] like Fig.12 As shown in FIG. 1 , the snapback suppression effect can be obtained by setting the ΔVth of the first gate structure portion 46 - 1 to be 0.1 V or more. The ΔVth of the first gate structure portion 46 - 1 may be 0.2 V or more.

[0139] On the other hand, if ΔVth is made too large, the difference in threshold voltage between the first gate structure 46-1 and the second gate structure 46-2 becomes large, and the operation of the semiconductor device 100 may become unstable. For example, when the transistor portion 70 is turned on, the current may be locally concentrated in the first gate structure 46-1, and the latch tolerance may be reduced. In addition, if the doping concentration of the base region 14 is too low, the resistance value of the base region 14 may increase, and the latch tolerance may be reduced. In addition, if the threshold voltage becomes small, when the semiconductor device 100 is short-circuited, avalanche breakdown is likely to occur on the lower surface 23 side. In addition, if crystal defects are excessively formed, the leakage current increases, and thermal breakdown is likely to occur.

[0140] like Fig.12 As shown, if ΔVth is greater than 1.0V, the semiconductor device 100 is easily destroyed. Therefore, the ΔVth of the first gate structure 46-1 in this example is 1.0V or less. More preferably, the ΔVth of the first gate structure 46-1 is 0.5V or less. Thus, the occurrence of snapback can be suppressed, and the semiconductor device 100 can be operated stably. The ΔVth of the first gate structure 46-1 can be 0.3V or less.

[0141] Fig.13 1 is a diagram showing an example of the configuration of the upper surface of the semiconductor device 100. The semiconductor device 100 of this example further includes a contact hole 56 for hole extraction. The contact hole 56 is provided between the first gate structure 46-1 and the end side 102 of the semiconductor substrate 10 in the Y-axis direction. The emitter electrode 52 is connected to the P-type region of the semiconductor substrate 10 through the contact hole 56. Although the contact hole 56 of this example is arranged above the base region 14-e, the contact hole 56 may also be arranged above the well region 11, may also be arranged above other base regions 14, and may also be arranged above the contact region 15.

[0142] The contact hole 56 has a long side in a direction different from the extension direction (Y-axis direction) of the gate groove portion 40. The contact hole 56 of this example has a long side in the X-axis direction. By providing the contact hole 56, the holes from the outside of the first gate structure portion 46-1 toward the first gate structure portion 46-1 can be extracted before reaching the first gate structure portion 46-1. As a result, the concentration of carriers in the first gate structure portion 46-1 with a low threshold can be suppressed.

[0143] Fig.14 1 is a diagram showing an example of the configuration of the cathode region 82 on the upper surface of the active portion 120. The cathode region 82 of this example has a long side 85 when viewed from above. The long side 85 is the longest straight side of the end side of the cathode region 82. The gate groove portion 40 of this example intersects with the long side 85 of the cathode region 82 when viewed from above. The gate groove portion 40 may be orthogonal to the long side 85. Fig.14 In FIG. 1 , the gate trench portion 40 is schematically shown by a thick line. In addition, the dummy trench portion 30 is omitted.

[0144] In this example, a gate mesa portion is also provided in a region adjacent to the gate trench portion 40. An emitter region 12 and a contact region 15 are provided on the upper surface of the gate mesa portion so as to contact the gate trench portion 40. That is, the gate structure portion 46 is disposed along the gate trench portion 40.

[0145] In this example, the first threshold of the first gate structure 46-1 closest to the end edge of the cathode region 82 is smaller than the second threshold of the second gate structure 46-2 farthest from the end edge of the cathode region 82. The cathode region 82 may extend along the X-axis direction and have a plurality of intersections 83 intersecting the gate trench portion 40 along the Y-axis direction. The gate trench portion 40 may intersect with the plurality of intersections 83.

[0146] The cathode region 82 may include a connection portion 84 connecting two adjacent intersections 83. The connection portion 84 may connect the ends of the intersections 83 in the X-axis direction. The connection portion 84 is provided to extend in the Y-axis direction. The cathode region 82 may be provided to be curved in a plan view.

[0147] The active portion 120 of this example may also have a contact hole 56. The contact hole 56 is disposed between the gate trench portion 40 and the end of the active portion 120, or between the cathode region 82 and the end of the active portion 120. The contact hole 56 may be disposed so as to surround the entire region where the gate trench portion 40 is disposed. The contact holes 56 may be disposed dispersedly along the periphery of the region where the gate trench portion 40 is disposed.

[0148] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be added to the above embodiments. According to the description in the claims, the method of adding such changes or improvements can also be included in the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having a drift region of a first conductivity type; a transistor portion having a plurality of gate structures on an upper surface of the semiconductor substrate; and a diode portion having a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on a lower surface of the semiconductor substrate, Each gate structure has: a gate trench portion, which is arranged in a manner of reaching the drift region from the upper surface of the semiconductor substrate; an emitter region of a first conductivity type, which is disposed between the upper surface of the semiconductor substrate and the drift region, in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; as well as a base region of a second conductivity type, which is disposed between the emitter region and the drift region and in contact with the gate trench portion, In a plan view, a first threshold value of the gate structure portion closest to the cathode region is lower by 0.1 V or more and 1 V or less than a second threshold value of the gate structure portion farthest from the cathode region. The gate trench portion is provided in a manner having a long side in a direction parallel to an end side of the cathode region, The transistor portion includes the gate structure portion and includes a plurality of gate mesas provided along the long sides of the gate trench portion. The gate structure having the first threshold value is provided on a gate mesa portion closest to the cathode region among the plurality of gate mesa portions, The channel density of the gate mesa portion having the first threshold is higher than the channel density of the gate mesa portion having the second threshold, The gate mesa portion has the emitter region and a second conductivity type contact region having a doping concentration higher than that of the base region on the upper surface of the semiconductor substrate. An area ratio of the contact region at the upper surface of the gate mesa portion having the first threshold to the emitter region is smaller than an area ratio of the contact region at the upper surface of the gate mesa portion having the second threshold to the emitter region.

2. A semiconductor device, characterized in that: have: a semiconductor substrate having a drift region of a first conductivity type; a transistor portion having a plurality of gate structures on an upper surface of the semiconductor substrate; and a diode portion having a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on a lower surface of the semiconductor substrate, Each gate structure has: a gate trench portion, which is arranged in a manner of reaching the drift region from the upper surface of the semiconductor substrate; an emitter region of a first conductivity type, which is disposed between the upper surface of the semiconductor substrate and the drift region, in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; as well as a base region of a second conductivity type, which is disposed between the emitter region and the drift region and in contact with the gate trench portion, In a plan view, a first threshold value of the gate structure portion closest to the cathode region is lower by 0.1 V or more and 1 V or less than a second threshold value of the gate structure portion farthest from the cathode region. The transistor portion includes the gate trench portion and a dummy trench portion, The density of the gate trench portions in the region close to the transistor portion in contact with the cathode region in a plan view is higher than the density of the gate trench portions in the central region of the region farthest from the cathode region. The gate structure having the first threshold is provided in the proximity region.

3. A semiconductor device, characterized in that: have: a semiconductor substrate having a drift region of a first conductivity type; a transistor portion having a plurality of gate structures on an upper surface of the semiconductor substrate; and a diode portion having a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on a lower surface of the semiconductor substrate, Each gate structure has: a gate trench portion, which is arranged in a manner of reaching the drift region from the upper surface of the semiconductor substrate; an emitter region of a first conductivity type, which is disposed between the upper surface of the semiconductor substrate and the drift region, in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; as well as a base region of a second conductivity type, which is disposed between the emitter region and the drift region and in contact with the gate trench portion, In a plan view, a first threshold value of the gate structure portion closest to the cathode region is lower by 0.1 V or more and 1 V or less than a second threshold value of the gate structure portion farthest from the cathode region. The cathode region has a long side in a plan view, The gate structure having the first threshold is provided at a position facing the center of the long side of the cathode region, and is not provided at a position facing both ends of the long side.

4. A semiconductor device, characterized in that: have: a semiconductor substrate having a drift region of a first conductivity type; a transistor portion having a plurality of gate structures on an upper surface of the semiconductor substrate; and a diode portion having a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on a lower surface of the semiconductor substrate, Each gate structure has: a gate trench portion, which is arranged in a manner of reaching the drift region from the upper surface of the semiconductor substrate; an emitter region of a first conductivity type, which is disposed between the upper surface of the semiconductor substrate and the drift region, in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; as well as a base region of a second conductivity type, which is disposed between the emitter region and the drift region and in contact with the gate trench portion, In a plan view, a first threshold value of the gate structure portion closest to the cathode region is lower by 0.1 V or more and 1 V or less than a second threshold value of the gate structure portion farthest from the cathode region. The cathode region has a long side in a plan view, The gate trench portion intersects with a long side of the cathode region in a plan view.

5. A semiconductor device, characterized in that: have: a semiconductor substrate having a drift region of a first conductivity type; a transistor portion having a plurality of gate structures on an upper surface of the semiconductor substrate; and a diode portion having a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on a lower surface of the semiconductor substrate, Each gate structure has: a gate trench portion, which is arranged in a manner of reaching the drift region from the upper surface of the semiconductor substrate; an emitter region of a first conductivity type, which is disposed between the upper surface of the semiconductor substrate and the drift region, in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; as well as a base region of a second conductivity type, which is disposed between the emitter region and the drift region and in contact with the gate trench portion, In a plan view, a first threshold value of the gate structure portion closest to the cathode region is lower by 0.1 V or more and 1 V or less than a second threshold value of the gate structure portion farthest from the cathode region. The semiconductor device further comprises: an interlayer insulating film disposed above the upper surface of the semiconductor substrate and having a contact hole; and an emitter electrode disposed above the interlayer insulating film and in contact with the semiconductor substrate through the contact hole, On the upper surface of the semiconductor substrate, the gate trench portion extends along a predetermined extension direction. In the extending direction, the contact hole having a long side in a direction different from the extending direction is arranged between the gate structure portion having the first threshold value and an end side of the semiconductor substrate.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The gate structure having the first threshold is provided parallel to an end side of the cathode region in a plan view.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The gate trench portion has: A gate conductive portion; as well as a gate insulating film disposed between the gate conductive portion and the semiconductor substrate, The film thickness of the gate insulating film in the gate trench portion of the gate structure portion having the first threshold value is smaller than the film thickness of the gate insulating film in the gate trench portion of the gate structure portion having the second threshold value.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that The doping concentration of the base region of the gate structure portion having the first threshold is lower than the doping concentration of the base region of the gate structure portion having the second threshold.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that The diode portion has an upper surface side lifetime control region on the upper surface side of the semiconductor substrate in which the lifetime of carriers is lower than the lifetime of carriers in other regions. The upper surface side lifetime control region is provided so as to extend to a region close to the transistor portion which is in contact with the cathode region in a plan view. The gate structure having the first threshold is provided in the proximity region.

10. The semiconductor device according to any one of claims 1 to 5, characterized in that The first threshold is lower than the second threshold by 0.1 V or more and 0.5 V or less.

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