A capacitor and a method for forming the same

Abstract

The present invention provides a method for forming a capacitor, comprising the following steps: providing a first metal layer, and forming a first electrode plate layer pattern with intervals on the first metal layer; depositing a dielectric layer and a second electrode plate layer pattern in sequence in a direction away from the first electrode plate layer pattern on the side walls of the first electrode plate layer pattern and on the side of the first electrode plate layer pattern away from the first metal layer; forming an isolation layer with through holes in the intervals of the second electrode plate layer pattern on the first metal layer; depositing a second metal layer in the through holes, and the second metal layer is in contact with the second electrode plate layer pattern and the first metal layer respectively. The capacitor formed by using the method for forming a capacitor provided by the present invention has a relatively high repetition rate and success rate, and the capacitor manufactured by using this method presents a three-dimensional structure, which can effectively improve the density of the capacitor, and then improve the capacitance value of the capacitor. The present invention also provides a capacitor, which solves the problem that the capacitor in the prior art has a flat structure and thus has a small capacitance value.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a capacitor and a method for forming the same. Background Art

[0002] A capacitor, usually simply referred to as having the ability to store charge as capacitance. A capacitor is one of the electronic components widely used in electronic devices, and is widely applied to functions such as blocking DC and passing AC, coupling, bypassing, filtering, tuning circuits, energy conversion, control, etc. The simplest capacitor is composed of two electrodes at both ends and an insulating dielectric (including air) in the middle.

[0003] The capacitance value refers to the charge storage capacity of a capacitor under a given potential difference, denoted as C, and the international unit is farad (F). Generally speaking, charges will be forced to move in an electric field. When there is a dielectric between conductors, the movement of charges is hindered, causing charges to accumulate on the conductors, resulting in the accumulation and storage of charges, and the stored charge quantity is called capacitance.

[0004] Currently, for the commonly used planar capacitor structure, the effective area of the capacitor is defined by the relative area of two electrodes on a one-dimensional plane, and the area of the one-dimensional plane is limited, which greatly limits the capacitance value of the capacitor. Increasing the capacitance density is an effective method to increase the capacitance value of the capacitor.

[0005] For example, the patent document with the application number 201480063001.9 discloses a method for manufacturing a capacitor structure, including manufacturing a polysilicon structure (PO) on a semiconductor substrate. The method further includes manufacturing M1 to diffusion (MD) interconnections on the semiconductor substrate. The polysilicon structure is arranged in an interleaved layout with MD interconnections. The method also includes selectively connecting the interleaved layout of MD interconnections and / or the polysilicon structure as a capacitor structure.

[0006] The method for manufacturing a capacitor structure disclosed in the above patent document can manufacture a capacitor with a relatively high capacitance density through multiple interconnected polysilicon structures. However, using the method for manufacturing a capacitor structure disclosed in the above patent document, the repeatability and success rate of the manufactured capacitor are relatively low, and thus the manufacturing cost is relatively high. Summary of the Invention

[0007] The object of the present invention is to provide a capacitor and a method for forming the same, to solve the problems that the repeatability and success rate of the capacitor produced by the manufacturing method of the capacitor in the prior art are both relatively low, the manufacturing cost is relatively high, and most of the capacitors in the prior art are of a planar structure and the capacitance value of the capacitor is relatively small.

[0008] The method for forming the capacitor provided by the present invention includes the following steps:

[0009] Provide a first metal layer, and form a first electrode plate layer pattern with intervals on the first metal layer;

[0010] On the side walls of the first electrode plate layer pattern and on the side of the first electrode plate layer pattern away from the first metal layer, deposit a dielectric layer and a second electrode plate layer pattern in sequence along the direction away from the first electrode plate layer pattern;

[0011] Form an isolation layer with through holes in the intervals of the second electrode plate layer pattern on the first metal layer;

[0012] Deposit a second metal layer in the through holes, and the second metal layer is in contact with the second electrode plate layer pattern and the first metal layer respectively.

[0013] Adopt the above technical solution, form a first electrode plate layer pattern and a second electrode plate layer pattern on the first metal layer. On the side of the second electrode plate layer away from the first metal layer, deposit a second metal layer. The first electrode plate layer pattern and the second electrode plate layer pattern are connected through the first metal layer and the second metal layer, so that the capacitor presents a three-dimensional structure, which can effectively improve the density of the capacitor, and then improve the capacitance value of the capacitor.

[0014] Further, provide a first metal layer, and form a first electrode plate layer pattern with intervals on the first metal layer, including:

[0015] Provide a substrate, coat a metal material on the substrate to form the first metal layer;

[0016] Deposit a first electrode plate layer on the first metal layer;

[0017] Form a first photoresist pattern on the first electrode plate layer, and etch the first electrode plate layer to form the first electrode plate layer pattern.

[0018] Adopt the above technical solution, the first metal layer can be obtained by coating a metal material on the substrate. The substrate can be a common polysilicon material, and a metal material is coated on the substrate to achieve metal conduction. In addition, form a first electrode plate layer pattern on the first metal layer, and the first electrode plate layer pattern is the lower electrode plate of the capacitor.

[0019] Further, on the side walls of the first electrode plate layer pattern and on the side of the first electrode plate layer pattern away from the first metal layer, deposit a dielectric layer and a second electrode plate layer pattern in sequence along the direction away from the first electrode plate layer pattern, including:

[0020] Deposit a dielectric layer on the side walls of the first electrode plate layer pattern, on the side of the first electrode plate layer pattern away from the first metal layer, and on the first metal layer corresponding to the intervals of the first electrode plate layer pattern;

[0021] Deposit a second electrode plate layer on the side of the dielectric layer away from the first metal layer;

[0022] A second photoresist pattern is formed on the second electrode layer on the side of the first electrode layer pattern away from the first metal layer;

[0023] The dielectric layer and the second electrode layer on the first metal layer between the second photoresist patterns are etched away to form a second electrode layer pattern.

[0024] With the above technical solution, a second electrode layer pattern is formed on the first metal layer, and the second electrode layer pattern is the upper electrode of the capacitor.

[0025] Further, an isolation layer with vias is formed in the spaces between the second electrode layer patterns on the first metal layer, including:

[0026] An isolation material is deposited on the sidewalls of the second electrode layer pattern, on the side of the second electrode layer pattern away from the first metal layer, and on the first metal layer between the spaced second electrode layer patterns;

[0027] A third photoresist pattern is formed on the side of the isolation material away from the first metal layer;

[0028] The isolation material is etched to form an isolation layer with vias.

[0029] With the above technical solution, an isolation layer with vias is formed in the spaces between the second electrode layer patterns on the first metal layer. The isolation layer is used to isolate the second electrode layer pattern and the first electrode layer pattern of the capacitor. Since the isolation layer is an insulating substance, the entire capacitor is non-conductive in a DC circuit.

[0030] Further, forming an isolation layer with vias in the spaces between the second electrode layer patterns on the first metal layer further includes: forming vias between the spaces of at least one second electrode layer pattern, and forming vias on the side of the second electrode layer pattern away from the first metal layer.

[0031] Further, the side of the isolation layer away from the first metal layer is higher than the second electrode layer pattern. The isolation layer contacts the second electrode layer pattern and the second metal layer. On the side away from the first metal layer, the second metal layer is flush with the isolation layer; and in the extending direction of the first metal layer, the width of the second metal layer is less than or equal to the width of the second electrode layer pattern.

[0032] Further, after depositing a second metal layer on the side of the second electrode layer away from the first metal layer, it further includes: polishing the second metal layer.

[0033] With the above technical solution, polishing and planarizing the second metal layer is beneficial for subsequent manufacturing, and thus improves the performance of the capacitor.

[0034] Further, the materials of the first electrode layer pattern and the second electrode layer pattern are metal nitrides;

[0035] The material of the dielectric layer is at least one of ternary oxide and binary oxide;

[0036] The material of the isolation layer is silicon oxide or silicon nitride.

[0037] Furthermore, the present invention also provides a capacitor, which is made based on the foregoing method for forming a capacitor. The capacitor includes a first metal layer, and spaced-apart first electrode layer patterns are provided on the first metal layer;

[0038] On the sidewalls of the first electrode layer patterns and on the side of the first electrode layer patterns away from the first metal layer, a dielectric layer and a second electrode layer pattern are sequentially deposited in a direction away from the first electrode layer patterns;

[0039] An isolation layer having through holes is provided in the spaces between the second electrode layer patterns on the first metal layer;

[0040] A second metal layer is deposited in the through holes, and the second metal layer is in contact with the second electrode layer patterns and the first metal layer respectively.

[0041] Furthermore, the through holes include through holes formed between the spaces of at least one second electrode layer pattern and through holes formed on the side of the second electrode layer pattern away from the first metal layer.

[0042] The beneficial effects of the present invention are as follows:

[0043] The method for forming a capacitor provided by the present invention includes the following steps: providing a first metal layer, forming spaced-apart first electrode layer patterns on the first metal layer; on the sidewalls of the first electrode layer patterns and on the side of the first electrode layer patterns away from the first metal layer, sequentially depositing a dielectric layer and a second electrode layer pattern in a direction away from the first electrode layer patterns; forming an isolation layer having through holes in the spaces between the spaced-apart second electrode layer patterns on the first metal layer; depositing a second metal layer in the through holes, and the second metal layer is in contact with the second electrode layer patterns and the first metal layer respectively. The method for forming a capacitor provided by the present invention has a relatively high repetition rate and success rate for the manufactured capacitor, effectively saves the manufacturing cost, and for the capacitor manufactured by this method, the first electrode layer pattern and the second electrode layer pattern are connected through the first metal layer and the second metal layer, so that the capacitor presents a three-dimensional structure, which can effectively increase the density of the capacitor, and then increase the capacitance value of the capacitor.

[0044] In addition, the present invention also provides a capacitor. Compared with the prior art, the capacitor provided by the present invention presents a three-dimensional structure, solving the problem in the prior art that the capacitor has a flat structure and thus has a small capacitance value. Description of the Drawings

[0045] Figure 1 It is a flowchart of the method for forming a capacitor provided by an embodiment of the present invention;

[0046] Figure 2a - 2k This is a schematic diagram of the manufacturing process flow of the capacitor provided by the embodiment of the present invention.

[0047] Reference numerals:

[0048] 11: The first metal layer; 12: The second metal layer; 21: The first electrode plate layer; 22: The second electrode plate layer; 211: The pattern of the first electrode plate layer; 221: The pattern of the second electrode plate layer; 31: The first photoresist pattern; 32: The second photoresist pattern; 33: The third photoresist pattern; 4: The dielectric layer; 51: The isolation material; 52: The isolation layer; 521: The through hole; 6: The capacitor. Detailed implementation manners

[0049] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0051] In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0052] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or a connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0053] To solve the problems that the repetition rate and success rate of the capacitors produced by the existing manufacturing methods of capacitors are relatively low, the manufacturing cost is relatively high, and most of the existing capacitors are of a flat plate structure and the capacitance value of the capacitors is relatively small.

[0054] Such as Figure 1As shown, this embodiment provides a method for forming a capacitor, including the following steps:

[0055] S11: Provide a first metal layer, and form a first electrode plate layer pattern with intervals on the first metal layer.

[0056] As Figure 2c shown, specifically, in this embodiment, a first metal layer 11 is provided, and a first electrode plate layer pattern 211 with intervals is formed on the first metal layer 11. The material of the first electrode plate layer pattern 211 can be a metal nitride, such as titanium nitride or tantalum nitride, etc., or other conductive materials. This embodiment does not make specific limitations on this. Further, when forming a first electrode plate layer pattern 211 with intervals on the first metal layer 11, the interval widths between the first electrode plate layer patterns 211 can be equal or unequal. The interval widths between the first electrode plate layer patterns 211 are selected according to actual needs. This embodiment does not make specific limitations on this. The first electrode plate layer pattern 211 is the lower electrode of the capacitor, which is used to connect with other metal structures subsequently to realize the conduction of the capacitor.

[0057] Further, providing a first metal layer and forming a first electrode plate layer pattern with intervals on the first metal layer includes: providing a substrate, plating a metal material on the substrate to form a first metal layer; depositing a first electrode plate layer on the first metal layer; forming a first photoresist pattern on the first electrode plate layer, and etching the first electrode plate layer to form a first electrode plate layer pattern.

[0058] As Figure 2a shown, a substrate is provided, and a metal material is plated on the substrate to form a first metal layer 11. The material of the substrate can be polysilicon, silicon nitride, silicon oxide and other materials. This embodiment does not make specific limitations on this. In addition, when plating a metal material on the substrate to form a first metal layer 11, the material of the first metal layer 11 can be copper, aluminum, ruthenium or cobalt, etc., or not limited to the metal materials provided in this embodiment, and is specifically selected according to actual needs. To make the conductivity of the first metal layer 11 better in subsequent use, after plating a metal material on the substrate, the plated metal material on the substrate can be polished to form a first metal layer 11 with better conductivity. Further, as Figure 2a shown, a first electrode plate layer 21 is deposited on the first metal layer 11. The deposited first electrode plate layer 21 is used to form the electrode plate of the capacitor subsequently. The material of the first electrode plate layer 21 can be a metal nitride, such as titanium nitride or tantalum nitride. The first electrode plate layer 21 is used as the etching material for forming the electrode plate of the capacitor subsequently. To ensure the conductivity of the capacitor in an AC circuit, the material of the first electrode plate layer 21 is a nitride-based metal. On the one hand, it is easier to deposit on the first metal layer 11, and on the other hand, it can ensure the conductivity of the capacitor in an AC circuit. The specific material of the first electrode plate layer 21 is selected according to actual needs. This embodiment does not make specific limitations on this.

[0059] As Figure 2b shown, a first photoresist pattern 31 is formed on the first electrode plate layer 21. The first photoresist pattern 31 is used to form the required first electrode plate layer pattern 211 next. Therefore, the shape of the first photoresist pattern 31 is the same as that of the first electrode plate layer pattern 211 formed next. That is, the spacing widths between the first photoresist patterns 31 may be equal or unequal, as long as the spacing widths between the first photoresist patterns 31 are the same as the shape of the first electrode plate layer pattern 211 formed next.

[0060] As Figure 2c shown, the first electrode plate layer 21 is etched to form the first electrode plate layer pattern 211. By forming the first photoresist pattern 31 on the first electrode plate layer 21 and then etching according to the pattern of the first photoresist pattern 31, the corresponding first electrode plate layer pattern 211 is formed. The first electrode plate layer pattern 211 is the lower electrode plate of the capacitor.

[0061] S12: On the sidewalls of the first electrode plate layer pattern and on the side of the first electrode plate layer pattern away from the first metal layer, a dielectric layer and a second electrode plate layer pattern are sequentially deposited in a direction away from the first electrode plate layer pattern.

[0062] As Figure 2g shown, on the sidewalls of the first electrode plate layer pattern 211 and on the side of the first electrode plate layer pattern 211 away from the first metal layer 11, a dielectric layer 4 and a second electrode plate layer pattern 221 are sequentially deposited in a direction away from the first electrode plate layer pattern 211. The thicknesses of the second electrode plate layer pattern 221 and the dielectric layer 4 sequentially deposited in a direction away from the first electrode plate layer pattern 211 can be selected according to actual needs, and this embodiment does not make specific limitations on this. In addition, the material of the dielectric layer 4 can be at least one of binary oxides and ternary oxides or a mixture thereof, such as zirconium oxide, hafnium oxide, hafnium oxynitride, zirconium oxynitride, or any mixture thereof, and it can also be not limited to the materials given in this embodiment, and can be specifically selected according to actual needs, and this embodiment does not make specific limitations on this. The method provided in this embodiment can relatively easily obtain the upper and lower electrode plates of the capacitor through the preset first photoresist pattern 31 and second photoresist pattern 32, and can repeatedly manufacture the upper and lower electrode plates of the capacitor with consistent standards, that is, the first electrode plate layer pattern 211 and the second electrode plate layer pattern 221 in this embodiment, effectively saving the manufacturing cost.

[0063] Further, on the sidewalls of the first electrode layer pattern and on the side of the first electrode layer pattern away from the first metal layer, a dielectric layer and a second electrode layer pattern are sequentially deposited in a direction away from the first electrode layer pattern, including depositing a dielectric layer on the sidewalls of the first electrode layer pattern, on the side of the first electrode layer pattern away from the first metal layer, and on the first metal layer corresponding to the interval of the first electrode layer pattern; depositing a second electrode layer on the side of the dielectric layer away from the first metal layer; forming a second photoresist pattern on the second electrode layer on the side of the first electrode layer pattern away from the first metal layer; and etching away the dielectric layer and the second electrode layer on the first metal layer between the second photoresist patterns to form the second electrode layer pattern.

[0064] As Figure 2d shown, a dielectric layer 4 is deposited on the sidewalls of the first electrode layer pattern 211, on the side of the first electrode layer pattern 211 away from the first metal layer 11, and on the first metal layer 11 corresponding to the interval of the first electrode layer pattern 211. The dielectric layer 4 is used to separate the first electrode layer pattern 211 and the second electrode layer pattern 221 and plays a role of separation and insulation. Therefore, the material of the dielectric layer 4 can be a binary oxide or a ternary oxide or a mixture thereof. For example, it can be zirconium oxide, hafnium oxide, hafnium oxynitride, zirconium oxynitride, or any mixture thereof, etc. It can also not be limited to the materials given in this embodiment and can be specifically selected according to actual needs. This embodiment does not make specific limitations in this regard.

[0065] As Figure 2e shown, a second electrode layer 22 is deposited on the side of the dielectric layer 4 away from the first metal layer 11. The thickness of the second electrode layer 22 is selected according to actual needs, and this embodiment does not make specific limitations in this regard. In addition, the material of the second electrode layer 22 can be a metal nitride, such as titanium nitride or tantalum nitride. The second electrode layer 22 is used as the material of the electrode for forming a capacitor later. To ensure the conductive performance of the capacitor in an AC circuit, the material of the second electrode layer 22 is a metal nitride because the material of the dielectric layer 4 is a binary oxide or a ternary oxide or a mixture thereof, such as zirconium oxide, hafnium oxide, hafnium oxynitride, zirconium oxynitride, or any mixture thereof, etc. Therefore, on the one hand, the metal nitride is relatively easy to deposit on the dielectric layer 4, and on the other hand, the nitride-based metal can ensure the conductive performance of the capacitor in an AC circuit. The specific material of the second electrode layer 22 is selected according to actual needs, and this embodiment does not make specific limitations in this regard.

[0066] As Figure 2fAs shown, a second photoresist pattern 32 is formed on the second electrode layer 22 on the side of the first electrode layer pattern 211 away from the first metal layer 11. In specific operations, the subsequent etching work is carried out along the outer sidewall of the second photoresist pattern 32. The interval widths between the second photoresist patterns 32 can be equal or unequal, and the interval width between the second photoresist patterns 32 is equal to the width between the first photoresist patterns 31 minus the width of the second photoresist pattern 32.

[0067] As Figure 2g shown, the dielectric layer and the second electrode layer 22 on the first metal layer 11 between the second photoresist patterns 221 are etched away to form a second electrode layer pattern 221. That is, along the outer sidewall of the second photoresist pattern 221, the dielectric layer 4 and the second electrode layer 22 on the first metal layer 11 between the second photoresist patterns 221 are etched away to form a second electrode layer pattern 221. The second electrode layer pattern 221 is the upper electrode of the capacitor.

[0068] S13: An isolation layer with through-holes is formed in the intervals between the second electrode layer patterns spaced on the first metal layer.

[0069] As Figure 2h shown, an isolation material 51 is deposited on the sidewalls of the second electrode layer pattern 221, on the side of the second electrode layer pattern 221 away from the first metal layer 11, and on the first metal layer 11 between the spaced second electrode layer patterns 221. The isolation material 51 can be silicon oxide or silicon nitride, etc., and is used to block the second electrode layer pattern 221 and the first electrode layer pattern 211 of the capacitor. The specific material of the isolation material 51 is not limited to the materials given in this embodiment and can be specifically selected according to actual needs. This embodiment does not make specific limitations in this regard.

[0070] As Figure 2j shown, an isolation layer 52 with through-holes 521 is formed in the intervals between the second electrode layer patterns 221 spaced on the first metal layer 11. The through-holes 521 are used for subsequent filling of metal materials. The isolation layer 52 is an insulating substance, and the isolation layer 52 is used to block the second electrode layer pattern 221 and the first electrode layer pattern 211 of the capacitor, so the entire capacitor is non-conductive in a DC circuit. The material of the isolation layer 52 can be silicon oxide or silicon nitride, etc., and is used to block the second electrode layer pattern 221 and the first electrode layer pattern 211 of the capacitor. The specific material of the isolation layer 52 is not limited to the materials given in this embodiment and can be specifically selected according to actual needs. This embodiment does not make specific limitations in this regard.

[0071] Further, forming an isolation layer with through-holes in the intervals between the second electrode layer patterns on the first metal layer further includes: forming through-holes between the intervals of at least one second electrode layer pattern and forming through-holes on the side of the second electrode layer pattern away from the first metal layer.

[0072] As shown Figure 2i in FIG. 1, the etch stop material 51 is etched to form an isolation layer 52 with through holes. The isolation layer 52 is an insulating material, which can specifically be silicon oxide, silicon nitride, etc., and is used to block the second electrode layer pattern 221 and the first electrode layer pattern 211 of the capacitor. The specific material of the isolation layer 52 is not limited to the materials given in this embodiment, and can be specifically selected according to actual needs. This embodiment does not make specific limitations on this.

[0073] As shown Figure 2j in FIG. 2, forming an isolation layer 52 with through holes 521 in the intervals of the second electrode layer pattern 221 on the first metal layer 11 further includes: forming through holes 521 between the intervals of at least one second electrode layer pattern 221, and forming through holes 521 on the side of the second electrode layer pattern 221 away from the first metal layer 11.

[0074] S14: Deposit a second metal layer in the through holes, and the second metal layer is in contact with the second electrode layer pattern and the first metal layer respectively.

[0075] As shown Figure 2k in FIG. 3, deposit a second metal layer 12 in the through holes 521, and the second metal layer 12 is in contact with the second electrode layer pattern 221 and the first metal layer 11 respectively. The second metal layer 12 is in contact with the second electrode layer pattern 221, and the first metal layer 11 is in contact with the first electrode layer pattern 211. In an AC circuit, the first electrode layer pattern 211 and the second electrode layer pattern 221 of the capacitor are connected and conducted through the first metal layer 11 and the second metal layer 12. The capacitor forming method provided in this embodiment has a high repetition rate and success rate for the manufactured capacitor, effectively saves the manufacturing cost, and for the capacitor manufactured by this method, its first electrode layer pattern 211 and second electrode layer pattern 221 are connected through the first metal layer 11 and the second metal layer 12, and the capacitor presents a three-dimensional structure, which can effectively increase the density of the capacitor, and then increase the capacitance value of the capacitor. The material of the second metal layer 12 can be copper, aluminum, ruthenium, cobalt, etc., and the material of the second metal layer 12 can be the same as or different from the material of the first metal layer 11, and is specifically selected according to actual needs. This embodiment does not make specific limitations on this.

[0076] As shown Figure 2k in FIG. 4, further, after depositing the second metal layer 12 on the side of the second electrode layer pattern 221 away from the first metal layer 11, it further includes: polishing the second metal layer 12. Polishing and planarizing the second metal layer 12 is beneficial for subsequent manufacturing, and thus improves the performance of the capacitor.

[0077] As shown Figure 2kAs shown, further, the side of the isolation layer 52 away from the first metal layer 11 is higher than the second electrode plate layer pattern 221. The isolation layer 52 is in contact with the second electrode plate layer pattern 221 and the second metal layer 12. On the side away from the first metal layer 11, the second metal layer 12 is flush with the isolation layer 52; and in the extending direction of the first metal layer 11, the width of the second metal layer 12 is less than or equal to the width of the second electrode plate layer pattern 221. On the side away from the first metal layer 11, the second metal layer 12 is flush with the isolation layer 52; and in the extending direction of the first metal layer 11, the width of the second metal layer 12 is less than or equal to the width of the second electrode plate layer pattern 221, and the use performance of the capacitor is better.

[0078] The method for forming a capacitor provided in this embodiment includes the following steps: providing a first metal layer, and forming a first electrode plate layer pattern with intervals on the first metal layer; depositing a dielectric layer and a second electrode plate layer pattern in sequence along the direction away from the first electrode plate layer pattern on the side walls of the first electrode plate layer pattern and on the side of the first electrode plate layer pattern away from the first metal layer; forming an isolation layer with through holes in the intervals between the second electrode plate layer patterns spaced on the first metal layer; and depositing a second metal layer on the side of the second electrode plate layer pattern away from the first metal layer. The method for forming a capacitor provided by the present invention has a high repetition rate and success rate for the manufactured capacitor, effectively saves the manufacturing cost, and for the capacitor manufactured by this method, its first electrode plate layer pattern and second electrode plate layer pattern are connected through the first metal layer and the second metal layer, so that the capacitor presents a three-dimensional structure, which can effectively increase the density of the capacitor, and then increase the capacitance value of the capacitor.

[0079] Further, this embodiment also provides a capacitor, and the capacitor is made based on the foregoing method for forming a capacitor.

[0080] As Figure 2k shown, the capacitor 6 is made based on the foregoing method for forming the capacitor 6, and details are not described herein again.

[0081] As Figure 2kAs shown, the capacitor 6 includes a first metal layer 11, and a first electrode plate layer pattern 211 spaced apart on the first metal layer 11; a dielectric layer 4 and a second electrode plate layer pattern 221 are sequentially deposited on the side wall of the first electrode plate layer pattern 211 and on the side of the first electrode plate layer pattern 211 away from the first metal layer 11 in a direction away from the first electrode plate layer pattern 211; an isolation layer 52 having a through hole 521 is provided in the space between the second electrode plate layer patterns 221 spaced apart on the first metal layer 11; a second metal layer 12 is in the through hole 521, and the second metal layer 12 is in contact with the second electrode plate layer pattern 221 and the first metal layer 11 respectively. In this embodiment, the first electrode plate layer pattern 211 and the second electrode plate layer pattern 221 are formed on the first metal layer 11, and the first electrode plate layer pattern 211 and the second electrode plate layer pattern 221, a second metal layer 12 is deposited on the side of the second electrode plate layer 221 away from the first metal layer 11, and the first electrode plate layer pattern 211 and the second electrode plate layer pattern 221 are connected through the first metal layer 11 and the second metal layer 12. The capacitor 6 presents a three-dimensional structure, which can effectively improve the density of the capacitor 6, and then improve the capacitance value of the capacitor 6.

[0082] Further, as Figure 2k shown, the through hole 521 includes a through hole formed between the spaces of at least one second electrode plate layer pattern 221, and a through hole formed on the side of the second electrode plate layer pattern 221 away from the first metal layer 11. For the capacitor 6 provided in this embodiment, the first electrode plate layer pattern 211 and the second electrode plate layer pattern 221 are connected through the first metal layer 11 and the second metal layer 12. The capacitor 6 presents a three-dimensional structure, which can effectively improve the density of the capacitor 6, and then improve the capacitance value of the capacitor 6.

[0083] Compared with the prior art, the capacitor provided in this embodiment presents a three-dimensional structure, solving the problem in the prior art that the capacitor has a flat structure and thus has a small capacitance value.

[0084] The above content is a further detailed description of the present invention in combination with specific embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for forming a capacitor, characterized in that, it includes the following steps: Provide a first metal layer, and form a first electrode layer pattern with intervals on the first metal layer; On the side walls of the first electrode layer pattern and on the side of the first electrode layer pattern away from the first metal layer, deposit a dielectric layer and a second electrode layer pattern in sequence in a direction away from the first electrode layer pattern; Form an isolation layer with through holes in the intervals of the second electrode layer pattern on the first metal layer; Deposit a second metal layer in the through holes, the second metal layer is in contact with the second electrode layer pattern and the first metal layer respectively, and the first electrode layer pattern and the second electrode layer pattern are connected through the first metal layer and the second metal layer.

2. The method for forming a capacitor according to claim 1, characterized in that, providing a first metal layer and forming a first electrode layer pattern with intervals on the first metal layer includes: Provide a substrate, coat a metal material on the substrate to form the first metal layer; Deposit a first electrode layer on the first metal layer; Form a first photoresist pattern on the first electrode layer, and etch the first electrode layer to form the first electrode layer pattern.

3. The method for forming a capacitor according to claim 1, characterized in that, depositing a dielectric layer and a second electrode layer pattern in sequence in a direction away from the first electrode layer pattern on the side walls of the first electrode layer pattern and on the side of the first electrode layer pattern away from the first metal layer includes: Deposit the dielectric layer on the side walls of the first electrode layer pattern, on the side of the first electrode layer pattern away from the first metal layer, and on the first metal layer corresponding to the intervals of the first electrode layer pattern; Deposit a second electrode layer on the side of the dielectric layer away from the first metal layer; Form a second photoresist pattern on the second electrode layer on the side of the first electrode layer pattern away from the first metal layer; Etch away the dielectric layer and the second electrode layer on the first metal layer between the second photoresist patterns to form the second electrode layer pattern.

4. The method for forming a capacitor according to claim 1, characterized in that, forming an isolation layer with through holes in the intervals of the second electrode layer pattern on the first metal layer includes: Deposit an isolation material on the side walls of the second electrode layer pattern, on the side of the second electrode layer pattern away from the first metal layer, and on the first metal layer between the second electrode layer patterns; Form a third photoresist pattern on the side of the isolation material away from the first metal layer; Etch the isolation material to form the isolation layer with through holes.

5. The method for forming a capacitor according to claim 4, characterized in that, forming an isolation layer with through holes in the intervals of the second electrode layer pattern on the first metal layer further includes: Form through holes between the intervals of at least one of the second electrode layer patterns, and form through holes on the side of the second electrode layer pattern away from the first metal layer.

6. The method for forming a capacitor according to claim 5, characterized in that, The side of the isolation layer away from the first metal layer is higher than the second electrode layer pattern. The isolation layer contacts the second electrode layer pattern and the second metal layer. On the side away from the first metal layer, the second metal layer is flush with the isolation layer; and in the extending direction of the first metal layer, the width of the second metal layer is less than or equal to the width of the second electrode layer pattern.

7. The method for forming a capacitor according to claim 1, wherein, after depositing a second metal layer on the side of the second electrode layer away from the first metal layer, it further includes: polishing the second metal layer.

8. The method for forming a capacitor according to claim 1, wherein, the materials of the first electrode layer pattern and the second electrode layer pattern are metal nitrides; the material of the dielectric layer is at least one of ternary oxides and binary oxides; the material of the isolation layer is silicon oxide or silicon nitride.

9. A capacitor, wherein, the capacitor is made based on the method for forming a capacitor according to any one of claims 1 - 8. The capacitor includes the first metal layer, and the spaced first electrode layer patterns are provided on the first metal layer; on the sidewalls of the first electrode layer pattern and on the side of the first electrode layer pattern away from the first metal layer, the dielectric layer and the second electrode layer pattern are sequentially deposited along the direction away from the first electrode layer pattern; the isolation layer having through - holes is provided in the spaces between the second electrode layer patterns on the first metal layer; the second metal layer is deposited in the through - holes, and the second metal layer contacts the second electrode layer pattern and the first metal layer respectively.

10. The capacitor according to claim 9, wherein, the through - holes include through - holes formed between the spaces of at least one of the second electrode layer patterns, and through - holes formed on the side of the second electrode layer pattern away from the first metal layer.

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