Adaptable and efficient standby power solution for next-generation low-power automotive systems

Abstract

The present disclosure relates to an adaptive high-efficiency standby power solution for next-generation low-power automotive systems. The present invention provides a method and system for supplying power using an LDO linear voltage regulator (110) having an LDO power supply (114, 115) and a load switch (116) by: during an active mode, connecting a power supply voltage (102, 104) to a main core (121) and a standby core (122) in a multi-core low-power microcontroller (120), such that the standby core receives a first supply voltage that tracks the power supply voltage during the active mode; and upon detecting a standby mode of the multi-core low-power microcontroller, disconnecting the power supply voltage from the standby core and connecting a low-dropout (LDO) linear power supply voltage to the standby core during the standby mode, such that the standby core receives the LDO linear power supply voltage as a second supply voltage during the standby mode.

Description

Technical Field

[0001] The present invention relates generally to power supplies. In one aspect, the present invention relates to a power supply suitable for use in a low-power multi-core automotive system. Background Art

[0002] As automotive vehicles become increasingly "smarter" with deeper connectivity to the internet, improved autonomous driving capabilities, and connected car safety systems, the technologies needed to keep these vehicles connected to the digital world are becoming increasingly important. However, the demand for more advanced embedded systems increasingly requires the integration of electronic components using higher-performance automotive microcontrollers manufactured using advanced manufacturing technologies (such as deep submicron CMOS processes). The development of automotive connected-car technology presents a variety of design and operational challenges. For example, automotive gateway embedded systems typically provide several necessary performance capabilities, such as standby or disconnect modes that allow for extended periods of low power operation while also being able to detect changes in the surrounding environment (such as peripheral devices and the car's ignition signal). Furthermore, such systems must be able to periodically wake up and become active and fully powered before returning to standby mode. As connected car technologies and remote access driver assistance features are added to vehicles, the need for frequent wake-ups increases.

[0003] Existing automotive systems with slower, lower-performance microcontrollers typically use a fixed power supply (e.g., a low-power linear regulator) to provide a single active power rail to maintain wake-up logic embedded within the microcontroller to meet operational requirements for providing a standby mode. However, higher-performance microcontrollers built with advanced manufacturing processes (e.g., deep submicron technologies) increasingly utilize multi-core architectures, where one CPU core supports standby mode and at least one other high-performance CPU core supports active or wake-up mode. With this type of multi-core architecture on next-generation low-power microcontrollers, the standby low-power core supply voltage must be maintained within a tight tolerance (typically 20mV-30mV) relative to the supply voltage of the high-performance active-mode main core after wakeup to avoid any glitches during transitions between standby and active modes (and vice versa), which could cause microcontroller resets and system failures. The need to keep the active and standby supply voltages close together becomes even more pressing in multi-core architectures, where individual active-mode cores can be set to different values across different segments through power optimization techniques, such as static voltage scaling or dynamic voltage scaling. Furthermore, the advancement of interconnect technology in the 24V truck market segment and the introduction of 48V mild hybrid vehicles will continue to push the maximum DC battery voltage to higher voltage levels (e.g., 70V), resulting in significant power dissipation requirements for conventional low-dropout (LDO) linear regulators used to maintain the microcontroller power rail during standby mode. As previously noted, existing solutions for powering low-power standby cores with a fixed supply are extremely challenging to implement in practice due to the difficulty in balancing the design and performance requirements of high-performance multi-core microcontrollers built using advanced manufacturing processes to keep the standby core supply voltage close to the active core supply voltage after wakeup. Summary of the Invention

[0004] According to one aspect of the present invention, there is provided a method for supplying electric power, comprising:

[0005] During an active mode of a multi-core low-power microcontroller, connecting a supply voltage to a main core and a standby core in the multi-core low-power microcontroller such that the standby core receives a first supply voltage that tracks the supply voltage during the active mode; and

[0006] After detecting a standby mode of the multi-core low-power microcontroller, the power supply voltage is disconnected from the standby core and a low dropout (LDO) linear power supply voltage is connected to the standby core during the standby mode of the multi-core low-power microcontroller, so that during the standby mode, the standby core receives the LDO linear power supply voltage as a second supply voltage.

[0007] According to one or more embodiments, the method additionally includes generating the supply voltage with a switch mode power supply including a pulse width modulator (PWM) controller and a buck converter.

[0008] According to one or more embodiments, the method further includes generating the low dropout (LDO) linear power supply voltage using an ultra-low quiescent current LDO voltage regulator.

[0009] According to one or more embodiments, connecting the power supply voltage includes closing a parallel load switch formed on an integrated circuit LDO linear voltage regulator with a switch enable signal to connect the power supply voltage to the standby core.

[0010] According to one or more embodiments, connecting the low dropout (LDO) linear supply voltage to the standby core includes enabling an integrated circuit LDO linear voltage regulator with an enable signal during the standby mode.

[0011] According to one or more embodiments, further comprising disabling an integrated circuit LDO linear voltage regulator with a disabling signal during the active mode.

[0012] According to one or more embodiments, further comprising detecting that the power supply voltage meets or exceeds a minimum voltage threshold before connecting the power supply voltage to the standby core.

[0013] According to one or more embodiments, further comprising:

[0014] Upon detecting an active mode of the multi-core low-power microcontroller, the supply voltage is reconnected to the main core and the standby core while disabling the LDO linear supply voltage, so that the standby core receives the first supply voltage that tracks the supply voltage during the active mode.

[0015] According to one or more embodiments, connecting the supply voltage includes providing a switch enable signal to a parallel load switch including an input inverter buffer control circuit connected to gate terminals of an NMOS switch and a PMOS switch connected in parallel between the supply voltage and the LDO linear supply voltage.

[0016] According to a second aspect of the present invention, there is provided a multi-core microcontroller processing system, comprising:

[0017] a first power supply for generating a first power supply voltage connected to a first core in the multi-core microcontroller; and

[0018] A low-dropout (LDO) linear power regulator, comprising:

[0019] an LDO linear power supply, the LDO linear power supply being configured to generate an LDO power supply voltage in response to a first enable signal, wherein the LDO power supply voltage is connected to a standby core in the multi-core microcontroller as a supply voltage;

[0020] a load switch that connects the first power supply voltage as the supply voltage to the standby core in response to a second enable signal; and

[0021] a digital control interface that generates the first and second enable signals such that, during an active mode, the first enable signal disables the LDO linear power regulator and the second enable signal closes the load switch to connect the first power supply voltage as the supply voltage to the standby core, and such that, during a standby mode, the first enable signal enables the LDO linear power regulator and the second enable signal opens the load switch to disconnect the first power supply voltage from the supply voltage to the standby core.

[0022] According to one or more embodiments, the first power supply comprises a switch mode power supply including a pulse width modulator (PWM) controller and a buck converter.

[0023] According to one or more embodiments, the LDO linear power supply includes an ultra-low quiescent current LDO voltage supply including an error amplifier driving an internal PMOS pass FET.

[0024] According to one or more embodiments, the LDO linear power supply, load switch, and digital control interface are formed in a single integrated circuit LDO linear power regulator.

[0025] According to one or more embodiments, the load switch includes an NMOS switch and a PMOS switch connected in parallel between the first power supply voltage and the LDO power supply voltage and controlled by the second enable signal.

[0026] According to one or more embodiments, the LDO linear power regulator includes a first voltage monitor circuit connected to detect that the first power supply voltage meets or exceeds a minimum voltage threshold before notifying the digital control interface that the second enable signal passed to the load switch can be generated for connecting the first power supply voltage as the supply voltage to the standby core.

[0027] According to one or more embodiments, the LDO linear power regulator includes a second voltage monitor circuit connected to detect that the first power supply voltage is at or below a maximum voltage threshold before notifying the digital control interface that the first enable signal can be generated to enable the LDO linear power supply.

[0028] According to a third aspect of the present invention, there is provided a device comprising:

[0029] a switched-mode power supply comprising a switching regulator configured to convert an input voltage of a power supply circuit to a supply voltage connected to a first core in a multi-core microcontroller; and

[0030] A low dropout (LDO) linear voltage regulator connected between the switch mode power supply and a standby core in the multi-core microcontroller, the multi-core microcontroller comprising:

[0031] an error amplifier and an internal pass FET configured to convert the input voltage of the power supply circuit to a standby low power core supply voltage when the power supply circuit is in a standby mode of operation and to be disabled when the power supply circuit is in an active mode of operation; and

[0032] an internal load switch that connects the supply voltage to a standby supply voltage node of the standby core during an active operating mode and disconnects the supply voltage from the standby supply voltage node of the standby core during a standby operating mode, such that a standby low power core supply voltage is maintained within approximately 20 mV-30 mV relative to the supply voltage after transitioning from the standby operating mode to the active operating mode.

[0033] According to one or more embodiments, the LDO linear voltage regulator includes a digital control that generates a first enable signal and a second enable signal such that, during an active operating mode, the first enable signal disables the LDO linear voltage regulator and the second enable signal closes the internal load switch to connect the power supply voltage as the supply voltage to the standby core, and such that, during a standby mode, the first enable signal enables the LDO linear voltage regulator and the second enable signal opens the internal load switch to disconnect the power supply voltage from the standby core.

[0034] According to one or more embodiments, the internal load switch includes an NMOS switch and a PMOS switch connected in parallel between the power supply voltage and the standby supply voltage node of the standby core and controlled by the second enable signal.

[0035] According to one or more embodiments, the LDO linear voltage regulator comprises a single integrated circuit LDO linear power regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention and the numerous objects, features and advantages attained thereby will be understood when the following detailed description is considered in conjunction with the following drawings, in which:

[0037] Figure 1 is a simplified schematic circuit diagram illustrating an adaptive standby power supply for a low power dual core microcontroller according to selected embodiments of the present disclosure;

[0038] Figure 2A is a simplified schematic circuit diagram illustrating a dual-mode low dropout (LDO) linear voltage regulator circuit according to selected embodiments of the present disclosure, the dual-mode low dropout linear voltage regulator circuit selectively providing an LDO output supply voltage to a standby core supply voltage node during a standby mode, and deactivating the LDO output supply voltage and connecting the standby core supply voltage node to a main core supply voltage during an active mode, thereby providing a tracking switching mode;

[0039] Figure 2B is a simplified schematic circuit description of selected PMOS and NMOS switch embodiments that may be used to implement a load switch according to selected embodiments of the present disclosure;

[0040] Figure 3 Show Figure 2A Mode transition timing diagram waveform of the dual-mode LDO linear voltage regulator circuit depicted in; and

[0041] Figure 4A simplified flow chart illustrating control logic for operating an adaptive standby power supply of a low power dual core microcontroller according to selected embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0042] Provided are an adaptive, high-efficiency standby power architecture, method, system, and apparatus for a high-performance multi-core microcontroller. The architecture selectively generates ultra-low quiescent current and supplies a low-dropout voltage to the standby core during standby mode, and tracks the main core supply voltage during active mode while maintaining the standby core supply voltage within a specified tolerance of the main core supply voltage, thereby seamlessly transitioning between standby and active modes. In selected embodiments, a dual-mode low-dropout (LDO) linear voltage regulator circuit selectively provides an LDO output supply voltage to the standby core under control of a digital control interface during standby mode. In standby mode, the digital control interface controls a parallel load switch to disconnect the high power supply from the standby core, connecting the LDO output supply voltage as the supply voltage for the standby core. During an active or awake mode of the active core, the digital control interface controls the parallel load switch to draw the standby core supply voltage from the main core supply voltage and disable the LDO output to provide a tracking switching mode for the standby core. Before sending confirmation of successful entry into standby mode to the microcontroller, the digital control interface detects when the supply voltage at the active core is sufficiently low, thereby ensuring that leakage in the active core is extremely low before confirming entry into standby mode. With the disclosed LDO linear voltage regulator circuit, system, and method, the digital control interface can be implemented with RTL control logic in a microcontroller integrated circuit to implement an efficient dual-mode power supply suitable for next-generation deep submicron multi-core automotive microcontrollers when operating in a seamless transition between shutoff (CAN standby) mode and active mode.

[0043] To provide additional details for improving understanding of selected embodiments of the present disclosure, reference is now made to Figure 1 , which is a simplified schematic circuit diagram showing an adaptive standby power supply 100 connected to a low power dual core microcontroller 120. As depicted, the adaptive standby power supply 100 includes a first switching power supply 101-104 and a second LDO power supply 114-115, which are connected to provide a supply voltage V SMPS 、V LDO The power supply voltage input pins VDD1 and VDD2 are provided to the main core 121 and the standby core 122 of the microcontroller 120 as described below. For this purpose, the LDO linear voltage regulator 110 is provided with a load switch 116 to connect the power supply voltage input pin VDD2 of the MCU 120 to receive the power supply voltage V generated by the first switching power supplies 101-104 during the tracking switching mode (for example, during the active mode).SMPS , and connected to the supply voltage input pin VDD2 of the MCU 120 to receive the supply voltage V generated by the second LDO power supply 110 during the LDO mode (eg, during the standby mode) LDO Therefore, the supply voltage V LDO The LDO pass FET 115 can be enabled or disabled, and the switch 116 can be disabled or enabled in a complementary manner. The supply voltage provided to the supply voltage input pin VDD2 is adjusted from the supply voltage VDD2 to the supply voltage VDD3. LDO switches to track the switch-mode power supply voltage (V SMPS ).

[0044] In operation, the first switching power supplies 101-104 may be connected and configured to periodically wake up from the standby mode (eg, in response to a start-up control signal) and generate a switching mode power supply voltage (V SMPS ) to provide the main core supply voltage input pin VDD1 during active mode. Although any suitable switching power supply arrangement may be used, the selected embodiment of the first switching power supply includes an LDO pre-regulator 101 and a switched mode power supply (SMPS) pulse width modulator (PWM) controller 102, which are connected to a battery voltage source 103 to drive a DC / DC step-down buck converter 104. The LDO pre-regulator 101 generates a bias voltage or supply voltage V for the SMPS PWM controller 102 and the second LDO power supplies 114-115, respectively. S1 、V S2 In this arrangement, the first switching power supplies 101-104 generate a supply voltage V at the input capacitor C1. SMPSFor connection to the supply voltage input pin VDD1 of the main core 121. During an active operating mode when voltage scaling is not present, the first switching power supplies 101-104 drive the main core supply voltage input pin VDD1 to a first voltage level (e.g., 0.8V), and during a standby operating mode, the first switching power supplies 101-104 drive the main core supply voltage input pin VDD1 to a second voltage level (e.g., 0.0V). However, during an active operating mode when voltage scaling is present, the first switching power supplies 101-104 drive the main core supply voltage input pin VDD1 to a first voltage level (e.g., 0.72-0.76V), and during a standby operating mode, the first switching power supplies 101-104 drive the main core supply voltage input pin VDD1 to a second voltage level (e.g., 0.0V). Therefore, the first switching power supplies 101-104 drive the main core supply voltage input pin VDD1 to 0V during standby mode. During this mode, the digital control 113 then controls enabling the LDO using the EN_LDO signal and disabling the load switch 116 using the EN_SW signal, thereby providing a supply voltage that can be used to drive the standby core 122 during standby mode as described below.

[0045] In the case where the cores 121, 122 of the multi-core controller 120 have separate power supplies with tight core-to-core differential voltage tolerance requirements, it is not possible to power the low power standby core 122 with a fixed power supply (e.g., a conventional single output low power linear regulator connected to a battery). Alternatively, an LDO linear voltage regulator 110 is provided to connect the standby core supply voltage input pin VDD2 during active mode to track the main core supply voltage V at input pin VDD1. SMPS , and during standby mode, the standby core supply voltage input pin VDD2 is connected to receive the LDO output supply voltage (V LDO To this end, the LDO linear voltage regulator 110 includes a second LDO power supply 114-115 that can be connected in a feedback configuration to generate an LDO output supply voltage (V LDO ) is realized by a linear amplifier 114 and a pass FET 115. As depicted, the input reference voltage VREF is connected to the inverting input of the amplifier 114. In addition, the LDO output voltage (V LDO) is connected in a feedback manner to the non-inverting input of the amplifier 114 to regulate the generated LDO output voltage when the amplifier 114 is enabled by the first enable control signal (EN_LDO). In addition, the LDO linear voltage regulator 110 may include a digital control 113 and a parallel load switch 116, which are connected to selectively provide the LDO output supply voltage V to the standby core 122 during the standby mode. LDO , but provides the main core supply voltage V to the standby core 122 during the active mode SMPS .

[0046] To selectively provide the standby core 122 with supply voltages from the first switching power supplies 101-104 and the second LDO power supplies 114-115 during active and standby modes, the digital control 113 generates an LDO enable signal (EN_LDO) during standby mode to start the LDO amplifier 114 and turn on the FET 115 to generate the LDO output supply voltage V at the input capacitor C2. LDO The digital control 113 generates a switch enable signal (EN_SW) in the standby mode to control the parallel load switch 116 to connect the standby core supply voltage input pin VDD2 to the main core supply voltage VDD1 generated at the main core supply voltage input pin VDD1 when transitioning from the active / tracking mode to the standby / LDO mode. SMPS Disconnect.

[0047] When the main core 121 transitions from the standby / LDO mode to the active / tracking mode, the digital control 113 controls the parallel load switch 116 to connect the standby core supply voltage input pin VDD2 to the main core supply voltage V SMPS And disable the LDO amplifier 114 to stop generating the LDO output supply voltage V LDO , thereby enabling the standby core supply voltage to track the main core supply voltage V generated by the first switching power supplies 101-104 SMPS Specifically, the digital control 113 detects the main core power supply voltage V SMPS The switch enable signal (EN_SW) is first enabled after a predetermined threshold voltage (e.g., PGOOD) has been reached. In selected embodiments, a voltage monitor or comparator circuit 111 is connected to measure the main core supply voltage V at the supply voltage input pin VDD1 of the main core 121. SMPSand generates a "PGOOD" signal that is input to digital control 113 when a predetermined threshold voltage is reached. While any suitable voltage monitoring circuit may be used, selected embodiments of voltage monitor circuit 111 may include an analog-to-digital converter circuit and / or a comparator circuit that is connected to detect whether the analog voltage provided at the VLS_IN input node meets or exceeds a predetermined threshold voltage Vth. In response to the main core supply voltage V SMPS When the predetermined threshold voltage is reached, the digital control 113 provides an enabled switch enable signal (EN_SW) to control the parallel load switch 116 to connect the standby core supply voltage input pin VDD2 to the main core supply voltage input pin VDD1. In addition, the digital control 113 disables the LDO enable signal (EN_LDO) during the active mode to deactivate the LDO amplifier 114 and the pass FET 115 to stop generating the LDO output supply voltage V LDO Therefore, during active mode, the standby core supply voltage input pin VDD2 is no longer supplied by the LDO output supply voltage V LDO driver, but instead is connected to track the main core supply voltage V SMPS .

[0048] When the main core 121 transitions from active / tracking mode to standby / LDO mode, the digital control 113 controls the parallel load switch 116 to connect the standby core supply voltage input pin VDD2 to the main core supply voltage VDD2. SMPS The LDO amplifier 114 is disconnected and enabled to generate the LDO output supply voltage V LDO , thereby enabling the standby core supply voltage to receive the LDO output supply voltage V generated by the second LDO power supply 114-115 LDO Specifically, upon detecting the start of the standby mode (e.g., STANDBY_B=0), the digital control 113 first disables the switch enable signal (EN_SW) and enables the first enable control signal (EN_LDO), thereby controlling the parallel load switch 116 to disconnect the standby core supply voltage input pin VDD2 from the main core supply voltage input pin VDD1 and simultaneously enabling the LDO amplifier 114 and the pass FET 115 to generate the LDO output supply voltage V LDOIn addition, the digital control 113 generates a signal or flag that is sent to the MCU 120 to indicate entry into standby mode. In selected embodiments, the digital control interface 113 detects when the supply voltage at the main core 121 is sufficiently low before confirmation of successful entry into standby mode is sent to the microcontroller 120, thereby ensuring that leakage in the main core 121 is extremely low before confirmation of entry into standby mode is confirmed. To this end, the digital control 113 may include a second voltage monitor or comparator circuit 112 that is connected to measure the main core supply voltage V at the supply voltage input pin VDD1 for the main core 121. SMPS And when the main core supply voltage is low enough to be at or below the maximum threshold voltage, a “V MAINCORE_LOW " signal. While any suitable voltage monitoring circuit may be used, selected embodiments of the voltage monitor circuit 112 may include an analog-to-digital converter circuit and / or a comparator circuit connected to detect whether the analog voltage provided at the VLS_IN input node is at or below a predetermined threshold voltage Vth2. In response to the main core supply voltage V SMPS When the predetermined threshold voltage Vth2 is reached, the digital control 113 provides a signal or flag “V MAINCORE_LOW ”.

[0049] As can be seen from the foregoing, the LDO linear voltage regulator 110 operates to provide a dual-mode operation to provide an LDO or standby mode (for providing an LDO output supply voltage V LDO supply to the standby core 122) and the tracking switch mode (for the active supply voltage V SMPS In standby mode, the digital control 113 controls the LDO amplifier 114 and the pass FET 115 to provide an ultra-low quiescent current with limited and optimal power dissipation to generate the standby core supply voltage V LDO , the standby core supply voltage V LDO By connecting the load switch 116 in parallel with the main core supply voltage V SMPS However, in the tracking switch mode of the service activation mode, the digital control 113 controls the parallel load switch 116 to connect the standby core supply voltage input pin VDD2 to the main core supply voltage V SMPS , in order to maintain the standby core supply voltage at the main core supply voltage V required by deep submicron dual-core low-power MCU SMPSDuring wakeup, a parallel load switch 116 is used to connect the standby core supply voltage input pin VDD2 to the main core supply voltage input pin VDD1, powering the standby low-power core 122 at a voltage within a small difference of typically 20 to 30 mV relative to the supply voltage of the higher-performance active-mode core 121, thereby providing a seamless transition between standby mode and active mode (and vice versa) to avoid any abrupt interruptions that could cause a microcontroller reset and system failure. In addition, deactivating the LDO amplifier 114 and pass FET 115 during active mode reduces power dissipation, providing significant power savings benefits for motor vehicles using high-voltage batteries (e.g., 24V truck vehicles, 48V mild hybrid vehicles), and even larger batteries.

[0050] To provide additional details for improving understanding of selected embodiments of the present disclosure, reference is now made to Figure 2A , which is a simplified schematic circuit diagram 200 illustrating a dual-mode low-dropout (LDO) linear voltage regulator circuit 210 that can be powered from a high-voltage car battery (e.g., VHV_REG_IN = 60V) in two modes, thereby providing good accuracy for the output voltage VDD2. In a first operating or standby mode, the LDO linear voltage regulator 210 enables LDO power supplies 214, 215 to generate an output voltage VLDO that is provided to a standby core supply voltage node VDD2, which is disconnected from the main core supply voltage node VLS_IN / VDD1 via a load switch 216. In a second operating or wake-up mode, the LDO linear voltage regulator 210 disables the LDO power supplies 214, 215 to stop generating the output voltage VLDO, and the standby core supply voltage node VDD2 is connected to the main core supply voltage node VLS_IN / VDD1 via the load switch 216 to provide a tracking switching mode. As depicted, the LDO linear voltage regulator circuit 210 is connected to receive inputs from the external digital control logic 201, as well as power supply inputs from a battery VHV_REG_IN, a main core supply voltage node VLS_IN / VDD1, and a lower voltage source Vdd_5V. Additionally, the LDO linear voltage regulator circuit 210 includes a comparator 211, a digital control circuit / module 213, an error amplifier 214, a PMOS pass FET switch 215D, a discharge switch 217 for discharging the output voltage VLDO in response to a discharge signal, a load switch 216, and a resistor divider circuit 219 for selectively generating a supply voltage for the standby core supply voltage node VDD2 in response to a switch enable signal (EN_SW).

[0051] In the LDO linear voltage regulator 210, the error amplifier 214, the PMOS pass FET switch and buffer circuit 215, and the load switch 216 are connected in any suitable configuration so that the switch / buffer circuit 215 can be turned off and the load switch 216 can be turned on to cause the standby core supply voltage node VDD2 to track the main core supply voltage node VLS_IN / VDD1 during standby mode. For example, the error amplifier 214 and the PMOS pass FET switch and buffer circuit 215 can be connected in a feedback arrangement with a resistor divider circuit 219 to generate the LDO output supply voltage VLDO across the capacitor C2 at the standby core supply voltage node VDD2. As described more fully below, LDO linear voltage regulator 210 operates to generate an LDO output supply voltage VLDO in response to a switch enable signal (EN_SW) connected between error amplifier 214 and resistor divider circuit 219 via a PMOS pass FET 215D of a buffer consisting of 215B and 215E, and disables or opens load switch 216. Specifically, error amplifier 214 is connected to the input gate of pass transistor 215. The source connection of pass transistor 215D is connected to a battery voltage source (VHV_REG_IN), and the drain of pass transistor 215D provides the LDO output supply voltage VLDO. Capacitor C2, which can be an internal capacitor or external to the regulator circuit, is connected to the LDO output supply voltage VLDO. Resistor divider network 219 is also connected to the LDO output supply voltage VLDO and is connected in parallel with capacitor C2. The node between resistors R1 and R2 of resistor divider network 219 is connected to the inverting input of error amplifier 214 and provides a scaled-down version of output voltage VLDO to error amplifier 214. Error amplifier 214 also receives a reference voltage signal Vref. Error amplifier 214 compares reference voltage signal Vref with the scaled-down version of output voltage signal VLDO to generate an amplified error signal, which is provided to buffer circuit 215. The amplified error signal is used to maintain the output of LDO linear voltage regulator 210 at a predetermined voltage during startup.

[0052] While the pass transistor 215D can be functionally implemented as a PMOS pass FET, it should be understood that additional buffering and switching circuitry can be included with the pass transistor 215D. For example, M1 (215B) NMOS and M2 (215E) PMOS form a buffer to isolate the error amplifier 214 from the PMOS pass FET 215D. This helps provide better stability and high voltage protection from the battery voltage applied at VHV_REG_IN. In addition, switches 215A, 215B, and 215C help close the path connecting the output of the error amplifier 214 to the gate of the NMOS 215B during the standby mode of operation. As depicted, the input gate of the NMOS 215B is connected to the output of the error amplifier 214 via a first control switch SW1 215A controlled by a switch enable signal (EN_SW). In addition, the gate of the NMOS 215B is connected to ground via a second control switch SW2 215C controlled by an inverted switch enable signal (EN_SW_B). The drain of the NMOS 215B is connected to a ratiometric PMOS current mirror circuit 215D across a resistor divider circuit 219 to generate an output voltage signal VLDO in response to a switch enable signal (EN_SW).

[0053] As indicated above, the error amplifier 214 is connected in a feedback configuration with the PMOS pass FET 215D and the resistor divider circuit 219 to provide a good output voltage VLDO at the standby core supply voltage node VDD2 while consuming an ultra-low quiescent current in the first standby operating mode of the LDO linear voltage regulator 210. However, the LDO linear voltage regulator 210 can be configured in a second tracking operating mode in which the LDO linear voltage regulator 210 is disabled to stop generating the output voltage VLDO, and the standby core supply voltage node VDD2 is connected to the main core supply voltage node VLS_IN / VDD1 through the load switch 216 under the control of the switch enable signal (EN_SW).

[0054] As disclosed herein, load switch 216 can be functionally implemented as a single FET switch, but it should be understood that additional switching circuitry can be included in load switch 216. For example, load switch 216 can be implemented as a parallel load switch connected to a lower voltage source up to 5.5V to power control circuit 216A. Parallel PMOS and NMOS switches can be incorporated to allow for a wide input range for tracking capability from the main core source to the standby core source. For example, PMOS 216B is used for high voltage (e.g., 3.3V) and NMOS 216C is used for low voltage (e.g., 0.8V). However, it should be understood that either or both of the parallel PMOS and NMOS switches 216B, 216C can be used, depending on the requirements of the application. Circuit 216A generates complementary output signals to drive a PMOS transistor 216B and an NMOS transistor 216C connected in parallel via appropriate isolation (e.g., as a back-to-back switch for providing reverse current protection), thereby connecting the standby core supply voltage node VDD2 to the main core supply voltage node VLS_IN / VDD1. In operation, load switch 216 is controlled by a switch enable signal (EN_SW) supplied to control circuit 216A to enable switch 216 during normal operation (active mode) to deliver significantly higher power to output pin VDD2, while disabling the low-power high-voltage LDO (e.g., by opening switch 216A).

[0055] To provide additional details for improving understanding of selected embodiments of the present disclosure, reference is now made to Figure 2B , which can be used to implement Figure 2A, a simplified schematic circuit depiction of selected PMOS switch embodiments 250 and 260 of the parallel-connected NMOS switch 216C and PMOS switch 216B in the load switch 216 is shown in FIG. If the common-mode voltage is very low, an NMOS switch will be required, and if the common-mode voltage is very high, a PMOS switch will be required. To cover a wide input common-mode range at the input, both the NMOS switch 216C and the PMOS switch 216B will be required. As will be appreciated, the NMOS switch 216C and the PMOS switch 216B can be implemented with different switch configurations. For example, the NMOS switch 216C can be implemented with any of the NMOS switch configurations 251, 252, or 253, or any other such equivalent, to ensure that there is no reverse current. Additionally, the PMOS switch 216B can be implemented with any of the PMOS switch configurations 261, 262, or 263, or any other such equivalent, to ensure that there is no reverse current. Of course, different combinations can be used by selecting one of NMOS switches 251, 252, or 253 and one of PMOS switches 261, 262, or 263 to implement load switch 216. Implementing load switch 216 using any combination of these switches 251-253, 261-263 ensures a bidirectional switch with proper isolation.

[0056] To control the operating mode of LDO linear voltage regulator 210 to limit power dissipation and provide input supply tracking characteristics, a digital control interface 213 is used to dictate the configuration of circuit 210. In a first configuration, LDO linear voltage regulator 210 generates an ultra-low quiescent current that is limited (e.g., to 10 mA) but sufficient to support a low-power standby mode of operation. In a second configuration, LDO linear voltage regulator 210 and load switch 216 are enabled during normal operation to deliver significantly higher power to output pin VDD2, while the low-power high-voltage LDO is disabled. In selected embodiments, digital control interface 213 can be programmed via an I2C / SPI interface or OTP bits provided by external digital control module 201 to operate LDO linear voltage regulator 210 in either standby mode (LDO mode) or active mode (tracking mode). While any suitable digital control logic and / or circuitry may be used, selected embodiments of digital control interface 213 may include blocks of level shifters, latches, and logic 213A that process signal information received from external digital control logic 201. Additionally, the digital control interface 213 may include an embedded brownout detector 213C and a low-power bandgap 213D, both powered by an internal 5V pre-regulator 213B as an internal voltage reference. As disclosed herein, the level shifter, latch, and logic 213A blocks are structured and configured to control the embedded brownout detector 213C and the low-power bandgap 213D. Furthermore, the logic circuit 213A is implemented to generate a switch enable signal (EN_SW) and an LDO enable signal (EN_LDO) in response to detecting that the main core supply voltage VDD1 has reached a predetermined threshold voltage Vth.

[0057] While the threshold voltage evaluation function can be implemented using any suitable detection circuit, LDO linear voltage regulator 210 may include a comparator 211 that provides a voltage monitoring function for comparing the main core supply voltage node VLS_IN / VDD1 with a predetermined threshold voltage Vth. In selected embodiments, comparator 211 may be implemented using an analog-to-digital converter circuit for generating a digital voltage value, a memory storage device or register for storing the predetermined threshold voltage Vth value, and a comparator for comparing the digital voltage value with the predetermined threshold voltage Vth value. Alternatively, comparator 211 may be implemented as an analog comparison circuit for comparing the analog voltage provided at the VLS_IN input node with the predetermined threshold voltage Vth value.

[0058] To provide additional details for improving understanding of selected embodiments of the present disclosure, reference is now made to Figure 3, which shows a mode transition timing diagram waveform 300 of a dual-mode LDO linear voltage regulator circuit transitioning from tracking switch mode 301 to LDO mode 302 and back to tracking switch mode 303. In general, by tracking the switch mode power supply voltage V SMPS The “standby” signal having a first value corresponding to the “active state” (e.g., STANDBY_B=1 or STANDBY=0) defines the tracking switch mode 301, 303, while the standby core supply voltage is connected to the low power high voltage supply voltage V LDO The “STANDBY” signal having a second value (eg, STANDBY_B=0 or STANDBY=1) when OFF defines the LDO mode 302 .

[0059] In selected embodiments, the initial state after power-up is an "active mode" in which both the main core and the standby core are powered by the same switch-mode power supply voltage source, such that the standby core tracks the supply voltage V generated by the first power supply. SMPS In active mode when the STANDBY_B signal waveform 310 is set, the main core supply voltage VDD1 311 is driven to a first output voltage level (e.g., 0.8V) reflected in the "PGOOD" signal waveform 312 indicating that the main core supply voltage exceeds a minimum threshold voltage. By the same token, the "STANDBY_GOOD" signal waveform 313 has a first or lower value indicating that the main core supply voltage is above a maximum threshold voltage and, therefore, is not in a low leakage current state ready to transition to standby mode. In active mode when the standby core supply voltage is connected to track the switch mode supply voltage V SMPS During active mode when EN_SW is set, the EN_SW control signal 314 is set to turn on the load switch, which connects the standby core to the switch mode supply voltage V SMPS At the same time, the EN_LDO control signal 315 is reset to disable the LDO power supply. Therefore, as can be seen on the VDD2 waveforms 316, 317, the standby core supply voltage has a first voltage value.

[0060] After transitioning from "active mode" to "standby mode," in which the standby core is powered by a separate LDO supply voltage source, the STANDBY_B signal waveform 310 is reset, at which point the main core supply voltage VDD1 311 is driven to a second output voltage level (e.g., 0.0V), which causes the "PGOOD" signal waveform 312 to be reset when the main core supply voltage 311 no longer exceeds the minimum threshold voltage. Once the main core supply voltage 311 is below the maximum threshold voltage, the "STANDBY_GOOD" signal waveform 313 transitions to a second or upper limit value, indicating that the main core supply voltage is below the maximum threshold voltage and is therefore in the low leakage current state of standby mode. In response to the transition from active mode to standby mode (e.g., when the STANDBY_B signal waveform 310 transitions from "high" to "low"), the EN_SW control signal 314 is reset to turn off the load switch, thereby isolating the standby core from the switch-mode supply voltage VDD1. SMPS The connection is disconnected. Simultaneously, the EN_LDO control signal 315 is set to enable the LDO power supply. Consequently, the standby core supply voltage has a second voltage value driven by the LDO power supply. In embodiments where scaling is absent, as seen on the VDD2 waveform 316, the second voltage value of the standby core supply voltage VDD2 is substantially the same as when in active / tracking mode. However, in embodiments where scaling is present, as seen on the VDD2 waveform 317, the second voltage value of the standby core supply voltage VDD2 is adjusted upward (or downward) based on the scaling.

[0061] After transitioning from “LDO / Standby Mode” back to “Tracking / Active Mode”, the Standby Core is disconnected from the LDO supply voltage source and reconnected to track the supply voltage V SMPS . This mode switch occurs when the STANDBY_B signal waveform 310 is set, at which point the main core supply voltage VDD1 311 is driven back to an output voltage level (e.g., 0.8V) that causes the "PGOOD" signal waveform 312 to be reset when the main core supply voltage 311 exceeds the minimum threshold voltage. And once the main core supply voltage 311 is above the maximum threshold voltage, the "STANDBY_GOOD" signal waveform 313 transitions to a first or lower value to indicate that the main core supply voltage is above the maximum threshold voltage. In response to switching from LDO / standby mode to tracking / active mode (e.g., when the STANDBY_B signal waveform 310 transitions from "low" to "high"), the EN_SW control signal 314 is set to turn on the load switch, thereby connecting the standby core to the switch mode supply voltage V SMPS At the same time, the EN_LDO control signal 315 is reset to disable the LDO power supply. Therefore, the standby core power supply voltage returns to the supply voltage V SMPSThe first driving voltage value.

[0062] To provide additional details for improving understanding of selected embodiments of the present disclosure, reference is now made to Figure 4 , which shows a simplified flow chart 400 of control logic for operating an adaptive standby power supply of a low power dual core microcontroller according to selected embodiments of the present disclosure. In an example embodiment, Figure 4 The processing shown in can be performed by a microcontroller or other processor-based functionality, such as a power management unit programmed with RTL code that is connected to detect the operating state of the switching power mode supply voltage relative to upper and lower voltage thresholds in order to selectively enable a high voltage low power low dropout (LDO) linear regulator and connect it to the standby core.

[0063] At step 402, the control logic and / or hardware at the power management unit is configured to begin the process, for example, when the system boots up or initially begins operation. At step 404, the control logic and / or hardware at the power management unit is configured to begin system monitoring to detect whether the SMPS is in wake-up or active mode. While any suitable detection method may be used, in selected embodiments, the wake-up or active mode may be detected with reference to a wake-up signal (e.g., STANDBY_B = 1) provided by the low-power MCU. If not (a negative result of detection step 404), the system continues to wait until the wake-up / active mode is detected. However, when the wake-up signal is detected (a positive result of detection step 404), the system enters the tracking switch mode.

[0064] At step 406, control logic and / or hardware at the power management unit is configured to evaluate the main core power supply output voltage against a specified minimum voltage threshold to detect whether a good supply voltage level is provided. As will be appreciated, dedicated voltage monitoring circuitry and / or software may be used to implement a comparator function for measuring the main core power supply output voltage against a minimum voltage threshold (e.g., Vth1) to generate a good supply voltage level signal (e.g., PGOOD) when the minimum voltage threshold is reached or exceeded.

[0065] The main core power supply output voltage is connected to the standby core power supply at step 408. While any suitable connection mechanism may be used, in selected embodiments of the present disclosure, a connection may be made to a shunt load switch controlled by a switch enable signal that is digitally generated in response to the good supply voltage level signal.

[0066] When the main core power supply output voltage is connected to the standby core power supply, the high-voltage low-power low-LDO linear regulator is disabled or otherwise disconnected from the standby core power supply at step 410. Thus, the standby core is powered by the main core power supply output voltage. While any suitable mechanism may be used to disable the LDO regulator, in selected embodiments of the present disclosure, the LDO regulator may be disabled by disabling a linear amplifier and / or a pass FET using an enable signal digitally generated in response to a good supply voltage level signal.

[0067] At step 412, the control logic and / or hardware at the power management unit is configured to initiate system monitoring to detect whether the SMP is in standby mode. While any suitable detection method may be used, in selected embodiments, standby mode may be detected by reference to a standby signal (e.g., STANDBY_B=0) provided by the low-power MCU. If not (a negative result of detection step 412), the system continues to wait until standby mode is detected. However, when a standby signal is detected (a positive result of detection step 412), the system enters standby or LDO mode.

[0068] At step 413, the control logic and / or hardware at the power management unit is configured to evaluate the main core power supply output voltage against a specified maximum voltage threshold to detect whether the main core power supply output voltage is below the maximum voltage threshold. As will be appreciated, dedicated voltage monitoring circuitry and / or software may be used to implement a comparator function for measuring the main core power supply output voltage against a maximum voltage threshold (e.g., Vth2) to generate a low voltage level signal (e.g., STANDBY_GOOD).

[0069] At step 414, a high-voltage, low-power, low-LDO linear regulator is enabled for connection to the standby core power supply. Thus, the standby core is powered by the LDO linear regulator. While any suitable mechanism may be used to enable the LDO regulator, in selected embodiments of the present disclosure, the LDO regulator may be enabled by enabling a linear amplifier and / or a turn-on FET using an enable signal digitally generated in response to a low voltage level signal.

[0070] When the LDO linear regulator is enabled, the main core power supply output voltage is disconnected from the standby core power supply at step 416. While any suitable disconnection mechanism may be used, in selected embodiments of the present disclosure, the disconnection may be implemented using a parallel load switch controlled by a switch enable signal digitally generated in response to a low voltage level signal. The system then returns to step 404 to detect when the SMPS returns to awake or active mode, and steps 404-416 are repeated.

[0071] As disclosed herein, a power supply controller method, system, and apparatus for a low-power multi-core integrated circuit microcontroller can be implemented using a first voltage source for a high-performance active-mode main core and a second LDO power source for a standby core, the first and second LDO power sources being selectively connected to the standby core via a parallel load switch digitally controlled by control logic and / or a computer program product. While embodiments are described in the context of monitoring a first voltage source from a buck converter SMSP circuit using digital control logic, the proposed power control steps and / or functionality can be applied to monitor any suitable voltage source for a high-performance active-mode main core and selectively generate a second LDO voltage source for the standby core during standby mode by tracking the first voltage source during active mode to maintain the standby core supply voltage within a specified tolerance of the main core supply voltage, thereby seamlessly transitioning between standby and active modes.

[0072] Depending on the needs, some of the above embodiments can be implemented using various data processing systems. Figure 1 2 and 3 and the discussion thereof describe an exemplary adaptive standby power architecture, but this architecture is presented merely to provide a useful reference when discussing various aspects of the present invention. Of course, the description of this architecture has been simplified for purposes of discussion, and it is only one of many different types of suitable architectures that may be used in accordance with the present invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and alternative embodiments may merge logic blocks or circuit elements, or impose alternative decompositions of functionality on various logic blocks or circuit elements. Therefore, it should be understood that the architectures depicted herein are merely exemplary, and that, in practice, many other architectures that achieve the same functionality may be implemented. In an abstract yet still explicit sense, any arrangement of components that achieve the same functionality is effectively "associated" to achieve the desired functionality. Thus, any two components herein that are combined to achieve a particular functionality may be considered "associated" with each other to achieve the desired functionality, regardless of the architecture or intervening components. Similarly, any two components so associated may also be considered "operably connected" or "operably coupled" to each other to achieve the desired functionality. Furthermore, those skilled in the art will recognize that the boundaries between the operational functionality described above are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed in additional operations. In addition, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may be changed in various other embodiments.

[0073] It should now be appreciated that power supply systems, devices, and methods for connecting dual power supplies to a high-performance main core and a standby core in a multi-core, low-power microcontroller are provided herein. The dual power supply may include a first power supply (generating a high supply voltage using a switch-mode power supply including a pulse-width modulator (PWM) controller and a buck converter) and a second, ultra-low quiescent current, low-dropout (LDO) voltage regulator for generating an LDO linear supply voltage. In the disclosed method, during an active mode of the multi-core, low-power microcontroller, the high supply voltage is connected to the high-performance main core and the standby core in the multi-core, low-power microcontroller, such that the standby core receives a first supply voltage that tracks the high supply voltage during the active mode. In selected embodiments, during the active mode, the high supply voltage is connected to the standby core by closing a parallel load switch formed on an integrated circuit LDO linear voltage regulator using a switch enable signal. During the active mode, the integrated circuit LDO linear voltage regulator can be disabled using a disable signal. Before connecting the high supply voltage to the standby core, the high supply voltage can be measured to detect whether it meets or exceeds a minimum voltage threshold. Upon subsequently detecting a standby mode of the multi-core low-power microcontroller, the high supply voltage is disconnected from the standby core and a low dropout (LDO) linear supply voltage is connected to the standby core during the standby mode of the multi-core low-power microcontroller, such that the standby core receives the LDO linear supply voltage as a second supply voltage during the standby mode. In selected embodiments, the low dropout (LDO) linear supply voltage is connected to the standby core by enabling an integrated circuit LDO linear voltage regulator with an enable signal during the standby mode. Upon detecting an active mode of the multi-core low-power microcontroller occurring after the standby mode, the high supply voltage can be reconnected to the high-performance main core and the standby core while disabling the LDO linear supply voltage, such that the standby core receives a first supply voltage that tracks the high supply voltage during the active mode. In selected embodiments, the high supply voltage is (re)connected by providing a switch enable signal to a parallel load switch including an input inverter buffer control circuit connected to gate terminals of an NMOS switch and a PMOS switch connected in parallel between the supply voltage and the LDO linear supply voltage.

[0074] In another embodiment, a method, processing system, and circuit are provided for providing adaptive standby power to a multi-core microcontroller including a first power supply and a low-dropout (LDO) linear power regulator. The disclosed first power supply generates a first supply voltage for connection to a first core in the multi-core microcontroller. In selected embodiments, the first power supply is implemented as a switch-mode power supply having a pulse-width modulator (PWM) controller and a buck converter. The disclosed LDO linear power regulator includes an LDO linear power supply for generating an LDO supply voltage in response to a first enable signal, wherein the LDO supply voltage is connected as a supply voltage to a standby core in the multi-core microcontroller. In selected embodiments, the LDO linear power supply is implemented as an ultra-low quiescent current LDO voltage supply including an error amplifier that drives an internal PMOS pass FET. The disclosed LDO linear power regulator also includes a load switch for connecting a first high supply voltage as a supply voltage to the standby core in response to a second enable signal. In selected embodiments, the load switch is implemented as an NMOS switch and a PMOS switch connected in parallel between the first high supply voltage and the LDO supply voltage and controlled by the second enable signal. In addition, the disclosed LDO linear power regulator includes a digital control interface that generates a first enable signal and a second enable signal such that, during an active mode, the first enable signal disables the LDO linear power regulator and the second enable signal closes a load switch to connect the first supply voltage as the supply voltage to the standby core, and such that, during a standby mode, the first enable signal enables the LDO linear power regulator and the second enable signal opens the load switch to disconnect the first high supply voltage from the supply voltage to the standby core. In selected embodiments, the LDO linear power regulator, the load switch, and the digital control interface are formed in a single integrated circuit, the LDO linear power regulator. In selected embodiments, the LDO linear power regulator may also include a first voltage monitor circuit connected to detect whether the first high supply voltage meets or exceeds a minimum voltage threshold before notifying the digital control interface that the second enable signal may be generated to the load switch for connecting the first high supply voltage as the supply voltage to the standby core. In other embodiments, the LDO linear power supply regulator includes a second voltage monitor circuit connected to detect that the first high power supply voltage is at or below a maximum voltage threshold before notifying the digital control interface that a first enable signal can be generated to enable the LDO linear power supply.

[0075] In yet another form, a power supply circuit or device for a multi-core microcontroller is provided. The disclosed power supply circuit includes a switch-mode power supply including a switching regulator configured to convert an input voltage of the power supply circuit to a high supply voltage for connection to a first core in the multi-core microcontroller. The disclosed power supply circuit also includes a low dropout (LDO) linear voltage regulator connected between the switch-mode power supply and a standby core in the multi-core microcontroller. In the LDO linear voltage regulator, an error amplifier and an internal pass FET are configured to convert the input voltage of the power supply circuit to a standby low-power core supply voltage for the standby core when the power supply circuit is in a standby operating mode, and to be disabled when the power supply circuit is in an active operating mode. Additionally, the LDO linear voltage regulator includes an internal load switch that connects the high supply voltage to a standby supply voltage node of the standby core during an active operating mode and disconnects the high supply voltage from the standby supply voltage node of the standby core during a standby operating mode, such that after transitioning from the standby operating mode to the active operating mode, the standby low-power core supply voltage is maintained within approximately 20 mV-30 mV of the high supply voltage. In selected embodiments of the internal load switch, an NMOS switch and a PMOS switch are connected in parallel between the high supply voltage and the standby supply voltage node of the standby core and are controlled by a second enable signal. In selected embodiments, the LDO linear voltage regulator further includes a digital control that generates a first enable signal and a second enable signal, such that during the active operating mode, the first enable signal disables the LDO linear voltage regulator and the second enable signal closes the internal load switch to connect the high supply voltage as the supply voltage to the standby core, and such that during the standby mode, the first enable signal enables the LDO linear voltage regulator and the second enable signal opens the internal load switch to disconnect the high supply voltage from the standby core. In selected embodiments, the LDO linear voltage regulator is a single integrated circuit LDO linear power regulator.

[0076] Various illustrative embodiments of the present invention have been described in detail with reference to the accompanying drawings to illustrate exemplary representations of adaptive standby power supplies and associated operating methods. However, the present disclosure is not necessarily limited to exemplary embodiments illustrating inventive aspects of the present invention applicable to a variety of power controllers. Therefore, while various details have been set forth in the foregoing description, it should be understood that the present invention can be practiced without these specific details, and that many specific implementation decisions may be made with respect to the present invention described herein to achieve the specific goals of the circuit designer, such as to comply with process technology or related design constraints, which may vary from implementation to implementation. While such development work can be complex and time-consuming, it is a routine task for those skilled in the art having the benefit of this disclosure. For example, selected aspects are shown in block diagram form rather than in detail to avoid limiting or obscuring the present invention. Additionally, some portions of the detailed description provided herein are presented in terms of algorithms or operations on data within a computer memory. Such descriptions and representations are used by those skilled in the art to describe and convey the essence of their work to others skilled in the art. Although the described exemplary embodiments disclosed herein are directed to an exemplary multi-channel direct memory access hardware engine, the present invention is not necessarily limited to the exemplary embodiments shown herein, and various embodiments of the circuits and methods disclosed herein may be implemented with other devices and software components. Therefore, the specific embodiments disclosed above are merely illustrative and should not be regarded as limitations on the present invention, as the present invention may be modified and implemented in different but equivalent ways that are obvious to those skilled in the art having the benefit of the teachings herein. Accordingly, the foregoing description is not intended to limit the present invention to a particular form of exposition, but rather is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the present invention as defined by the appended claims, so that those skilled in the art understand that various changes, substitutions and variations may be made in the broadest form without departing from the spirit and scope of the present invention.

[0077] Benefits, other advantages, and solutions to problems are described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more apparent, should not be construed as key, required, or essential features of any or all of the claims. As used herein, the term "comprise" or any other variation thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A method for supplying electric power, characterized in that include: During an active mode of a multi-core low-power microcontroller, connecting a power supply voltage to a main core and a standby core in the multi-core low-power microcontroller such that the standby core receives a first supply voltage that tracks the power supply voltage during the active mode; and After detecting a standby mode of the multi-core low-power microcontroller, the power supply voltage is disconnected from the standby core and, during the standby mode of the multi-core low-power microcontroller, a low-dropout (LDO) linear power supply voltage is connected to the standby core, so that during the standby mode, the standby core receives the LDO linear power supply voltage as a second supply voltage; connecting the power supply voltage includes closing a parallel load switch formed on an integrated circuit LDO linear voltage regulator using a switch enable signal to connect the power supply voltage to the standby core, the parallel load switch including a parallel NMOS switch and a PMOS switch.

2. The method according to claim 1, characterized in that Furthermore, the supply voltage is generated using a switch mode power supply including a pulse width modulator (PWM) controller and a buck converter.

3. The method according to claim 1, characterized in that The invention also includes using an ultra-low quiescent current LDO voltage regulator to generate the low voltage drop LDO linear power supply voltage.

4. The method according to claim 1, wherein Connecting the low dropout (LDO) linear supply voltage to the standby core includes enabling an integrated circuit (IC) LDO linear voltage regulator with an enable signal during the standby mode.

5. The method according to claim 1, wherein Additionally included is disabling an integrated circuit LDO linear voltage regulator with a disable signal during the active mode.

6. The method according to claim 1, characterized in that Also included is detecting, before connecting the power supply voltage to the standby core, that the power supply voltage meets or exceeds a minimum voltage threshold.

7. The method according to claim 1, characterized in that Also includes: Upon detecting an active mode of the multi-core low-power microcontroller, the supply voltage is reconnected to the main core and the standby core while disabling the LDO linear supply voltage, so that the standby core receives the first supply voltage that tracks the supply voltage during the active mode.

8. A multi-core microcontroller processing system, characterized in that: include: a first power supply for generating a first power supply voltage connected to a first core in the multi-core microcontroller; and A low-voltage dropout (LDO) linear power regulator, comprising: an LDO linear power supply, the LDO linear power supply being configured to generate an LDO power supply voltage in response to a first enable signal, wherein the LDO power supply voltage is connected to a standby core in the multi-core microcontroller as a supply voltage; a load switch that connects the first power supply voltage as the supply voltage to the standby core in response to a second enable signal; and a digital control interface that generates the first enable signal and the second enable signal such that, during an active mode, the first enable signal disables the LDO linear power regulator and the second enable signal closes the load switch to connect the first power supply voltage as the supply voltage to the standby core, and such that, during a standby mode, the first enable signal enables the LDO linear power regulator and the second enable signal opens the load switch to disconnect the first power supply voltage from the supply voltage to the standby core; the load switch includes an NMOS switch and a PMOS switch, is connected in parallel between the first power supply voltage and the standby core, and is controlled by the second enable signal.

9. A device, characterized in that include: a switch-mode power supply comprising a switching regulator configured to convert an input voltage of a power supply circuit to a supply voltage connected to a first core in a multi-core microcontroller; and A low-dropout (LDO) linear voltage regulator, wherein the low-dropout (LDO) linear voltage regulator is connected between the switch-mode power supply and a standby core in the multi-core microcontroller, wherein the multi-core microcontroller comprises: an error amplifier and an internal pass FET configured to convert the input voltage of the power supply circuit to a standby low power core supply voltage when the power supply circuit is in a standby mode of operation and to be disabled when the power supply circuit is in an active mode of operation; and an internal load switch that connects the power supply voltage to a standby supply voltage node of the standby core during an active operating mode and disconnects the power supply voltage from the standby supply voltage node of the standby core during a standby operating mode, such that after transitioning from the standby operating mode to the active operating mode, the standby low power core supply voltage is maintained within 20 mV-30 mV relative to the power supply voltage; wherein the LDO linear voltage regulator includes a digital control that generates first and second enable signals, such that during the active operating mode, the first enable signal disables the LDO linear voltage regulator and the second enable signal turns off the internal load switch to connect the power supply voltage as the power supply voltage to the standby core, and such that during the standby mode, the first enable signal enables the LDO linear voltage regulator and the second enable signal turns on the internal load switch to disconnect the power supply voltage from the standby core, and the internal load switch includes an NMOS switch and a PMOS switch, the NMOS switch and the PMOS switch being connected in parallel between the power supply voltage and the standby supply voltage node of the standby core and being controlled by the second enable signal.

Images