Integrated circuit substrate and integrated circuit substrate manufacturing method

Abstract

An integrated circuit substrate. The integrated circuit substrate comprises: an auxiliary positioning structure and an offset detection structure. The auxiliary positioning structure is used to define a drilling position. The offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure.

Description

Technical Field

[0001] The present application relates to a device, and more specifically, to an integrated circuit substrate and an integrated circuit substrate manufacturing method. Background Art

[0002] Conventionally, when drilling holes in a circuit board, especially a multi-layer circuit board, it is impossible to effectively detect whether the drilling position is offset from the preset position because the drilling position is covered by an upper insulating layer (such as resin) and a conductive layer (such as copper layer). Summary of the invention

[0003] In view of this, one of the objectives of the present application is to provide an integrated circuit substrate and an integrated circuit substrate manufacturing method.

[0004] According to an embodiment of the present application, an integrated circuit substrate is disclosed. The integrated circuit substrate includes: an auxiliary positioning structure and an offset detection structure. The auxiliary positioning structure is used to define a drilling position. The offset detection structure is disposed on the auxiliary positioning structure and is symmetrically disposed relative to the center of the auxiliary positioning structure.

[0005] According to an embodiment of the present application, the auxiliary positioning structure and the deviation detection structure are structures formed by etching, and the deviation detection structure includes two auxiliary lines symmetrically arranged to the center of the auxiliary positioning structure.

[0006] According to an embodiment of the present application, the two auxiliary lines are two parallel lines extending toward the first direction.

[0007] According to an embodiment of the present application, the width of each auxiliary line is in the range of 0.075-0.085 mm.

[0008] According to an embodiment of the present application, the line width of each auxiliary line is 0.08 mm.

[0009] According to one embodiment of the present application, the line spacing of the two auxiliary lines is the sum of the drilling diameter, half the line width of each of the two auxiliary lines, and the side etching amount generated in the second direction when etching the two auxiliary lines, minus the maximum offset allowed in the second direction, wherein the first direction is perpendicular to the second direction.

[0010] According to one embodiment of the present application, an integrated circuit substrate is disclosed. The integrated circuit substrate includes: a substrate, a first conductive layer, an insulating layer, a second conductive layer and a through hole. The first conductive layer is formed on the substrate. The first conductive layer includes: an auxiliary positioning structure and an offset detection structure. The auxiliary positioning structure is used to define a drilling position. The offset detection structure is arranged on the auxiliary positioning structure and is symmetrically arranged relative to the center of the auxiliary positioning structure. The insulating layer is formed on the first conductive layer. The second conductive layer is formed on the insulating layer. The through hole penetrates the substrate, the first conductive layer, the insulating layer and the second conductive layer.

[0011] According to an embodiment of the present application, the auxiliary positioning structure surrounds the through hole.

[0012] According to an embodiment of the present application, the offset detection structure partially overlaps with the through hole.

[0013] According to one embodiment of the present application, a method for manufacturing an integrated circuit substrate is disclosed. The method for manufacturing an integrated circuit substrate includes: forming a first conductive layer on a substrate; performing an etching process on the first conductive layer to generate a patterned conductive layer, the patterned conductive layer includes an auxiliary positioning structure and an offset detection structure, the auxiliary positioning structure is used to define a drilling position, and the offset detection structure is disposed on the auxiliary positioning structure and is symmetrically disposed relative to the center of the auxiliary positioning structure; sequentially forming an insulating layer and a second conductive layer on the patterned conductive layer; performing a drilling operation on the insulating layer and the second conductive layer corresponding to the center position of the auxiliary positioning structure to generate a through hole; and judging whether the through hole is offset according to the through hole and the offset detection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0015] Figure 1 It is a top view of an integrated circuit substrate according to an embodiment of the present application.

[0016] Figure 2 It is a top view of a patterned structure according to an embodiment of the present application.

[0017] FIG. 3A to FIG. 3E The invention is a flow chart of manufacturing an integrated circuit substrate according to an embodiment of the present application.

[0018] Figure 4 FIG. 1 is a top view of a patterned conductive layer after a drilling operation according to an embodiment of the present application.

[0019] Figure 5 It is a flow chart of a method for manufacturing an integrated circuit substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following disclosure provides a variety of implementations or illustrations that can be used to implement different features of the present disclosure. The specific examples of components and configurations described below are used to simplify the present disclosure. As can be imagined, these descriptions are only illustrative and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or above a second feature may include certain embodiments in which the first and second features are directly in contact with each other; and may also include certain embodiments in which additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may reuse component symbols and / or labels in multiple embodiments. Such repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0021] Furthermore, spatially relative terms such as "below," "below," "below," "above," and the like may be used herein to facilitate description of the relationship between one component or feature shown in the figure relative to another or more components or features. These spatially relative terms are intended to encompass a variety of different orientations of the device during use or operation in addition to the orientation shown in the figure. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and these spatially relative descriptive terms should be interpreted accordingly.

[0022] Although the numerical ranges and parameters used to define the broader scope of this application are approximate, the relevant numerical values ​​in the specific embodiments have been presented as accurately as possible. However, any numerical value inherently inevitably contains standard deviations due to individual testing methods. Here, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the mean, depending on the consideration of those with ordinary knowledge in the technical field to which this application belongs.

[0023] It should be understood that, except for the experimental examples or unless otherwise explicitly stated, all ranges, quantities, values ​​and percentages used herein (e.g., to describe the amount of material used, the length of time, temperature, operating conditions, quantitative ratios and the like) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the attached claims are approximate values ​​and can be changed as needed. At least these numerical parameters should be understood as the indicated significant digits and the values ​​obtained by applying the general rounding method. Here, the numerical range is expressed from one end point to another end point or between two end points; unless otherwise stated, the numerical range described herein includes the end points.

[0024] A traditional multi-layer circuit board (such as a four-layer circuit board) includes a substrate (such as a BT board) in the middle, a first conductive layer (such as a copper layer) formed on the upper and lower sides of the substrate, an insulating layer (such as a resin) formed on the upper and lower sides of the first conductive layer, and a second conductive layer (such as a copper layer) formed on the upper and lower sides of the insulating layer. Traditionally, when drilling a multi-layer circuit board, part of the conductive material (such as copper) is removed by etching on the first conductive layer (such as a copper layer) to form a patterned conductive layer, and the patterned structure in the patterned conductive layer will serve as a target for drilling.

[0025] Next, an insulating layer and a second conductive layer are sequentially formed on the patterned conductive layer. When drilling is to be performed, the patterned conductive layer covered by the insulating layer and the second conductive layer is first observed by X-ray to confirm the position of the patterned structure as a target, and then the drilling operation is performed. The horizontal deviation of drilling using a conventional patterned structure is easy to observe and allowable, however, it is not possible to effectively detect whether the drilling position is offset in the vertical direction. Therefore, the present application proposes an integrated circuit substrate and an integrated circuit substrate manufacturing method to solve the above-mentioned problems.

[0026] Figure 1 1 is a top view of an integrated circuit substrate 1 according to an embodiment of the present application. In some embodiments, the integrated circuit substrate 1 is a multi-layer circuit board. In some embodiments, the integrated circuit substrate 1 is a four-layer circuit board. The integrated circuit substrate 1 includes a substrate (not shown) located in the middle and a conductive layer 10 formed on the upper and lower sides of the substrate. In some embodiments, the substrate may be a BT substrate, and the conductive layer 10 may include copper.

[0027] As described above, the integrated circuit substrate 1 may further include an insulating layer formed on the upper and lower sides of the conductive layer 10 and another conductive layer formed on the upper and lower sides of the insulating layer. Figure 1 Only the parts related to the spirit of the invention of this application are depicted for the convenience of explanation.

[0028] The conductive layer 10 includes patterned structures 11 and 12. In some embodiments, the patterned structures 11 and 12 are located in the middle of the left and right sides of the integrated circuit substrate 1. The patterned structures 11 and 12 are used as targets to define the drilling positions, wherein the patterned structures 11 and 12 are horizontally symmetrical structures. In some embodiments, the patterned structures 11 and 12 are formed by etching the conductive layer 10.

[0029] Figure 2 This is a top view of a patterned structure 11 according to an embodiment of the present application. Since the patterned structure 11 and the patterned structure 12 are horizontally symmetrical structures, the subsequent embodiments are only described using the patterned structure 11 as an example, and those skilled in the art should be able to easily extend it to the patterned structure 12.

[0030] The patterned structure 11 includes an auxiliary positioning structure 21, a main positioning structure 22, and an offset detection structure 23. The auxiliary positioning structure 21 and the main positioning structure 22 are used to define the drilling position. In detail, the main positioning structure 22 serves as a target bull's eye to mark the drilling position. The auxiliary positioning structure 21 surrounds the main positioning structure 22, and the auxiliary positioning structure 21 and the main positioning structure 22 are arranged concentrically. Therefore, the auxiliary positioning structure 21 can be regarded as the boundary of the drilling position. In other words, the auxiliary positioning structure 21 can define the maximum offset of the drilling position.

[0031] The offset detection structure 23 is disposed on the auxiliary positioning structure 21 and is symmetrically disposed relative to the center of the main positioning structure 22 and the auxiliary positioning structure 21. In detail, the offset detection structure 23 includes an auxiliary line 231 and an auxiliary line 232 that are symmetrically disposed relative to the center position of the auxiliary positioning structure 21. The auxiliary line 231 and the auxiliary line 232 extend along the first direction (x-axis direction) and are parallel. In some embodiments, the line width of the auxiliary lines 231 and 232 is in the range of 0.075 to 0.085 mm. Preferably, the line width of the auxiliary lines 231 and 232 is 0.08 mm.

[0032] In some embodiments, the auxiliary positioning structure 21, the main positioning structure 22, and the offset detection structure 23 are made by etching. Due to the isotropic nature of etching, lateral etching will occur when etching the auxiliary positioning structure 21, the main positioning structure 22, and the offset detection structure 23. In some embodiments, the line spacing of the auxiliary lines 231 and 232 (i.e., the distance from the center of the line to the center of the line) is designed to be the sum of the diameter of the drilled hole, the line width of half of the auxiliary lines 231 and 232 (i.e., the line width of a single auxiliary line), and the side etching amount generated in the second direction (y-axis direction) when etching the auxiliary lines 231 and 232 minus the maximum offset allowed in the second direction (y-axis direction).

[0033] It should be noted that, in the present embodiment, the auxiliary positioning structure 21 and the main positioning structure 22 are concentric structures. In some embodiments, the aperture of the main positioning structure 22 is 3.15 mm. However, this is not a limitation of the present application. In other embodiments, the auxiliary positioning structure 21 and the main positioning structure 22 can be other shapes that are concentrically arranged.

[0034] FIG. 3A to FIG. 3E is a flow chart of manufacturing an integrated circuit substrate according to an embodiment of the present application. In some embodiments, FIG. 3A to FIG. 3E The process shown can be used to implement Figure 1 The integrated circuit substrate 1. It should be noted that FIG. 3A to FIG. 3E The illustrated process only depicts the portion of the integrated circuit substrate that is relevant to the spirit of the present invention.

[0035] exist Figure 3A In the embodiment, the conductive layer 31 is formed on the upper side of the substrate 30. In addition, the conductive layer 31' is formed under the substrate 30. In some embodiments, the substrate 30 is a BT board, and the conductive layers 31 and 31' include copper.

[0036] exist Figure 3B In the embodiment, the conductive layer 31 is etched to produce a patterned conductive layer 32. The patterned conductive layer 32 includes an auxiliary positioning structure 321, a main positioning structure 322, and a displacement detection structure 323, wherein the displacement detection structure 323 includes auxiliary lines 3231 and 3232. Similarly, the conductive layer 31' is etched to produce a patterned conductive layer 32'. The patterned conductive layer 32' includes an auxiliary positioning structure 321', a main positioning structure 322', and a displacement detection structure 323', wherein the displacement detection structure 323' includes auxiliary lines 3231' and 3232'. The auxiliary positioning structures 321 and 321', the main positioning structures 322 and 322', and the displacement detection structures 323 and 323' are connected to the conductive layer 31'. Figure 2 The corresponding components shown are the same and detailed description is omitted here.

[0037] exist Figure 3C In the embodiment, the insulating layer 33 is formed above the patterned conductive layer 32, and the insulating layer 33' is formed below the patterned conductive layer 32'. In some embodiments, the insulating layers 33 and 33' include resin.

[0038] exist Figure 3D In the embodiment of the present invention, conductive layer 34 is formed above insulating layer 33, and conductive layer 34' is formed below insulating layer 33'. In some embodiments, conductive layers 34 and 34' include copper.

[0039] exist Figure 3EIn the embodiment, the positions of the auxiliary positioning structure 321 , the main positioning structure 322 and the offset detection structure 323 are observed by irradiating X-rays, and a drilling operation is performed according to the target position represented by the main positioning structure 322 to form a through hole 35 .

[0040] Figure 4 FIG. 1 is a top view of the patterned conductive layer 32 after the drilling operation according to an embodiment of the present application. Figure 4 As shown, the auxiliary positioning structure 321 surrounds the through hole 35, and the offset detection structure 323 partially overlaps with the through hole 35. According to the overlap between the offset detection structure 323 and the through hole 35, it can be determined whether the through hole 35 is offset in the second direction (ie, the y-axis direction). Figure 4 The embodiment is an example for illustration, the through hole 35 cuts the edges of the auxiliary line 3231 and partially overlaps the auxiliary line 3232. Thus, it can be seen that the through hole 35 is offset downward.

[0041] Figure 5 FIG. 5 is a flow chart of a method 50 for manufacturing an integrated circuit substrate according to an embodiment of the present application. In some embodiments, the method 50 for manufacturing an integrated circuit substrate can be used to implement Figure 1 If substantially the same result can be obtained, the present application does not limit the invention to be completely in accordance with Figure 5 The integrated circuit substrate manufacturing method 50 can be summarized as follows:

[0042] Step 51: Form a first conductive layer on a substrate.

[0043] Step 52: Perform an etching process on the first conductive layer to generate a patterned conductive layer, wherein the patterned conductive layer includes an auxiliary positioning structure and an offset detection structure, wherein the auxiliary positioning structure is used to define a drilling position, and the offset detection structure is disposed on the auxiliary positioning structure and is symmetrically disposed relative to the center of the auxiliary positioning structure.

[0044] Step 53: Sequentially form an insulating layer and a second conductive layer on the patterned conductive layer.

[0045] Step 54: Drilling operations are performed on the center positions of the insulating layer and the second conductive layer corresponding to the auxiliary positioning structures to form through holes.

[0046] Step 55: Determine whether the through hole is offset according to the through hole and the offset detection structure.

[0047] Those skilled in the art should be able to easily understand the details of the integrated circuit substrate manufacturing method 50 after reading the above embodiments, and the detailed description is omitted here to save space.

Claims

1. An integrated circuit substrate, It is characterized in that include: An auxiliary positioning structure and a main positioning structure, wherein the main positioning structure serves as a target bull's eye to mark the drilling position, and the auxiliary positioning structure is arranged concentrically with the main positioning structure; and The offset detection structure is disposed on the auxiliary positioning structure and is symmetrically disposed relative to the center of the auxiliary positioning structure; wherein the auxiliary positioning structure and the offset detection structure are structures made by etching, and the offset detection structure comprises two auxiliary lines symmetrically arranged at the center of the auxiliary positioning structure, and the two auxiliary lines are two parallel lines extending in the first direction; The line spacing of the two auxiliary lines is the sum of the drilling diameter, half the line width of the two auxiliary lines, and the side etching amount generated in the second direction when etching the two auxiliary lines, minus the maximum offset allowed in the second direction, wherein the first direction is perpendicular to the second direction.

2. The integrated circuit substrate according to claim 1, It is characterized in that The line width of each auxiliary line is in the range of 0.075 to 0.085 mm.

3. The integrated circuit substrate according to claim 2, It is characterized in that The line width of each auxiliary line is 0.08mm.

4. An integrated circuit substrate, It is characterized in that include: substrate; The first conductive layer is formed on the substrate and includes: An auxiliary positioning structure and a main positioning structure, wherein the main positioning structure serves as a target bull's eye to mark the drilling position, and the auxiliary positioning structure is arranged concentrically with the main positioning structure; and The offset detection structure is disposed on the auxiliary positioning structure and is symmetrically disposed relative to the center of the auxiliary positioning structure; wherein the auxiliary positioning structure and the offset detection structure are structures made by etching, and the offset detection structure comprises two auxiliary lines symmetrically arranged at the center of the auxiliary positioning structure, and the two auxiliary lines are two parallel lines extending in the first direction; The line spacing of the two auxiliary lines is the sum of the diameter of the drill hole, half the line width of the two auxiliary lines, and the amount of undercut generated in the second direction when etching the two auxiliary lines, minus the maximum offset allowed in the second direction, wherein the first direction is perpendicular to the second direction; an insulating layer formed on the first conductive layer; A second conductive layer formed on the insulating layer; and A through hole passes through the substrate, the first conductive layer, the insulating layer and the second conductive layer.

5. The integrated circuit substrate according to claim 4, It is characterized in that The auxiliary positioning structure surrounds the through hole.

6. The integrated circuit substrate according to claim 4, It is characterized in that The offset detection structure partially overlaps with the through hole.

7. A method for manufacturing an integrated circuit substrate, It is characterized in that include: forming a first conductive layer on a substrate; Performing an etching process on the first conductive layer to generate a patterned conductive layer, wherein the patterned conductive layer includes an auxiliary positioning structure, a main positioning structure, and a deviation detection structure, wherein the main positioning structure serves as a target bull's eye to mark a drilling position, and the auxiliary positioning structure is concentrically arranged with the main positioning structure, and the deviation detection structure is arranged on the auxiliary positioning structure and symmetrically arranged relative to the center of the auxiliary positioning structure, wherein the auxiliary positioning structure and the deviation detection structure are structures made by etching, and the deviation detection structure includes two auxiliary lines symmetrically arranged with respect to the center of the auxiliary positioning structure, wherein the two auxiliary lines are two parallel lines extending in a first direction, wherein the line spacing of the two auxiliary lines is the sum of the drilling diameter, the line width of each half of the two auxiliary lines, and the amount of side etching generated in the second direction when etching the two auxiliary lines, minus the maximum deviation allowed in the second direction, wherein the first direction is perpendicular to the second direction; forming an insulating layer and a second conductive layer in sequence on the patterned conductive layer; Drilling the insulating layer and the second conductive layer at the center position corresponding to the auxiliary positioning structure to form a through hole; and Whether the through hole is offset is determined according to the through hole and the offset detection structure.

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