Three-dimensional semiconductor memory device

Abstract

A three-dimensional (3D) semiconductor memory device includes: first and second semiconductor layers spaced apart from each other horizontally; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure extending onto the buried insulating layer, the isolation structure being between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device in which memory cells are arranged in three dimensions. Background Technology

[0002] In the consumer electronics market, there is a continuous demand for highly integrated semiconductor devices with excellent performance and low cost. In terms of integration, semiconductor devices can be two-dimensional or three-dimensional. In the case of two-dimensional or planar semiconductor devices, their integration is largely determined by the area occupied by a single memory cell, and therefore is greatly affected by the level of fine patterning technology. However, the extremely expensive process equipment required to improve pattern fineness makes pursuing improved integration in two-dimensional or planar semiconductor devices impractical. Therefore, three-dimensional semiconductor memory devices, including three-dimensionally arranged memory cells, are being used to improve integration. Summary of the Invention

[0003] According to an exemplary embodiment of the inventive concept, a three-dimensional (3D) semiconductor memory device is provided, comprising: a first semiconductor layer and a second semiconductor layer horizontally spaced apart from each other; a buried insulating layer between the first semiconductor layer and the second semiconductor layer; a first cell array structure disposed on the first semiconductor layer and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first cell array structure and the second cell array structure, wherein the first cell array structure comprises: an electrode structure including electrodes stacked in a direction perpendicular to the top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure extending onto the buried insulating layer, and the isolation structure between the first source structure of the first cell array structure and the second source structure of the second cell array structure.

[0004] According to an exemplary embodiment of the inventive concept, a 3D semiconductor memory device is provided, comprising: a first semiconductor layer and a second semiconductor layer horizontally spaced apart from each other on a substrate; a first cell array structure and a second cell array structure respectively disposed on the first semiconductor layer and the second semiconductor layer; and an isolation structure disposed on the substrate between the first cell array structure and the second cell array structure, wherein the first cell array structure comprises: an electrode structure including electrodes stacked in a direction perpendicular to the top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure of the first cell array structure extending horizontally to the region of the substrate between the first semiconductor layer and the second semiconductor layer, and the first source structure of the first cell array structure and the second source structure of the second cell array structure being electrically separated from each other by the isolation structure.

[0005] According to an exemplary embodiment of the inventive concept, a 3D semiconductor memory device is provided, comprising: peripheral circuitry on a substrate; a lower insulating layer disposed on the substrate to cover the peripheral circuitry; a semiconductor layer on the lower insulating layer; a cell array structure on the semiconductor layer; and an isolation structure disposed on the lower insulating layer and on one side of the cell array structure, wherein the cell array structure includes: an electrode structure including electrodes stacked in a direction perpendicular to the top surface of the semiconductor layer; and a source structure disposed between the semiconductor layer and the electrode structure, the source structure extending from the semiconductor layer onto the lower insulating layer and contacting the side surface of the isolation structure.

[0006] According to an exemplary embodiment of the inventive concept, a 3D semiconductor memory device is provided, comprising: a first semiconductor layer and a second semiconductor layer separated from each other by a buried insulating layer; a first cell array structure disposed on the first semiconductor layer and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer and separating the first cell array structure and the second cell array structure from each other, wherein the first cell array structure comprises: a plurality of electrodes stacked in a direction perpendicular to the top surface of the first semiconductor layer; and a source structure disposed between the first semiconductor layer and the lowermost electrode of the electrodes, wherein the source structure overlaps with the buried insulating layer. Attached Figure Description

[0007] The above and other features of the inventive concept will be more clearly understood by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings.

[0008] Figure 1 This is a diagram showing a semiconductor substrate on which a three-dimensional semiconductor memory device, according to an exemplary embodiment of the inventive concept, is integrated.

[0009] Figure 2 This schematically illustrates a portion of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept (e.g. Figure 1 Enlarged plan view of part "A".

[0010] Figure 3 This is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0011] Figure 4 This is a plan view showing a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0012] Figure 5 It is along Figure 4 A sectional view taken by line I-I'.

[0013] Figure 6 It is shown Figure 5 A planar view of the source structure SC.

[0014] Figure 7 yes Figure 5 A magnified view of part "B".

[0015] Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 This is a cross-sectional view of an exemplary embodiment based on the inventive concept, which along... Figure 4 The line I-I' is cut off to illustrate a method for manufacturing three-dimensional semiconductor memory devices.

[0016] Figure 20 This schematically illustrates a portion of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept (e.g. Figure 1 Enlarged plan view of part "A".

[0017] Figure 21 This schematically illustrates a portion of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept (e.g. Figure 1 Enlarged plan view of part "A".

[0018] Figure 22 This illustrates an exemplary embodiment of a three-dimensional semiconductor memory device according to the inventive concept. Figure 4 A sectional view taken by line I-I'. Detailed Implementation

[0019] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings.

[0020] It should be noted that the accompanying drawings are not necessarily drawn to scale and therefore should not be construed as limiting or restricting the range of values ​​or characteristics included in the exemplary embodiments. For example, the relative thickness and location of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the drawings may indicate the presence of similar or identical elements or features.

[0021] Figure 1This is a diagram showing a semiconductor substrate on which a three-dimensional semiconductor memory device, according to an exemplary embodiment of the inventive concept, is integrated.

[0022] Reference Figure 1 The semiconductor substrate 1 (e.g., a wafer) may include chip regions 10 on which semiconductor chips are formed respectively, and dicing groove regions 20 located between the chip regions 10. The chip regions 10 may be arranged two-dimensionally in two different directions (e.g., a first direction D1 and a second direction D2). When viewed in a plan view, each chip region 10 may be surrounded by a dicing groove region 20. In other words, the dicing groove regions 20 may be interposed between chip regions 10 adjacent to each other in the first direction D1 and between chip regions 10 adjacent to each other in the second direction D2. The semiconductor substrate 1 may be a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, a germanium wafer, a germanium-on-insulator (GOI) wafer, a silicon-germanium wafer, or a wafer containing an epitaxial layer formed by a selective epitaxial growth (SEG) process. The semiconductor substrate 1 may be formed of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). Three-dimensional semiconductor memory devices, with memory cells arranged three-dimensionally therein, may be provided on each chip region 10 of the semiconductor substrate 1.

[0023] Figure 2 This schematically illustrates a portion of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept (e.g. Figure 1 Enlarged plan view of part "A".

[0024] Reference Figure 1 and Figure 2 Multiple cell array structures CS can be disposed on each chip region 10 of the semiconductor substrate 1. On each chip region 10, the cell array structures CS can be arranged in a first direction D1 and a second direction D2 and can be spaced apart from each other. Each cell array structure CS can include a cell array in which multiple memory cells are arranged in three dimensions. The cell array structures CS can be disposed on multiple semiconductor layers 100 respectively. On each chip region 10, the semiconductor layers 100 can be arranged in the first direction D1 and the second direction D2 and can be spaced apart from each other. Each cell array structure CS and a corresponding one of the semiconductor layers 100 can constitute a single memory array chip MAT. In this case, the memory array chip MAT can be a unit region of a three-dimensional semiconductor memory device, which can be erased independently. For example, the first MAT can be erased without performing an erase operation, while the second MAT can be erased.

[0025] A buried insulating layer 105 may be disposed on each chip region 10 and may be interposed between semiconductor layers 100. When viewed in plan view, each semiconductor layer 100 may be surrounded by the buried insulating layer 105. For example, semiconductor layers 100 may be surrounded by the buried insulating layer 105. The buried insulating layer 105 may be interposed between semiconductor layers 100 adjacent to each other in a first direction D1 and between semiconductor layers 100 adjacent to each other in a second direction D2. The cell array structure CS may each include a source structure SC. The source structure SC may extend horizontally on the semiconductor layers 100 (e.g., in the first direction D1 and the second direction D2) and intersect with the dicing region 20. Furthermore, the source structure SC may extend from a region on the semiconductor layers 100 to a region on the buried insulating layer 105 between the semiconductor layers 100.

[0026] Multiple isolation structures IS can be disposed on each chip region 10 of the semiconductor substrate 1. Viewed in plan view, the isolation structures IS can be disposed on the buried insulating layer 105 between semiconductor layers 100 and can be positioned around each cell array structure CS. In an exemplary embodiment of the inventive concept, the isolation structures IS disposed around each cell array structure CS can be spaced apart from each other. The first of the isolation structures IS can be disposed between a first pair of cell array structures CS adjacent to each other in the first direction D1, and in this case, the first isolation structure IS can have a linear shape extending in the second direction D2. The second isolation structure IS can be disposed between a second pair of cell array structures CS adjacent to each other in the second direction D2, and in this case, the second isolation structure IS can have a linear shape extending in the first direction D1.

[0027] The source structures SC of the unit array structure CS can be electrically disconnected from each other through the isolation structure IS. The source structure SC of each unit array structure CS can extend horizontally onto the buried insulating layer 105 and can contact a corresponding isolation structure in the isolation structure IS. Each isolation structure IS can be inserted between adjacent source structures in the source structures SC of the unit array structure CS, and can electrically disconnect the adjacent source structures in the source structures SC from each other. The first isolation structure IS can be inserted between the source structures SC of a first pair of unit array structures CS that are adjacent to each other in the first direction D1, and can electrically disconnect the source structures SC of the first pair of unit array structures CS from each other. The source structures SC of the first pair of unit array structures CS can extend horizontally onto the buried insulating layer 105 and can contact the first isolation structure IS. The second isolation structure IS can be inserted between the source structures SC of a second pair of unit array structures CS that are adjacent to each other in the second direction D2, so as to electrically disconnect the source structures SC of the second pair of unit array structures CS from each other. The source structure SC of the second pair of unit array structures CS can extend horizontally onto the buried insulating layer 105 and can make contact with the second one in the isolation structure IS.

[0028] Figure 3 This is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0029] Reference Figure 3 , Figure 2 Each cell array structure CS may include a common source line CSL, multiple bit lines BL0, BL1, and BL2, and multiple cell strings CSTRs disposed between the common source line CSL and the bit lines BL0-BL2. The multiple cell strings CSTRs may be connected in parallel to each of the bit lines BL0-BL2. The cell strings CSTRs may be commonly connected to the common source line CSL. Each cell string CSTR may include series-connected string select transistors SST1 and SST2, a memory cell transistor MCT, a ground select transistor GST, and an erase control transistor ECT. Each memory cell transistor MCT may include a data storage element. As an example, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series, the second string select transistor SST2 being connected to a corresponding bit line BL0, BL1, and BL2. In an exemplary embodiment of the inventive concept, each cell string CSTR may have a single string select transistor.

[0030] The memory cell transistors (MCTs) can be connected in series between the first string select transistor (SST1) and the ground select transistor (GST). The erase control transistor (ECT) for each cell string (CSTR) can be disposed between and connected to the ground select transistor (GST) and the common source line (CSL). In an exemplary embodiment of the inventive concept, each cell string (CSTR) may further include a dummy cell (DMC) connected between the first string select transistor (SST1) and the memory cell transistors (MCTs) and / or between the ground select transistor (GST) and the memory cell transistors (MCTs). The first string select transistor (SST1) can be controlled by a first string select line (SSL1) (e.g., SSL10, SSL11, or SSL12), and the second string select transistor (SST2) can be controlled by a second string select line (SSL2) (e.g., SSL20, SSL21, or SSL22). The memory cell transistors (MCTs) can be controlled by signals transmitted via multiple word lines WL0-WLn, and the dummy cell (DMC) can be controlled by signals transmitted via a dummy word line (DWL). Furthermore, the ground select transistor GST can be controlled by a signal transmitted via the ground select line GSL (e.g., GSL0, GSL1, or GSL2), and the erase control transistor ECT can be controlled by a signal transmitted via the erase control line ECL. The common source line CSL can be connected to the source of the erase control transistor ECT. The erase control transistors ECT of different cell strings in the cell string CSTR can be controlled jointly by a signal transmitted via the erase control line ECL. During an erase operation on the memory cell array, the erase control transistor ECT can generate gate-induced drain leakage (GIDL).

[0031] Figure 4 This is a plan view showing a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept. Figure 5 It is along Figure 4 A sectional view taken by line I-I'. Figure 6 It is shown Figure 5 A planar view of the source structure SC. Figure 7 yes Figure 5 A magnified view of part "B".

[0032] Reference Figure 4 and Figure 5The peripheral circuit structure PS can be disposed on the semiconductor substrate 1. The semiconductor substrate 1 can be a silicon wafer, a silicon-germanium wafer, a germanium wafer, or a single-crystal epitaxial layer grown on a single-crystal silicon wafer. The peripheral circuit structure PS can include peripheral circuits integrated on the semiconductor substrate 1 and a lower insulating layer 40 covering the peripheral circuits. The peripheral circuits can be row decoders and column decoders, page buffers, and control circuits for the control unit array, and can include n-type metal-oxide-semiconductor (NMOS) transistors and p-type metal-oxide-semiconductor (PMOS) transistors, low-voltage transistors and high-voltage transistors, and resistors integrated on the semiconductor substrate 1.

[0033] As an example, a device isolation layer 11 may be disposed in a semiconductor substrate 1 to define an active region ACT. Multiple peripheral transistors (PTRs) may be disposed on the active region ACT of the semiconductor substrate 1. Each peripheral transistor PTR may include: a peripheral gate electrode 21 on the semiconductor substrate 1; a peripheral gate insulating layer 23 between the semiconductor substrate 1 and the peripheral gate electrode 21; a peripheral gate overlay pattern 25 on the peripheral gate electrode 21; and peripheral gate spacers 27 on the side surface of the peripheral gate electrode 21. Each peripheral transistor PTR may also include peripheral source / drain regions 29 disposed in portions of the semiconductor substrate 1 located on either side of the peripheral gate electrode 21. Peripheral circuit interconnects 33 may be electrically connected to the peripheral source / drain regions 29 of the peripheral transistors PTRs via peripheral contact plugs 31. The peripheral transistors PTRs, peripheral circuit interconnects 33, and peripheral contact plugs 31 may constitute peripheral circuitry (e.g., row and column decoders, page buffers, control circuitry, etc.).

[0034] The lower insulating layer 40 may cover the peripheral transistor PTR, the peripheral circuit interconnects 33, and the peripheral contact plugs 31. The lower insulating layer 40 may include a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and / or a low-k dielectric layer.

[0035] Semiconductor layers 100 may be disposed on the lower insulating layer 40 and horizontally spaced apart from each other. The semiconductor layers 100 may be spaced apart from each other in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., the second direction D2), and the bottom surface of the semiconductor layers 100 may be in contact with the lower insulating layer 40. The semiconductor layers 100 may be formed of a semiconductor material and may include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). The semiconductor layers 100 may include doped semiconductor materials of a first conductivity type and / or undoped or intrinsic semiconductor materials, and may have a single-crystal, amorphous, or polycrystalline structure.

[0036] A buried insulating layer 105 may be disposed between the semiconductor layers 100 and on the lower insulating layer 40. The semiconductor layers 100 may be separated from each other by the buried insulating layer 105, and the bottom surface of the buried insulating layer 105 may be in contact with the lower insulating layer 40. The buried insulating layer 105 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and / or a low-k dielectric layer.

[0037] The cell array structure CS can be disposed on the semiconductor layer 100. Each cell array structure CS can include a source structure SC and an electrode structure ST stacked sequentially on each semiconductor layer 100. The source structure SC can be inserted between each semiconductor layer 100 and the electrode structure ST. The source structure SC and the electrode structure ST can be stacked sequentially on a third direction D3 perpendicular to the top surface 1U of the semiconductor substrate 1.

[0038] Each semiconductor layer 100 may include a cell array region CAR and a connection region CNR. An electrode structure ST may be disposed on the cell array region CAR of each semiconductor layer 100 and may extend from the cell array region CAR to the connection region CNR in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., a second direction D2). A source structure SC may be disposed below the electrode structure ST and may extend from the cell array region CAR to the connection region CNR in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., a second direction D2). The source structure SC may further extend onto the buried insulating layer 105 between the semiconductor layers 100.

[0039] The source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on each semiconductor layer 100. The first source conductive pattern SCP1 may be in direct contact with each semiconductor layer 100. In an exemplary embodiment of the inventive concept, an insulating layer may be provided between the first source conductive pattern SCP1 and each semiconductor layer 100. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 may include a doped semiconductor material of a second conductivity type. The impurity concentration of the first source conductive pattern SCP1 may be higher than the impurity concentration of the second source conductive pattern SCP2. In an exemplary embodiment of the inventive concept, the second source conductive pattern SCP2 may include a metallic material.

[0040] Reference Figure 5 and Figure 6A first source conductive pattern SCP1 may be locally provided on each semiconductor layer 100 and may have an opening OP formed to expose a portion of the semiconductor layer 100. A first portion of the first source conductive pattern SCP1 may be disposed on the cell array region CAR of each semiconductor layer 100, and a second portion of the first source conductive pattern SCP1 may be disposed on the connection region CNR of each semiconductor layer 100. The opening OP may be provided on the connection region CNR of each semiconductor layer 100 and between the first and second portions of the first source conductive pattern SCP1.

[0041] The second source conductive pattern SCP2 may cover the top surface of the first source conductive pattern SCP1 and may fill the opening OP in the first source conductive pattern SCP1. For example, a portion of the second source conductive pattern SCP2 may cover the inner surface of the opening OP in the first source conductive pattern SCP1 and may contact the first insulating layer 107 on each semiconductor layer 100. In an exemplary embodiment of the inventive concept, the first insulating layer 107 may be omitted, and in this case, said portion of the second source conductive pattern SCP2 may directly contact each semiconductor layer 100. The second source conductive pattern SCP2 may extend into the buried insulating layer 105 between the semiconductor layers 100 in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., the second direction D2). In an exemplary embodiment of the inventive concept, the second source conductive pattern SCP2 may include at least one protruding portion SCP2_P extending from each semiconductor layer 100 into the buried insulating layer 105. The first insulating layer 107 may be disposed on the buried insulating layer 105 and may be interposed between the second source conductive pattern SCP2 and the buried insulating layer 105. The second source conductive pattern SCP2 may have a recessed top surface RS, and a second insulating layer 109 may be disposed on the recessed top surface RS of the second source conductive pattern SCP2. The first insulating layer 107 and the second insulating layer 109 may include, for example, silicon oxide layers.

[0042] Return to reference Figure 4 and Figure 5The electrode structure ST may include a lower electrode structure LST, an upper electrode structure UST, and an insulating planarization layer 120 provided between the lower electrode structure LST and the upper electrode structure UST. The lower electrode structure LST may include lower gate electrodes EGE and GGE alternately stacked on the source structure SC in a third direction D3, and a lower insulating layer 110a. The upper electrode structure UST may include upper gate electrodes CGE and SGE alternately stacked on the insulating planarization layer 120 in a third direction D3, and an upper insulating layer 110b. The insulating planarization layer 120 may be interposed between the uppermost gate electrode GGE of the lower gate electrodes EGE and GGE and the lowermost gate electrode CGE of the upper gate electrodes CGE and SGE. Each of the lower insulating layer 110a, the upper insulating layer 110b, and the insulating planarization layer 120 may have a thickness in the third direction D3. The insulating planarization layer 120 may be thicker than the lower insulating layer 110a and the upper insulating layer 110b. The uppermost insulating layer 110b of the lower insulating layer 110a and the upper insulating layer 110b may be thicker than the remaining insulating layers in the lower insulating layer 110a and the upper insulating layer 110b. The lower gate electrodes EGE and GGE and the upper gate electrodes CGE and SGE may include doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitrides, tantalum nitrides, etc.) and / or transition metals (e.g., titanium, tantalum, etc.). The lower insulating layer 110a, the upper insulating layer 110b, and the insulating planarization layer 120 may include a silicon oxide layer and / or a low-k dielectric layer.

[0043] The lower gate electrodes EGE and GGE may include an erase control gate electrode EGE and a ground selection gate electrode GGE on the erase control gate electrode EGE. The erase control gate electrode EGE may be disposed adjacent to the source structure SC. The lowermost one of the lower insulating layers 110a may be interposed between the erase control gate electrode EGE and the source structure SC. The erase control gate electrode EGE may be the gate electrode of an erase control transistor ECT, which is used to control the... Figure 3 The erase operation of the memory cell array. The ground selection gate electrode GGE can be Figure 3 The gate electrode of the ground-select transistor GST. The upper gate electrodes CGE and SGE may include a unit gate electrode CGE and a series-select gate electrode SGE. The unit gate electrode CGE may be located between the ground-select gate electrode GGE and the series-select gate electrode SGE, and may be situated at different heights from the top surface 1U of the semiconductor substrate 1. The unit gate electrode CGE may be... Figure 3 The gate electrode of the memory cell transistor MCT. The string select gate electrode SGE can be... Figure 3The gate electrode of the string select transistor SST2. In an exemplary embodiment of the inventive concept, an additional string select gate electrode SGE may be provided between the uppermost of the cell gate electrodes CGE and the string select gate electrode SGE. In this case, the additional string select gate electrode SGE may be Figure 3 The gate electrode of the string selection transistor SST1. The lengths of the gate electrodes EGE, GGE, CGE, and SGE of the electrode structure ST (e.g., measured in the second direction D2) can decrease as the distance from each semiconductor layer 100 increases. The gate electrodes EGE, GGE, CGE, and SGE of the electrode structure ST may include electrode pads configured to form a stepped structure on the connection region CNR.

[0044] The insulating planarization layer 120 may cover the lower electrode structure LST and may extend onto the buried insulating layer 105 in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., the second direction D2). A first covering insulating layer 122 may be disposed on the connection region CNR of each semiconductor layer 100 to cover the electrode pads, which are configured to form a stepped structure. The first covering insulating layer 122 may extend onto the buried insulating layer 105 in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., the second direction D2) and may cover the insulating planarization layer 120. The first covering insulating layer 122 may include an insulating material (e.g., silicon oxide).

[0045] Each cell array structure CS may include multiple vertical structures VS, which are provided to penetrate the source structure SC and the electrode structure ST. The vertical structures VS may be disposed on the cell array region CAR of each semiconductor layer 100. Each vertical structure VS may extend in a third direction D3 to penetrate the electrode structure ST and the source structure SC. In an exemplary embodiment of the inventive concept, when viewed in a plan view, the vertical structures VS may be arranged to form a Z-shape in a second direction D2.

[0046] Reference Figure 5 and Figure 7Each vertical structure VS may include a vertical semiconductor pattern VSP. The vertical semiconductor pattern VSP may extend on the third direction D3 to penetrate the electrode structure ST and the source structure SC. The vertical semiconductor pattern VSP may extend into each semiconductor layer 100. The vertical semiconductor pattern VSP may have a bottom surface VSP_B located in each semiconductor layer 100. The vertical semiconductor pattern VSP may be shaped like a bottom-closed tube. The vertical semiconductor pattern VSP may include semiconductor materials such as silicon (Si), germanium (Ge), or compounds thereof. In an exemplary embodiment of the inventive concept, the vertical semiconductor pattern VSP may be formed of a doped semiconductor material or an undoped or intrinsic semiconductor material, or may include a doped semiconductor material or an undoped or intrinsic semiconductor material. The vertical semiconductor pattern VSP may be used as a reference. Figure 3 The channel of each of the erase control transistor ECT, string select transistors SST1, SST2, ground select transistor GST, and memory cell transistor MCT is described.

[0047] The lower side surface of the vertical semiconductor pattern VSP can contact the first source conductive pattern SCP1. The first source conductive pattern SCP1 may include a horizontal portion HP and a vertical portion SP. The horizontal portion HP is disposed below the second source conductive pattern SCP2 and extends substantially parallel to the top surface 1U of the semiconductor substrate 1. The vertical portion SP protrudes vertically from the horizontal portion HP. The vertical portion SP of the first source conductive pattern SCP1 can contact a portion of the side surface of the vertical semiconductor pattern VSP and can surround said portion of the side surface of the vertical semiconductor pattern VSP. The horizontal portion HP of the first source conductive pattern SCP1 can be interposed between the top surface 100U of each semiconductor layer 100 and the second source conductive pattern SCP2. The horizontal portion HP of the first source conductive pattern SCP1 can contact the top surface 100U of each semiconductor layer 100. The vertical portion SP of the first source conductive pattern SCP1 can extend into the region between the side surface of the vertical semiconductor pattern VSP and each semiconductor layer 100 and between the side surface of the vertical semiconductor pattern VSP and the second source conductive pattern SCP2. In other words, the first portion of the vertical portion SP of the first source conductive pattern SCP1 can be disposed between one side of the vertical semiconductor pattern VSP and one side of the semiconductor layer 100, and the second portion of the vertical portion SP of the first source conductive pattern SCP1 can be disposed between that side of the vertical semiconductor pattern VSP and one side of the second source conductive pattern SCP2.

[0048] Each vertical structure VS may include a data storage pattern DSP, which is interposed between a vertical semiconductor pattern VSP and an electrode structure ST. The data storage pattern DSP may extend in a third direction D3 and may surround the side surface of the vertical semiconductor pattern VSP. The data storage pattern DSP may have a tubular shape with its top and bottom open. The bottom surface DSP_B of the data storage pattern DSP may contact a first source conductive pattern SCP1. The data storage pattern DSP may include a data storage layer of a NAND flash memory device. For example, the data storage pattern DSP may include a charge storage layer 320 between the vertical semiconductor pattern VSP and the electrode structure ST, a barrier insulating layer 310 between the electrode structure ST and the charge storage layer 320, and a tunnel insulating layer 330 between the vertical semiconductor pattern VSP and the charge storage layer 320. The charge storage layer 320 may include a silicon nitride layer, a silicon oxide nitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a stacked trap layer. The barrier insulating layer 310 may include a material whose band gap is larger than that of the charge storage layer 320. The barrier insulating layer 310 may include a high-k dielectric material, such as aluminum oxide and hafnium oxide. The tunnel insulating layer 330 may include a material whose band gap is larger than that of the charge storage layer 320. The tunnel insulating layer 330 may include, for example, a silicon oxide layer.

[0049] Each vertical structure VS may include a residual data storage pattern DSPr, which is interposed between the vertical semiconductor pattern VSP and each semiconductor layer 100. The residual data storage pattern DSPr may be provided in each semiconductor layer 100, and the vertical semiconductor pattern VSP may be spaced apart from each semiconductor layer 100 by the residual data storage pattern DSPr. The vertical semiconductor pattern VSP may be electrically isolated from each semiconductor layer 100 by the residual data storage pattern DSPr. The residual data storage pattern DSPr may be interposed between the bottom surface VSP_B of the vertical semiconductor pattern VSP and each semiconductor layer 100, and may extend to the side surface of the vertical semiconductor pattern VSP. The residual data storage pattern DSPr may have a U-shape. The data storage pattern DSP may be vertically spaced apart from the residual data storage pattern DSPr. For example, the data storage pattern DSP may be spaced apart from the residual data storage pattern DSPr by a vertical portion SP of the first source conductive pattern SCP1.

[0050] The uppermost surface DPSr_U of the remaining data storage pattern DSPr can be located at a height lower than the top surface 100U of each semiconductor layer 100. The remaining data storage pattern DSPr can be perpendicularly spaced from the data storage pattern DSP, such that the vertical portion SP of the first source conductive pattern SCP1 is interposed between them. The uppermost surface DPSr_U of the remaining data storage pattern DSPr can contact the vertical portion SP of the first source conductive pattern SCP1. The remaining data storage pattern DSPr can have a layer structure substantially the same as that of the data storage pattern DSP. For example, the remaining data storage pattern DSPr may include a remaining charge storage layer 320r between the vertical semiconductor pattern VSP and each semiconductor layer 100, a remaining barrier insulating layer 310r between each semiconductor layer 100 and the remaining charge storage layer 320r, and a remaining tunnel insulating layer 330r between the vertical semiconductor pattern VSP and the remaining charge storage layer 320r. Each of the remaining charge storage layer 320r, the remaining barrier insulation layer 310r, and the remaining tunnel insulation layer 330r may include the same material as the corresponding one of the charge storage layer 320, barrier insulation layer 310, and tunnel insulation layer 330.

[0051] Each vertical structure VS may include an insulating pattern 150 filling the internal space of a vertical semiconductor pattern VSP. The insulating pattern 150 may include, for example, silicon oxide. Each vertical structure VS may include a conductive pad 160 disposed on the vertical semiconductor pattern VSP. The conductive pad 160 may cover the top surface of the insulating pattern 150 and the uppermost surface of the vertical semiconductor pattern VSP. The conductive pad 160 may include doped semiconductor material and / or conductive material. A data storage pattern DSP may extend from the side surface of the vertical semiconductor pattern VSP to the side surface of the conductive pad 160. The data storage pattern DSP may surround the side surface of the conductive pad 160, and the uppermost surface of the data storage pattern DSP may be substantially coplanar with the top surface of the conductive pad 160.

[0052] Return to reference Figure 4 and Figure 5Each cell array structure CS may include multiple electrode isolation structures GIS that penetrate the source structure SC and the electrode structure ST. The electrode isolation structures GIS may be disposed on the cell array region CAR of each semiconductor layer 100 and may extend to the connection region CNR of each semiconductor layer 100. The electrode isolation structures GIS may have a linear shape extending in a second direction D2 and may be spaced apart from each other in a first direction D1. Each electrode isolation structure GIS may extend in a third direction D3 to penetrate the electrode structure ST and the source structure SC, and may be coupled to a corresponding one in the semiconductor layer 100. In an exemplary embodiment of the inventive concept, each electrode isolation structure GIS may include a common source plug CSP extending in the third direction D3 and insulating spacers SSP along the side surface of the common source plug CSP or along the side surface extending in the third direction D3. The common source plug CSP may penetrate the electrode structure ST and the source structure SC and may be coupled to each semiconductor layer 100. The side-surface insulating spacer SSP can be inserted between the electrode structure ST and the common source plug CSP, and can extend into the region between the source structure SC and the common source plug CSP. The common source plug CSP may include a conductive material, and the side-surface insulating spacer SSP may include, for example, a silicon nitride.

[0053] An isolation structure IS can be disposed on a buried insulating layer 105 between semiconductor layers 100. The isolation structure IS can be linear, extending in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., a first direction D1). The isolation structure IS can extend in a third direction D3 between cell array structures CS and can penetrate the first covering insulating layer 122, the insulating planarization layer 120, and the second insulating layer 109. The isolation structure IS can be interposed between the source structures SC of the cell array structures CS. The source structures SC of the cell array structures CS can contact the side surface IS_S of the isolation structure IS and can be electrically isolated from each other through the isolation structure IS. For example, the isolation structure IS can be interposed between the second source conductive patterns SCP2 of the cell array structures CS. The second source conductive patterns SCP2 of the cell array structures CS can contact the side surface IS_S of the isolation structure IS and can be electrically isolated from each other through the isolation structure IS. The isolation structure IS can penetrate the first insulating layer 107 and can contact the buried insulating layer 105. The bottom surface IS_B of the isolation structure IS can contact the buried insulating layer 105. The top surface IS_U of the isolation structure IS can be positioned at substantially the same height as the top surface GIS_U of the electrode isolation structure GIS. In this specification, height can refer to the distance from the top surface 1U of the semiconductor substrate 1.

[0054] The isolation structure IS may include the same material as the electrode isolation structure GIS. In an exemplary embodiment of the inventive concept, the isolation structure IS may include a conductive pattern 200 extending in the third direction D3 and an insulating spacer 210 extending along the side surface of the conductive pattern 200 or in the third direction D3. The conductive pattern 200 may penetrate the first covering insulating layer 122, the insulating planarization layer 120, and the second insulating layer 109, and may be interposed between the source structures SC of the cell array structure CS. The conductive pattern 200 may penetrate the first insulating layer 107 and may contact the buried insulating layer 105. The insulating spacer 210 may be interposed between the first covering insulating layer 122 and the conductive pattern 200, between the insulating planarization layer 120 and the conductive pattern 200, and between the second insulating layer 109 and the conductive pattern 200, and may extend into the region between each source structure SC of the cell array structure CS and the conductive pattern 200. The insulating spacer 210 may extend into the region between the first insulating layer 107 and the conductive pattern 200 and may contact the buried insulating layer 105. The conductive pattern 200 may include the same material as the common source plug CSP, and the insulating spacer 210 may include the same material as the side surface insulating spacer SSP.

[0055] The second cover insulating layer 170 may be configured to cover the top surface of the electrode structure ST and the top surface of the first cover insulating layer 122. The isolation structure IS and each electrode isolation structure GIS may penetrate the second cover insulating layer 170, and the top surface of the second cover insulating layer 170 may be located at substantially the same height as the top surface IS_U of the isolation structure IS and the top surface GIS_U of the electrode isolation structure GIS. An interlayer insulating layer 180 may be provided on the second cover insulating layer 170 to cover the top surface IS_U of the isolation structure IS and the top surface GIS_U of the electrode isolation structure GIS. The second cover insulating layer 170 and the interlayer insulating layer 180 may be formed of, or comprise, an insulating material (e.g., silicon oxide).

[0056] Contact plugs 185 may be provided to penetrate the second overlay insulating layer 170 and the interlayer insulating layer 180, and may be connected to conductive pads 160. Contact plugs 185 may be formed of or comprise conductive material. Bit lines BL may be provided on the interlayer insulating layer 180 to extend in a first direction D1 and may be spaced apart from each other in a second direction D2. At least one of the vertical structures VS may be a dummy vertical structure that is not connected to contact plugs 185. In addition to the dummy vertical structures, the vertical semiconductor pattern VSP of each vertical structure VS may be electrically connected to a corresponding one of the bit lines BL via contact plugs 185. Bit lines BL may comprise conductive material. The top surface IS_U of the isolation structure IS may be located at a height higher than the top surface VS_U of the vertical structure VS (e.g., the top surface of conductive pad 160) and may be located at a height lower than the bottom surface BL_L of the bit line BL. Conductive contacts and conductive lines (not shown) may be connected to the electrode pads of the gate electrodes EGE, GGE, CGE, and SGE. Figure 3 During the erase operation of the memory cell array, when an erase voltage is applied to the source structure SC, Figure 3 Gate-induced leakage current can occur in the erase control transistor (ECT). Therefore, it is possible to... Figure 3 The storage unit effectively performs the erase operation.

[0057] Figures 8 to 19 This is a cross-sectional view of an exemplary embodiment based on the inventive concept, which along... Figure 4 Line I-I' is cut off to illustrate a method for fabricating three-dimensional semiconductor memory devices. For convenience, the previous reference is... Figures 4 to 7 The elements described may be identified by the same reference numerals without repeating their descriptions.

[0058] Reference Figure 4 and Figure 8 A semiconductor substrate 1 can be fabricated. The semiconductor substrate 1 may include a chip region 10 and a dicing region 20, as shown in reference... Figure 1 The peripheral circuit structure PS can be formed on each chip region 10 of the semiconductor substrate 1. The peripheral circuit structure PS can include peripheral circuits integrated on the semiconductor substrate 1 and a lower insulating layer 40 covering the peripheral circuits. The peripheral circuits can include peripheral transistors PTR, peripheral circuit interconnects 33, and peripheral contact plugs 31. In this case, the peripheral circuit interconnects 33 and peripheral contact plugs 31 can be connected to the peripheral transistors PTR.

[0059] First, a device isolation layer 11 can be formed in the semiconductor substrate 1 to define the active region ACT. In an exemplary embodiment of the inventive concept, the formation of the peripheral transistor PTR may include: forming a peripheral gate insulating layer 23, a peripheral gate electrode 21, and a peripheral gate cover pattern 25 stacked sequentially on the active region ACT of the semiconductor substrate 1; forming peripheral gate spacers 27 on both side surfaces of the peripheral gate electrode 21; and implanting impurities into portions of the semiconductor substrate 1 on both sides of the peripheral gate electrode 21 to form peripheral source / drain regions 29. A peripheral contact plug 31 may be electrically connected to the peripheral source / drain regions 29 of the peripheral transistor PTR, and a peripheral circuit interconnect 33 may be connected to the peripheral contact plug 31. A lower insulating layer 40 may be formed on the semiconductor substrate 1 to cover the peripheral transistor PTR, the peripheral circuit interconnect 33, and the peripheral contact plug 31. The lower insulating layer 40 may have a planarized or flat top surface 40U and may be patterned to expose Figure 1 The top surface of the edge of the semiconductor substrate 1.

[0060] Semiconductor layers 100 can be formed on chip regions 10 of the semiconductor substrate 1. The semiconductor layers 100 can be formed on the lower insulating layer 40 and horizontally spaced apart from each other. The semiconductor layers 100 can be in a direction parallel to the top surface 1U of the semiconductor substrate 1 (e.g., ...). Figure 2 The semiconductor layers 100 are spaced apart from each other in the first direction D1 and the second direction D2, and the bottom surface of the semiconductor layer 100 can contact the lower insulating layer 40. For example, the bottom surface of the semiconductor layer 100 can directly contact the lower insulating layer 40. The formation of the semiconductor layer 100 can include depositing a semiconductor layer on the lower insulating layer 40 and patterning the semiconductor layer. As a result of patterning the semiconductor layer, the semiconductor layer 100 can be partially formed on the top surface 40U of the lower insulating layer 40, and the top surface 40U of the lower insulating layer 40 can be partially exposed through the gap regions between the semiconductor layers 100.

[0061] A buried insulating layer 105 may be formed on the lower insulating layer 40 and between the semiconductor layers 100. The buried insulating layer 105 may fill the gap regions between the semiconductor layers 100 and cover the exposed top surface 40U of the lower insulating layer 40. The buried insulating layer 105 may have a planarized top surface (e.g., the top surface of the buried insulating layer 105 may be flush with the top surface of the semiconductor layers 100) and may be patterned to expose Figure 1 The top surface of the edge of the semiconductor substrate 1 shown.

[0062] Reference Figure 4 and Figure 9 A first insulating layer 107 can be formed to cover the top surface of the semiconductor layer 100 and the top surface of the buried insulating layer 105. The first insulating layer 107 can be patterned to expose... Figure 1The top surface of the edge of the semiconductor substrate 1 shown. A lower sacrificial pattern LSP can be formed on the first insulating layer 107. The lower sacrificial pattern LSP can be partially formed on the semiconductor layer 100. The formation of the lower sacrificial pattern LSP may include: forming a lower sacrificial layer on the first insulating layer 107; forming a mask pattern on the lower sacrificial layer; and using the mask pattern as an etching mask to etch the lower sacrificial layer to expose the first insulating layer 107. As a result of this etching process, the lower sacrificial pattern LSP can be formed with openings OP that expose the first insulating layer 107. Some of the openings OP can be formed on the semiconductor layer 100 and can be perpendicularly overlapped with the semiconductor layer 100, and other openings in the openings OP can be formed on the buried insulating layer 105 and can be perpendicularly overlapped with the buried insulating layer 105. For example, some of the openings OP can overlap with the semiconductor layer 100, while other openings OP overlap with the buried insulating layer 105. The lower sacrificial pattern LSP can be formed of or include a material that has etch selectivity relative to the first insulating layer 107. As an example, a lower sacrificial patterned LSP may include a silicon nitride layer, a silicon oxide nitride layer, a silicon carbide layer, or a silicon germanium layer.

[0063] The buffer insulating layer 108 can be formed to cover the lower sacrificial pattern LSP. The buffer insulating layer 108 can cover the top surface of the lower sacrificial pattern LSP and the side surfaces of the lower sacrificial pattern LSP exposed by the opening OP with a uniform thickness. In an exemplary embodiment of the inventive concept, the buffer insulating layer 108 can extend onto the first insulating layer 107 exposed by the opening OP. In this case, the buffer insulating layer 108 can be patterned to expose... Figure 1 The top surface of the edge of the semiconductor substrate 1 shown. The buffer insulating layer 108 may include, for example, a silicon oxide layer.

[0064] Reference Figure 4 , Figure 10A and Figure 10B The source conductive layer SCL can be formed to cover the top surface of the lower sacrificial pattern LSP and the inner surface of the opening OP with a uniform thickness. Because the source conductive layer SCL covers the top surface of the lower sacrificial pattern LSP and the inner surface of the opening OP with a uniform thickness, the source conductive layer SCL can have a top surface RS recessed towards the opening OP. In other words, the recessed top surface RS can overlap with the opening OP. The source conductive layer SCL can be formed to cover... Figure 1 The entire top surface of the semiconductor substrate 1. The source conductive layer SCL can be a single layer covering the semiconductor layer 100 and the buried insulating layer 105. The source conductive layer SCL can cover the entire top surface of the semiconductor substrate 100 and the buried insulating layer 105. Figure 1 The edge 1ED of the semiconductor substrate 1 (e.g. Figure 10B(As shown) Adjacent buried insulating layers 105 and first insulating layers 107 may cover the top surface of the edge 1ED of the semiconductor substrate 1. At the edge 1ED of the semiconductor substrate 1, the source conductive layer SCL may be in direct contact with the semiconductor substrate 1. Furthermore, at the edge 1ED, the semiconductor substrate 1 not covered by the source conductive layer SCL may be exposed. The source conductive layer SCL may include a doped semiconductor material or a metal material. The second insulating layer 109 may be formed to cover the recessed top surface RS of the source conductive layer SCL. In other words, the second insulating layer 109 may be disposed in the recessed top surface RS of the source conductive layer SCL. The formation of the second insulating layer 109 may include forming the second insulating layer 109 on the source conductive layer SCL and planarizing the second insulating layer 109 to expose the source conductive layer SCL. The second insulating layer 109 may cover the source conductive layer SCL adjacent to the edge 1ED of the semiconductor substrate 1.

[0065] Reference Figure 4 and Figure 11 A pattern structure MS can be formed on the source conductive layer SCL. The pattern structure MS can be formed on the semiconductor layer 100. The formation of the pattern structure MS may include: alternately stacking a lower insulating layer 110a and a lower sacrificial layer LSL on the source conductive layer SCL; forming an insulating planarization layer 120 on the uppermost layer of the lower sacrificial layer LSL; and alternately stacking an upper insulating layer 110b and an upper sacrificial layer USL on the insulating planarization layer 120. The lower sacrificial layer LSL may include a material with etch selectivity relative to the lower insulating layer 110a, and the insulating planarization layer 120 may be formed to be thicker than the lower insulating layer 110a. The upper sacrificial layer USL may include a material with etch selectivity relative to the upper insulating layer 110b. In an exemplary embodiment of the inventive concept, the upper sacrificial layer USL may include the same material as the lower sacrificial layer LSL and the lower sacrificial pattern LSP. As an example, the upper sacrificial layer USL and the lower sacrificial layer LSL may include silicon nitride layers, and the upper insulating layer 110b and the lower insulating layer 110a may include silicon oxide layers.

[0066] Each semiconductor layer 100 may include a cell array region (CAR) and a connection region (CNR). Each module structure (MS) may extend from the cell array region (CAR) of each semiconductor layer 100 to the connection region (CNR) and may have a stepped end on the connection region (CNR). The lower insulating layer 110a, the lower sacrificial layer (LSL), the upper sacrificial layer (USL), and the upper insulating layer 110b may be patterned such that each module structure (MS) has a stepped end on the connection region (CNR). An insulating planarization layer 120 may cover the patterned lower insulating layer 110a and the lower sacrificial layer (LSL) and may extend onto the buried insulating layer 105 between the semiconductor layers 100. The buried insulating layer 105 may be disposed between the stepped ends of adjacent module structures (MS). A first overlay insulating layer 122 may be formed to cover the stepped ends of the module structures (MS). The first overlay insulating layer 122 may extend onto the buried insulating layer 105 between the semiconductor layers 100 to cover the insulating planarization layer 120.

[0067] Reference Figure 4 and Figure 12 Multiple vertical vias VH can be formed in each module MS. The vertical vias VH can be formed on the cell array region CAR of each semiconductor layer 100. In an exemplary embodiment of the inventive concept, the vertical vias VH can be arranged in a zigzag pattern in the second direction D2. Each vertical via VH can penetrate the module MS, the source conductive layer SCL, the buffer insulating layer 108, the lower sacrificial pattern LSP, and the first insulating layer 107, and expose a corresponding one of the semiconductor layers 100.

[0068] The formation of the vertical via VH may include performing an anisotropic etching process to etch the mold structure MS, the source conductive layer SCL, the buffer insulating layer 108, the lower sacrificial pattern LSP, and the first insulating layer 107. In an exemplary embodiment of the inventive concept, the anisotropic etching process may be a plasma etching process, a reactive ion etching (RIE) process, an inductively coupled plasma reactive ion etching (ICP-RIE) process, or an ion beam etching (IBE) process. In anisotropic etching processes, positive charges (such as ions and / or free radicals) can be generated by plasma. When positive charges accumulate in the semiconductor layer 100, an arc discharge occurs in the semiconductor layer 100.

[0069] According to an exemplary embodiment of the inventive concept, the source conductive layer SCL can be a single layer covering the semiconductor layer 100 and the buried insulating layer 105, and can be in direct contact with the semiconductor substrate 1 at the edge 1ED of the semiconductor layer 1, such as... Figure 10BAs shown. During the anisotropic etching process used to form the vertical hole VH, a ground voltage can be applied to the semiconductor substrate 1. Therefore, the positive charge generated during the anisotropic etching process can be released to the semiconductor substrate 1 through the source conductive layer SCL. Thus, it is possible to prevent the accumulation of positive charge generated during the anisotropic etching process in the semiconductor layer 100 and to prevent arc discharge in the semiconductor layer 100.

[0070] Reference Figure 4 and Figure 13 A data storage layer DSL, a vertical semiconductor pattern VSP, an insulating pattern 150, and a conductive pad 160 can be formed in each vertical hole VH. The data storage layer DSL can fill a portion of each vertical hole VH and cover the inner surface of each vertical hole VH with a uniform thickness. The vertical semiconductor pattern VSP can fill a portion of each vertical hole VH and cover the inner surface of each vertical hole VH with a uniform thickness. The data storage layer DSL can be interposed between the inner surface of each vertical hole VH and the vertical semiconductor pattern VSP. The insulating pattern 150 can fill a portion of each vertical hole VH or the internal space of the vertical semiconductor pattern VSP. The vertical semiconductor pattern VSP can be interposed between the data storage layer DSL and the insulating pattern 150. The conductive pad 160 can fill the remaining empty portion of each vertical hole VH. The conductive pad 160 can cover the top surface of the insulating pattern 150 and the uppermost surface of the vertical semiconductor pattern VSP. The data storage layer DSL can be interposed between the inner surface of each vertical hole VH and the conductive pad 160. A second cover insulating layer 170 may be formed on the mold structure MS to cover the top surface of the conductive pad 160. The second cover insulating layer 170 may extend from the semiconductor layer 100 to the buried insulating layer 105 to cover the top surface of the first cover insulating layer 122.

[0071] Reference Figure 4 and Figure 14 A first trench T1 can be formed to penetrate the second overlay insulating layer 170 and each mold structure MS, thereby exposing the source conductive layer SCL. The first trench T1 can extend in the second direction D2 and can be spaced apart from each other in the first direction D1. The first trench T1 can correspond to Figure 4 The electrode isolation structure GIS is shown. A first trench T1 can be formed on the cell array region CAR of each semiconductor layer 100 and can extend to the connection region CNR of each semiconductor layer 100. A second trench T2 can be formed to penetrate the second cover insulating layer 170, the first cover insulating layer 122, the insulating planarization layer 120, and the second insulating layer 109 and expose the source conductive layer SCL. The second trench T2 can overlap with the buried insulating layer 105 between the semiconductor layers 100 and can have a linear shape extending in the first direction D1, such as... Figure 4The isolation structure IS is shown in the diagram. The first trench T1 and the second trench T2 can be formed simultaneously. As an example, the first trench T1 and the second trench T2 can be formed simultaneously using a single anisotropic etching process.

[0072] Sacrificial spacer 172 may be formed on the inner surface of each of the first trench T1 and the second trench T2. Sacrificial spacer 172 may fill a portion of each of the first trench T1 and the second trench T2 and cover the inner surface of each of the first trench T1 and the second trench T2 with a uniform thickness. Sacrificial spacer 172 may include a material having etch selectivity relative to the mold structure MS. As an example, sacrificial spacer 172 may include a polysilicon layer. Forming sacrificial spacer 172 may include: forming a sacrificial spacer layer to cover the inner surface of each of the first trench T1 and the second trench T2 with a uniform thickness; and then anisotropically etching the sacrificial spacer layer.

[0073] Reference Figure 4 and Figure 15 The portions of the source conductive layer SCL exposed by each first trench T1 and the portions of the buffer insulating layer 108 exposed by each first trench T1 can be etched. Therefore, a first through-hole H1 can be formed to expose the lower sacrificial pattern LSP in each first trench T1. The portions of the source conductive layer SCL exposed by the second trench T2 and the portions of the first insulating layer 107 exposed by the second trench T2 can be etched. Therefore, a second through-hole H2 can be formed to expose the buried insulating layer 105 in the second trench T2. The first through-hole H1 and the second through-hole H2 can be formed simultaneously. As an example, the first through-hole H1 and the second through-hole H2 can be formed simultaneously by a single anisotropic etching process. Thereafter, an isotropic etching process can be performed to remove the lower sacrificial pattern LSP exposed by the first through-hole H1. Due to the removal of the lower sacrificial pattern LSP, a horizontal recessed region HR can be formed. The horizontal recessed region HR can expose a portion of the side surface of the data storage layer DSL.

[0074] Reference Figure 4 and Figure 16The portion of the data storage layer DSL exposed by the horizontal recessed region HR can be removed, thus exposing a portion of the side surface of the vertical semiconductor pattern VSP. Since this portion of the data storage layer DSL is removed, the data storage layer DSL can be divided into data storage patterns DSP and remaining data storage patterns DSPr that are perpendicularly spaced apart from each other. In other words, the data storage patterns DSP and the remaining data storage patterns DSPr can be separated from each other. The remaining data storage patterns DSPr can be formed in a corresponding semiconductor layer in semiconductor layer 100. Removing the portion of the data storage layer DSL may include removing a portion of the first insulating layer 107 and at least a portion of the buffer insulating layer 108. For example, the buffer insulating layer 108 can be completely removed. Therefore, the bottom surface of the source conductive layer SCL and the top surface of each semiconductor layer 100 can be exposed through the horizontal recessed region HR. An undercut region UC can be formed by partially removing the data storage patterns DSP. The undercut region UC can be an empty region extending vertically from the horizontal recessed region HR. The undercut region UC can extend into the region between the side surface of the vertical semiconductor pattern VSP and the source conductive layer SCL, and between the side surface of the vertical semiconductor pattern VSP and the corresponding semiconductor layer 100. The bottom surface of the data storage pattern DSP and the top surface of the remaining data storage pattern DSPr can be disposed in the undercut region UC.

[0075] Reference Figure 4 and Figure 17 A sidewall conductive layer 174 can be formed to fill the undercut region UC and the horizontal recessed region HR, and to fill a portion of each of the first through-hole H1 and the second through-hole H2. The sidewall conductive layer 174 may include a doped semiconductor material. The sidewall conductive layer 174 may cover the inner surface of each of the first through-hole H1 and the second through-hole H2 with a uniform thickness, and may not fill all of each of the first through-hole H1 and the second through-hole H2. The sidewall conductive layer 174 may be in direct contact with the side surface of the vertical semiconductor pattern VSP, the bottom surface of the source conductive layer SCL, and the top surface of the semiconductor layer 100.

[0076] Reference Figure 4 and Figure 18An isotropic etching process can be performed on the sidewall conductive layer 174 to form a first source conductive pattern SCP1 in the undercut region UC and the horizontal recessed region HR. During the isotropic etching process on the sidewall conductive layer 174, sacrificial spacers 172 in each of the first through-hole H1 and the second through-hole H2 can be etched to form a gate isolation region GIR on each semiconductor layer 100 and an isolation region IR on the buried insulating layer 105 between the semiconductor layers 100. The gate isolation region GIR can expose the upper surface of the semiconductor layer 100, and the isolation region IR can expose the upper surface of the buried insulating layer 105. During the isotropic etching process on the sidewall conductive layer 174, the source conductive layer SCL can be etched to form a second source conductive pattern SCP2. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 can constitute a source structure SC.

[0077] Each gate isolation region (GIR) can penetrate the corresponding mode structure in the mode structure MS and the source structure SC located below the corresponding mode structure MS, and can expose the top surface of the corresponding semiconductor layer in the semiconductor layer 100. The isolation region (IR) can penetrate the second cover insulating layer 170, the first cover insulating layer 122, the insulating planarization layer 120, the second insulating layer 109, the second source conductive pattern SCP2, and the first insulating layer 107, and can expose the top surface of the buried insulating layer 105 between the semiconductor layers 100. The gate isolation region (GIR) and the isolation region (IR) can be formed simultaneously. As an example, the gate isolation region (GIR) and the isolation region (IR) can be formed simultaneously by a single etching process (e.g., an isotropic etching process for the sidewall conductive layer 174).

[0078] Reference Figure 4 and Figure 19 The lower sacrificial layer LSL and upper sacrificial layer USL exposed by the gate isolation region GIR can be removed. Therefore, a gate region can be formed between the lower insulating layer 110a and the upper insulating layer 110b. Forming the gate region may include performing an isotropic etching process to selectively etch the lower sacrificial layer LSL and the upper sacrificial layer USL. Subsequently, gate electrodes EGE, GGE, CGE, and SGE can be formed to fill the gate region.

[0079] Return to reference Figure 4 and Figure 5Side surface insulating spacers SSP can be formed in the gate isolation region GIR, and insulating spacers 210 can be formed in the isolation region IR. The formation of the side surface insulating spacers SSP and insulating spacers 210 may include forming an insulating spacer layer to fill a portion of each of the gate isolation region GIR and the isolation region IR, and anisotropically etching the insulating spacer layer. Due to the anisotropic etching process, the side surface insulating spacers SSP can be locally formed in the gate isolation region GIR, and the insulating spacers 210 can be locally formed in the isolation region IR. Common source plugs CSP can be formed in the gate isolation region GIR, and conductive patterns 200 can be formed in the isolation region IR. The formation of the common source plugs CSP and conductive patterns 200 may include forming a conductive layer to fill the remaining empty regions of each of the gate isolation region GIR and the isolation region IR, and planarizing the conductive layer to expose the second overlay insulating layer 170. Due to this planarization process, the common source plug CSP can be locally formed in the gate isolation region GIR, and the conductive pattern 200 can be locally formed in the isolation region IR. Each common source plug CSP and each side surface insulating spacer SSP can constitute an electrode isolation structure GIS, and the conductive pattern 200 and the insulating spacer 210 can constitute an isolation structure IS.

[0080] An interlayer insulating layer 180 can be formed on the second cover insulating layer 170 to cover the top surface IS_U of the isolation structure IS and the top surface GIS_U of the electrode isolation structure GIS. A contact plug 185 can be formed to penetrate the second cover insulating layer 170 and the interlayer insulating layer 180 and can be connected to the conductive pad 160. A bit line BL can be formed on the interlayer insulating layer 180, and the contact plug 185 can be connected to the corresponding bit line in the bit line BL. Furthermore, conductive contacts and conductive lines (not shown) can be formed to connect to the electrode pads of the gate electrodes EGE, GGE, CGE, and SGE.

[0081] Figure 20 This schematically illustrates a portion of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept (e.g. Figure 1 A magnified plan view of part "A". For convenience, the following description will primarily refer to the reference. Figures 1 to 7 The characteristics described are different.

[0082] Reference Figure 1 and Figure 20An isolation structure IS can be disposed on each chip region 10 of the semiconductor substrate 1. The isolation structure IS can be disposed on the buried insulating layer 105 between the semiconductor layers 100. In this embodiment, the isolation structure IS can be interposed between first pairs of cell array structures CS adjacent to each other in the first direction D1, and can extend to the region between second pairs of cell array structures CS adjacent to each other in the first direction D1. Furthermore, the isolation structure IS is also disposed between third pairs of cell array structures CS adjacent to each other in the second direction D2, and can extend to the region between fourth pairs of cell array structures CS adjacent to each other in the second direction D2. When viewed in a plan view, the isolation structure IS can have a cross shape.

[0083] The isolation structure IS electrically isolates the source structures SC of the cell array structure CS from each other. The source structure SC of each cell array structure CS can extend horizontally onto the buried insulating layer 105 and can contact the isolation structure IS. The isolation structure IS can be inserted between the source structures SC of the first pair of cell array structures CS adjacent to each other in the first direction D1, and can extend into the region between the source structures SC of the second pair of cell array structures CS adjacent to each other in the first direction D1. Furthermore, the isolation structure IS can also be inserted between the source structures SC of the third pair of cell array structures CS adjacent to each other in the second direction D2, and can extend into the region between the source structures SC of the fourth pair of cell array structures CS adjacent to each other in the second direction D2. The isolation structure IS electrically isolates the source structures SC of the cell array structures CS adjacent to each other in the first direction D1 and the second direction D2.

[0084] Additional isolation structures IS can be disposed on each chip region 10 of the semiconductor substrate 1. The additional isolation structures IS can be disposed along the edge of each chip region 10 to surround the cell array structure CS. The additional isolation structures IS at the edge of each chip region 10 can be adjacent to the dicing region 20. The source structure SC of the cell array structure CS arranged in the first direction D1 can share contact with the first of the additional isolation structures IS. In this case, the first of the additional isolation structures IS can have a linear shape extending in the first direction D1. The source structure SC of the cell array structure CS arranged in the second direction D2 can share contact with the second of the additional isolation structures IS. In this case, the second of the additional isolation structures IS can have a linear shape extending in the second direction D2. In an exemplary embodiment of the inventive concept, the additional isolation structures IS can be spaced apart from the isolation structures IS, but the inventive concept is not limited to this example. For example, the additional isolation structures IS and the isolation structures IS can be connected to each other to form a single object.

[0085] Figure 21 This schematically illustrates a portion of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept (e.g. Figure 1 A magnified plan view of part "A". For convenience, the following description will primarily refer to the reference. Figures 1 to 7 The characteristics described are different.

[0086] Reference Figure 21 An isolation structure IS can be disposed on each chip region 10 of the semiconductor substrate 1. For example, the isolation structure IS can be disposed on the buried insulating layer 105 between semiconductor layers 100. The isolation structure IS can be compared with a reference... Figure 20 The described isolation structures IS are substantially the same. However, in this embodiment, additional isolation structures IS may be disposed on the dicing region 20 and may surround each chip region 10. The source structure SC of the cell array structure CS arranged in the first direction D1 may commonly contact the first of the additional isolation structures IS. In this case, the first of the additional isolation structures IS may have a linear shape extending in the first direction D1. The source structure SC of the cell array structure CS arranged in the second direction D2 may commonly contact the second of the additional isolation structures IS. In this case, the second of the additional isolation structures IS may have a linear shape extending in the second direction D2. In an exemplary embodiment of the inventive concept, the additional isolation structures IS may be spaced apart from the isolation structures IS on the chip region 10.

[0087] Figure 22 This illustrates an exemplary embodiment of a three-dimensional semiconductor memory device according to the inventive concept. Figure 4 The sectional view taken by line I-I'. For convenience, the following description will primarily refer to the reference. Figures 1 to 7 The characteristics described are different.

[0088] Reference Figure 4 and Figure 22 In this embodiment, the electrode isolation structure GIS can be formed of an insulating material. In this case, each cell array structure CS may include additional interconnects to apply a source voltage to the source structure SC. The isolation structure IS can be formed of an insulating material. The isolation structure IS may include the same insulating material as the electrode isolation structure GIS.

[0089] According to an exemplary embodiment of the inventive concept, the source conductive layer SCL can be formed as a single layer covering the semiconductor layer 100 and the buried insulating layer 105, and can be in direct contact with the semiconductor substrate 1 at its edge 1ED. An anisotropic etching process for forming a vertical hole VH can be performed on the structure in which the source conductive layer SCL contacts the semiconductor substrate 1, thus allowing positive charges generated during the anisotropic etching process to be released to the semiconductor substrate 1 through the source conductive layer SCL. Therefore, the accumulation of positive charges generated during the anisotropic etching process in the semiconductor layer 100 and the generation of arc discharge in the semiconductor layer 100 can be prevented. An isolation structure IS can be used to cut (or separate) the source conductive layers SCL on the buried insulating layer 105 between the semiconductor layers 100. The cut source conductive layers SCL can form a second source conductive pattern SCP2 of the source structure SC. A cell array structure CS can be disposed on the semiconductor layers 100 that are horizontally spaced apart from each other, and the source structures SC of the cell array structure CS can be electrically separated from each other through the isolation structure IS. Therefore, the erasure operation can be performed independently on each cell array structure CS.

[0090] According to an exemplary embodiment of the inventive concept, the source conductive layer can be formed as a single layer disposed at the edge of a semiconductor substrate for direct contact with the semiconductor substrate. When an anisotropic etching process is performed to form vertical holes, the source conductive layer can contact the semiconductor substrate, thus allowing positive charges generated during the anisotropic etching process to be released to the semiconductor substrate through the source conductive layer. Therefore, arc discharge faults caused by positive charges can be prevented, thereby improving the reliability of the three-dimensional semiconductor memory device.

[0091] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0092] This application claims priority to Korean Patent Application No. 10-2019-0050750, filed on April 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional (3D) semiconductor memory device, comprising: The first semiconductor layer and the second semiconductor layer are horizontally spaced apart from each other; An insulating layer is buried between the first semiconductor layer and the second semiconductor layer; A first unit array structure disposed on the first semiconductor layer and a second unit array structure disposed on the second semiconductor layer; as well as An isolation structure is disposed on the buried insulating layer between the first unit array structure and the second unit array structure. The first unit array structure includes: An electrode structure comprising electrodes stacked in a direction perpendicular to the top surface of the first semiconductor layer; and A first source structure is disposed between the first semiconductor layer and the electrode structure. The first source structure extends onto the buried insulating layer, and The isolation structure is located between the first source structure of the first unit array structure and the second source structure of the second unit array structure.

2. The three-dimensional semiconductor memory device according to claim 1, wherein the first source structure of the first cell array structure and the second source structure of the second cell array structure are electrically separated from each other by the isolation structure.

3. The three-dimensional semiconductor memory device according to claim 1, wherein the first source structure of the first cell array structure is in contact with the side surface of the isolation structure.

4. The three-dimensional semiconductor memory device according to claim 1, wherein the bottom surface of the isolation structure is in contact with the buried insulating layer.

5. The three-dimensional semiconductor memory device according to claim 1, wherein the first cell array structure includes an electrode isolation structure that penetrates the electrode structure and the first source structure. The electrode isolation structure has a linear shape extending in a direction parallel to the top surface of the first semiconductor layer, and The isolation structure comprises the same material as the electrode isolation structure.

6. The three-dimensional semiconductor memory device according to claim 5, wherein the top surface of the isolation structure is at the same height as the top surface of the electrode isolation structure.

7. The three-dimensional semiconductor memory device of claim 5, wherein the first cell array structure includes a vertical structure penetrating the electrode structure and the first source structure, and Each of the vertical structures extends into the first semiconductor layer.

8. The three-dimensional semiconductor memory device of claim 7, wherein the vertical structure is connected to the first source structure.

9. The three-dimensional semiconductor memory device of claim 7, wherein the first cell array structure includes bit lines disposed on the electrode structure and connected to the vertical structure, and The top surface of the isolation structure is higher than the top surface of the vertical structure and lower than the bottom surface of the bit line.

10. The three-dimensional semiconductor memory device according to claim 1, wherein the first cell array structure comprises: A vertical structure that penetrates both the electrode structure and the first source structure; and Bit lines are disposed on the electrode structure and connected to the vertical structure. The top surface of the isolation structure is higher than the top surface of the vertical structure and lower than the bottom surface of the bit line.

11. The three-dimensional semiconductor memory device according to claim 1, further comprising a peripheral circuit structure on the substrate. The peripheral circuit structure includes peripheral circuits disposed on the substrate and a lower insulating layer covering the peripheral circuits. The first semiconductor layer, the second semiconductor layer, and the buried insulating layer are disposed on the lower insulating layer.

12. The three-dimensional semiconductor memory device of claim 1, wherein the isolation structure comprises a conductive pattern and an insulating spacer between the first source structure and the second source structure and the conductive pattern.

13. The three-dimensional semiconductor memory device according to claim 1, further comprising an insulating layer disposed on the buried insulating layer and filling the region between the first cell array structure and the second cell array structure. The isolation structure extends in a direction perpendicular to the top surface of the first semiconductor layer and penetrates at least a portion of the insulating layer.

14. A three-dimensional (3D) semiconductor memory device, comprising: The first semiconductor layer and the second semiconductor layer are horizontally spaced apart from each other on the substrate; The first unit array structure and the second unit array structure are respectively disposed on the first semiconductor layer and the second semiconductor layer; as well as An isolation structure is disposed on the substrate between the first unit array structure and the second unit array structure. The first unit array structure includes: An electrode structure comprising electrodes stacked in a direction perpendicular to the top surface of the first semiconductor layer; and A first source structure is disposed between the first semiconductor layer and the electrode structure, and The first source structure of the first cell array structure extends horizontally to the region of the substrate between the first semiconductor layer and the second semiconductor layer, and the first source structure of the first cell array structure and the second source structure of the second cell array structure are electrically separated from each other by the isolation structure.

15. The three-dimensional semiconductor memory device according to claim 14, further comprising: A third semiconductor layer on the substrate; and The third unit array structure disposed on the third semiconductor layer The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are spaced apart from each other in a first direction and a second direction parallel to the top surface of the substrate. The isolation structure includes multiple isolation structures. The first of the plurality of isolation structures is disposed between the first unit array structure and the second unit array structure that are adjacent to each other in the first direction. The second of the plurality of isolation structures is disposed between the first unit array structure and the third unit array structure that are adjacent to each other in the second direction, and The multiple isolation structures are spaced apart from each other.

16. The three-dimensional semiconductor memory device according to claim 14, further comprising: A third semiconductor layer and a fourth semiconductor layer are horizontally spaced apart from each other on the substrate; and The third unit array structure and the fourth unit array structure are respectively disposed on the third semiconductor layer and the fourth semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are spaced apart from each other in a first direction and a second direction parallel to the top surface of the substrate, and The isolation structure is disposed between the first unit array structure and the second unit array structure that are adjacent to each other in the first direction, and extends into the region between the third unit array structure and the fourth unit array structure that are adjacent to each other in the first direction.

17. The three-dimensional semiconductor memory device according to claim 14, further comprising: Peripheral circuits disposed on the substrate; and The lower insulating layer covering the peripheral circuit. The first semiconductor layer, the second semiconductor layer, and the isolation structure are disposed on the lower insulating layer, and The first source structure of the first cell array structure and the second source structure of the second cell array structure extend horizontally onto the lower insulating layer between the first semiconductor layer and the second semiconductor layer.

18. The three-dimensional semiconductor memory device of claim 14, wherein the first source structure of the first cell array structure and the second source structure of the second cell array structure are in contact with the side surface of the isolation structure.

19. The three-dimensional semiconductor memory device of claim 14, further comprising a buried insulating layer disposed on the substrate and between the first semiconductor layer and the second semiconductor layer. The isolation structure is disposed on the buried insulation layer, and The first source structure of the first unit array structure and the second source structure of the second unit array structure extend from the first semiconductor layer and the second semiconductor layer, respectively, onto the buried insulating layer.

20. The three-dimensional semiconductor memory device of claim 19, wherein the bottom surface of the isolation structure is in contact with the buried insulating layer.

21. The three-dimensional semiconductor memory device of claim 14, wherein the first cell array structure comprises: A vertical structure that penetrates both the electrode structure and the first source structure; and Bit lines are disposed on the electrode structure and connected to the vertical structure. The top surface of the isolation structure is higher than the top surface of the vertical structure and lower than the bottom surface of the bit line.

22. The three-dimensional semiconductor memory device of claim 21, wherein each of the vertical structures includes a vertical semiconductor pattern extending in a direction perpendicular to the top surface of the first semiconductor layer.

23. A three-dimensional (3D) semiconductor memory device, comprising: Peripheral circuitry on the substrate; A lower insulating layer is disposed on the substrate to cover the peripheral circuit; Semiconductor layer on the lower insulating layer; A cell array structure on the semiconductor layer; as well as An isolation structure is disposed on the lower insulating layer and on one side of the unit array structure. The unit array structure includes: An electrode structure comprising electrodes stacked in a direction perpendicular to the top surface of the semiconductor layer; and A source structure is disposed between the semiconductor layer and the electrode structure, and The source structure extends horizontally to protrude from the semiconductor layer and contact the side surface of the isolation structure.

24. The three-dimensional semiconductor memory device according to claim 23, wherein the cell array structure comprises: A vertical structure that penetrates both the electrode structure and the source structure; and Bit lines are disposed on the electrode structure and connected to the vertical structure. The top surface of the isolation structure is higher than the top surface of the vertical structure and lower than the bottom surface of the bit line.

25. A three-dimensional (3D) semiconductor memory device, comprising: The first semiconductor layer and the second semiconductor layer are separated from each other by a buried insulating layer; A first unit array structure disposed on the first semiconductor layer and a second unit array structure disposed on the second semiconductor layer; as well as An isolation structure is disposed on the buried insulating layer to separate the first unit array structure and the second unit array structure from each other. The first unit array structure includes: Multiple electrodes are stacked in a direction perpendicular to the top surface of the first semiconductor layer; and The source structure is disposed between the first semiconductor layer and the lowest electrode of the electrodes. The source structure overlaps with the buried insulating layer.

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