Semiconductor memory device including a variable resistance layer

Abstract

The present inventive concepts relate to a semiconductor memory device including a variable resistance layer. The semiconductor memory device includes a stack structure including a plurality of insulating layers and a plurality of interconnection layers alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and between the insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

Description

Technical Field

[0001] Devices and methods consistent with exemplary embodiments relate to semiconductor memory devices having a variable resistance layer, methods of operating the device, and methods of forming the device. Background Technology

[0002] Techniques using stacked structures have been developed to increase the integration density of semiconductor memory devices. Channel pillars are configured to extend through the stacked structure. These channel pillars comprise memory layers. However, the physical and chemical configuration of the memory layers directly impacts the high integration density, power consumption, and operating speed of the semiconductor memory device. Summary of the Invention

[0003] Exemplary embodiments of the present invention are intended to provide semiconductor memory devices that facilitate high integration density and exhibit low power consumption, methods of operating the devices, and methods of forming the devices.

[0004] According to an exemplary embodiment of the present invention, a semiconductor memory device includes a stacked structure comprising a plurality of insulating layers and a plurality of interconnect layers stacked alternately and repeatedly. Pillar structures are disposed on a side surface of the stacked structure. Each pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and located between the insulating pillar and the stacked structure. A channel layer is disposed on the variable resistance layer and located between the variable resistance layer and the stacked structure. A gate dielectric layer is disposed on the channel layer and located between the plurality of interconnect layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

[0005] According to an exemplary embodiment of the present invention, a semiconductor memory device includes a first stacked structure and a second stacked structure, each including a plurality of insulating layers and a plurality of interconnect layers stacked alternately and repeatedly. An isolation insulating layer is disposed between the first and second stacked structures. A pillar structure is disposed between the first and second stacked structures and configured to extend through the isolation insulating layer. Each pillar structure includes an insulating pillar and a first variable resistance layer disposed on the insulating pillar and located between the insulating pillar and the first stacked structure. A second variable resistance layer is disposed on the insulating pillar and located between the insulating pillar and the second stacked structure. A first channel layer is disposed on the first variable resistance layer and located between the first variable resistance layer and the first stacked structure. A second channel layer is disposed on the second variable resistance layer and located between the second variable resistance layer and the second stacked structure. A first gate dielectric layer is disposed on the first channel layer and located between the first channel layer and the first stacked structure. A second gate dielectric layer is disposed on the second channel layer and located between the second channel layer and the second stacked structure.

[0006] According to an exemplary embodiment of the present invention, a semiconductor memory device is provided, comprising a stacked structure including a plurality of insulating layers and a plurality of interconnect layers stacked alternately and repeatedly. Pillar structures are configured to extend through the stacked structure in a vertical direction. Isolating insulating layers are configured to intersect the stacked structure and the pillar structures, and extend through the stacked structure and the pillar structures in a vertical direction. Each pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and located between the insulating pillar and the stacked structure. A channel layer is disposed on the variable resistance layer and located between the variable resistance layer and the stacked structure. A gate dielectric layer is disposed on the channel layer and located between the plurality of interconnect layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

[0007] According to an exemplary embodiment of the present invention, a semiconductor memory device includes a stacked structure comprising a plurality of insulating layers and a plurality of interconnect layers stacked alternately and repeatedly. An isolation insulating layer is configured to intersect the stacked structure and extend through it in a vertical direction. A pillar structure is configured to intersect the isolation insulating layer and extend through both the stacked structure and the isolation insulating layer in a vertical direction. Each pillar structure includes an insulating pillar and a variable resistance layer configured to surround a side surface of the insulating pillar. A channel layer is configured to surround a side surface of the variable resistance layer. A gate dielectric layer is configured to surround a side surface of the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor memory device includes a stacked structure comprising a plurality of insulating layers and a plurality of memory layers stacked alternately and repeatedly. A gate structure is disposed on a side surface of the stacked structure. Each of the plurality of memory layers includes a channel layer and a variable resistance layer configured as a contact channel layer. Attached Figure Description

[0009] Figure 1 This is a perspective view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0010] Figure 2 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0011] Figure 3 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0012] Figure 4 This is an exemplary embodiment of the concept of the present invention. Figure 3 A partial sectional view.

[0013] Figure 5 This is an exemplary embodiment of the concept of the present invention. Figure 4A perspective view of some of the components.

[0014] Figure 6 This is a partial cross-sectional view and equivalent circuit diagram illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0015] Figure 7 and Figure 8 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0016] Figures 9 to 11 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0017] Figure 12 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0018] Figure 13 and Figure 14 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0019] Figure 15 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0020] Figure 16 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0021] Figure 17 and Figure 18 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0022] Figure 19 This is a perspective view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0023] Figure 20 This is an exemplary embodiment of the concept of the present invention. Figure 19 A perspective view of some of the components.

[0024] Figures 21 to 26 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0025] Figure 27 , Figure 28 , Figures 31 to 33 , Figures 35 to 37 and Figures 39 to 43 This is a cross-sectional view illustrating a method for forming a semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0026] Figure 29 , Figure 30 , Figure 34 , Figure 38 This is a top view illustrating a method for forming a semiconductor memory device according to an exemplary embodiment of the concept of the present invention. Detailed Implementation

[0027] Figure 1 This is a perspective view illustrating a semiconductor memory device according to an exemplary embodiment of the concept of the present invention. The semiconductor memory device according to this exemplary embodiment may include non-volatile memory, such as vertical NAND (VNAND) with a discrete cell structure or three-dimensional (3D) flash memory with a discrete cell structure.

[0028] Reference Figure 1 The semiconductor memory device may include a substrate 21, a first insulating layer 23, a plurality of stacked structures 30, a plurality of pillar structures 40, a source plug 61, a bit plug 63, a source line 65, and a bit line 67. Each of the plurality of stacked structures 30 may include a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are stacked alternately and repeatedly. For example, the alternating insulating layers 33 and interconnect layers W1 to Wn may be arranged in the Z direction.

[0029] Figure 2 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0030] Reference Figure 2 The semiconductor memory device may include multiple stacked structures 30, multiple pillar structures 40, and an insulating layer 48. The multiple stacked structures 30 may include a first stacked structure 30A and a second stacked structure 30B. The first stacked structure 30A and the second stacked structure 30B may be arranged in the X direction. Each of the multiple pillar structures 40 may include a first gate dielectric layer 42A and a second gate dielectric layer 42B, a first channel layer 43A and a second channel layer 43B, a first variable resistance layer 44A and a second variable resistance layer 44B, and an insulating pillar 45. Figure 2 In the exemplary embodiment shown, the first gate dielectric layer 42A and the second gate dielectric layer 42B are directly disposed on the first channel layer 43A and the second channel layer 43B in the X direction, respectively. The first variable resistance layer 44A and the second variable resistance layer 44B are also directly disposed on the first channel layer 43A and the second channel layer 43B in the X direction, respectively. The first variable resistance layer 44A and the second variable resistance layer 44B are also directly disposed on the insulating pillar 45 in the X direction. A plurality of pillar structures 40 are disposed between adjacent stacked structures 30 in the X direction, and an insulating layer 48 (e.g., in the Y direction) is disposed between adjacent pillar structures 40.

[0031] Figure 3 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention. Figure 4 yes Figure 3 A partial sectional view. Figure 5 yes Figure 4 A perspective view of some of the components.

[0032] Reference Figure 3 The semiconductor memory device may include a substrate 21, a first insulating layer 23, a plurality of stacked structures 30, a plurality of pillar structures 40, an isolation insulating layer 48, second to fifth insulating layers 52, 53, 54 and 55, a source plug 61, a bit plug 63, a source line 65 and a bit line 67. As previously described, each of the plurality of stacked structures 30 may include a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are stacked alternately and repeatedly.

[0033] Substrate 21 may include a semiconductor substrate such as a silicon wafer. The plurality of interconnect layers W1 to Wn may include conductive materials such as polysilicon, metal, metal nitride, metal oxide, metal silicide, conductive carbon, or combinations thereof. In one exemplary embodiment, the plurality of interconnect layers W1 to Wn may include polysilicon. However, exemplary embodiments of the present invention are not limited thereto. Each of the first insulating layer 23, the plurality of insulating layers 33, the isolation insulating layer 48, and the second to fifth insulating layers 52, 53, 54, and 55 may include silicon oxide, silicon nitride, silicon oxide nitride, a low-k dielectric material, a high-k dielectric material, or combinations thereof. Source plug 61, bit plug 63, source line 65, and bit line 67 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof. However, exemplary embodiments of the present invention are not limited thereto.

[0034] Reference Figure 4 The semiconductor memory device may include a substrate 21, a first insulating layer 23, a first stacked structure 30A and a second stacked structure 30B, a pillar structure 40, second to fifth insulating layers 52, 53, 54 and 55, a source plug 61, a bit plug 63, a source line 65, and a bit line 67. As previously described, each of the first stacked structure 30A and the second stacked structure 30B may include a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are alternately and repeatedly stacked. As previously described, the pillar structure 40 may include a first gate dielectric layer 42A and a second gate dielectric layer 42B, a first channel layer 43A and a second channel layer 43B, a first variable resistor layer 44A and a second variable resistor layer 44B, and an insulating pillar 45.

[0035] The first gate dielectric layer 42A and the second gate dielectric layer 42B may comprise silicon oxide, silicon nitride, silicon oxide nitride, high-k dielectric material, or a combination thereof. The first channel layer 43A and the second channel layer 43B may comprise semiconductor layers such as polysilicon layers. The first variable resistivity layer 44A and the second variable resistivity layer 44B may include at least one of the following: NiO, CuO, CoO, Fe2O3, HfO, TiO2, Ta2O5, Nb2O5, SrTiO3 (STO), SrZrO3, AlO, SiO, SiN, lanthanum strontium manganese oxide (LSMO), lanthanum calcium manganese oxide (LCMO), praseodymium calcium manganese oxide (PCMO), praseodymium lanthanum calcium manganese oxide (PLCMO), yttrium barium copper oxide (YBCO), bismuth strontium calcium copper oxide (BSCCO), Bi:SrTiO3, Cr:SrTiO3, HfSiO, AlSiO, tungsten oxide (WO), Mott, GeSbTe, carbon-doped (C) GeSbTe, nitrogen-doped (N) GeSbTe, SnSbTe, GeAsTe, GeSbSe, GeTe-Sb2Te3, Zr 60 Al 15 Ni 25 Fe-Co-B-Si-Nb. The insulating pillar 45 may include silicon oxide, silicon nitride, silicon nitride oxide, low-k dielectric material, high-k dielectric material, or a combination thereof. However, exemplary embodiments of the present invention are not limited thereto.

[0036] In one exemplary embodiment, among the plurality of interconnect layers W1 to Wn, the lowest interconnect layer W1 (e.g., in the Z direction) may correspond to a connection gate. Among the plurality of interconnect layers W1 to Wn, some interconnect layers W2 to Wn-1 may correspond to word lines. Among the plurality of interconnect layers W1 to Wn, the highest interconnect layer Wn of the first stack structure 30A (e.g., in the Z direction) may correspond to a Serial Select Line (SSL). Among the plurality of interconnect layers W1 to Wn, the highest interconnect layer Wn of the second stack structure 30B (e.g., in the Z direction) may correspond to a Ground Select Line (GSL).

[0037] Reference Figure 5The second gate dielectric layer 42B may be continuous with the first gate dielectric layer 42A. The second channel layer 43B may be continuous with the first channel layer 43A. The second variable resistor layer 44B may be continuous with the first variable resistor layer 44A. For example, the first gate dielectric layer 42A and the second gate dielectric layer 42B may extend in the Z direction and may include a bottom surface extending in the X direction connecting the first gate dielectric layer and the second gate dielectric layer. The first channel layer 43A and the second channel layer 43B may extend in the Z direction and may include a bottom surface extending in the X direction connecting the first channel layer and the second channel layer. The first variable resistor layer 44A and the second variable resistor layer 44B may extend in the Z direction and may include a bottom surface extending in the X direction connecting the first variable resistor layer and the second variable resistor layer.

[0038] Refer again Figures 1 to 5 A first insulating layer 23 may be disposed on a substrate 21. A first stacked structure 30A and a second stacked structure 30B may be disposed on the first insulating layer 23. An insulating isolation layer 48 and a pillar structure 40 may be disposed between the first stacked structure 30A and the second stacked structure 30B. The insulating isolation layer 48 may intersect the space between the first stacked structure 30A and the second stacked structure 30B and extend through the space in a vertical direction (e.g., the Z direction). The lower end of the insulating isolation layer 48 (e.g., in the Z direction) may contact the first insulating layer 23. For example, the lower end of the insulating isolation layer 48 may contact the top surface of the first insulating layer 23 (e.g., in the Z direction).

[0039] The column structure 40 can extend through the insulating layer 48 and contact the first insulating layer 23. For example, as Figure 4 As shown, the bottom surfaces (e.g., in the Z direction) of the first gate dielectric layer 42A and the second gate dielectric layer 42B can contact the top surface of the first insulating layer 23. A first variable resistance layer 44A can be disposed between the insulating pillar 45 and the first stacked structure 30A. A second variable resistance layer 44B can be disposed between the insulating pillar 45 and the second stacked structure 30B. A first channel layer 43A can be disposed between the first variable resistance layer 44A and the first stacked structure 30A. A second channel layer 43B can be disposed between the second variable resistance layer 44B and the second stacked structure 30B.

[0040] A first gate dielectric layer 42A may be disposed between a first channel layer 43A and a first stacked structure 30A. The first gate dielectric layer 42A may also be disposed between multiple interconnect layers W1 to Wn and the first channel layer 43A. The first gate dielectric layer 42A may be in direct contact with the corresponding interconnect layer among the multiple interconnect layers W1 to Wn and the first channel layer 43A. A second gate dielectric layer 42B may be disposed between a second channel layer 43B and a second stacked structure 30B. The second gate dielectric layer 42B may also be disposed between multiple interconnect layers W1 to Wn and the second channel layer 43B. The second gate dielectric layer 42B may be in direct contact with the corresponding interconnect layer among the multiple interconnect layers W1 to Wn and the second channel layer 43B.

[0041] The first channel layer 43A can be disposed between the first variable resistance layer 44A and the first gate dielectric layer 42A. The first variable resistance layer 44A can be in direct contact with the insulating post 45 and the first channel layer 43A. The second channel layer 43B can be disposed between the second variable resistance layer 44B and the second gate dielectric layer 42B. The second variable resistance layer 44B can be in direct contact with the insulating post 45 and the second channel layer 43B.

[0042] Bit line 67 can be connected to the upper end of the first channel layer 43A (e.g., in the Z direction) via bit plug 63. The bottom surface of bit plug 63 (e.g., in the Z direction) can contact the top surface of the first channel layer 43A (e.g., in the Z direction). Figure 1 As shown, bit plug 63 can extend to bit line 67. Source line 65 can be connected to the upper end of the second channel layer 43B via source plug 61. The bottom surface of source plug 61 (e.g., in the Z direction) can contact the top surface of the second channel layer 43B (e.g., in the Z direction).

[0043] Figure 6 A partial cross-sectional view and equivalent circuit diagram are shown, illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0044] Reference Figure 6 The semiconductor memory device may include multiple insulating layers 33, first to third interconnect layers W11, W12, and W13, and a pillar structure 40. As previously described, the pillar structure 40 may include a gate dielectric layer 42, a channel layer 43, a variable resistance layer 44, and an insulating pillar 45. First to third memory cells C1, C2, and C3 may be formed in the regions where the first to third interconnect layers W11, W12, and W13 intersect with the pillar structure 40. Each of the first to third interconnect layers W11, W12, and W13 may serve as a gate electrode. The variable resistance layer 44 may include a reference... Figure 4The first variable resistor layer 44A and the second variable resistor layer 44B are described in substantially the same configuration. The variable resistor layer 44 may present a plurality of variable resistors R adjacent to and corresponding to the first to third interconnect layers W11, W12 and W13.

[0045] In one exemplary embodiment, a first voltage higher than a threshold voltage can be applied to each of the first interconnect layer W11 and the third interconnect layer W13, and a second voltage lower than the threshold voltage can be applied to the second interconnect layer W12, or the second interconnect layer can be grounded, thereby selecting the second memory cell C2. A write current can be applied to both ends of the channel layer 43. The write current can flow through the channel layer 43 adjacent to the first interconnect layer W11, the variable resistor layer 44 adjacent to the second interconnect layer W12, and the channel layer 43 adjacent to the third interconnect layer W13. The write current can switch the variable resistor layer 44 adjacent to the second interconnect layer W12 to a low-resistance state or a high-resistance state. A read current can be applied to both ends of the channel layer 43. The read current can flow through the channel layer 43 adjacent to the first interconnect layer W11, the variable resistor layer 44 adjacent to the second interconnect layer W12, and the channel layer 43 adjacent to the third interconnect layer W13. Data can be read from the second memory cell C2 in response to the read current.

[0046] Figure 7 and Figure 8 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0047] Reference Figure 7 The insulating layer 48 can take various shapes. The insulating layer 48 can extend (e.g., in the X direction) through the plurality of stacked structures 30 and can extend in the Z direction. The lateral width (e.g., length in the X direction) of the insulating layer 48 can be greater than the lateral width (e.g., length in the X direction) of each of the plurality of pillar structures 40. The insulating layer 48 can be in direct contact with the plurality of stacked structures 30.

[0048] In one exemplary embodiment, each of the plurality of stacked structures 30 may include a minor axis in a first lateral direction (e.g., the X direction) and a major axis in a second lateral direction (e.g., the Y direction). However, the exemplary embodiments of the present invention are not limited thereto. The second lateral direction may be perpendicular to the first lateral direction. The plurality of stacked structures 30 may be arranged separately from each other in the first lateral direction. The plurality of stacked structures 30 may be arranged parallel to each other. An insulating layer 48 and a plurality of pillar structures 40 may be disposed between the plurality of stacked structures 30. As previously described, the lateral width of the insulating layer 48 in the first lateral direction may be greater than the lateral width of each of the plurality of pillar structures 40 in the first lateral direction. The insulating layer 48 may intersect with the entire portion of the plurality of pillar structures 40 in the first lateral direction. The insulating layer 48 can be in direct contact with the side surfaces (e.g., lateral ends in the Y direction) of the first gate dielectric layer 42A and the second gate dielectric layer 42B, the side surfaces (e.g., lateral ends in the Y direction) of the first channel layer 43A and the second channel layer 43B, the side surfaces (e.g., lateral ends in the Y direction) of the first variable resistor layer 44A and the second variable resistor layer 44B, the side surface (e.g., lateral ends in the Y direction) of the insulating pillar 45, and the side surfaces (e.g., side surfaces extending in the Y direction) of the plurality of stacked structures 30.

[0049] Reference Figure 8 The lateral width of the insulating layer 48 in the first lateral direction may be less than the lateral width of each of the plurality of pillar structures 40 in the first lateral direction. The first gate dielectric layer 42A and the second gate dielectric layer 42B may be disposed between the plurality of stacked structures 30 and the side surface of the insulating layer 48 extending in the Y direction.

[0050] In one exemplary embodiment, an insulating layer 48 and a plurality of pillar structures 40 may be disposed between a plurality of stacked structures 30. For example, the plurality of stacked structures 30 may be arranged in the X direction relative to the insulating layer 48 and the plurality of pillar structures 40. The lateral width of the insulating layer 48 in a first lateral direction may be smaller than the lateral width of each of the plurality of pillar structures 40 in the first lateral direction. A first gate dielectric layer 42A may extend between a side surface of the insulating layer 48 extending in the Y direction and the first stacked structure 30A. A second gate dielectric layer 42B may extend between a side surface of the insulating layer 48 extending in the Y direction and the second stacked structure 30B.

[0051] Figures 9 to 11 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention.

[0052] Reference Figure 9Among the multiple interconnect layers W1 to Wn, the lowest interconnect layer W1 (e.g., in the Z direction) may correspond to a connection gate. The lowest interconnect layer W1 may surround the lower side surface (e.g., extending in the Z direction) and bottom (e.g., extending in the X direction) of the multiple pillar structures 40. For example, a portion of the lowest interconnect layer W1 may be directly disposed between the bottom surfaces of the first dielectric layer and the second dielectric layer and the first insulating layer 23.

[0053] Reference Figure 10 The lower conductive layer 25 can be disposed on the substrate 21. For example, the lower conductive layer 25 can be disposed directly on the top surface of the substrate (e.g., in the Z direction). The lower conductive layer 25 can be used as a source line. The lower conductive layer 25 can be formed by implanting N-type or P-type impurities into the substrate 21. In an exemplary embodiment, the substrate 21 may include P-type impurities, and the lower conductive layer 25 may include N-type impurities. However, exemplary embodiments of the inventive concept are not limited thereto. Among the plurality of interconnect layers W1 to Wn, the lowermost interconnect layer W1 (e.g., in the Z direction) may correspond to GSL. Among the plurality of interconnect layers W1 to Wn, the uppermost interconnect layer Wn (e.g., in the Z direction) may correspond to SSL. The first channel layer 43A and the second channel layer 43B can extend through the first gate dielectric layer 42A and the second gate dielectric layer 42B and directly contact the lower conductive layer 25. The first gate dielectric layer 42A and the second gate dielectric layer 42B may not include a bottom surface extending in the X direction.

[0054] Reference Figure 11 The insulating post 45 can extend through the first variable resistance layer 44A and the second variable resistance layer 44B, the first channel layer 43A and the second channel layer 43B, and the first gate dielectric layer 42A and the second gate dielectric layer 42B, and directly contact the lower conductive layer 25.

[0055] Figure 12 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention. Figure 13 and Figure 14 It is shown Figure 12 A cross-sectional view of the semiconductor memory device shown.

[0056] Reference Figure 12The semiconductor memory device may include multiple stacked structures 130, multiple pillar structures 140, and an insulating layer 148. The multiple stacked structures may be arranged in the X direction and may have a major axis in the Y direction and a minor axis in the X direction. The insulating layer 148 may be arranged in the X direction and may extend through the pillar structures 140 in the Y direction. Each of the multiple pillar structures 140 may include a gate dielectric layer 142, a channel layer 143, a variable resistance layer 144, and an insulating pillar 145.

[0057] Reference Figure 13 The semiconductor memory device may include a substrate 121, a lower conductive layer 125, a stacked structure 130, a plurality of pillar structures 140, an isolation insulating layer 148, a third insulating layer 53, a plurality of bit pads 62, a plurality of bit plugs 63, and bit lines 67. As previously described, the stacked structure 130 may include a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are alternately and repeatedly stacked. As previously described, each of the plurality of pillar structures 140 may include a gate dielectric layer 142, a channel layer 143, a variable resistance layer 144, and an insulating pillar 145.

[0058] Refer again Figure 12 and Figure 13 A lower conductive layer 125 may be disposed on a substrate 121. For example, the lower conductive layer 125 may be disposed directly on the top surface of the substrate 121 in the Z direction. A stack structure 130 may be disposed on the lower conductive layer 125. Each of a plurality of pillar structures 140 may extend through the stack structure 130 in a vertical direction (e.g., the Z direction) and contact the lower conductive layer 125. A channel layer 143 may extend through the gate dielectric layer 142 and directly contact the lower conductive layer 125. A plurality of pads 62 may be disposed on the plurality of pillar structures 140. Each of the plurality of pads 62 may directly contact the channel layer 143. An isolation insulating layer 148 may intersect the plurality of pads 62, the plurality of pillar structures 140 and the stack structure 130, extend through them in a vertical direction (e.g., the Z direction) and contact the lower conductive layer 125. The isolation insulating layer 148 may extend from the lower conductive layer 125 to the bottom surface of the third insulating layer 53 in the Z direction.

[0059] In one exemplary embodiment, a variable resistance layer 144 may be disposed between an insulating pillar 145 and a stacked structure 130. A channel layer 143 may be disposed between the variable resistance layer 144 and the stacked structure 130. A gate dielectric layer 142 may be disposed between the channel layer 143 and the stacked structure 130. The gate dielectric layer 142 may be disposed between a plurality of interconnect layers W1 to Wn and the channel layer 143. The channel layer 143 may be disposed between the variable resistance layer 144 and the gate dielectric layer 142. An insulating insulating layer 148 may extend in a vertical direction (e.g., the Z direction) through a plurality of bit pads 62, an insulating pillar 145, a variable resistance layer 144, a channel layer 143, and a gate dielectric layer 142, and contact the underlying conductive layer 125. Bit lines 67 may be connected to the upper end of the channel layer 143 via bit plugs 63 and a plurality of bit pads 62.

[0060] Reference Figure 14 The semiconductor memory device may include a substrate 121, a lower conductive layer 125, a buried conductive layer 126, a support plate 127, a stacked structure 130, multiple pillar structures 140, an isolation insulating layer 148, a third insulating layer 53, a bit pad 62, a bit plug 63, and a bit line 67. Each of the multiple pillar structures 140 may include a gate dielectric layer 142, a channel layer 143, a variable resistance layer 144, and an insulating pillar 145.

[0061] A lower conductive layer 125 may be disposed on a substrate 121. For example, the lower conductive layer 125 may be disposed directly on the top surface of the substrate 121 (e.g., in the Z direction). A buried conductive layer 126 may be disposed on the lower conductive layer 125. For example, the buried conductive layer 126 may be disposed directly on the top surface of the lower conductive layer 125 (e.g., in the Z direction). A support plate 127 may be disposed on the buried conductive layer 126. For example, the support plate 127 may be disposed directly on the top surface of the buried conductive layer 126 in the Z direction. A stack structure 130 may be disposed on the support plate 127. The support plate 127 may include polysilicon. The buried conductive layer 126 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the plurality of pillar structures 140 may extend through the stack structure 130, the support plate 127, and the buried conductive layer 126 in a vertical direction (e.g., the Z direction) and contact the lower conductive layer 125.

[0062] The buried conductive layer 126 can be used as a source line. The buried conductive layer 126 can extend through the side surface of the gate dielectric layer 142 and directly contact the lower side surface of the channel layer 143 extending in the Z direction.

[0063] Figure 15 This is a top view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention. Figure 16 It is shown Figure 15 A cross-sectional view of the semiconductor memory device shown.

[0064] Reference Figure 15 The semiconductor memory device may include multiple stacked structures 230, multiple pillar structures 240, and an insulating layer 248. Each of the multiple pillar structures 240 may include a gate dielectric layer 242, a channel layer 243, a variable resistance layer 244, and an insulating pillar 245.

[0065] Reference Figure 16 The semiconductor memory device may include a substrate 221, a lower conductive layer 225, multiple stacked structures 230, multiple pillar structures 240, an isolation insulating layer 248, a pad isolation layer 249, a third insulating layer 53, a bit pad 62, a bit plug 63, and a bit line 67. As previously described, each of the multiple stacked structures 230 may include multiple insulating layers 33 and multiple interconnect layers W1 to Wn that are alternately and repeatedly stacked. As previously described, each of the multiple pillar structures 240 may include a gate dielectric layer 242, a channel layer 243, a variable resistance layer 244, and an insulating pillar 245.

[0066] Refer again Figure 15 and Figure 16 A lower conductive layer 225 can be disposed on a substrate 221. A stacked structure 230 can be disposed on the lower conductive layer 225. An insulating layer 248 can intersect the stacked structure 230, extend through the stacked structure 230 in a vertical direction (e.g., the Z direction), and contact the lower conductive layer 225. However, with Figure 13 The insulating layer 148 in the exemplary embodiment is different. Figure 15 and Figure 16 In an exemplary embodiment, the insulating layer 248 does not extend through the plurality of column structures 240. For example... Figure 16 As shown, the pad isolation layer 249 may extend through multiple pads and may have a bottom surface (e.g., in the Z direction) disposed in the upper region of the insulating post 245.

[0067] Each of the plurality of pillar structures 240 may (e.g., in the Y direction) intersect with the insulating layer 248, extend through the stack structure 230 and the insulating layer 248 in a vertical direction (e.g., the Z direction), and contact the lower conductive layer 225. A variable resistance layer 244 may surround the side surfaces and bottom of the insulating pillars 245. A channel layer 243 may surround the side surfaces and bottom of the variable resistance layer 244. A gate dielectric layer 242 may surround the side surfaces of the channel layer 243. The gate dielectric layer 242 does not include a bottom surface extending in the X direction. The channel layer 243 may be disposed between the variable resistance layer 244 and the gate dielectric layer 242. The channel layer 243 may extend through the gate dielectric layer 242 and directly contact the lower conductive layer 225. The gate dielectric layer 242 may directly contact the side surfaces of the insulating layer 248, the side surfaces of the channel layer 243, and the side surfaces of the plurality of interconnect layers W1 to Wn. Bit line 67 can be connected to the upper end of channel layer 243 through multiple bit plugs 63 and multiple bit pads 62.

[0068] Figure 17 and Figure 18 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention. Figure 18 It is perpendicular to Figure 17 A cross-sectional view taken in the direction of [the specified direction]. A semiconductor memory device according to this exemplary embodiment may include a center bit line and a wafer bonding structure.

[0069] Reference Figure 17 and Figure 18 The semiconductor memory device may include a first substrate 321, a lower conductive layer 325, a buried conductive layer 326, a support plate 327, a lower stack structure 330, a plurality of lower pillar structures 340, a lower isolation insulating layer 348, a second insulating layer 352, a sixth insulating layer 356, a plurality of lower pads 362, a plurality of lower plugs 363, a plurality of lower lines 367, a seventh insulating layer 457, an eighth insulating layer 458, a plurality of upper lines 467, a plurality of upper plugs 463, a plurality of upper pads 462, an upper stack structure 430, a plurality of upper pillar structures 440, an upper isolation insulating layer 448, a source pad 429, an upper source line 426, a ninth insulating layer 459, a second substrate 521, a tenth insulating layer 523, and a plurality of transistors 571.

[0070] Multiple transistors 571 can form a peripheral circuit in the tenth insulating layer 523 on the second substrate 521. For example... Figure 17As shown in the exemplary embodiment, the tenth insulating layer 523 can be directly disposed on and bonded to the ninth insulating layer 459. As previously described, the lower stack structure 330 may include (e.g., in the Z direction) a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are alternately and repeatedly stacked. As previously described, the upper stack structure 430 may include (e.g., in the Z direction) a plurality of upper insulating layers 433 and a plurality of upper interconnect layers W41 to Wm that are alternately and repeatedly stacked.

[0071] Each of the plurality of lower pillar structures 340 may include a lower gate dielectric layer 342, a lower channel layer 343, a lower variable resistor layer 344, and a lower insulating pillar 345. Each of the plurality of upper pillar structures 440 may include an upper gate dielectric layer 442, an upper channel layer 443, an upper variable resistor layer 444, and an upper insulating pillar 445.

[0072] The upper stack structure 430 and the lower stack structure 330 are spaced apart in the Z direction. Multiple lower part lines 367 and multiple upper part lines 467 can be disposed between the lower stack structure 330 and the upper stack structure 430.

[0073] Figure 19 This is a perspective view illustrating an exemplary embodiment of a semiconductor memory device according to a concept of the present invention. Figure 20 yes Figure 19 A perspective view of some of the components. Figures 21 to 26 It is shown Figure 19 The cross-sectional view of the semiconductor memory device shown.

[0074] Reference Figure 19 The semiconductor memory device may include a substrate 621, a first insulating layer 623, a plurality of stacked structures 680, and a plurality of gate structures G1 to Gn. The plurality of gate structures G1 to Gn may extend in a plane defined by the X and Z directions and may be arranged in the Y direction. Each of the plurality of stacked structures 680 may include a plurality of insulating layers 633 and a plurality of memory layers M1 to Mn that are alternately and repeatedly stacked. For example, the alternating insulating layers 633 and memory layers M1 to Mn may be arranged in the Z direction. Each of the plurality of stacked structures 680 may also include an isolation insulating layer 648 disposed between the plurality of insulating layers 633.

[0075] Reference Figure 20The semiconductor memory device may include a first memory layer M1 to a third memory layer M3 and a plurality of gate structures G1 to Gn. Each of the first memory layer M1 to the third memory layer M3 may include a channel layer 643 and a variable resistance layer 644. Each of the plurality of gate structures G1 to Gn may include a gate electrode 691 and a gate dielectric layer 642. The first memory layer M1 to the third memory layer M3 may be stacked in a vertical direction (e.g., the Z direction). Each of the plurality of gate structures G1 to Gn may be disposed in a vertical direction. Each of the plurality of gate structures G1 to Gn may contact a side surface of the first memory layer M1 to the third memory layer M3 extending in the Z direction.

[0076] Reference Figure 21 The semiconductor memory device may include a substrate 621, a first insulating layer 623, a plurality of stacked structures 680, and a gate structure G1. Each of the plurality of stacked structures 680 may include (e.g., in the Z direction) a plurality of insulating layers 633 and a plurality of memory layers M1 to Mn that are alternately and repeatedly stacked. Each of the plurality of stacked structures 680 may also include (e.g., in the Z direction) an isolation insulating layer 648 disposed between the plurality of insulating layers 633.

[0077] Each of the plurality of memory layers M1 to Mn may include a channel layer 643 and a variable resistance layer 644. The variable resistance layer 644 may be in direct contact with the channel layer 643. The variable resistance layer 644 may surround an upper surface, a lower surface, and a side surface of the channel layer 643. An isolation insulating layer 648 may be disposed on one side of the variable resistance layer 644. The isolation insulating layer 648 may contact the side surface of the variable resistance layer 644. For example, the side edges of the isolation insulating layer 648 extending in the Z direction may each contact the variable resistance layer 644 of the memory layer. The variable resistance layer 644 may be disposed between the isolation insulating layer 648 and the channel layer 643. The variable resistance layer 644 may extend between the upper surface of the channel layer 643 and the lower surface of an adjacent insulating layer among the plurality of insulating layers 633. The variable resistance layer 644 may extend between the lower surface of the channel layer 643 and the upper surface of an adjacent insulating layer among the plurality of insulating layers 633.

[0078] A gate structure G1 may be disposed on the side surface of each of the plurality of stacked structures 680. For example, the gate structure G1 may be disposed on the side surfaces of the plurality of stacked structures having planes defined by the Z and X directions. The gate structure G1 may include a gate electrode 691 and a gate dielectric layer 642. The gate dielectric layer 642 may be disposed between the plurality of stacked structures 680 and the gate electrode 691. The gate dielectric layer 642 may be disposed between the plurality of memory layers M1 to Mn and the gate electrode 691. The gate dielectric layer 642 may be in direct contact with the plurality of memory layers M1 to Mn and the gate electrode 691. The gate dielectric layer 642 may be in direct contact with the side surfaces of the channel layer 643 and the variable resistance layer 644, the side surfaces of the channel layer 643 and the variable resistance layer 644 having planes defined by the Z and Y directions.

[0079] Reference Figure 22 The channel layer 643 may surround the upper surface, lower surface, and one side surface of the variable resistance layer 644. An insulating layer 648 may be disposed on one side of the channel layer 643. A side edge of the channel layer 643 extending in the Z direction may be disposed between the variable resistance layer 644 and the insulating layer 648. An upper edge of the channel layer 643 extending in the X direction may be disposed between the upper surface of the variable resistance layer 644 (e.g., in the Z direction) and the lower surface of an adjacent insulating layer among the plurality of insulating layers 633. A lower edge of the channel layer 643 extending in the X direction may be disposed between the lower surface of the variable resistance layer 644 (e.g., in the Z direction) and the upper surface of an adjacent insulating layer among the plurality of insulating layers 633.

[0080] Reference Figure 23 The variable resistance layer 644 can be disposed on the channel layer 643. For example, the bottom surface of the variable resistance layer 644 (e.g., in the Z direction) can be directly disposed on the top surface of the channel layer (e.g., in the Z direction). The Z-direction extending side surfaces of the variable resistance layer 644 and the channel layer 643 can be in direct contact with the Z-direction extending side edge of the insulating layer 648.

[0081] Reference Figure 24 The variable resistance layer 644 and the channel layer 643 can be disposed between the isolation insulating layer 648 and the gate dielectric layer 642. The variable resistance layer 644 can be disposed between the channel layer 643 and the isolation insulating layer 648. The channel layer 643 can be disposed between the variable resistance layer 644 and the gate dielectric layer 642. The gate dielectric layer 642 can be in direct contact with the Z-direction extending side surface of the channel layer 643 and the side surface of the gate electrode 691.

[0082] Reference Figure 25The variable resistance layer 644 and the channel layer 643 can be disposed between multiple insulating layers 633. The channel layer 643 can be disposed between the variable resistance layer 644 and the gate dielectric layer 642. The Z-direction extending side surface of the variable resistance layer 644 can be in direct contact with the Z-direction extending side surface of the channel layer 643.

[0083] Reference Figure 26 Multiple storage layers M1 to Mn can be disposed between multiple insulating layers 633. Each of the multiple storage layers M1 to Mn may include a channel layer 643 and a variable resistor layer 644 disposed on the channel layer 643. For example, the bottom surface of the variable resistor layer 644 extending in the X direction may be in direct contact with the top surface of the channel layer 643 extending in the X direction. Storage layers M1 to Mn may have side surfaces extending in the Z direction that contact the side surfaces of the gate dielectric layer 642 extending in the Z direction.

[0084] Figure 27 , Figure 28 and Figures 31 to 33 This is a cross-sectional view illustrating a method for forming a semiconductor memory device according to an exemplary embodiment of the present invention. Figure 29 and Figure 30 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 27 , Figure 28 and Figures 31 to 33 The image shows a top view of a method for forming a semiconductor memory device.

[0085] Reference Figure 27 A first insulating layer 23 may be formed on the substrate 21. A stacked structure 30 may be formed on the first insulating layer 23. The stacked structure 30 may include (e.g., in a direction perpendicular to the top surface of the substrate 21) a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are stacked alternately and repeatedly.

[0086] Reference Figure 28 and Figure 29 The stacked structure 30 can be patterned to form multiple isolation trenches 48T. The multiple isolation trenches 48T can be arranged parallel to each other. The multiple isolation trenches 48T can intersect the stacked structure 30 and extend through the stacked structure 30 in a vertical direction. The stacked structure 30 can be divided into several sections by the multiple isolation trenches 48T.

[0087] In one exemplary embodiment, each of the plurality of isolation trenches 48T may have a configuration substantially perpendicular to the top surface of the substrate 21. Side surfaces of the plurality of insulating layers 33 extending in a direction perpendicular to the top surface of the substrate and side surfaces of the plurality of interconnect layers W1 to Wn extending in a direction perpendicular to the top surface of the substrate may be exposed at the sidewalls of the plurality of isolation trenches 48T. A first insulating layer 23 may be exposed at the bottom of the plurality of isolation trenches 48T.

[0088] Reference Figure 30 and Figure 31 A first gate dielectric layer 42A and a second gate dielectric layer 42B, a first channel layer 43A and a second channel layer 43B, a first variable resistor layer 44A and a second variable resistor layer 44B, and an insulating pillar 45 can be sequentially stacked in multiple isolation trenches 48T. The first gate dielectric layer 42A and the second gate dielectric layer 42B, the first channel layer 43A and the second channel layer 43B, the first variable resistor layer 44A and the second variable resistor layer 44B, and the insulating pillar 45 can constitute a pillar structure 40. The pillar structure 40 can fill the multiple isolation trenches 48T and cover the stacked structure 30. For example, as... Figure 31 As shown, column structure 40 covers the top and side surfaces of the stacked structure.

[0089] Reference Figure 2 and Figure 32 An insulating layer 48 may be formed to extend vertically through the column structure 40. In one exemplary embodiment, the process of forming the insulating layer 48 may include a patterning process and a thin film formation process. The lower end of the insulating layer 48 may be in direct contact with the first insulating layer 23. For example, the lower end of the insulating layer 48 may be in direct contact with the top surface of the first insulating layer 23.

[0090] Reference Figure 2 and Figure 33 A second insulating layer 52 can be formed on the stacked structure 30. The pillar structure 40 can be divided into several parts by the insulating layer 48 and the second insulating layer 52.

[0091] Reference Figure 2 and Figure 3 A third to fifth insulating layers 53, 54 and 55, a plurality of source plugs 61, a plurality of bit plugs 63, a plurality of source lines 65 and a bit line 67 may be formed on the column structure 40, the isolation insulating layer 48 and the second insulating layer 52.

[0092] Figure 34 This is a top view illustrating a method for forming a semiconductor memory device according to an exemplary embodiment of the concept of the present invention. Figures 35 to 37 It is shown Figure 34 A cross-sectional view of the method for forming a semiconductor memory device shown.

[0093] Reference Figure 34 and Figure 35 A lower conductive layer 125 can be formed on the substrate 121. A stacked structure 130 can be formed on the lower conductive layer 125. The stacked structure 130 may include a plurality of insulating layers 33 and a plurality of interconnect layers W1 to Wn that are stacked alternately and repeatedly. A plurality of vias 140H may be formed to extend through the stacked structure 130 in the vertical direction.

[0094] Reference Figure 34 and Figure 36 Multiple pillar structures 140 can be formed within multiple channel vias 140H. Multiple pads 62 can be formed on the multiple pillar structures 140. The upper ends of the multiple pillar structures 140 can be formed at a level lower than the upper surface of the stack structure 130. The upper ends of the multiple pads 62 and the upper ends of the multiple insulating layers 33 can be substantially coplanar. As previously described, each of the multiple pillar structures 140 may include a gate dielectric layer 142, a channel layer 143, a variable resistance layer 144, and an insulating pillar 145.

[0095] A variable resistance layer 144 may surround the side surface and bottom of the insulating pillar 145. A channel layer 143 may surround the side surface and bottom of the variable resistance layer 144. A gate dielectric layer 142 may surround the side surface of the channel layer 143. The channel layer 143 may extend through the gate dielectric layer 142 and directly contact the underlying conductive layer 125. Each of the plurality of pads 62 may directly contact the channel layer 143.

[0096] Reference Figure 12 and Figure 37 An insulating layer 148 may be formed to intersect with the plurality of pads 62, the plurality of pillar structures 140, and the stacked structure 130, and extend vertically through the plurality of pads 62, the plurality of pillar structures 140, and the stacked structure 130. The insulating layer 148 may extend vertically through the plurality of pads 62, the insulating pillars 145, the variable resistance layer 144, the channel layer 143, and the gate dielectric layer 142, and contact the underlying conductive layer 125.

[0097] Refer again Figure 12 and Figure 13 A third insulating layer 53, multiple bit plugs 63, and bit lines 67 can be formed on multiple bit pads 62, stacked structure 130, and isolation insulating layer 148.

[0098] Figure 38 This is a top view illustrating a method for forming a semiconductor memory device according to an exemplary embodiment of the concept of the present invention. Figures 39 to 41 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 38 A cross-sectional view of a method for forming a semiconductor memory device is shown in the figure.

[0099] Reference Figure 38 and Figure 39 A lower conductive layer 225 can be formed on the substrate 221. A stacked structure 230 can be formed on the lower conductive layer 225. An insulating layer 248 can be formed to intersect the stacked structure 230 and extend through the stacked structure 230 in a vertical direction. For example, multiple insulating layers 248 can be formed parallel to each other and spaced apart in a direction perpendicular to their extension direction. The stacked structure 230 can be divided into several parts by the insulating layers 248. The lower end of the insulating layer 248 can contact the lower conductive layer 225 (e.g., the upper surface of the lower conductive layer 225). The stacked structure 230 can include multiple insulating layers 33 and multiple interconnect layers W1 to Wn that are stacked alternately and repeatedly.

[0100] Reference Figure 15 and Figure 40 Multiple pillar structures 240 may be formed to intersect with and extend vertically through the stack structure 230 and the insulating layer 248. As previously described, each of the multiple pillar structures 240 may include a gate dielectric layer 242, a channel layer 243, a variable resistance layer 244, and an insulating pillar 245. Multiple pads 62 may be formed on the multiple pillar structures 240. For example, pads 62 may be formed on the top surface of the pillar structure 240.

[0101] Reference Figure 15 and Figure 41 The pad isolation layer 249 can be formed to extend through the plurality of pads 62. The pad isolation layer 249 can be formed to extend through the plurality of pads 62 and can have a bottom surface disposed in the upper region of the insulating post 245 of the post structure.

[0102] Refer again Figure 15 and Figure 16 A third insulating layer 53, multiple bit plugs 63, and bit lines 67 can be formed on the stacked structure 230, the isolation insulating layer 248, the multiple bit pads 62, and the pad isolation layer 249.

[0103] Figure 42 and Figure 43 This is a cross-sectional view illustrating a method for forming a semiconductor memory device according to an exemplary embodiment of the present invention.

[0104] Reference Figure 42A first insulating layer 623 may be formed on a substrate 621. A plurality of insulating layers 633 and a plurality of insulating isolation layers 648 may be alternately and repeatedly stacked on the first insulating layer 623 in a direction perpendicular to the top surface of the substrate 621. Each of the plurality of insulating isolation layers 648 may be formed between the plurality of insulating layers 633. The plurality of insulating isolation layers 648 may include a material having etch selectivity relative to the plurality of insulating layers 633. For example, the plurality of insulating layers 633 may include silicon oxide, and the plurality of insulating isolation layers 648 may include silicon nitride. However, exemplary embodiments of the inventive concept are not limited thereto.

[0105] Reference Figure 43 Multiple insulating layers 633 and multiple isolation insulating layers 648 can be patterned to form multiple gate trenches GT. The multiple isolation insulating layers 648 exposed within the multiple gate trenches GT can be selectively etched to form multiple undercut regions UC. Each of the multiple undercut regions UC can be formed between the multiple insulating layers 633. Each of the multiple undercut regions UC can communicate with a corresponding one of the multiple gate trenches GT. Each of the multiple isolation insulating layers 648 can be retained between the multiple undercut regions UC. Side surfaces of the multiple isolation insulating layers 648 extending in a direction perpendicular to the top surface of the substrate 621 can be exposed within the multiple undercut regions UC.

[0106] Refer again Figure 19 and Figure 21 Multiple memory layers M1 to Mn can be formed within multiple undercut regions UC. Each of the multiple memory layers M1 to Mn may include a channel layer 643 and a variable resistor layer 644. Multiple gate structures G1 to Gn can be formed within multiple gate trenches GT.

[0107] According to an exemplary embodiment of the present invention, a pillar structure may be disposed on the side surface of a stacked structure. The pillar structure may include an insulating pillar, a variable resistance layer, a channel layer, and a gate dielectric layer. The channel layer may be disposed between the variable resistance layer and the gate dielectric layer. Therefore, a semiconductor memory device with high integration density and low power consumption can be provided.

[0108] Although exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the inventive concept and without changing its essential characteristics. Therefore, the above exemplary embodiments should be considered in a descriptive sense only and not for limiting purposes.

[0109] This application claims priority to Korean Patent Application No. 10-2019-0048981, filed on April 26, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a stack structure including a plurality of insulating layers and a plurality of interconnection layers alternately and repeatedly stacked on a substrate, wherein an uppermost insulating layer of the plurality of insulating layers is disposed directly above an uppermost interconnection layer of the plurality of interconnection layers; and a pillar structure disposed on a side surface of the stack structure, wherein the pillar structure includes: an insulating pillar; a variable resistance layer disposed on the insulating pillar and between the insulating pillar and the stack structure; a channel layer disposed on the variable resistance layer and between the variable resistance layer and the stack structure; and a gate dielectric layer disposed on the channel layer and between the plurality of interconnection layers and the channel layer, wherein the channel layer is disposed between the variable resistance layer and the gate dielectric layer, and wherein a height from an upper surface of the substrate to upper surfaces of the insulating pillar, the variable resistance layer, the channel layer, and the gate dielectric layer is greater than a height from the upper surface of the substrate to an upper surface of the uppermost insulating layer, respectively. 3.The semiconductor memory device of claim 1, wherein the variable resistance layer is in direct contact with the channel layer.

2. The semiconductor memory device of claim 1, wherein the variable resistance layer comprises at least one compound selected from the group consisting of: NiO, CuO, CoO, Fe203, HfO, Ti02, Ta205, Nb205, SrTi03 (STO), SrZr03, A10, SiO, SiN, lanthanum strontium manganese oxide (LSMO), lanthanum calcium manganese oxide (LCMO), praseodymium calcium manganese oxide (PCMO), praseodymium lanthanum calcium manganese oxide (PLCMO), yttrium barium copper oxide (YBCO), bismuth strontium calcium copper oxide (BSCCO), Bi: SrTi03, Cr: SrTi03, HfSiO, AlSiO, tungsten oxide (WO), Mott, GeSbTe, carbon (C) doped GeSbTe, nitrogen (N) doped GeSbTe, SnSbTe, GeAsTe, GeSbSe, GeTe-Sb2Te3, Zr 60 Al 15 Ni 25 and Fe-Co-B-Si-Nb. 4.The semiconductor memory device of claim 1, wherein the channel layer includes polysilicon. 5.The semiconductor memory device of claim 1, further comprising a bit line connected to a first end of the channel layer. 6.The semiconductor memory device of claim 1, further comprising a source line connected to a second end of the channel layer. 7.The semiconductor memory device of claim 1, wherein the gate dielectric layer is in direct contact with the plurality of interconnection layers and the channel layer. 8.A semiconductor memory device, comprising: a first stack structure and a second stack structure, each including a plurality of insulating layers and a plurality of interconnection layers alternately and repeatedly stacked; an isolation insulating layer disposed between the first stack structure and the second stack structure; and a pillar structure disposed between the first stack structure and the second stack structure and configured to extend through and contact the isolation insulating layer, and including a region partially covering upper surfaces of the first stack structure and the second stack structure, wherein the pillar structure includes: an insulating pillar; a first variable resistance layer disposed on the insulating pillar and between the insulating pillar and the first stack structure; a second variable resistance layer disposed on the insulating pillar and between the insulating pillar and the second stack structure; a first channel layer disposed on the first variable resistance layer and between the first variable resistance layer and the first stack structure; a second channel layer disposed on the second variable resistance layer and between the second variable resistance layer and the second stack structure; a first gate dielectric layer disposed on the first channel layer and between the first channel layer and the first stack structure; and a second gate dielectric layer disposed on the second channel layer and between the second channel layer and the second stack structure. ​ ​ 9.The semiconductor memory device of claim 8, wherein the second channel layer is continuous with the first channel layer. 10.The semiconductor memory device of claim 9, further comprising a bit line connected to a first end of the first channel layer and a source line connected to a second end of the second channel layer. 11.The semiconductor memory device of claim 9, wherein the second variable resistance layer is continuous with the first variable resistance layer. 12.The semiconductor memory device of claim 8, wherein the first variable resistance layer is in direct contact with the insulating pillar and the first channel layer, and the second variable resistance layer is in direct contact with the insulating pillar and the second channel layer. 13.The semiconductor memory device of claim 8, wherein the first gate dielectric layer is in direct contact with the plurality of interconnection layers of the first stack structure and the first channel layer, and the second gate dielectric layer is in direct contact with the plurality of interconnection layers of the second stack structure and the second channel layer. 14.The semiconductor memory device of claim 8, wherein a lateral width of the isolation insulating layer is greater than a lateral width of the pillar structure. 15.The semiconductor memory device of claim 14, wherein the isolation insulating layer is in direct contact with the first stack structure and the second stack structure. 16.The semiconductor memory device of claim 8, wherein a lateral width of the isolation insulating layer is less than a lateral width of the pillar structure. 17.The semiconductor memory device of claim 16, wherein the first gate dielectric layer extends between the isolation insulating layer and the first stack structure, and the second gate dielectric layer extends between the isolation insulating layer and the second stack structure. 18.A semiconductor memory device, comprising: a lower conductive layer; a stack structure including a plurality of insulating layers and a plurality of interconnection layers alternately and repeatedly stacked on the lower conductive layer; a pillar structure configured to extend through the stack structure in a vertical direction; and an isolation insulating layer configured to intersect the stack structure and the pillar structure and extend through and contact the stack structure and the pillar structure in the vertical direction, wherein the pillar structure includes: an insulating pillar; a variable resistance layer disposed on the insulating pillar and between the insulating pillar and the stack structure; a channel layer disposed on the variable resistance layer and between the variable resistance layer and the stack structure; and a gate dielectric layer disposed on the channel layer and between the plurality of interconnection layers and the channel layer, wherein the channel layer is disposed between the variable resistance layer and the gate dielectric layer, and wherein the isolation insulating layer extends in the vertical direction to contact the lower conductive layer, thereby separating the channel layer into a first channel layer and a second channel layer. 19.The semiconductor memory device of claim 18, wherein the isolation insulating layer extends through the insulating pillar, the variable resistance layer, the channel layer, and the gate dielectric layer in the vertical direction.

20. The semiconductor memory device of claim 18, further comprising a bit line connected to a first end of the channel layer.

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