Memory element and method for manufacturing the same

Abstract

A memory element and a method for manufacturing the same, wherein the memory element comprises a plurality of word lines of a plurality of stacks alternately stacked with a plurality of insulating strips, wherein the stacks are separated by a plurality of trenches, and the word lines extend along a first direction. A plurality of vertical conductor structures are located in the trenches between adjacent stacks. A plurality of layers of memory materials and a layer of channel materials are located on the sidewalls of the word lines on at least one side of the trenches, wherein the trenches are located between adjacent vertical conductor structures, and the layer of channel materials are in ohmic contact with the vertical conductor structures. At the positions of the vertical conductor structures, the sidewalls of the word lines are recessed between the insulating strips to form a plurality of depressions on the sidewalls of the word lines, thereby separating the word lines from the vertical conductor structures.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory devices, and relates to a high-density memory element and a manufacturing method thereof, and in particular to a 3D stereoscopic array memory element with multi-layer memory cells and a manufacturing method thereof. Background Art

[0002] As the critical dimensions of devices of common memory cells in integrated circuits shrink to the limits of technology, designers have been looking for technologies to stack multiple memory cell planes to achieve greater storage capacity and lower cost per bit. For example, thin film transistor technology is used in Lai et al., "Multi-layer Stackable Thin Film Transistor (TFT) NAND Flash Memory Technology," IEEE International Electron Devices Meeting, December 11-13, 2006; and in Jung et al., "Three-dimensional Stacked NAND Flash Memory Technology Using Stacked Single Crystal Silicon Layers on ILD and TANOS Structures Beyond the 30nm Node," IEEE International Electron Devices Meeting, December 11-13, 2006.

[0003] Planar NOR flash is a random access memory for high-speed applications, but has limited density. Three-dimensional stacked NAND flash has higher density than planar NOR flash, but is not a random access memory and has a relatively low operating speed.

[0004] Therefore, the related art expects to have a technology of a three-dimensional stacked integrated circuit memory with higher density, higher random access and higher operating speed. Summary of the invention

[0005] In an embodiment of the present specification, a memory element includes a plurality of word lines and a plurality of insulating strips alternately stacked in a plurality of stacks, the stacks are separated by a plurality of trenches, and the word lines extend along a first direction. A plurality of vertical conductor structures are located in the trenches between adjacent stacks. A plurality of layers of memory material and channel material are located on the sidewalls of the word lines on at least one side of the trenches, the trenches are located between adjacent vertical conductor structures, and the layers of channel material are in ohmic contact with the vertical conductor structures. At the locations of the vertical conductor structures, the sidewalls of the word lines are recessed between the insulating strips to form a plurality of depressions on the sidewalls of the word lines, thereby separating the word lines from the vertical conductor structures.

[0006] In other embodiments of the present disclosure, the memory element further includes an insulating material located in the recesses on the sidewalls of the word lines.

[0007] In other embodiments of the present specification, the channels have a first width in a second direction, the second direction being perpendicular to the first direction, and the vertical conductor structures have a second width in the second direction, the second width being greater than the first width.

[0008] In other embodiments of the present specification, a specific vertical conductor structure is in ohmic contact with a first layer and a second layer of the channel materials, and the first layer and the second layer are opposite to each other along the first direction and across the specific vertical conductor structure.

[0009] In other embodiments of the present specification, the memory element further includes a plurality of bit line transistors covering and connected to the corresponding vertical conductor structures, and a plurality of bit lines covering and connected to the bit line transistors in corresponding rows of the bit line transistors, wherein the bit lines extend along a second direction perpendicular to the first direction.

[0010] In other embodiments of the present specification, the memory element further includes a memory element, further including a plurality of gate lines located at the same level as the bit line transistors and connected to the bit line transistors in corresponding columns of the bit line transistors, and the gate lines extend along the first direction.

[0011] In other embodiments of the present specification, the bit line transistors include a plurality of channel layers, and the lower ends thereof are connected to the corresponding vertical conductor structures, and the bit lines are connected to the corresponding upper ends of the channel layers of the bit line transistors in the corresponding row through a plurality of plugs.

[0012] In other embodiments of the present disclosure, the memory device further includes circuits connected to the bit lines, so as to apply a first voltage and a second voltage to the bit lines.

[0013] In other embodiments of the present specification, the circuit is used to select a specific memory cell having a drain in a first vertical conductive structure, a source in a second vertical conductive structure, and a channel in a specific channel material layer that is in ohmic contact with the first and second vertical conductive structures, the channel being disposed on the sidewall of a specific word line, and includes: turning on a first bit line transistor, the first bit line transistor being connected to the first vertical conductor structure and a second bit line transistor, the second bit line transistor being connected to the second vertical conductor structure; applying the first voltage to a first bit line, the first bit line being connected to the first vertical conductor structure; applying the second voltage to a second bit line, the second bit line being connected to the second vertical conductor structure; and applying a word line voltage to the specific word line.

[0014] In other embodiments of the present disclosure, the insulating material within the recesses on the sidewalls of the word lines includes a dielectric material.

[0015] In other embodiments of the present disclosure, the insulating material within the recesses on the sidewalls of the word lines includes oxides of the word lines.

[0016] In an embodiment of the present specification, a method for manufacturing a memory element includes the following steps: forming a plurality of stacks of alternately stacked word lines and a plurality of insulating strips, the stacks being separated by a plurality of trenches, the word lines extending along a first direction; forming a plurality of layers of memory material and channel material, the sidewalls of the word lines being located on at least one side of the trenches; etching a plurality of holes through the layers of memory material and the channel material; etching a plurality of recesses on the sidewalls of the word lines between the insulating strips; and forming a plurality of vertical conductor structures located in the trenches between adjacent stacks, wherein the recesses separate the word lines from the vertical conductor structures.

[0017] In an embodiment of the present disclosure, the memory device manufacturing method further includes forming an insulating material in the recesses on the sidewalls of the word lines.

[0018] In an embodiment of the present specification, in a memory element manufacturing method, the channels have a first width in a second direction perpendicular to the first direction, and the vertical conductor structures have a second width in the second direction greater than the first width.

[0019] In an embodiment of the present specification, the memory device manufacturing method further includes filling the trenches with an insulating material to cover the channel material; and etching the holes includes etching through the insulating material in the trenches.

[0020] In an embodiment of the present specification, the memory element manufacturing method further includes forming a plurality of bit line transistors covering and connected to the corresponding vertical conductor structures; and forming a plurality of bit lines covering and connected to the bit line transistors of corresponding rows of the bit line transistors, wherein the bit lines extend along a second direction perpendicular to the first direction.

[0021] In an embodiment of the present specification, the memory device manufacturing method further includes forming a plurality of gate lines located at the same level of the bit line transistors and connected to the bit line transistors in corresponding columns of the bit line transistors, wherein the gate lines extend along the first direction.

[0022] In the embodiments of the present specification, forming these bit line transistors also includes: forming a first insulating layer covering these word lines of these stacks and covering the top surfaces of these vertical conductor structures; forming a horizontal conductive layer covering the first insulating layer; forming a second insulating layer covering the horizontal conductive layer; and etching the first insulating layer, the horizontal conductive layer and the second insulating layer to separate the horizontal conductive layer into the gate line, which covers and is insulated from the vertical conductor structures of the corresponding columns.

[0023] In an embodiment of the present specification, the memory element manufacturing method further includes etching a plurality of holes through the gate line located on the top surface of the vertical conductor structures and stopping at the top surface; forming insulating spacers on the side walls of the holes; forming a film layer of the channel material to cover the insulating spacers, wherein the lower end of the film layer of the channel material is connected to the vertical conductor structure; filling insulating material into the holes; and forming a landing pad connected to the upper end of the corresponding film layer of the channel material.

[0024] In an embodiment of the present specification, forming these bit lines also includes: forming a third insulating layer on these bit line transistors; etching a plurality of holes through the insulating layer located at these bit line transistors and stopping at these landing pads; forming a plurality of plugs in these holes, and the plugs cover and connect to the landing pads; forming a conductive layer located on these plugs; and etching the conductive layer to form a plurality of word lines.

[0025] The above description will be described in detail below with reference to implementation examples, and a further explanation will be provided for the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0027] Figure 1A , Figure 1B , Figure 1C as well as Figure 1D A simplified cross-sectional view of a memory device according to an embodiment of the present disclosure is shown;

[0028] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A as well as Fig. 12B The stages of the memory simplification process flow according to the embodiment of the present disclosure are illustrated;

[0029] Figure 2 depicts the stage in the process flow after the conductive layer stack is formed;

[0030] Figure 3A , Figure 3B depicts a stage in the process flow after forming a plurality of word line stacks;

[0031] Figure 4A , Figure 4B depicts a stage in the process flow after forming a multi-layer film of memory material and channel material disposed on the sidewalls of the word lines;

[0032] Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B depicts stages in a process flow for forming vertical conductive structures disposed in trenches between adjacent wordline stacks;

[0033] Figure 5A , Figure 5B , Figure 5C depicts a stage in the process flow after etching holes between wordline stacks through multiple films of memory material and channel material;

[0034] Fig. 6A , Figure 6B depicts a stage in the process flow after etching a recess on the sidewalls of a word line in the stack;

[0035] Fig. 7A , Figure 7B depicts a stage in the process flow after forming an insulating material in a recess through a hole;

[0036] Fig. 8A , Figure 8B depicts a stage in the process flow after forming a plurality of rows of vertical conductive structures disposed in the trenches;

[0037] Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B illustrates stages in a process flow for forming a plurality of bit line transistors disposed on and connected to corresponding vertical conductive structures;

[0038] Fig. 12A , Fig. 12B depicts a stage in the process flow after forming a plurality of bit lines disposed over and connected to each row of bit line transistors;

[0039] Fig.13A schematic diagram is shown for selecting a memory cell from a NOR memory cell array;

[0040] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D depicts stages of a simplified process flow for fabricating a memory device in an alternative embodiment;

[0041] Fig.14E , Fig.14F illustrates stages of a simplified process flow for fabricating a memory device in another alternative embodiment;

[0042] Fig.15 A simplified flow chart showing the process of manufacturing an integrated circuit memory device; and

[0043] Fig.16 A simplified functional block diagram of an integrated circuit memory element in accordance with the present technique is shown.

[0044]

Explanation of symbols

[0045] D: Drain

[0046] S: Source

[0047] 100: Memory components

[0048] 111, 112: Width

[0049] 191-195: Storage unit

[0050] 201: Base material

[0051] 202: Insulation layer

[0052] 220: Hard mask

[0053] 305: Insulation tape

[0054] 311-315, 321-325, 331-335: word lines

[0055] 351, 361: Channel

[0056] 363, 373, 383, 393, 303: word lines

[0057] 405, 406: Side wall

[0058] 420: Channel Materials

[0059] 430: Insulation material

[0060] 570T, 580T, 590T, 500T: Channel

[0061] 501-502, 551-552, 561-562, 571-573, 581-582, 591-593: Hole

[0062] 511, 512: Memory materials

[0063] 521, 522: Channel material

[0064] 751: Insulation materials

[0065] 851-854, 861-864, 871-874, 881-884: Vertical conductor structure

[0066] 910: Conductive layer

[0067] 905, 915: Insulation layer

[0068] 1051, 1061, 1071, 1081: Gate lines

[0069] 1110, 1120: Bit line transistors

[0070] 1141: Insulation materials

[0071] 1151-1152, 1161-1162: Landing pad

[0072] 1020, 1210: Insulation layer

[0073] 1251, 1261: Plug

[0074] 1301, 1302: Storage unit

[0075] 1311-1314, 1321-1324, 1331-1334, 1341-1344: Bit line transistors

[0076] 1231-1234: bit line

[0077] 1411, 1412, 1421, 1422: film layer

[0078] 1431, 1432, 1441, 1442: film layer

[0079] 1401: Channel

[0080] 1410: Hole

[0081] 1415: Width

[0082] 1450, 1460: Insulation materials

[0083] 1461A, 1462A: Depression

[0084] 1413: Dashed circle

[0085] 1461, 1462: word line

[0086] 1471, 1472: Dielectric materials

[0087] 1480: Vertical conductor structure

[0088] 1491, 1492: Oxide

[0089] 1510-1570: Steps

[0090] 1600: Integrated Circuits

[0091] 1650: Bit Line Decoder

[0092] 1652: Circuit

[0093] 1655: Bit line

[0094] 1660: Memory Array

[0095] 1663: Word line decoder

[0096] 1664: Word Line

[0097] 1665: Bus

[0098] 1666: Box

[0099] 1668: Box

[0100] 1669: Controller

[0101] 1671: Data input line

[0102] 1674: Other circuits DETAILED DESCRIPTION

[0103] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0104] This specification provides a method for manufacturing a three-dimensional memory element, which can obtain a higher storage capacity in a smaller element size while taking into account the operational stability of the element. In order to make the above embodiments and other purposes, features and advantages of this specification more clearly understandable, a memory element and its manufacturing method are specifically cited as a preferred embodiment, and are described in detail with the accompanying drawings.

[0105] However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention may still be implemented using other features, components, methods and parameters. The preferred embodiments are only intended to illustrate the technical features of the present invention and are not intended to limit the scope of protection of the present invention. A technician with common knowledge in the technical field will be able to make equal modifications and changes based on the description of the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0106] Figure 1A , Figure 1B , Figure 1C as well as Figure 1D A simplified cross-sectional view of a memory device according to an embodiment of the present disclosure is shown. Figure 1A is a simplified vertical cross-sectional view of the memory element 100, along the Figure 1C The line AA' shown is taken. Figure 1A As shown in the embodiment of the present invention, the memory element 100 includes a stack of a plurality of insulating strips 305 and word lines (311-315, 321-325, 331-335) alternating with each other. The stack may be disposed on an insulating layer 202 on a substrate 201. The stack is formed by channels (351, 361, Figure 1C ) are separated. The word lines extend in a first direction (Y direction) perpendicular to the XZ plane. A hard mask 220 may be disposed on top of the stack of word lines.

[0107] Multiple rows of vertical conductor structures may be disposed in the trenches between adjacent stacks. For example, a first vertical conductor structure 851 may be disposed between a first stack including word lines 311-315 and a second stack including word lines 321-325. Similarly, a second vertical conductor structure 861 may be disposed between a second stack including word lines 321-325 and a third stack including word lines 331-335.

[0108] In one embodiment, the conductor material filling the hole may include N+ polysilicon. Other embodiments may include metals, metal nitrides, other metal compounds, or combinations of metals and metal compounds, such as platinum, tantalum nitride, metal silicide, aluminum, or other metal or metal compound gate materials (e.g., Ti, TiN, Ta, Ru, Ir, RuO2, IrO2, W, WN), etc. For some applications, it is preferred to use materials with a work function higher than 4 eV, or preferably, materials with a work function higher than 4.5 eV.

[0109] The insulating material 751 may be disposed in a recess on a sidewall of the word line in a stack between the word line (313, 323) and the vertical conductor structure 851, wherein the word line is recessed relative to the vertical conductor structure.

[0110] Figure 1B is a simplified vertical cross-sectional view of the memory element 100, along the Figure 1C The line BB' shown is intercepted. Figure 1B As shown in the example of FIG. 5 , the channel material 522 is disposed on the sidewalls of the stack, and the memory material 512 is disposed between the channel material and the stack. Figure 1C ) can be filled with insulating material 430 to cover the channel material 522.

[0111] The channel material may include undoped polysilicon or P-type doped polysilicon. The memory material 512 may include a multi-layer dielectric charge trapping structure known from flash memory technology, such as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide-nitride-oxide), SONOS (silicon oxide-nitride-oxide-silicon), BE-SONOS (band engineered silicon-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide), and MA BE-SONOS (metal high dielectric constant band engineered silicon-silicon oxide-nitride-oxide-silicon) or other charge trapping layers or combinations of these layers.

[0112] Figure 1C is a simplified horizontal cross-sectional view of memory element 100, taken from Figure 1A and Figure 1B The horizontal lines of word lines 313, 323, 333. Figure 1C As shown in the embodiment, the storage unit 193 has a drain in the first vertical conductor structure 861, a source in the second vertical conductor structure 862, and a channel in the semiconductor layer of the channel material. The channel material is ohmically contacted to the first and second vertical conductor structures and is arranged on the side walls of the word line 333.

[0113] like Figure 1C As shown in the example of FIG. 1 , the film layer of the channel material (e.g., 521, 522) is disposed on the sidewalls of the stack between adjacent vertical conductor structures (851, 852) along the first direction. The film layer of the channel material (e.g., 521) in a specific channel (351) on one side of a specific vertical conductor structure (851) in the specific channel is discontinuous with the film layer of the channel material (e.g., 522) on the opposite side thereof.

[0114] Figure 1D is a simplified schematic diagram of a vertical string of memory cells (191-195), including Figure 1C The storage unit 193 shown. Figure 1DAs shown in the example of FIG. 1 , the memory cells in the vertical string of memories have a drain D in the first vertical conductor structure 861 and a source S in the second vertical conductor structure 862. Each memory cell in the vertical string of memories has a channel with ohmic contacts to the first and second vertical conductor structures. The memory cells (191-195) in the vertical string of memories have gates connected to corresponding word lines (331-335).

[0115] A particular film layer of channel material 522 is in ohmic contact with the first vertical conductor structure 851 and the second vertical conductor structure 852. A second particular film layer of channel material 522L is in contact with the first vertical conductor structure 851 and the second vertical conductor. The first and second vertical conductor structures are disposed on opposite sidewalls of the stack of word lines (313, 323) across channel 351.

[0116] The channel may have a first width 111 in a second direction (X direction) perpendicular to the first direction (Y direction). The vertical conductor structure may have a second width 112 in the second direction that is greater than the first width.

[0117] like Figure 1C As shown in the example, the specific vertical conductor structure 851 is ohmically contacted to the first film layer of the channel material 521 and the second film layer of the channel material 522, wherein the first and second film layers of the channel material are arranged opposite to each other and cross the specific vertical conductor structure 851 along the first direction.

[0118] like Figure 1A As shown in the example of, the memory element 100 may include a plurality of bit line transistors (1110, 1120) located in the insulating layer 1020, which are arranged on the corresponding vertical conductor structure (851, 861) and connected to the corresponding vertical conductor structure (851, 861). The memory element 100 may include a plurality of bit lines 1231, which are arranged above the bit line transistors (1110, 1120) of the corresponding rows among the plurality of bit line transistors, and the plurality of bit lines 1231 cover and are connected to the bit line transistors (1110, 1120) of the corresponding rows of the plurality of bit line transistors (1110, 1120), wherein the bit lines extend along the second direction (X direction). The plurality of gate lines (1051, 1061, 1071, 1081, Figure 1A , Figure 1B 14) are arranged at the same level as the bit line transistors and connected to the bit line transistors of the corresponding columns. The gate lines extend along a first direction.

[0119] The bit line transistors (1110, 1120) may include a channel layer, the lower end of which is connected to the corresponding vertical conductor structure (851, 861). The bit line 1231 is connected to the corresponding upper end of the channel layer of the bit line transistors (1110, 1120) of each row via the plug (1251, 1261). The landing pad (1151, 1161) may be disposed at the upper end of the channel layer and in contact with the channel layer, and the plug (1251, 1261) may be disposed above the landing pad and in contact with it. The bit line transistors and the bit lines will be described in detail below with reference to Fig. 12A , Fig. 12B , Figure 14 further describes.

[0120] Although not in Figure 1A , Figure 1B , Figure 1C and Figure 1D , but the memory element includes circuits connected to the bit lines in the stack (1652, Fig.16 ), whereby the first and second voltages are applied to the bit line. In one embodiment, the first voltage may be a drain side voltage (eg, VCC), and the second voltage may be a source side voltage (eg, 0V).

[0121] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A as well as Fig. 12B The diagram shows the stages of a memory simplification process flow according to an embodiment of the present disclosure.

[0122] Figure 2 The process flow is shown after forming a stack of conductive layers 211-215 alternating with insulating layer 205 on insulating layer 202 on substrate 201. In one embodiment, the conductive layers may include N+ polysilicon. A hard mask 220 may be formed on top of the stack of conductive layers.

[0123] Figure 3A , Figure 3BFIG. 1 shows a stage in the process flow after forming a plurality of word line stacks. The platform may include patterning the lines of the hard mask and then etching the conductive layers 211-215 ( Figure 2 ) and stop on the insulating layer 202 to form a plurality of stacked word lines (311-315, 321-325, 331-335) alternating with insulating strips 305. The stacked word lines are separated by trenches (351, 361) that pass through the conductive layer to the insulating layer 202. In the present embodiment, the word lines extend along a first direction (Y direction).

[0124] Figure 3A is a top view of an example structure at this stage of processing, depicting word lines ( 313 , 323 , and 333 ) and trenches ( 351 , 361 ) passing through the stack of conductive layers to expose insulating layer 202 . Figure 3B It is along Figure 3A 1 and 2. A vertical cross-sectional view taken along line BB' is shown, wherein line BB' extends in a second direction (X direction) perpendicular to the first direction. Figure 3B A stack of alternating word lines ( 311 - 315 , 321 - 325 , 331 - 335 ) and insulating strips 305 is depicted, with trenches ( 351 , 361 ) extending vertically from the hard mask 220 through the conductive layers of the stack to the insulating layer 202 .

[0125] Figure 4A , Figure 4B A stage in the process flow is depicted after forming multiple layers of films of memory material and channel material on the sidewalls of the wordline. This stage may include depositing memory material 410 on the sidewalls (405, 406) of the wordline stack (e.g., 323, 333), and depositing channel material 420 on the memory material 410 on the sidewalls. The trenches (351, 361) are then filled with insulating material 430 on the channel material 420. A chemical mechanical planarization (CMP) process may then be applied to the structure, stopping on the hard mask 220 on top of the wordline stack.

[0126] Figure 4A is a top view of an example structure at this stage of processing, depicting memory material 410 on the sidewalls ( 405 , 406 ) of the wordline stack and channel material 420 overlying memory material 410 . Figure 4B is along Figure 4A A vertical cross-sectional view taken along line BB′ shown in FIG.

[0127] Figure 4BThe memory material 410 on the sidewalls of the stack, the channel material 420 on the memory material on the sidewalls of the stack, and the insulating material 430 filling the trenches (351, 361) are shown. The memory material 410 and the channel material 420 are continuous on the sidewalls and bottom surfaces of the trenches 351 / 361 of the adjacent stacks, where the trenches 351 / 361 are on the top surface of the insulating layer 202. The memory material 410 and the channel material 420 are continuous from the sidewalls of the trenches 351 / 361 of the adjacent stacks to their bottom surfaces.

[0128] The word lines (311-315, 321-325, 331-335) of adjacent stacks may be physically or electrically separated from each other, such as by insulating material 430 in the trench, so that the adjacent word line stacks may operate independently. For example, the first stack of word lines 311-315 is physically separated from the second stack of word lines 321-325, and the second stack is physically separated from the third stack of word lines 331-335. The sidewalls of the word lines of adjacent stacks are physically separated from each other. For example, the sidewall 405 on the second stack of word lines 321-325 is physically separated from the sidewall 406 on the adjacent third stack of word lines 331-335.

[0129] The channel material 420 may include undoped polysilicon or P-type doped polysilicon. The memory material 410 may include a multi-layer dielectric charge trapping structure known from flash memory technology, such as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide-nitride-oxide), SONOS (silicon oxide-nitride-oxide-silicon), BE-SONOS (band engineered silicon-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide), and MA BE-SONOS (metal high dielectric constant band engineered silicon-silicon oxide-nitride-oxide-silicon) or other charge trapping layers or combinations of these layers.

[0130] Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B A method for forming a vertical conductive structure (eg, Fig. 8A , Figure 8B 851, 861) stages in the process flow.

[0131] Figure 5A , Figure 5B , Figure 5CMarked in the memory material 410 ( Figure 4A , Figure 4B ) and channel material 420 ( Figure 4A , Figure 4B ) is a stage in the process flow after etching holes (551-552, 561-562) in the word lines of the multilayer film stack. These holes in the sidewalls of the stack pass through the sidewalls (405, 406) of the word lines and through the insulating material 430 in the trench (351, 361). Figure 5A is a top view of the structure at this stage. Figure 5B is a vertical cross-sectional view of the structure passing through a row of holes (551, 561), taken along line AA′ extending in the second direction (X direction) (e.g. Figure 5A The etching step may stop on the insulating layer (202, Figure 5B ). The channel (351, 361) may have a first width 111 in the second direction (X direction). The hole may have a second width 112 greater than the first width 111 in the second direction.

[0132] These holes can be used to pass the channel material (420, Figure 4A , Figure 4B ) is separated into a first film layer (521) of a channel material and a second film layer (522) of a channel material, wherein the first and second film layers of the channel material are arranged opposite to each other across a specific hole (551) in a first direction. These holes can make the memory material (410, Figure 4A , Figure 4B ) is separated into a first film layer (511) of memory material and a second film layer (512) of memory material, wherein the first and second film layers of memory material are arranged opposite to each other across a specific hole (551) in a first direction.

[0133] Figure 5C An alternative layout of holes is depicted, where the holes (571-573, 581-582, 591-593, 501-502) may be arranged in a honeycomb pattern, allowing for an increased density of the memory cell array. Figure 5C Word lines (363, 373, 383, 393, 303) and channels (570T, 580T, 590T, 500T) are depicted through the stack of conductive layers. Holes (571-573, 581-582, 591-593, 501-502) pass through the memory material and channel material (410, 420, Figure 4A , Figure 4B ), and on the sidewalls of the stack, and through the sidewalls of the word lines (405, 406, Figure 4A ), and through the insulating material (430, Figure 4A). In this embodiment, the holes (571-573, 581-582, 591-593, 501-502) are arranged in a honeycomb shape.

[0134] Fig. 6A , Figure 6B The stage in the process flow is shown after a recess 651 is etched through a hole (551, 561) on the sidewalls of a word line (313, 323, 333) in the stack. The recess is disposed between vertically adjacent insulating strips 305 in the stack. Fig. 6A This is a top view of the structure at this stage. Fig. 6A It is shown with a dotted line in FIG. 6 to indicate that the recess 651 is not visible in the top view. Figure 6B is a vertical cross-sectional view of the structure through a row of holes (551, 561), along Fig. 6A The AA' line shown is intercepted. In one embodiment, the etching step can use a selective etching process and a cleaning solution, such as SC1 or NH4OH solution known in the art. Here, SC1 refers to a Standard Clean-1 procedure using, for example, a cleaning solution H2O2-NH4OH-H2O. NH4OH or SC1 etches the word lines (311-315, 321-325, 331-335) including N+ polysilicon much faster than the film layer of the channel material (521, 522).

[0135] Fig. 7A , Figure 7B The depression (651, Fig. 6A and Figure 6B ) is a stage in the process flow after an insulating material (751) is formed through holes (551, 561). Fig. 7A This is a top view of the structure at this stage. Insulation material 751 is Fig. 7A The dotted line in the figure indicates that the insulating material 751 is not visible in the top view. Figure 7B is a vertical cross-sectional view of the structure through a row of holes (551, 561), along Fig. 7A The AA′ line shown is intercepted. In one embodiment, this step may use conformal dielectric deposition. When the insulating material 751 is formed in the recess, the insulating material 751 may be deposited on the channel material through the hole. For example, the insulating material 751 may be formed on the first and second film layers (521, 522) of the channel material through a specific hole (551). After the insulating material 751 is formed in the recess, an isotropic isotropic etch may be applied to expose the film layer of the channel material through the hole, so that the film layer of the channel material can be connected to the vertical conductor structure (refer to Fig. 8A , Figure 8B ).

[0136] Fig. 8A , Figure 8B A stage in the process flow is shown after forming multiple rows of vertical conductor structures disposed in trenches between adjacent stacks of word lines. This stage may include filling the holes (551, 561, Fig. 7A , Figure 7B ), thereby forming a plurality of rows of vertical conductor structures (851-852, 861-862) disposed within the trenches (351, 361) and between adjacent stacks (313, 323, 333). Fig. 8A is a top view of the structure at this stage. Figure 8B is a vertical cross-sectional view of a structure passing through a row of vertical conductor structures (851, 861), along Fig. 8A A chemical mechanical planarization (CMP) process may then be applied to the structure, stopping at the hard mask 220 on top of the word line stack.

[0137] The insulating material 751 is disposed between the word lines (311-315, 321-325, 331-335) and the vertical conductor structures (851-852, 861-862), thereby isolating the word lines from the vertical conductor structures. The word lines are recessed relative to the vertical conductor structures.

[0138] like Fig. 8A As shown in the example of FIG. 3 , a specific film layer of channel material (522) contacts the first vertical conductor structure (851) and the second vertical conductor structure (852). A second specific film layer (522L) of channel material contacts the first vertical conductor structure (851) and the second vertical conductor structure (852). The first and second vertical conductor structures are arranged on opposite sidewalls of the stack of word lines (313, 323) across the channel 351.

[0139] The channel may have a first width 111 in a second direction (X direction) perpendicular to the first direction (Y direction). The vertical conductor structure may have a second width 112 in the second direction that is greater than the first width.

[0140] In one embodiment, the conductor material filling the hole may include N+ polysilicon. Other embodiments may include metals, metal nitrides, other metal compounds, or combinations of metals and metal compounds, such as platinum, tantalum nitride, metal silicide, aluminum, or other metal or metal compound gate materials (e.g., Ti, TiN, Ta, Ru, Ir, RuO2, IrO2, W, WN), etc. For some applications, it is preferred to use materials with a work function higher than 4 eV, preferably, materials with a work function higher than 4.5 eV.

[0141] Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B Stages in a process flow for forming a plurality of bit line transistors disposed above and connected to corresponding vertical conductive structures are shown.

[0142] Fig. 9A Fig. 9A , Fig. 9B The stage in the process flow is depicted after forming a first insulating layer (905) on the stack of word lines (311-315, 321-325, 331-335), forming a conductive layer (910) above the first insulating layer, and forming a second insulating layer (915) on the horizontal conductive layer 910. Fig. 9A is along Fig. 8A A vertical cross-sectional view of the structure taken along line AA′. Fig. 9A A horizontal conductive layer 910 is depicted above the stack of word lines and above the top surfaces of the vertical conductor structures (eg, 851, 861). Fig. 9B is along Fig. 8A A vertical cross-sectional view of the structure taken along line BB′. Fig. 9B The conductive layer 910 above the stack of word lines and the memory material 512 and the channel material 522 is shown. The memory material 512 and the channel material 522 are arranged adjacent to the vertical conductor structure (851, 852, Fig. 8A ) on the stacked sidewalls of the word lines between them.

[0143] Fig. 10A , Fig. 10B The process flow is shown after etching the first insulating layer 905, the horizontal conductive layer 910, and the second insulating layer 915 to separate the horizontal conductive layer into gate lines (1051, 1061). The gate lines (1051, 1061) cover and are insulated from the vertical conductor structures (851, 861) of the corresponding columns. The width of the gate lines can be narrower than the width of the vertical conductor structures (e.g., 851, 861) in the X direction. Fig. 10A is along Fig. 8A The gate line extends along the first direction (Y direction). Fig. 10B is along Fig. 8A A vertical cross-sectional view of the structure taken along line BB′.

[0144] Fig.11A , Fig. 11B Stages of a process flow for forming a bit line and a landing pad on a bit line transistor are depicted. Fig.11A is a top view of the structure, showing that the gate lines (1051, 1061) are covered by landing pads (1151-1152, 1161-1162) and connected to the vertical conductor structures (851-852, 861-862) of the corresponding columns. Fig. 11B Fig. 11B is along Fig.11A A vertical cross-sectional view of the structure taken along line AA′ shows the bit line transistors (1110, 1120) and the landing pads (1151, 1161).

[0145] The process flow may include etching a hole through a gate line (1051, 1061), which is located on the top surface of the vertical conductor structure (851, 861) and insulated therefrom, and the etching stops on the top surface. An insulating spacer (1121) may be formed on the sidewall of the hole through the gate line. A film layer of channel material 1131 may be formed on the insulating spacer on the sidewall of the hole, wherein the lower end of the film layer of the channel material is connected to the vertical conductor structure. Insulating material 1141 may be filled into the hole passing through the gate line. Landing pads (1151, 1161) may be formed on the insulating material 1141 and connected to the upper end of the corresponding film layer of the channel material.

[0146] Fig. 12A , Fig. 12B The invention shows a stage in a process flow after forming a plurality of bit lines (1231, 1232), which are arranged to cover and connect to a plurality of bit line transistors (1110, 1120) of corresponding rows. The bit lines extend in a second direction (X direction) perpendicular to a first direction (Y direction). The gate lines (1051, 1061) extend in the first direction. The bit line (1231) is connected to the bit line transistors (1110, 1120) of the corresponding row via plugs (1251, 1261) and landing pads (1151, 1161).

[0147] The process at this stage may include forming an insulating layer 1210 on the plurality of bit line transistors (1110, 1120), and etching holes through the insulating layer 1210 on the plurality of bit line transistors, the etching stopping on the landing pads (1151, 1161). Plugs (1251, 1261) may then be formed in the holes, wherein the plugs are arranged to cover and connect to the corresponding landing pads (1151, 1161). A conductive layer may be formed on the plugs, and the conductive layer is etched to form a plurality of bit lines (1231).

[0148] Fig.13 A schematic diagram showing the selection of a memory cell from a NOR array memory cell is shown. Fig.13As shown in the example of FIG. 1 , a plurality of bit line transistors (1311-1314, 1321-1324, 1331-1334, 1341-1344) are arranged to cover and connect to corresponding vertical conductor structures (851, 861, 871, 881; 852, 862, 872, 882; 853, 863, 873, 883; 854, 864, 874, 884). The vertical conductor structures (851-854, 861-864, 871-874, 881-884) are arranged in rows between adjacent word line (313, 323, 333, 343, 353) stacks. A plurality of bit lines (1231-1234) are provided to cover and connect to the bit line transistors (1311-1314, 1321-1324, 1331-1334, 1341-1344) of the corresponding rows, and the bit lines extend in a second direction (X direction) perpendicular to the first direction (Y direction).

[0149] Multiple gate lines (1051, 1061, 1071, 1081) of the bit line transistors are arranged at the same level of the bit line transistors and connected to multiple bit line transistors (1311, 1321, 1331, 1341; 1312, 1322, 1332, 1342; 1313, 1323, 1333, 1343; 1314, 1324, 1334, 1344) of corresponding columns, and these gate lines extend along a first direction.

[0150] The specific memory cell 1301 has a drain in the first vertical conductor structure 851, a source in the second vertical conductor structure 852, and a channel (522, Fig. 8A ), which is in ohmic contact with the first and second vertical conductor structures, wherein a specific film layer of the channel material is disposed on the sidewall of the specific word line 323.

[0151] A circuit (1652, connected to the bit lines (1231-1234) Fig.16 ) can apply the first and second voltages to the bit lines. To select a specific memory cell (e.g., 1301), the circuit can turn on the first bit line transistor 1311 connected to the first vertical conductor structure 851 and the second bit line transistor 1321 connected to the second vertical conductor structure 852. The first voltage can be applied to the first bit line 1231 connected to the first vertical conductor structure, the second voltage can be applied to the second bit line 1232 connected to the second vertical conductor structure, and the word line voltage can be applied to the specific word line 323.

[0152] The first and second bit lines (1231, 1232) are adjacent to each other and are disposed on the first and second vertical conductor structures (851, 852), respectively. The first voltage may be a drain side voltage (e.g., VCC) and the second voltage may be a source side voltage (e.g., 0V). When the first and second voltages are applied to the first and second bit lines, the bit lines other than the first and second bit lines may be floating. The order of the aforementioned steps does not necessarily represent the order in which the steps are performed. For example, the first and second voltages may be applied before or after the word line voltage is applied. For example, the first and second bit line transistors may be turned on before or after the word line voltage is applied to a particular word line.

[0153] For dual channel operation, in addition to selecting the previously mentioned specific memory cell 1301, the circuit can also select a second specific memory cell 1302. The specific memory cell 1302 has a drain in the first vertical conductor structure 851, a source in the second vertical conductor structure 852, and a channel (522L, Fig. 8A ), which is in ohmic contact with the first and second vertical conductor structures. The second specific film layer of the channel material is disposed on the sidewall of the second specific word line 313, and the second specific word line 313 and the previously mentioned specific word line 323 cross the channel (351, Fig. 8A A second specific film layer of channel material contacts the first and second vertical conductor structures (851, 852).

[0154] In order to select the second specific memory cell 1302, in addition to the steps described for selecting the previously mentioned specific memory cell 1301, the circuit can also perform the following steps: when the previously mentioned word line voltage is applied to the previously mentioned specific word line, a second word line voltage is further applied to the second specific word line.

[0155] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D Shown are stages of a simplified process flow for fabricating a memory device in an alternative embodiment.

[0156] Fig.14A The stage in the process flow is depicted after a hole (1410) is etched between the stacked layers of word lines (1461, 1462) through the multiple layers of memory material, channel material, and insulating material 1450. This etching step causes the multiple layers of memory material and channel material to separate into a film layer of memory material (1411, 1412, 1421, 1422) and a film layer of channel material (1431, 1432, 1441, 1442) on the sidewalls of the word lines. In one embodiment, this etching step may use RIE (reactive ion etching). Fig.14A14 is a simplified horizontal cross-sectional view of the structure of the memory element at this stage, which is taken along the horizontal direction of the word line in the stack. The word line in the stack extends along a first direction (Y direction). The channel 1401 and the hole 1410 can have the same width 1415 in a second direction perpendicular to the first direction.

[0157] The holes (1410) can separate the channel material into a first film layer (1431, 1441) of the channel material and a second film layer (1432, 1442) of the channel material, wherein the first and second film layers of the channel material are disposed opposite to each other across the specific holes (1410) in the first direction (Y direction). The holes can separate the memory material into a first film layer (1411, 1421) of the memory material and a second film layer (1412, 1422) of the memory material, wherein the first and second film layers of the memory material are disposed opposite to each other across the specific holes 1410 in the first direction.

[0158] Fig. 14B The stage in the process flow is depicted after a recess (1461A, 1462A) is etched through the hole (141) on the sidewalls of the word lines (1461, 1462) in the stack. Fig. 14B 1431, 1441, 1432, 1442, as shown in dashed circle 1413.

[0159] Fig. 14C The diagram shows the formation of recesses (1461A, 1462A, 1462B) of dielectric material (1471, 1472) on the sidewalls of the word lines in the stack through the hole (1410). Fig. 14B ) stage in the process flow after. Fig. 14C 14 is a simplified horizontal cross-sectional view of the structure of the memory element at this stage, taken in the horizontal direction of the word line in the stack. In one embodiment, this step may deposit a conformal dielectric to fill the recess. When the dielectric material is formed in the recess, the dielectric material may be deposited on the channel material through the hole. After the insulating material 1460 is formed in the recess, an isotropic etch may be applied to expose the channel material through the hole so that the channel material can be connected to the vertical conductor structure (refer to Fig.14D described in subsequent stages).

[0160] Fig.14DThe stage in the process flow is depicted after forming multiple rows of vertical conductor structures disposed in trenches between adjacent stacks of word lines. Fig.14D 1 is a simplified horizontal cross-sectional view of the structure of the memory element at this stage, taken along the horizontal direction of the word line in the stack. At this stage, the holes (1410) can be filled with a conductor material to form multiple rows of vertical conductor structures (1480) in the trenches (1401) between adjacent stacks (1461, 1462). In one embodiment, conformal N+ polysilicon deposition can be used to fill the holes at this stage, followed by a chemical mechanical planarization (CMP) process on the structure.

[0161] The dielectric material (1471, 1472) is disposed between the word lines (1461, 1462) and the vertical conductor structure (1480), thereby isolating the word lines from the vertical conductor structure. The word lines are recessed relative to the vertical conductor structure.

[0162] Fig.14E , Fig.14F Stages of a simplified process flow for fabricating a memory device in another alternative embodiment are shown.

[0163] Fig.14E The stage in the process flow after the word line oxide (1491, 1492) is formed in the recess is shown. Fig.14E The stages shown are continuations of Fig. 14B The stage shown, wherein the depressions (1461A, 1462A, Fig. 14B ) is formed on the sidewalls of the stacked word lines (1461, 1462) by etching holes (1410). Fig.14E is a simplified horizontal cross-sectional view of the structure of the memory element at this stage, taken along the horizontal direction of the word line in the stack. Fig.14E At this stage shown, a thermal oxidation process may be applied to the word lines (1461, 1462) to form word line oxides (1491, 1492) in the recesses. The film layer of the channel material (e.g., 1431) may have a first thickness 1494, and the word lines may have a second thickness 1495 at least 5 times greater than the first thickness, the thickness depending on the doping type and concentration.

[0164] When the oxide (1491, 1492) of the word line is formed in the recess using a thermal oxidation process, an oxide 1493 may also be formed on the sidewalls of the film layer of the channel material. Due to the N+ polysilicon material of the word line (1461, 1462), the oxide thickness of the oxide (1491, 1492) of the word line is about 2-5 times thicker than the oxide thickness of the oxide 1493. After the oxide (1491, 1492) of the word line is formed, an isotropic etch or a wet etch may be applied to remove the oxide 1493 and expose the film layer of the channel material, so that the film layer of the channel material can be connected to the vertical conductor structure (described below with reference to FIG. Fig.14F After this etching step, the oxide 1493 on the sidewalls of the film layer of the channel material is removed, but the oxide (1491, 1492) of the word line is retained, thereby preventing short circuits between the vertical conductor structure 1480 and the word line (1461, 1462).

[0165] Fig.14F A stage in the process flow is shown after forming multiple rows of vertical conductor structures disposed in trenches between adjacent stacks of word lines. Fig.14F The stages shown are in sequence Fig.14E The stage shown is where word line oxide (1491, 1492) is formed.

[0166] Fig.14F A simplified horizontal cross-sectional view of the structure of the memory element at this stage is shown, taken along the horizontal direction of the word lines in the stack. This stage may include filling the holes (1410) with a conductive material to form multiple rows of vertical conductor structures (1480) disposed in the channels (1401, 1402) between adjacent stacks (1461, 1462). Fig.14A In one embodiment, a conformal N+ polysilicon deposition may be used to fill the holes at this stage, and a chemical mechanical planarization (CMP) process may then be applied to the structure.

[0167] The oxide (1491, 1492) is disposed between the word lines (1461, 1462) and the vertical conductor structure (1480) to isolate the word lines from the vertical conductor structure. The word lines are recessed relative to the vertical conductor structure.

[0168] Fig.15 A simplified flow chart of the manufacturing process of an integrated circuit memory device is shown. In step 1510, a plurality of word lines (311-315, 321-325, 331-335, 331-335) alternating with the insulating band 305 may be formed. Figure 3A , Figure 3B ), wherein the stack is separated by a trench. The word line extends along a first direction (Y direction). In one embodiment, the stack of word lines can be formed on an insulating layer on a substrate.

[0169] At step 1520, a memory material and a channel material may be formed on the sidewalls of the word line on at least one side of the channel (410, 420, Figure 4A , Figure 4B The trench may be filled with insulating material 430 on the channel material.

[0170] In step 1530, a plurality of holes (551, 561, Figure 5A , Figure 5B ) through the multilayer film of memory material and channel material. In one embodiment, a hole ( Figure 5A , Figure 5B In an alternative embodiment, the hole (1410, Fig.14A ) is not etched through the word lines (1461, 1462, Fig.14A ) side wall.

[0171] In step 1540, the depression (651, Fig. 6A , Figure 6B ) can be formed by etching the sidewalls of the word lines (313, 323, 333) between the insulating bands in the plurality of stacks. In one embodiment, the insulating material (751, Fig. 7A , Figure 7B ) can be formed in a recess on the sidewall of the word line.

[0172] At step 1550, a plurality of vertical conductor structures (851-852, 861-862, 863-864) may be formed in the trenches (351, 361) between adjacent stacks of word lines (between 313 and 323; between 323 and 333). Fig. 8A , Figure 8B ). The insulating material (751) may be disposed between the word lines (313, 323) and the vertical conductor structure (851). The word lines (eg, 313) are recessed relative to the vertical conductor structure (eg, 851).

[0173] At step 1560, a plurality of bit line transistors (1110, 1120, Fig. 11B , Fig. 12B ) covers and is connected to the corresponding vertical conductor structure (851, 861).

[0174] In step 1570, a plurality of bit lines (1231, Fig. 12A , Fig. 12B ) cover and are connected to the bit line transistors (1110, 1120) of the corresponding row. The bit lines extend in a second direction (X direction) perpendicular to the first direction (Y direction).

[0175] The process may further include forming a circuit connected to the bit line (1652, Fig.16 ), whereby the first and second voltages are applied to the bit lines (eg Fig.13 ).

[0176] Fig.16 A simplified functional block diagram of an integrated circuit memory device according to the present technique is shown. Fig.16 In the example shown, the integrated circuit memory element 1600 includes a 3D NOR memory array 1660, which includes a plurality of word line stacks alternating with insulating strips, the stacks are separated by trenches, and the word lines extend along a first direction. The memory element may include multiple rows of vertical conductor structures, which are arranged in the trenches between adjacent stacks. Insulating material (751) may be arranged in a recess on the sidewall of the word line in the stack between the word line and the vertical conductor structure. The word line is recessed relative to the vertical conductor structure.

[0177] The multilayer film layer of memory material and channel material can be disposed on the sidewalls of the word line on at least one side of the channel between adjacent vertical conductor structures in the plurality of vertical conductor structures. The channel material is in ohmic contact with the vertical conductor structure. At the location of the plurality of vertical conductor structures, the sidewalls of the word lines are recessed between the insulating bands in the stack to form a depression on the sidewalls of the word line, thereby isolating the word line from the vertical conductor structure.

[0178] The channel may have a first width in a second direction (X direction) perpendicular to the first direction, and the vertical conductor structure may have a second width in the second direction that is greater than the first width.

[0179] The specific vertical conductor structure may be in ohmic contact with a first film layer of channel material and a second film layer of channel material, wherein the first and second film layers of channel material are disposed opposite to each other across the specific vertical conductor structure in a first direction.

[0180] A plurality of bit line transistors may be arranged to cover and be connected to a corresponding vertical conductor structure. A plurality of bit lines may be arranged to cover and be connected to bit line transistors of corresponding rows among a plurality of bit line transistors, and the bit lines may extend in a second direction perpendicular to the first direction. A plurality of gate lines may be arranged at the same level as the bit line transistors and connected to bit line transistors of corresponding columns among a plurality of bit line transistors, and the gate lines extend in the first direction. The bit line transistor may include a channel layer, the lower end of which is connected to the corresponding vertical conductor structure. The bit line may be connected to the corresponding upper end of the channel layer of the bit line transistor of the corresponding row through a plug.

[0181] The memory element may include a circuit 1652 connected to a bit line 1655, whereby the first and second voltages are applied to the bit line. A further description of the circuit 1652 may be found in Fig.13 .

[0182] The bit line decoder 1650 may include a circuit 1652 connected to the bit line 1655 to apply the first and second voltages to the bit line. The circuit 1652 is used to select a specific memory in the memory array, such as the reference Fig.13 as further described.

[0183] The word line decoder 1663 is connected to a plurality of word lines 1664 for reading and programming data from memory cells in the memory array 1660. The address is provided to the word line decoder 1663 and the bit line decoder 1650 via bus 1665. In this embodiment, the sense amplifiers and data input structures in block 1666 are connected to the bit line decoder 1650 via data bus 1667. Data is provided to the data input structures in block 1666 via data input lines 1671 from an input / output port of the integrated circuit 1600 or from other data sources internal or external to the integrated circuit 1600. In this embodiment, other circuits 1674 are also included on the integrated circuit, such as a general purpose processor (GPP) or an application specific integrated circuit (ASIC), or a combination of modules that provide system functions supported by the programmable resistor cell array. Data is provided from the sense amplifiers in block 1666 to an input / output port on the integrated circuit 1600 or to other data destinations internal or external to the integrated circuit 1600 via data output lines 1672.

[0184] In this embodiment, the controller 1669 uses a bias configuration state machine to control the bias configuration supply voltages generated or provided by the voltage supply in box 1668, such as programming, erase, and read voltages.

[0185] The controller may be implemented using a dedicated integrated circuit as is known in the art. In alternative embodiments, the controller includes a general purpose processor, which may be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In other embodiments, a combination of a dedicated integrated circuit and a general purpose processor may be used to implement the controller.

[0186] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any technician with common knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

[0187] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory element, characterized in that: Include: A plurality of word lines of a plurality of stacks are alternately stacked with a plurality of insulating bands, the stacks are separated by a plurality of trenches, and the word lines of the stacks extend along a first direction; a plurality of vertical conductor structures located in the trench between adjacent stacked layers; as well as A plurality of layers of memory material and a layer of channel material are located on the sidewalls of the word lines on at least one side of the channels, the channels are located between adjacent vertical conductor structures, the layers of channel material are in ohmic contact with the vertical conductor structures, Wherein, at the positions of the vertical conductor structures, the sidewalls of the word lines are recessed between the insulating bands to form a plurality of recesses on the sidewalls of the word lines, thereby separating the word lines from the vertical conductor structures; A plurality of bit line transistors are arranged to cover and be connected to corresponding vertical conductor structures; a plurality of bit lines are arranged to cover and be connected to bit line transistors of corresponding rows among the plurality of bit line transistors, and the bit lines extend in a second direction perpendicular to the first direction; A plurality of gate lines are arranged at the same level of the bit line transistors and are connected to the bit line transistors of corresponding columns among the plurality of bit line transistors, and the gate lines extend in a first direction; the bit line transistors include a channel layer, the lower end of which is connected to the corresponding vertical conductor structure; the bit line is connected to the corresponding upper end of the channel layer of the bit line transistor of the corresponding row through a plug. 2 . The memory device of claim 1 , further comprising an insulating material in the recesses on the sidewalls of the word lines. 3 . The memory device according to claim 1 , wherein the channels have a first width in a second direction, the second direction being perpendicular to the first direction, and the vertical conductor structures have a second width in the second direction, the second width being greater than the first width. 4 . The memory device according to claim 1 , wherein a vertical conductor structure is in ohmic contact with a first layer and a second layer of the channel materials, and the first layer and the second layer are opposite to each other across the vertical conductor structure along the first direction.

5. The memory element according to claim 1, further comprising: a plurality of bit line transistors covering and connected to corresponding vertical conductor structures; and A plurality of bit lines cover and are connected to the bit line transistors in corresponding rows of the bit line transistors. The bit lines extend along a second direction that is perpendicular to the first direction.

6. The memory element according to claim 5, further comprising: A plurality of gate lines are located at the same level of the bit line transistors and connected to the bit line transistors in corresponding columns of the bit line transistors. The gate lines extend along the first direction.

7. The memory device according to claim 5, wherein the bit line transistors include a plurality of channel layers, and the lower ends thereof are connected to the corresponding vertical conductor structures, and the bit lines are connected to the corresponding upper ends of the channel layers of the bit line transistors in the corresponding row through a plurality of plugs.

8. The memory device according to claim 5, further comprising a circuit connected to the bit lines to apply a first voltage and a second voltage to the bit lines.

9. The memory element according to claim 8, wherein: The circuit is used to select a memory cell having a drain in a first vertical conductor structure, a source in a second vertical conductor structure, and a channel in a channel material layer in ohmic contact with the first and second vertical conductor structures, wherein the channel is arranged on a sidewall of a word line, and comprises: Turning on a first bit line transistor connected to the first vertical conductor structure and a second bit line transistor connected to the second vertical conductor structure; Applying the first voltage to a first bit line connected to the first vertical conductor structure; applying the second voltage to a second bit line connected to the second vertical conductor structure; and A word line voltage is applied to the word line. 10 . The memory device of claim 2 , wherein the insulating material within the recesses on the sidewalls of the word lines comprises a dielectric material. 11 . The memory device of claim 2 , wherein the insulating material within the recesses on the sidewalls of the word lines comprises oxides of the word lines.

12. A method for manufacturing a memory element, characterized in that: Include: Forming a plurality of stacks of alternately stacked word lines and a plurality of insulating strips, the stacks being separated by a plurality of trenches, the word lines extending along a first direction; forming a plurality of layers of memory material and a layer of channel material on sidewalls of the word lines on at least one side of the channels; etching a plurality of holes through the layers of memory material and the channel material; etching a plurality of recesses on the sidewalls of the word lines between the insulating bands; as well as forming a plurality of vertical conductor structures in the trench between adjacent stacked layers, wherein the recesses separate the word lines from the vertical conductor structures; forming a plurality of bit line transistors covering and connecting to the corresponding vertical conductor structures; The forming of the bit line transistors further comprises: forming a first insulating layer covering the word lines of the stacked layers and the top surfaces of the vertical conductor structures; forming a horizontal conductive layer covering the first insulating layer; forming a second insulating layer covering the horizontal conductive layer; and The first insulating layer, the horizontal conductive layer and the second insulating layer are etched to separate the horizontal conductive layer into gate lines, and the gate lines cover and are insulated from the vertical conductor structures of the corresponding columns.

13. The method according to claim 12, further comprising: An insulating material is formed within the recesses on the sidewalls of the word lines. 14 . The manufacturing method according to claim 12 , wherein the channels have a first width in a second direction, the second direction being perpendicular to the first direction, and the vertical conductor structures have a second width in the second direction, the second width being greater than the first width.

15. The method according to claim 12, further comprising: filling the trenches with insulating material to cover the channel material; and Etching the holes includes etching through the insulating material within the trenches.

16. The method according to claim 12, further comprising: A plurality of bit lines are formed to cover and connect to the bit line transistors in corresponding rows of the bit line transistors. The bit lines extend along a second direction that is perpendicular to the first direction.

17. The method according to claim 16, further comprising: A plurality of gate lines are formed, located at the same level as the bit line transistors and connected to the bit line transistors in corresponding columns of the bit line transistors, and the gate lines extend along the first direction.

18. The method according to claim 17, further comprising: Etching a plurality of holes through the gate line located on the top surface of the vertical conductor structures and stopping at the top surface; forming insulating spacers on sidewalls of the holes; Forming a film layer of the channel material to cover the insulating gap wall, wherein the lower end of the film layer of the channel material is connected to the vertical conductor structure; filling the holes with insulating material; and A plurality of landing pads are formed to be connected to upper ends of corresponding film layers of the channel material.

19. The method according to claim 18, wherein forming the bit lines further comprises: forming a third insulating layer on the bit line transistors; Etching a plurality of holes through the insulating layer located at the bit line transistors and stopping at the landing pads; forming a plurality of plugs in the holes, the plugs covering and connecting to the landing pads; forming a conductive layer on the plugs; as well as The conductive layer is etched to form a plurality of bit lines.

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