A low-power, low-noise front-end sense amplifier for DNA sequencing signals

Abstract

The present invention discloses a low-power, low-noise front-end sensing amplifier suitable for DNA sequencing signals, comprising: n sets of front-end amplification devices, a 1-in-n data selector, and a unity-gain buffer. The n sets of front-end amplification devices simultaneously detect n different DNA sequencing signals, reduce noise in the low-frequency band of the DNA sequencing signals, perform low-pass filtering and amplification on the noise-reduced signals, and output n sets of amplified signals to the 1-in-n data selector. The 1-in-n data selector receives the n sets of amplified signals, selects one set of amplified signals for output into a channel of the unity-gain buffer, and drives the load of the back-end analog-to-digital conversion circuit through the unity-gain buffer. The embodiments of the present invention can successfully amplify tiny DNA sequencing signals to an output swing close to analog rail-to-rail in frequency bands with severe flicker noise, thereby reducing power consumption and noise during the amplification process of the weak signals generated by DNA sequencing, and increasing signal resolution.

Description

Technical Field

[0001] The present invention relates to the field of gene detection, and in particular to a low-power and low-noise front-end sensing amplifier suitable for DNA sequencing signals. Background Art

[0002] At present, due to its extremely high detection reliability, DNA (DeoxyriboNucleic Acid) sequencing technology is becoming a hot topic in life science and medical science research, and has achieved rapid and rapid development.

[0003] Among various DNA sequencing technologies, since the signals generated by DNA sequencing are very weak, the weak signals generated by DNA sequencing need to be amplified.

[0004] However, the amplification process of the weak signals generated by DNA sequencing suffers from significant power consumption and low-frequency noise, including flicker noise. This means that all current DNA sequencing technologies face a challenge: reducing power consumption and noise during the amplification process. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a low-power, low-noise front-end sense amplifier suitable for DNA sequencing signals. This amplifier can successfully amplify tiny DNA sequencing signals to an output swing close to analog rail-to-rail even in frequency bands with severe flicker noise, and then transmit the signals to the back-end analog-to-digital conversion circuit for conversion. This reduces power consumption and noise during the amplification process of the weak signals generated by DNA sequencing, thereby increasing signal resolution.

[0006] The technical solutions adopted by the present invention to solve the above technical problems are as follows:

[0007] According to one aspect of an embodiment of the present invention, a low-power, low-noise front-end sensing amplifier suitable for DNA sequencing signals is provided, comprising: n groups of front-end amplification devices, an n-to-1 data selector, and a unity-gain buffer; wherein:

[0008] n groups of the front-end amplifier devices are used to simultaneously detect n different DNA sequencing signals, reduce the noise of the DNA sequencing signals in the low-frequency band, perform low-pass filtering and amplify the noise-reduced signals, and output n groups of amplified signals to the n-to-1 data selector;

[0009] The n-to-1 data selector receives n groups of amplified signals output by n groups of the front-end amplifier devices, selects one group of amplified signals to output to the channel of the unity gain buffer, and drives the load of the back-end analog-to-digital conversion circuit through the unity gain buffer.

[0010] Compared with related technologies, embodiments of the present invention provide a low-power, low-noise front-end sensing amplifier suitable for DNA sequencing signals, comprising: n groups of front-end amplifying devices, a 1-in-n data selector, and a unity-gain buffer. The n groups of front-end amplifying devices are configured to simultaneously detect n different DNA sequencing signals, reduce the noise of the DNA sequencing signals in the low-frequency band, perform low-pass filtering and amplification on the noise-reduced signals, and output n groups of amplified signals to the 1-in-n data selector. The 1-in-n data selector receives the n groups of amplified signals output by the n groups of front-end amplifying devices, selects one of the amplified signals to output to a channel of the unity-gain buffer, and drives the load of a back-end analog-to-digital conversion circuit via the unity-gain buffer. Through the embodiments of the present invention, n sets of front-end amplification devices simultaneously detect n different DNA sequencing signals. A 1-of-n data selector then selects the channel to be sent to a unity-gain buffer. The unity-gain buffer then drives the load of the back-end analog-to-digital conversion circuit (ADC). This allows the tiny DNA sequencing signal (25uV to 1mV) to be successfully amplified to an output swing close to analog rail-to-rail in the frequency band (0.05 to 4000Hz) with severe flicker noise. The signal is then sent to the back-end analog-to-digital conversion circuit for conversion. This reduces power consumption and noise during the amplification process of the weak signal generated by DNA sequencing, while increasing signal resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of the structure of a low-power, low-noise front-end sensing amplifier suitable for DNA sequencing signals provided by an embodiment of the present invention.

[0012] Figure 2 A schematic structural diagram of a low-noise amplifier circuit in a front-end amplifier device provided by an embodiment of the present invention.

[0013] Figure 3 A schematic diagram of the circuit structure of a low noise amplifier (LNA) provided in an embodiment of the present invention.

[0014] Figure 4 A schematic diagram of the circuit structure of an adjustable low-pass filter provided by an embodiment of the present invention.

[0015] Figure 5 A schematic diagram of the circuit structure of a variable gain amplifier provided by an embodiment of the present invention.

[0016] Figure 6 A schematic diagram of the circuit structure of a rail-to-rail operational amplifier provided in an embodiment of the present invention.

[0017] Figure 7 A circuit structure and operation diagram of a motion noise detector provided by an embodiment of the present invention.

[0018] Figure 8 A schematic diagram of the circuit structure of a unity gain buffer provided by an embodiment of the present invention.

[0019] Figure 9 A schematic diagram of the circuit structure of a unity gain buffer provided by an embodiment of the present invention.

[0020] Figure 10 This is a simulation diagram of the overall input equivalent noise of a low-power, low-noise front-end sense amplifier suitable for DNA sequencing signals provided by an embodiment of the present invention.

[0021] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0022] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0023] In the subsequent description, suffixes such as "module," "component," or "unit" used to represent elements are only used to facilitate the description of the present invention and have no specific meaning. Therefore, "module," "component," or "unit" can be used interchangeably.

[0024] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] In one embodiment, Figure 1 and Figure 2 As shown, the present invention provides a low-power, low-noise front-end sensing amplifier suitable for DNA sequencing signals, comprising: n groups of front-end amplification devices 10, n-to-1 data selectors 20, and a unity gain buffer 30; wherein:

[0026] The n groups of front-end amplifiers 10 are used to simultaneously detect n different DNA sequencing signals, reduce the noise of the DNA sequencing signals in the low-frequency band, perform low-pass filtering and amplification on the noise-reduced signals, and output n groups of amplified signals to the n-to-1 data selector 20.

[0027] The n-to-1 data selector 20 receives n groups of amplified signals output by the n groups of front-end amplifiers 10, selects one of the amplified signals and outputs it to the channel of the unity gain buffer 30, thereby driving the load of the back-end analog-to-digital conversion circuit (ADC) through the unity gain buffer 30.

[0028] In this embodiment, the present invention discloses a low-power, low-noise front-end sense amplifier for DNA sequencing signals. This amplifier utilizes n sets of front-end amplification devices to simultaneously detect n different DNA sequencing signals. A 1-in-n data selector then selects the channel to be fed into a unity-gain buffer. This buffer then drives the load of the back-end analog-to-digital converter (ADC). This amplifier can successfully amplify tiny DNA sequencing signals (25 μV to 1 mV) to a near-rail-to-rail output swing within the frequency range (0.05 to 4000 Hz) where flicker noise is severe, before being fed to the back-end ADC for conversion. This reduces power consumption and noise during the amplification of the weak DNA sequencing signals, while increasing signal resolution. The low-power, low-noise front-end sense amplifier system utilizes a standard 0.18 μm CMOS process, operates from a 1 V power supply, and consumes 18 μW per channel. It resists motion noise and high-voltage stimulation, and features an adjustable bandwidth for distinguishing DNA sequencing signals across different frequency bands (low-frequency potential: 0.05 to 250 Hz; peak: 400 to 4000 Hz).

[0029] In one embodiment, Figure 1 and Figure 2 As shown, the front-end amplifier device 10 includes: a low-noise amplifier circuit 11, an adjustable low-pass filter (TLF) 12, a variable gain amplifier (VGA) 13 and a motion noise detector (MAD) 14; wherein:

[0030] The low-noise amplifier circuit 11 is used to reduce the noise of the DNA sequencing signal in the low-frequency band, and perform a first-stage amplification on the noise-reduced signal to obtain a first-stage amplified signal, and then send the first-stage amplified signal to the adjustable low-pass filter 12 and the variable gain amplifier 13.

[0031] The adjustable low-pass filter 12 is used to perform low-pass filtering on the first-stage amplified signal to form low-pass filtered signals with different cutoff frequencies.

[0032] The variable gain amplifier 13 is used to amplify the low-pass filtered signal at various magnifications.

[0033] The motion noise detector 14 is used to dynamically detect whether the output end of the variable gain amplifier 13 is saturated, and output a control signal to feedback control the operation of the offset cancellation switch of the low noise amplifier circuit 11.

[0034] In one embodiment, the low-noise amplifier circuit 11 is used to reduce the noise of the DNA sequencing signal in the low-frequency band, and perform a first-stage amplification on the noise-reduced signal to obtain a first-stage amplified signal, and then send the first-stage amplified signal to the adjustable low-pass filter 12 and the variable gain amplifier 13.

[0035] like Figure 2 As shown, the low-noise amplifier circuit 11 includes a DC blocking circuit 111, a high-pass corner circuit, and a low-noise amplifier (LNA) 112. The low-noise amplifier circuit 11 amplifies the DNA sequencing signal through the DC blocking circuit 111, the high-pass corner circuit, and the low-noise amplifier 112, and then sends the signal to the adjustable low-pass filter 12 and variable gain amplifier 13 at the back end.

[0036] The DC blocking circuit 111 is connected to the input end of the low noise amplifier 112 and is used to block the DC return of the low noise amplifier 112, thereby preventing DNA sequencing errors caused by the DC return of the low noise amplifier 112.

[0037] The high-pass corner circuit is connected to the input terminal and the output terminal of the low-noise amplifier 112 respectively, and is used to determine the high-pass corner of the low-noise amplifier circuit.

[0038] The low noise amplifier 112 includes a first input terminal inp and a second input terminal inn, and a first output terminal outn and a second output terminal outp. The first output terminal outn and the second output terminal outnp are grounded via a load capacitor Cload.

[0039] The DC blocking circuit 111 includes two DC blocking capacitors C1, one end of each of which is connected to the input terminal of the low-noise amplifier 112 and the other end is connected to the signal terminal. Specifically, one DC blocking capacitor C1 has one end connected to the first input terminal inp of the low-noise amplifier 112 and the other end connected to the positive signal terminal PS; the other DC blocking capacitor C1 has one end connected to the second input terminal inn of the low-noise amplifier 112 and the other end connected to the negative signal terminal PS.

[0040] In this embodiment, the DC blocking capacitor C1 can prevent DNA sequencing errors caused by DC backflow of the low-noise amplifier circuit.

[0041] The positive signal terminal PS is connected to the sensing probe and then to the positive electrode of the DNA sequencing electrode to be tested, while the negative signal terminal NS (Negative Signal) is connected to the reference probe and then to the negative electrode of the DNA sequencing electrode of the object to be tested, serving as a reference potential.

[0042] The high-pass corner circuit is formed by a capacitor C2 and a resistor R2 connected in parallel. The capacitor C2 and the resistor R2 are connected in parallel to the input terminal and the output terminal of the low-noise amplifier 112, respectively. In this embodiment, the low-noise amplifier circuit 11 includes two high-pass corner circuits, one of which is formed by a capacitor C2 and a resistor R2 connected in parallel, respectively connected to the first input terminal inp and the first output terminal outn of the low-noise amplifier 112; the other high-pass corner circuit is formed by a capacitor C2 and a resistor R2 connected in parallel, respectively connected to the second input terminal inn and the second output terminal outp of the low-noise amplifier 112.

[0043] In this embodiment, to effectively pass the DNA sequencing signal (0.05-4000 Hz), the high-pass filter angle is set at 0.05 Hz. To conserve capacitor area, the DC blocking capacitor C1 is set to 50 pF, the capacitor C2 is set to 2.5 pF, and the resistor R2 is set to 600 GΩ using a pseudo-resistor design. The first-stage gain of the low-noise amplifier circuit 11 is C1 / C2 = 20. The DNA sequencing signal undergoes first-stage gain amplification before being fed into the adjustable low-pass filter 12 and variable gain amplifier 13 at the back end.

[0044] Figure 3 FIG. 1 is a schematic diagram of the circuit structure of the low noise amplifier (LNA) 112. Figure 3 In the figure, cmfb is the common-mode feedback signal, and b1, b2, and b4 are the drive voltage control signals. To reduce flicker noise in the low-frequency band, the input MOS transistors M1 and M2 use pMOS inputs and are larger in size. The overdrive voltage for MOS transistors M1, M7, M8, and M9 is designed to be 0.1-0.15V, and the overdrive voltage for MOS transistors M3, M4, and M10 is set to 0.3-0.35V to achieve a good signal-to-noise ratio. Current shunting is used to separate the loading MOS transistors into MOS transistors M3 and M4. As a result, the transconductance of each loading MOS transistor is halved, and the resulting flicker noise current spectral density is also halved, as shown in the following equation:

[0045] ;

[0046] Where In is the flicker noise current spectral density; gm is the transconductance value in the operational transconductance amplifier; W and L are the width and length of the MOS tube, respectively; f is the frequency; k is the proportional coefficient; and Cox is the capacitance between the gate and the substrate.

[0047] pass Figure 3, the gain of the first stage of the low-noise amplifier circuit 11 can be doubled, which can effectively suppress the influence of the second stage noise on the input reference noise.

[0048] In this embodiment, the low-noise amplifier (LNA) employs low-noise circuit design techniques and current shunting to effectively suppress low-frequency noise that can cause severe flicker noise. A pseudo-resistance architecture with complementary PMOS and NMOS leakage currents is employed to form a very high-resistance feedback resistor, thereby reducing the input capacitor area.

[0049] In one embodiment, Figure 4 As shown, the adjustable low-pass filter 12 is used to perform low-pass filtering on the first-stage amplified signal to form low-pass filtered signals with different cut-off frequencies.

[0050] The adjustable low-pass filter 12 includes a front-end buffer 121, a switch 122, two sets of pseudo resistors 123, and a load capacitor C3. The switch 122 switches pseudo resistors of different resistance values ​​to connect to the load capacitor C3 to form low-pass filter signals with different cutoff frequencies.

[0051] Figure 4 FIG. 1 is a schematic diagram of the circuit structure of the adjustable low-pass filter 12. Figure 4 The adjustable low-pass filter TLF includes a front-end buffer 121, two sets of pseudo-resistors 122 (resistance values ​​of 45MΩ and 725MΩ, respectively), and a 300fF load capacitor. The two sets of pseudo-resistors use a MOS resistor structure with signal reversibility and low distortion. Switches are used to connect pseudo-resistors of different resistance values ​​to the load capacitor to form low-pass filter signals with different cutoff frequencies. Figure 4 In the experiment, the two sets of pseudo-resistors have resistances of 45 MΩ and 725 MΩ, respectively, which can generate low-pass filters with two different low-pass angles of 10 kHz and 632 Hz to distinguish low-frequency potentials and peaks in DNA sequencing signals.

[0052] In this embodiment, the adjustable low-pass filter TLF uses a MOS resistor structure with signal reversibility and low distortion to achieve adjustable and low-power filtering functions.

[0053] In one embodiment, the variable gain amplifier 13 is used to amplify the low-pass filtered signal at multiple magnifications.

[0054] like Figure 5As shown, the variable gain amplifier 13 includes a first-stage amplifier 131 and a second-stage amplifier 132. The first-stage amplifier 131 includes a first rail-to-rail operational amplifier 1311, a second rail-to-rail operational amplifier 1312, and a first variable resistor RG. The variable resistor RG is connected to one input end of the first rail-to-rail operational amplifier 1311 and the second rail-to-rail operational amplifier 1312, respectively. The other input ends of the first rail-to-rail operational amplifier 1311 and the second rail-to-rail operational amplifier 1312 are respectively connected to the two output ends of the adjustable low-pass filter 12.

[0055] The second-stage amplifier 132 includes a third rail-to-rail operational amplifier 1321 and two second variable resistors RG2. The two input terminals of the third rail-to-rail operational amplifier 1321 are respectively connected to the output terminals of the first rail-to-rail operational amplifier 1311 and the second rail-to-rail operational amplifier 1312. One terminal of the two second variable resistors RG2 is respectively connected to the two input terminals of the third rail-to-rail operational amplifier 1321, and the other terminal is respectively connected to the output terminals of the first rail-to-rail operational amplifier 1311 and the second rail-to-rail operational amplifier 1312.

[0056] The variable gain amplifier 13 can achieve different amplification gains by adjusting the resistance values ​​of the first variable resistor RG and the second variable resistor RG2.

[0057] Preferably, the first rail-to-rail operational amplifier 1311 , the second rail-to-rail operational amplifier 1312 , and the third rail-to-rail operational amplifier 1321 have the same structure and function.

[0058] In this embodiment, the variable gain amplifier utilizes an instrumentation amplifier architecture, providing extremely high input impedance and excellent common-mode signal rejection. By adjusting the resistance values ​​of the first variable resistor RG and the second variable resistor RG2, the variable gain amplifier can achieve different amplification gains (e.g., 25, 50, 100, 200, and 400 times). After amplification by the first-stage amplifier, the signal in the variable gain amplifier already has a certain voltage swing. To prevent signal distortion, the output terminals of the first and second rail-to-rail operational amplifiers of the first-stage amplifier utilize a push-pull architecture. This ensures sufficient open-loop gain even with a large output swing, thereby enhancing the accuracy of the closed-loop gain of the first-stage amplifier VGA1.

[0059] Figure 6 Schematic diagram of the circuit structure of the rail-to-rail operational amplifier. Figure 6In the circuit, high-resistance pseudo-resistors MrP1 to MrP4 are added to form a floating voltage. They sense the common-mode input voltage and generate a floating gate bias rP2 to offset the threshold voltage at the input end. The floating gate at the input end combines with the input signals inn and inp to reduce the common-mode input voltage, thereby effectively reducing the input common-mode signal variation.

[0060] In this embodiment, the variable gain amplifier (VGA) achieves high-quality signal linearity through clever switch position arrangement and rail-to-rail operational amplifier design, and minimizes the resistor area in system gain conversion.

[0061] In one embodiment, the motion noise detector 14 is used to dynamically detect whether the output end of the variable gain amplifier 13 is saturated, and output a control signal to feedback control the operation of the offset cancellation switch S1 of the low noise amplifier circuit 11.

[0062] like Figure 1 and Figure 2 As shown, the low noise amplifier circuit 11 further includes a cancellation switch S1 , and the cancellation switch S1 is connected in parallel to both ends of the resistor R2 .

[0063] like Figure 7 As shown, the motion noise detector 14 is connected to the output of the variable gain amplifier 13 and can dynamically detect whether the output of the variable gain amplifier 13 is saturated. The motion noise detector 14 includes a level shifter 141, an active comparator 142, and a digital logic circuit 143. The motion noise detector 14 outputs a control signal that feedback controls the operation of the offset cancellation switch S1 of the low-noise amplifier circuit 11.

[0064] The input end of the level converter 141 is connected to the output end of the variable gain amplifier 13 , and is used to perform level conversion on the output of the variable gain amplifier 13 and output the converted voltage to the active comparator 142 .

[0065] The active comparator 142 has one input connected to the output of the level shifter 141, and another input connected to a reference voltage. The output of the active comparator 142 is connected to an input of the digital logic circuit 143. The active comparator 142 compares the converted voltage after being converted by the level shifter 141 with the reference voltage. When the converted voltage is higher than the reference voltage, the active comparator 142 outputs a high-level signal to the digital logic circuit 143.

[0066] The input terminal of the digital logic circuit 143 is connected to the output terminal of the active comparator 142 , and the output terminal outputs a control signal to feedback control the operation of the offset cancellation switch S1 of the low-noise amplifier circuit 11 .

[0067] Specifically, the digital logic circuit 143 generates a delay time for the cancellation switch S1 to be disconnected when performing motion noise elimination. When receiving the high level output of the active comparator 142, it outputs a control signal to turn on the cancellation switch S1, and feedback controls the cancellation switch S1 of the low-noise amplifier circuit 11 to turn on. After the cancellation switch S1 is turned on, it ensures that the conduction time is greater than the delay time before outputting a signal to disconnect the cancellation switch S1, so that the front-end motion noise is completely eliminated.

[0068] Figure 7 FIG. 1 is a circuit structure and operation diagram of the motion noise detector 14. Figure 7 In the figure, the motion noise detector 14 is connected to the output end of the variable gain amplifier 13 and can dynamically detect whether the output end of the variable gain amplifier 13 is saturated. The motion noise detector 14 includes a level converter 141, an active comparator 142 and a digital logic circuit 143, and finally outputs a control signal to feedback control the operation of the offset cancellation switch S1 of the low-noise amplifier circuit 11.

[0069] Figure 7 The operation mode of the motion noise detector 14 is as follows:

[0070] The output of the variable-gain amplifier 13, out3, is connected to the input of the motion noise detector 14. After passing through a level shifter 141 with a -390mV voltage span, the output is sent to an active comparator 142 on the back end for comparison with a reference voltage of 0.5V. When the shifted voltage exceeds the reference voltage by 50mV, the active comparator 142 sends a high-level signal to a digital logic circuit 143 on the back end (with a hysteresis window of ±50mV). This digital logic circuit 143 then generates a control signal to control the operation of the cancellation switch S1. When performing the motion noise cancellation effect, the digital logic circuit 143 generates a 200μs delay to delay the opening of the cancellation switch S1. This delay is not noticeable when motion noise is detected, allowing the control signal to turn on the cancellation switch S1 immediately. However, once the cancellation switch S1 is turned on, it is ensured to remain on for at least the 200μs delay before outputting the signal to turn it off, effectively eliminating the motion noise at the front end. The motion noise detector 14 and the front-end offset cancellation switch S1 are perfectly combined into a motion noise cancellation system.

[0071] In this embodiment, a group of motion noise sensors are designed through the motion noise detector, and the bias removal in the low-noise amplifier is combined to effectively suppress the interference of motion noise. In addition, with the addition of PMOS diodes, a dual current conduction path for DNA sequencing is provided, effectively protecting the input gate from breakdown.

[0072] In one embodiment, the n-to-1 data selector 20 is connected to the n groups of front-end amplifier devices 10, receives n groups of amplified signals output by the n groups of front-end amplifier devices 10, selects one group of amplified signals to output to the channel of the unity gain buffer 30, and drives the load of the back-end analog-to-digital conversion circuit (ADC) through the unity gain buffer 30.

[0073] Specifically, the n input ends of the n-to-1 data selector 20 are connected to the output ends out3 of the variable gain amplifiers 13 of the n groups of front-end amplifying devices 10, and receive the amplified signals output by the variable gain amplifiers 13 of the n groups of front-end amplifying devices; the output end of the n-to-1 data selector is connected to the input end of the unit gain buffer 30.

[0074] In one embodiment, Figure 8 As shown, the unity gain buffer 30 is connected to the output end of the n-to-1 data selector 20 to provide high-speed channel switching for the sensing system and provide sufficient current driving capability for the back-end analog-to-digital conversion circuit to drive the load of the back-end analog-to-digital conversion circuit.

[0075] Preferably, the unity gain buffer 30 is a set of rail-to-rail buffers with high bandwidth and high conversion rate to provide high-speed channel switching for the sensing system.

[0076] Figure 9 FIG. 3 is a schematic diagram of the circuit structure of the unit gain buffer 30. Figure 9Because the output signal amplitude of the final stage of the variable gain amplifier 13 is already near rail-to-rail, the unity gain buffer 30 must also have rail-to-rail input and output characteristics. A switching current architecture achieves rail-to-rail input, while a push-pull approach achieves rail-to-rail output. Both NMOS and PMOS transistors are used as input MOSFETs, and a pair of n-type and p-type reference MOSFETs are added internally for current switching. When the input common-mode voltage is at the normal 0.5V, the NMOS, PMOS, and reference MOS transistors all simultaneously flow a unit current, I. When the input common-mode voltage approaches VDD, the PMOS and n-type reference MOS transistors turn off, while the NMOS and p-type reference MOS transistors flow twice the unit current, 2I. Conversely, when the input common-mode voltage approaches GND, the NMOS and p-type reference MOS transistors turn off, while the PMOS and n-type reference MOS transistors flow twice the unit current, 2I. Therefore, regardless of the input voltage, the total current flowing through the NMOS and PMOS transistors at the input is always a unit current of 2I, achieving the input rail-to-rail constant, gm. A push-pull architecture is used at the output to achieve rail-to-rail output capability.

[0077] like Figure 10 As shown in FIG, it is a simulation diagram of the input equivalent noise of a low-power and low-noise front-end sensing amplifier suitable for DNA sequencing signals provided by the present invention. Figure 10 As can be seen from the figure, the low-power, low-noise front-end sensing and amplification system of the present invention can successfully amplify tiny DNA sequencing signals (25uV to 1mV) to an output swing close to analog rail-to-rail in the frequency band (0.05-4000Hz) with severe flicker noise, and then send them to the back-end ADC for conversion, thereby increasing signal resolution. The overall system input equivalent noise is 1.92μV, which is within the acceptable range even for the smallest DNA sequencing signal with an average amplitude of 35μV.

[0078] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0079] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0080] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is the more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (such as a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in the various embodiments of the present invention.

[0081] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A low-power, low-noise front-end sense amplifier suitable for DNA sequencing signals, characterized in that: The amplifier includes: n groups of front-end amplifier devices, n-to-1 data selectors, and a unity gain buffer; wherein: n groups of front-end amplifiers are used to simultaneously detect n different DNA sequencing signals, reduce the noise of the DNA sequencing signals in the low-frequency band, perform low-pass filtering and amplify the noise-reduced signals, and output n groups of amplified signals to the n-to-1 data selector; The front-end amplifier device includes: a low-noise amplifier circuit, an adjustable low-pass filter, and a variable gain amplifier; wherein: the low-noise amplifier circuit is used to reduce the noise of the DNA sequencing signal in the low-frequency band, and performs a first-stage amplification on the noise-reduced signal to obtain a first-stage amplified signal, and then sends the first-stage amplified signal to the adjustable low-pass filter; the adjustable low-pass filter is used to perform low-pass filtering on the first-stage amplified signal to form low-pass filtered signals with different cutoff frequencies; and the variable gain amplifier is used to amplify the low-pass filtered signal. The low-noise amplifier circuit includes a motion noise detector, which is used to dynamically detect whether the output end of the variable gain amplifier is saturated, output a control signal, and feedback-control the operation of the offset cancellation switch of the low-noise amplifier circuit; The motion noise detector includes a level converter, an active comparator, and a digital logic circuit; wherein: the input end of the level converter is connected to the output end of the variable gain amplifier, and is used to convert the output of the variable gain amplifier into a converted voltage and output it to the active comparator; one input end of the active comparator is connected to the output end of the level converter, and the other input end is connected to the reference voltage end; the output end of the active comparator is connected to the input end of the digital logic circuit; the active comparator compares the converted voltage after conversion by the level converter with the reference voltage, and when the converted voltage is higher than the reference voltage, it outputs a high-level signal to the digital logic circuit; the input end of the digital logic circuit is connected to the output end of the active comparator, and the output end outputs a control signal to feedback control the operation of the offset cancellation switch of the low-noise amplifier circuit; The n-to-1 data selector receives n groups of amplified signals output by n groups of the front-end amplifier devices, selects one group of amplified signals to output to the channel of the unity gain buffer, and drives the load of the back-end analog-to-digital conversion circuit through the unity gain buffer.

2. The amplifier according to claim 1, wherein The low-noise amplifier circuit also includes a DC blocking circuit, a high-pass corner circuit, and a low-noise amplifier. The low-noise amplifier circuit amplifies the DNA sequencing signal through the DC blocking circuit, the high-pass corner circuit, and the low-noise amplifier, and then sends it to the adjustable low-pass filter at the back end.

3. The amplifier according to claim 2, wherein The DC blocking circuit includes two DC blocking capacitors, one end of the DC blocking capacitor is connected to the input end of the low noise amplifier, and the other end is connected to the signal end.

4. The amplifier according to claim 2, wherein The high-pass corner circuit is formed by a capacitor and a resistor in parallel. The capacitor and the resistor are connected in parallel to the input and output ends of the low-noise amplifier respectively; the offset cancellation switch is connected in parallel to both ends of the resistor.

5. The amplifier according to claim 1, wherein The adjustable low-pass filter includes a front-end buffer, a switching switch, two sets of pseudo resistors and a load capacitor; the switching switch switches pseudo resistors with different resistance values ​​to be connected to the load capacitor to form low-pass filter signals with different cutoff frequencies.

6. The amplifier according to claim 1, wherein The variable gain amplifier includes a first-stage amplifier, which includes a first rail-to-rail operational amplifier, a second rail-to-rail operational amplifier and a first variable resistor. The variable resistor is connected to one input end of the first rail-to-rail operational amplifier and the second rail-to-rail operational amplifier respectively, and the other input ends of the first rail-to-rail operational amplifier and the second rail-to-rail operational amplifier are respectively connected to the two output ends of the adjustable low-pass filter.

7. The amplifier according to claim 6, wherein The variable gain amplifier also includes a second-stage amplifier, which includes a third rail-to-rail operational amplifier and two second variable resistors; the two input ends of the third rail-to-rail operational amplifier are respectively connected to the output ends of the first rail-to-rail operational amplifier and the second rail-to-rail operational amplifier; one end of the two second variable resistors is respectively connected to the two input ends of the third rail-to-rail operational amplifier, and the other end is respectively connected to the output ends of the first rail-to-rail operational amplifier and the second rail-to-rail operational amplifier.

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