Impedance compensation system with microstrip and slotline coupling and controllable capacitance

Abstract

The present disclosure relates to an impedance compensation system with microstrip and slotline coupling and controllable capacitance. Embodiments of a circuit, system, and method are disclosed. In one embodiment, the circuit includes a first microstrip transmission line (230), a second microstrip transmission line (232), and a slotline structure (236), wherein the slotline structure extends between the first microstrip transmission line and the second microstrip transmission line, so that the slotline structure is configured to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line during operation of the circuit. In addition, the circuit includes at least one controllable capacitance circuit (238), the at least one controllable capacitance circuit (238) being electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line, wherein the magnitude of the capacitance of the at least one controllable capacitance circuit (e.g., in response to a capacitance control signal received at a control interface) is controllable.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to impedance compensation circuits with microstrip and slotline coupling and controllable capacitance. Background Art

[0002] Radio frequency (RF) front-end modules are important components in RF systems, including base transceiver stations (BTS) in 5G wireless networks. An important operating parameter that affects the performance of RF front-end modules is antenna impedance mismatch. Various techniques have been used to manage antenna impedance mismatch, including, for example, adding an impedance compensation network or an impedance tunable matching network (TMN) between the antenna and other RF components in the RF front-end module. Such impedance compensation networks and impedance tunable matching networks are typically implemented with π and T structures based on parts of variable reactance connected to microstrip transmission lines. These implementations typically rely on bulky components, which tend to be high-loss and may not scale well at higher powers. Summary of the invention

[0003] Embodiments of a circuit, system, and method are disclosed. In one embodiment, the circuit includes a first microstrip transmission line, a second microstrip transmission line, and a slotline structure, wherein the slotline structure extends between the first microstrip transmission line and the second microstrip transmission line, so that the slotline structure is configured to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line during operation of the circuit, and at least one controllable capacitance circuit is electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line, wherein the capacitance of the at least one controllable capacitance circuit is controllable.

[0004] In one embodiment, the at least one controllable capacitor circuit includes a first controllable capacitor circuit, which is electrically connected to the first microstrip transmission line and includes a first control interface, wherein the capacitance of the first controllable capacitor circuit is controllable in response to a first capacitor control signal received at the first control interface; and a second controllable capacitor circuit, which is electrically connected to the second microstrip transmission line and includes a second control interface, wherein the capacitance of the second controllable capacitor circuit is controllable in response to a second capacitor control signal received at the second control interface.

[0005] In one embodiment, the first microstrip transmission line includes an open short stub, and the first controllable capacitance circuit is electrically connected to the first microstrip transmission line at the open short stub of the first microstrip transmission line, and the second microstrip transmission line includes an open short stub, and the second controllable capacitance circuit is electrically connected to the second microstrip transmission line at the open short stub of the second microstrip transmission line.

[0006] In one embodiment, the at least one controllable capacitive circuit is controlled in response to a digital capacitive control signal received at a control interface of the at least one controllable capacitive circuit.

[0007] In one embodiment, the at least one controllable capacitor circuit includes a first digital controllable capacitor circuit, which is electrically connected to the first microstrip transmission line and includes a first control interface, wherein the size of the capacitance of the first digital controllable capacitor circuit is controllable in response to a first digital capacitor control signal received at the first control interface; and a second digital controllable capacitor circuit, which is electrically connected to the second microstrip transmission line and includes a second control interface, wherein the size of the capacitance of the second digital controllable capacitor circuit is controllable in response to a second digital capacitor control signal received at the second control interface.

[0008] In one embodiment, from a plan view perspective, a portion of the first microstrip transmission line intersects a portion of the slotline configuration, and wherein from a plan view perspective, a portion of the second microstrip transmission line intersects a portion of the slotline configuration.

[0009] In one embodiment, the first microstrip transmission line includes an open stub, and the first microstrip transmission line intersects the portion of the slotline construction proximate to the open stub of the first microstrip transmission line; and the second microstrip transmission line includes an open stub, and the second microstrip transmission line intersects the portion of the slotline construction proximate to the open stub of the second microstrip transmission line.

[0010] In one embodiment, the intersection of the first microstrip transmission line and the slotline configuration is separated by a dielectric layer, and wherein the intersection of the second microstrip transmission line and the slotline configuration is separated by the dielectric layer.

[0011] In one embodiment, the slotline configuration is formed as a gap in a conductive layer of a printed circuit board (PCB).

[0012] In one embodiment, a linear portion of the gap of the slotline configuration extends perpendicularly to a portion of the first microstrip transmission line and a portion of the second microstrip transmission line.

[0013] In one embodiment, the gap of the slot line configuration includes a first rounded end portion at a first end of the linear portion and a second rounded end portion at a second end of the linear portion.

[0014] In one embodiment, the first microstrip transmission line comprises an L-shaped portion having a first linear portion and a second linear portion substantially perpendicular to the first linear portion, and wherein the second microstrip transmission line comprises an L-shaped portion having a third linear portion and a fourth linear portion substantially perpendicular to the third linear portion.

[0015] In one embodiment, the first microstrip transmission line includes an open stub, and the first microstrip transmission line intersects a portion of the slotline structure proximate to the open stub of the first microstrip transmission line; and the second microstrip transmission line includes an open stub, and the second microstrip transmission line intersects a portion of the slotline structure proximate to the open stub of the second microstrip transmission line.

[0016] In one embodiment, the first microstrip transmission line and the second microstrip transmission line are coplanar.

[0017] In one embodiment, the first microstrip transmission line and the second microstrip transmission line are on different planes.

[0018] In one embodiment, an RF front end comprises the above described circuit.

[0019] In another embodiment, a system is disclosed. The system includes a first microstrip transmission line, a second microstrip transmission line, and a slotline structure, wherein the slotline structure extends between the first microstrip transmission line and the second microstrip transmission line to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line, and at least one controllable capacitance circuit is electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line and includes a control interface, wherein the capacitance of the at least one controllable capacitance circuit is controllable in response to a capacitance control signal received at the control interface.

[0020] In one embodiment, the at least one controllable capacitor circuit includes a first controllable capacitor circuit, which is electrically connected to the first microstrip transmission line and includes a first control interface, wherein the capacitance of the first controllable capacitor circuit is controllable in response to a first capacitor control signal received at the first control interface; and a second controllable capacitor circuit, which is electrically connected to the second microstrip transmission line and includes a second control interface, wherein the capacitance of the second controllable capacitor circuit is controllable in response to a second capacitor control signal received at the second control interface.

[0021] A method for providing impedance compensation for an RF front end is also disclosed. The method involves receiving an RF signal at one of a first microstrip transmission line and a second microstrip transmission line, wherein a slotline structure extends between the first microstrip transmission line and the second microstrip transmission line to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line; and adjusting a capacitance at an open stub of at least one of the first microstrip transmission line and the second microstrip transmission line to provide impedance compensation.

[0022] In one embodiment, adjusting the capacitance at the open stub of at least one of the first microstrip transmission line and the second microstrip transmission line involves adjusting capacitance at a first controllable capacitance circuit electrically connected to the open stub of the first microstrip transmission line in response to receiving a first capacitance control signal, and adjusting capacitance at a second controllable capacitance circuit electrically connected to the open stub of the second microstrip transmission line in response to receiving a second capacitance control signal.

[0023] Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of an example RF front end including an impedance compensation system.

[0025] Figure 2 Describes the use Figure 1 The RF front end of the antenna provides compensation for antenna impedance mismatch.

[0026] Figure 3A Describes Figure 2 The first microstrip transmission line, the second microstrip transmission line, and the slotline configuration are shown.

[0027] Figure 3B yes Figure 3A Examples of equivalent circuits of the components shown.

[0028] Figure 3C yes Figure 3B The equivalent circuit of port 1 is transformed into the equivalent circuit of port 1.

[0029] Figure 4 Describes the Figure 2 An embodiment of a digitally controllable capacitor of at least one component of a controllable capacitance circuit is shown.

[0030] Figure 5 Embodiments of a system in an RF front end configured to provide compensation for antenna impedance mismatch are described.

[0031] Figure 6 It is a graph of return loss (RL) (in dB) and phase (in degrees) at a phase angle of 360° at three radio frequencies of 3.4 GHz, 3.5 GHz and 3.6 GHz, when the reflection coefficient Γ=0.2.

[0032] Fig. 7A is a top plan view of an example layout of an assembly including a first microstrip transmission line, a second microstrip transmission line, and a slotline configuration, wherein the first microstrip transmission line and the second microstrip transmission line are on the same side of the assembly.

[0033] Figure 7B yes Fig. 7A A side cross-sectional view of the component at cross section AA.

[0034] Fig. 8A is a top plan view of another example layout of an assembly including a first microstrip transmission line, a second microstrip transmission line, and a slotline configuration, wherein the first microstrip transmission line and the second microstrip transmission line are not on the same side of the assembly.

[0035] Figure 8B yes Fig. 8A A side cross-sectional view of the component at cross section AA.

[0036] Fig. 9 is an example of a slotline construction where the shorted stubs are radially shaped stubs.

[0037] Fig.10 A process flow diagram of a method for providing impedance compensation for an RF front end.

[0038] Similar reference numerals may be used to identify similar elements throughout the specification. DETAILED DESCRIPTION

[0039] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a wide variety of different configurations. Therefore, the following more detailed description of various embodiments, as represented in the accompanying drawings, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0040] The present invention may be embodied in other specific forms without departing from the spirit or essential features of the present invention. The described embodiments are to be considered in all respects as merely illustrative and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than this detailed description. All changes within the equivalent meaning and scope of the claims should be included within their scope.

[0041] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that can be achieved using the present invention should be or are in any single embodiment of the present invention. Rather, language referring to features and advantages should be understood to mean that a specific feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same embodiment.

[0042] In addition, the described features, advantages and characteristics of the present invention may be combined in one or more embodiments in any suitable manner. In view of the description herein, those skilled in the relevant art will recognize that the present invention may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present invention may be recognized in certain embodiments.

[0043] References throughout this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0044] Figure 1 1 is a block diagram of an example RF front end 100, which includes a transmit signal power amplifier (PA) 102, a receive signal low noise amplifier (LNA) 104, a transmitter / receiver switch (Tx / Rx switch) 106, a directional coupler 108, an incident power monitor 110, a reflected power monitor 112, a monitoring and control system 114, an impedance compensation system 120, and an antenna 122. In transmit operation, the Tx / Rx switch is set to a transmit state (e.g., Figure 1 ), and the transmit signal (Tx) is passed to the power amplifier, through or through the directional coupler, through the Tx / Rx switch, through the impedance compensation system and to the antenna to be transmitted as an RF signal. In receive operation, the Tx / Rx switch will be set to the receive state ( Figure 1), and the received signal (Rx) will be transmitted from the antenna, through the impedance compensation system, through the switch and to the low noise amplifier. During the transmit operation, the incident power and the reflected power can be monitored by the incident power monitor and the reflected power monitor through the directional coupler, respectively. The monitoring and control system can control various aspects of the power amplifier, the Tx / Rx switch and the impedance compensation system through control signals, and can control the impedance compensation system in response to power information from the incident power monitor and / or power information from the reflected power monitor. In one embodiment and as described in more detail below, the monitoring and control system provides a digital capacitance control signal to the impedance compensation system to compensate for the antenna impedance mismatch.

[0045] According to an embodiment of the present invention, a circuit is disclosed. The circuit can be used in an RF front end to provide impedance compensation for antenna impedance mismatch. In one embodiment, the circuit includes a first microstrip transmission line, a second microstrip transmission line and a slot line structure. The slot line structure extends between the first microstrip transmission line and the second microstrip transmission line, and the slot line structure is electromagnetically coupled to the ends of both the first microstrip transmission line and the second microstrip transmission line. The circuit also includes at least one controllable capacitance circuit, which is electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line and includes a control interface, wherein the size of the capacitance of at least one controllable capacitance circuit is controllable in response to a capacitance control signal received at the control interface. In one embodiment, the first controllable capacitance circuit is electrically connected to an open stub of the first microstrip transmission line, and the second controllable capacitance circuit is electrically connected to an open stub of the second microstrip transmission line, and the size of the capacitance is digitally controlled. In one embodiment, from a plan view perspective, a portion of a first microstrip transmission line intersects or crosses over a portion of a slotline construction but is not directly electrically connected to a portion of the slotline construction to produce a microstrip to slotline transition, and a portion of a second microstrip transmission line intersects or crosses over a different portion of the slotline construction but is not directly electrically connected to a different portion of the slotline construction to produce a slotline to microstrip transition. The use of microstrip to slotline transitions and slotline to microstrip transitions with one or more controllable capacitors electrically connected to at least one of the microstrip transmission lines enables dynamic impedance compensation to be implemented in a manner that provides adjustability over a wide dynamic range over a wide frequency range with compact components. For example, a system implementing such a circuit can be adjustable over an instantaneous bandwidth of approximately 200 megahertz (MHz), but adjustment over narrower or wider bandwidths can also be achieved.

[0046] Figure 2 A circuit 200 (eg, Figure 1The impedance compensation system 120 includes a first microstrip transmission line 230, a second microstrip transmission line 232, a slotline structure 236, and a controllable capacitance circuit 238 electrically connected to the first microstrip transmission line and the second microstrip transmission line. Figure 2 The depicted first and second microstrip transmission lines are L-shaped planar microstrip transmission lines of conductive (e.g., metal) material formed on a multilayer substrate (not shown), which may include a printed circuit board (PCB) having a plurality of patterned conductive layers and one or more dielectric layers. More specifically, the L-shaped first microstrip transmission line includes a first linear portion and a second linear portion, the second linear portion extending substantially perpendicularly from the first linear portion at an elbow between the first portion and the second portion. Similarly, the L-shaped second microstrip transmission line includes a third linear portion and a fourth linear portion, the fourth linear portion extending substantially perpendicularly from the third linear portion at an elbow between the third portion and the fourth portion. Both the first and second microstrip transmission lines may be formed in a first patterned conductive layer of the PCB, or the first and second microstrip transmission lines may be formed in two different patterned conductive layers of the PCB (e.g., in various embodiments, one layer above the slotline structure 236 and another layer below the slotline structure 236). The first microstrip transmission line includes an open stub 240 (i.e., approximately located at a position between the slotline structure 236 and the first microstrip transmission line). Figure 2 The second microstrip transmission line includes an open stub 242 (ie, approximately located at the end of the second linear portion of the first microstrip transmission line at the center of Figure 2 In one embodiment, the open stubs 240 and 242 are open circuit stubs known in the art.

[0047] The slot line structure 236 is formed in a patterned conductive layer (hereinafter referred to as a "conductive slot line layer") of the PCB that is different from one or more layers formed by the first microstrip transmission line and the second microstrip transmission line. The slot line structure 236 includes two circular short-circuit stubs 250 and 252 connected by an elongated linear portion 254. In one embodiment, the short-circuit stubs 250 and 252 are short-circuit stubs known in the art. Figure 2As shown, from a plan view perspective, the first microstrip transmission line 230 electromagnetically intersects (i.e., passes over without being directly electrically connected) a first portion of an open stub 240 of a slotline construction that is proximate to the first microstrip transmission line (e.g., between an elbow of an L-shaped microstrip transmission line and an open stub), and the second microstrip transmission line 232 electromagnetically intersects (i.e., passes over without being directly electrically connected) a second portion of an open stub 242 of a slotline construction that is proximate to the second microstrip transmission line (e.g., between an elbow of an L-shaped microstrip transmission line and an open stub). As used herein, the term "gap" means a removed portion of a patterned planar conductive layer. Additionally, the term "near" when used in the context of a microstrip transmission line proximate to a slotline construction means a location of the microstrip transmission line between the elbow of the corresponding L-shaped microstrip transmission line and the open stub. In one embodiment, the slotline construction includes an elongated, substantially linear gap (i.e., an elongated linear portion 254) formed within a conductive slotline layer such as a first conductive layer (e.g., a conductive ground layer) of a PCB. For example, the slotline configuration includes a linear gap portion extending between a first circular end gap portion (or simply a circular end or stub 250) and a second circular end gap portion (or simply a circular end or stub 252), and is formed as a first inner sidewall of a first conductive layer (i.e., a conductive slotline layer), a second inner sidewall of the first conductive layer, a first circular inner end wall of the first conductive layer, and an area between a second circular inner end wall of the first conductive layer. For example, the electrical length of the shorting stubs 250 and 252 may be a length that is shorted by a transmit signal power amplifier (see FIG. 1 ) during operation. Figure 1 ) is provided / generated by the power amplifier, or is about one-quarter the wavelength of the fundamental operating frequency of the power amplifier. In various embodiments, the fundamental operating frequency of the power amplifier ranges from about 800 MHz to about 6 gigahertz (GHz), but the fundamental operating frequency can also be lower or higher. In other embodiments, the slotline configuration can have other lengths or characteristics, including, for example, those described elsewhere herein.

[0048] refer to Figure 2 , the first microstrip transmission line 230 is electrically connected to other front-end components such as the RF front-end, for example, Figure 1 The Tx / Rx switch 106 and amplifiers 102 and 104 are shown, and the second microstrip transmission line 232 is electrically connected to, for example, Figure 1 The antenna 122 is shown. The open stubs 240 and 242 of the first microstrip transmission line and the second microstrip transmission line are electrically connected (e.g., by conductive metal) to the controllable capacitance circuit 238. Although the first microstrip transmission line 230 and the second microstrip transmission line 232 are depicted as L-shaped microstrip transmission lines, other shapes of the first microstrip transmission line and the second microstrip transmission line are possible, depending on, for example, the locations of the RF input and output ports. Figure 2 In the example of the slotted line configuration, the shorting stubs 250 and 252 of the slotted line configuration are circular in shape, but other shapes of shorting stubs and / or slotted line configurations are generally possible. In addition, although the slotted line configuration is shown as being symmetrical (e.g., because the shorting stubs 250, 252 are of the same shape and size), the slotted line configuration may be asymmetrical.

[0049] Although from Figure 2 It may not be apparent from the top plan view of the drawing, but the first microstrip transmission line 230 and the second microstrip transmission line 232 and the slotline structure 236 are physically (and galvanically) separated from each other by a dielectric layer (e.g., in the vertical direction, i.e., in a direction perpendicular to the plane of the drawing). Because the microstrip transmission line is physically separated from the slotline structure by the dielectric material, there is no direct electrical connection (i.e., a coupling in which current can be transmitted through a conductive material such as a metal) between either the first microstrip transmission line or the second microstrip transmission line and the slotline structure. However, the first microstrip transmission line and the second microstrip transmission line are electromagnetically coupled to the slotline structure, for example, by inductive coupling, and therefore, the microstrip transmission lines are electromagnetically coupled to each other through the slotline structure. For example, with respect to RF energy in transmission (e.g., from the first microstrip transmission line to the second microstrip transmission line), the RF energy encounters a transition from microstrip to slotline involving electromagnetic coupling, and then a transition from slotline to microstrip also involving electromagnetic coupling.

[0050] In one embodiment, the controllable capacitance circuit 238 includes a variable capacitor (e.g., a digitally controllable micro-electromechanical system (MEMS) capacitor) electrically connected to the open stub of each microstrip transmission line, for example, by direct physical contact between the conductive elements of each component. For example, a first variable capacitor 260 is electrically connected to the open stub 240 of the first microstrip transmission line 230, and a second variable capacitor 262 is electrically connected to the open stub 242 of the second microstrip transmission line 232. Although in Figure 2 In the example of , the controllable capacitor circuit is electrically connected to both the first microstrip transmission line and the second microstrip transmission line, but in other embodiments, at least one of the microstrip transmission lines is not electrically connected to the controllable capacitor circuit. In the case where at least one of the microstrip transmission lines is not electrically connected to the controllable capacitor circuit, in order to achieve minimum insertion loss of the impedance compensation system, the open stub impedance at the intersection should be zero or close to zero. The impedance of a simple quarter-wavelength open stub is expected to be approximately zero, and in one embodiment the physical length of the stub is approximately equal to one-quarter of the wavelength of the RF signal. Therefore, having a capacitor connected to each open stub can provide the desired low impedance at the intersection, where the physical stub length is much shorter than if there were no capacitors attached.

[0051] In operation, the monitoring and control system (see Figure 1 , the monitoring and control system 114) receives a capacitance control signal to control and / or adjust the controllable capacitance circuit 238. For example, the capacitance control signal is generated by the monitoring and control system in response to the monitored incident power and / or in response to the monitored reflected power, and the capacitance control signal is dynamically adjusted to compensate for the antenna impedance mismatch. In one embodiment, the monitoring and control system is configured to implement an optimization algorithm to attempt to achieve maximum incident power or minimum reflected power. For example, a power amplifier (see Figure 1 , PA 102) only transmits power to the antenna (see Figure 1 , antenna 122) supplies maximum power. When the antenna is mismatched (e.g., Γ=0.2), the incident power will drop, and the capacitance of the controllable capacitance circuit is adjusted to restore the incident power until the antenna mismatch is compensated to provide Γ→0 at the output of the power amplifier. In operation, the power amplifier desirably generates maximum power and delivers all generated power to the antenna under compensated impedance mismatch conditions.

[0052] As described above, the capacitance of the controllable capacitance circuit 238 is controlled to compensate for the antenna impedance mismatch. Figures 3A-3C A description of some of the design and theory of operation is provided. Figure 3A Describes Figure 2 The first microstrip transmission line 330, the second microstrip transmission line 332 and the slot line structure 336 are shown, and Figure 3B yes Figure 3A An example of an equivalent circuit 300 of the components shown. Figure 3A and 3B In the example, the interface to the first microstrip transmission line is identified as "Port 1" and the interface to the second microstrip transmission line is identified as "Port 2". Figure 3B The components of the equivalent circuit shown include:

[0053] Zμ – characteristic impedance of microstrip transmission line;

[0054] Zoμ – characteristic impedance of microstrip transmission line stub;

[0055] Θομ - electrical length of the microstrip transmission line stub;

[0056] Cομ-microstrip transmission line stub capacitance;

[0057] Zs – slot line structure characteristic impedance;

[0058] Zos – characteristic impedance of the short stub of slotline construction;

[0059] Θοs – electrical length of the short stub in the slot line construction;

[0060] Los – the slotline construction stub inductance; and

[0061] n—transformer turns ratio, which represents the magnitude of coupling between the microstrip transmission line and the slotline structure.

[0062] exist Figure 3B In the equivalent circuit 300 shown, the inductive coupling at the transition from the first microstrip transmission line to the slotline structure is represented by a transformer formed in inductors 360 and 361 (n:1 coupling), and the inductive coupling at the transition from the slotline structure to the second microstrip transmission line is represented by a transformer formed in inductors 362 and 363 (1:n coupling). The equivalent circuit elements identified within the dashed circle "A" and corresponding to the microstrip transmission line open stubs 340 and 342 include Zoμ, Θομ, and Cομ, and the equivalent circuit elements identified within the dashed circle "B" and corresponding to the slotline structure short-circuited stubs 350 and 352 include Zos, Θοs, and Los. Using the equivalent circuit and transforming the components of the circuit to the port 1 side (e.g., the first microstrip transmission line), the following is obtained. Figure 3C The equivalent circuit 301 is shown, where:

[0063]

[0064]

[0065] Xμ=Xinμ (3)

[0066] exist Figure 3C In , "j" represents the imaginary part of the complex characteristic impedance of the transmission line. Therefore, "jXμ" is the imaginary part of the characteristic impedance of the microstrip transmission line, and "jXs" is the imaginary part of the characteristic impedance of the slotline structure.

[0067] If the two microstrip transmission line open stubs 340 and 342 are identical, and the two slotline construction short stubs 350 and 352 are identical, the input reflection coefficient Γin can be expressed as:

[0068]

[0069] as well as

[0070]

[0071] Where n is the ratio of the characteristic impedance of the microstrip line to the characteristic impedance of the slot line at the intersection point.

[0072] Therefore, by changing the microstrip transmission line open stub parameter Xinμ in equation (3) and the transformer turns ratio n in equations (2) and (3), the port 2 impedance can be compensated at port 1 over a wide range of impedances and instantaneous RF bandwidth. That is, the input reflection coefficient Γin (Equation 4) can be controlled by changing the microstrip transmission line stub capacitance Coμ. Therefore, by changing the microstrip transmission line stub capacitance Coμ, Rs (Equation 1), Xs (Equation 2), Xμ (Equation 3), and the transformer turns ratio n (Equation 5) can be controlled. Although the two microstrip transmission line open stubs 340, 342 can be identical (e.g., have the same electrical and / or physical properties), it should be understood that in some embodiments, the microstrip transmission line open stubs 340, 342 do not need to be identical.

[0073] Figure 4 Describes the Figure 2 An embodiment of a digitally controllable capacitor 438 of at least one component of the controllable capacitance circuit 238 is shown. The digitally controllable capacitor includes a control interface 470, a control circuit 472, an adjustable (variable) capacitor 474 (e.g., an adjustable MEMS capacitor), an RF ground interface 476 (RFGND), and an RF interface 478. Figure 4 In the example of , the control interface includes a voltage input (VIO), a clock signal input (SCLK), a control data input (SDATA) and a ground interface (GND), and the size of the capacitance of the capacitor 474 can be controlled in response to the digital value of the control data input (SDATA). In one embodiment, the RF interface 478 of the digitally controllable capacitor is physically and electrically connected to an open short stub of one of the microstrip transmission lines, for example, a conductive element coupled to the end of one of the lines 330, 332 with a conductive material such as conductive solder, the conductive material physically bonding the open short stub of the microstrip transmission line to and electrically connecting it to the RF interface of the digitally controllable capacitor. The ground interface 476 can be physically connected to and electrically connected to a ground reference voltage (e.g., system ground). Digitally controllable capacitors including, for example, adjustable MEMS capacitors are known in the art. In one embodiment, the digitally controllable capacitor can be a discrete packaged semiconductor device (e.g., having a physical size of approximately 1-1.5 mm×1-1.5 mm and being 0.4-0.5 mm thick) surface mounted to a PCB. In an example embodiment, capacitor 474 may have an adjustable capacitance in the range of 0.5-1.6 picofarads (pF) and a quality factor (Q) of about 400 at about 700 MHz. In alternative embodiments, capacitor 474 may have a wider, narrower, and / or different range of capacitance, and / or a higher or lower Q.

[0074] Figure 5An embodiment of a system 500 configured to provide compensation for antenna impedance mismatch in an RF front end is depicted, as described above with reference to FIG. Figure 1-4 Described. Figure 5 In the embodiment of the present invention, the system (referred to as an "impedance compensation system") includes a first microstrip transmission line 530, a second microstrip transmission line 532, a slot line structure 536 and a reference Figure 2-4 The described circuit is similar to the controllable capacitance circuit 538. Figure 5 In the example of FIG. 1 , the controllable capacitance circuit includes digitally controllable capacitors 560 and 562, as described above with reference to FIG. Figure 4 Two examples of digitally controllable capacitor circuits are described, with the controllable capacitors 560 and 562 each being electrically connected to one of the open stubs 540 and 542 of the first microstrip transmission line 530 and the second microstrip transmission line 532 at a corresponding RF interface 578. The control interface 570 of each digitally controllable capacitor 560, 562 is connected to a different control signal line 582, and each control signal line is connected to a system control interface 584, through which a digital capacitance control signal can travel. In operation, the capacitance at the open stub of the microstrip transmission line is controlled in response to the digital capacitance control signal to compensate for antenna impedance mismatch. For example, the capacitance of the adjustable capacitors is independently controlled and / or adjusted in response to a digital capacitance control signal received, for example, from a monitoring and control system of the RF front end (see Figure 1 In one embodiment, the digital capacitance control signal includes a transition-specific control signal for independently controlling a first digitally controllable capacitor 560 connected to a transition of a first microstrip transmission line to a slotline configuration and a second digitally controllable capacitor 562 connected to a transition of a second microstrip transmission line to a slotline configuration. At any given time, the capacitors 560, 562 may be controlled to have substantially the same capacitance value or different capacitance values.

[0075] Figure 6 It is a graph of return loss (RL) (in decibels (dB)) and phase (in degrees) at a phase angle of 360° at three radio frequencies of 3.4 GHz, 3.5 GHz and 3.6 GHz when the reflection coefficient Γ=0.2. Figure 6 The graph shows that under certain operating conditions and using an embodiment of the inventive subject matter, an antenna mismatch equal to Γ = 0.2 (RL = -20lgΓ ≈ -14 dB) can be compensated to above -25 dB (Γ < 0.014) at 3.5 GHz and above -20 dB (Γ < 0.04) at the edge of the 200 MHz bandwidth (e.g., at 3.4 GHz and 3.6 GHz).

[0076] Fig. 7Ais a top plan view of an example layout of an assembly 700 including a first microstrip transmission line 730 (e.g., microstrip transmission line 230), a second microstrip transmission line 732 (e.g., microstrip transmission line 232), and a slotline construction 736 (e.g., slotline construction 236), as described above with respect to the footprint of the assembly. Figure 7B yes Fig. 7A A side view of the component at cross section AA. Fig. 7A and 7B In the example of FIG. 1 , the first microstrip transmission line 730 and the second microstrip transmission line 732 are located on the same side of the component (e.g., the first microstrip transmission line and the second microstrip transmission line are coplanar). For example, the first microstrip transmission line 730 and the second microstrip transmission line 732 can be two conductive features of a first patterned conductive layer of a substrate (e.g., a PCB). From top to bottom, Figure 7B The cross section of FIG. 1 shows that the PCB (or other substrate) includes a first patterned conductive layer 786 (the first patterned conductive layer 786 corresponds to the first microstrip transmission line and the second microstrip transmission line), a dielectric layer 788, a second patterned conductive layer 790 (the second patterned conductive layer 790 corresponds to the slot line structure) and a bottom dielectric layer 792. Fig. 7A In an exemplary embodiment, the assembly 700 is approximately 10 millimeters (mm) by 6 mm, and the microstrip transmission lines 730, 732 have a width of approximately 0.25 mm and a total length of approximately 15 mm, the elongated portion 754 of the slotline construction has a width in the range of approximately 0.25-0.3 mm and a length in the range of approximately 2.5-3 mm, and the shorting stubs 750, 752 of the slotline construction have a diameter of approximately 3.5 mm. In other embodiments, the actual or relative dimensions listed in the preceding sentence may be smaller and / or larger. Reference Figure 7B In one embodiment, the microstrip layer 786 is approximately 25 microns thick (vertical dimension), the dielectric layer 788 is approximately 75 microns thick, the conductive layer 790 of the slotline construction is approximately 20 microns thick, and the bottom dielectric layer 792 is approximately 200 microns thick, with a dielectric constant of approximately εr=3.3. In other embodiments, the actual or relative dimensions or values ​​listed in the previous sentence may be smaller and / or larger. Although Fig. 7A and 7B The assembly 700 is depicted as having a certain footprint size, but in some other embodiments, the first and second microstrip transmission lines, the slotline configuration, and the controllable capacitance circuit are integrated into a substrate (such as a PCB) that includes other components (e.g., components of an RF front end). In other words, the assembly 700 can be a discrete component formed on a different substrate, or the assembly 700 can be integrally formed in a PCB with other parts of the RF system.

[0077] Fig. 8Ais a top plan view of an example layout of an assembly 800 including a first microstrip transmission line 830 (e.g., microstrip transmission line 230), a second microstrip transmission line 832 (e.g., microstrip transmission line 232), and a slotline construction 836 (e.g., slotline construction 236), wherein the first microstrip transmission line and the second microstrip transmission line are not on the same side of the slotline construction 836. Figure 8B yes Fig. 8A A side view of the component at cross section AA. Fig. 8A and 8B In the example of , the first microstrip transmission line and the second microstrip transmission line are located on opposite sides of the component substrate (e.g., the first microstrip transmission line and the second microstrip transmission line are formed by conductive portions of different patterned conductive layers on different planes). For example, the first microstrip transmission line 830 and the second microstrip transmission line 832 can be two conductive features of two different patterned conductive layers of a substrate (e.g., a PCB), and the slotline structure 836 can be formed in a third conductive layer of the substrate, which is positioned between the two conductive layers including the first microstrip transmission line 830 and the second microstrip transmission line 832. From top to bottom, the cross section shows a first patterned conductive layer 886 (the first patterned conductive layer 886 corresponds to the first microstrip transmission line 830), a first dielectric layer 888, a second patterned conductive layer 890 (the second patterned conductive layer 890 corresponds to the slotline structure 836), a second dielectric layer 892, and a third patterned conductive layer 894 (the third patterned conductive layer 894 corresponds to the second microstrip transmission line 832). Reference Fig. 8A In an exemplary embodiment, the assembly is approximately 10 mm x 6 mm, and the width of the microstrip transmission line is approximately 0.25 mm and the total length is approximately 15 mm, the width of the elongated portion of the slotline construction is in the range of approximately 0.25-0.3 mm and the length is in the range of approximately 2.5-3 mm, and the diameter of the shorting stub of the slotline construction is approximately 3.5 mm. Figure 8B , in one embodiment, microstrip layers 886 and 894 are approximately 25 microns thick, dielectric layer 888 is approximately 75 microns thick, conductive layer 890 of the slotline construction is approximately 20 microns thick, and bottom dielectric layer 892 is approximately 200 microns thick. In other embodiments, the actual or relative dimensions listed in the previous two sentences may be smaller and / or larger. Although the second microstrip transmission line is shown as being exposed to an open environment, the second microstrip transmission line may be embedded in or surrounded by a dielectric layer having a dielectric constant of about εr=3.3 or some other value. In addition, although Fig. 8A and 8BA component having a certain footprint size is depicted, but in some other embodiments, the first and second microstrip transmission lines, the slotline configuration, and the controllable capacitance circuit are integrated into a substrate (e.g., a PCB) that includes other components (e.g., components of an RF front end). In other words, the component 800 can be a discrete component formed on a different substrate, or the component 800 can be integrally formed in a PCB with other parts of the RF system.

[0078] Fig. 9 is an example of a slot line structure 936 in a conductive layer 990 in which short-circuiting stubs 950 and 952 are radially shaped stubs. The slot line structure 936 can be used, for example, to replace Figure 2 , 3, 5, 7 and 8. Fig. 9 In the example shown, the radial spread of the radially shaped shorting stubs is about 90 degrees, but other radial spreads are possible.

[0079] Microstrip transmission lines and / or slotline constructions with Figure 7A-9 Configurations different from those shown are possible. For example, a configuration of a microstrip transmission line may include only straight microstrip transmission lines and / or multi-arm stubs. Configurations of slotline construction may include, for example, "Y"-shaped shorted stubs, multi-arm stubs, or a simple unified slotline.

[0080] As described above, the use of microstrip to slotline transitions and slotline to microstrip transitions with controllable capacitance electrically connected to at least one of the microstrip transmission lines enables dynamic impedance compensation to be implemented in a manner that provides adjustability over a wide dynamic range over a wide frequency range with compact components. Some benefits of this technology may include increasing the range of impedance compensation, increasing the instantaneous frequency band of impedance compensation, suppressing system gain at low frequencies due to filter-shaped frequency response, compactness of the impedance compensation system, RF power transfer from the power amplifier side substrate to the antenna side, galvanic isolation of the RF front end from the antenna, and expansion to higher output powers.

[0081] Although the conductive layers of the microstrip transmission line and slotline structures are described as being separated by one or more dielectric layers, the microstrip transmission line and slotline structures may alternatively be separated from each other by an open space filled with a gas (such as air). Figure 1-9The impedance compensation system implemented as described can be implemented on a two-layer PCB or a multi-layer PCB, or on any other substrate capable of operating at RF frequencies ranging from, for example, 800 MHz to 6 GHz, not excluding lower or higher frequencies. Example performance parameters for 5G wireless applications may include: operating frequency - Band 42 (3.4-3.6 GHz); signal bandwidth - 200 MHz; average output power - 5 Watts; and load mismatch - 14 dB return loss (RL). The performance parameters may also be in different ranges and / or may also be lower or higher.

[0082] As discussed above, the present disclosure is intended to cover Figure 1-9 Many embodiments other than those described in any of the figures of the drawings. For example, it is contemplated that many different embodiments may employ any of a variety of different types of slotline constructions having any of a variety of configurations, sizes, and shapes, including end gap portions of different sizes and shapes. Although several of the above-described embodiments employ a PCB in which a slotline construction is formed and a plurality of microstrip transmission lines are provided at one or more layers or one or more levels above or below the slotline construction, the microstrip transmission lines are described as being located above or below the slotline construction for convenience only, and the microstrip transmission lines may also be positioned on the side of the slotline construction in other embodiments, or arranged in other different ways relative to the conductive layer in which the slotline construction is provided.

[0083] In addition, if Figure 1-9 As should be apparent in the disclosure, the present disclosure is intended to cover a variety of different embodiments and arrangements having any arbitrary number of layers and / or having any various different types of input or output structures or components. For example, as has been discussed above, in some embodiments, a two-layer PCB is employed in which a first patterned conductive layer and a second patterned conductive layer are separated by a dielectric layer, one or more microstrip transmission lines are formed by portions of one of the conductive layers, and a slotline structure is formed by removed portions of the other conductive layer (or gaps in other conductive layers). In addition, for example, in other embodiments, a multilayer PCB having more than two conductive layers and a dielectric layer positioned therebetween may be employed (e.g., a PCB having a first conductive layer, a second conductive layer, and a third conductive layer, with a first dielectric layer positioned between the first conductive layer and the second conductive layer and a second dielectric layer positioned between the second conductive layer and the third conductive layer). In such embodiments, a slotline structure may be provided in any one of the conductive layers (or multiple slotline structures may be provided in one or more of the conductive layers). In addition, for example, it should be understood that, depending on the embodiment, Figure 1-9 Any of the embodiments of the present invention may be implemented on a two-layer PCB or a multi-layer PCB (or modified to be implemented on the substrate). Still further, it should be understood that, according to the embodiment, Figure 1-9 Any of the embodiments may be implemented in (or modified to be implemented in) a substrate other than a PCB type substrate, such as a multilayer ceramic substrate (e.g., a co-fired ceramic substrate), a semiconductor material substrate, etc.

[0084] Fig.10 A process flow chart of a method for providing impedance compensation for an RF front end. According to the method, at box 1002, an RF signal is received at one of a first microstrip transmission line and a second microstrip transmission line, wherein a slot line structure extends between the first microstrip transmission line and the second microstrip transmission line to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line. At box 1004, the capacitance at an open stub of at least one of the first microstrip transmission line and the second microstrip transmission line is adjusted to provide impedance compensation. In one embodiment of the method, adjusting the capacitance at the open stub of at least one of the first microstrip transmission line and the second microstrip transmission line involves adjusting the capacitance at a first controllable capacitance circuit (or variable capacitor) electrically connected to the open stub of the first microstrip transmission line in response to receiving a first capacitance control signal, and adjusting the capacitance at a second controllable capacitance circuit (or variable capacitor) electrically connected to the open stub of the second microstrip transmission line in response to receiving a second capacitance control signal.

[0085] Although the operations of one or more methods herein are shown and described in a particular order, the order of the operations of each method may be changed so that certain operations may be performed in reverse order, or certain operations may be performed at least partially simultaneously with other operations. In another embodiment, instructions or sub-operations of different operations may be implemented in an intermittent and / or alternating manner.

[0086] It should also be noted that at least some of the operations of the methods described herein can be implemented using software instructions stored on a computer-usable storage medium for computer execution. For example, an embodiment of a computer program product includes a computer-usable storage medium for storing a computer-readable program.

[0087] A computer-usable or computer-readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or apparatus). Examples of non-transitory computer-usable and computer-readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), hard disk, and optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and digital video disk (DVD).

[0088] Alternatively, embodiments of the present invention may be implemented entirely in hardware or in an implementation scheme comprising both hardware and software elements. In embodiments using software, the software may include, but is not limited to, firmware, resident software, microcode, etc.

[0089] Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.

Claims

1. A circuit, characterized in that: include: a first L-shaped microstrip transmission line (230), the first L-shaped microstrip transmission line comprising a first linear portion and a second linear portion, the second linear portion extending substantially perpendicularly from the first linear portion at an elbow between the first linear portion and the second linear portion; a second L-shaped microstrip transmission line (232), the second L-shaped microstrip transmission line comprising a third linear portion and a fourth linear portion, the fourth linear portion extending substantially perpendicularly from the third linear portion at an elbow between the third linear portion and the fourth linear portion; a slotline construction (236) comprising an elongated linear portion (254), wherein the slotline configuration extends between the first L-shaped microstrip transmission line and the second L-shaped microstrip transmission line and extends perpendicularly to a portion of the first L-shaped microstrip transmission line and a portion of the second L-shaped microstrip transmission line, such that the slotline configuration is configured to electromagnetically couple the first L-shaped microstrip transmission line to the second L-shaped microstrip transmission line during operation of the circuit; as well as at least one controllable capacitance circuit (238), the at least one controllable capacitance circuit (238) being electrically connected to at least one of the first L-shaped microstrip transmission line and the second L-shaped microstrip transmission line, wherein the capacitance of the at least one controllable capacitance circuit is controllable, Wherein, the at least one controllable capacitance circuit comprises: a first controllable capacitance circuit (260), the first controllable capacitance circuit (260) being electrically connected to the first L-shaped microstrip transmission line and comprising a first control interface, wherein the capacitance of the first controllable capacitance circuit is controllable in response to a first capacitance control signal received at the first control interface; and A second controllable capacitor circuit (262), the second controllable capacitor circuit (262) is electrically connected to the second L-shaped microstrip transmission line and includes a second control interface, wherein the capacitance of the second controllable capacitor circuit is controllable in response to a second capacitor control signal received at the second control interface.

2. The circuit according to claim 1, characterized in that: The first L-shaped microstrip transmission line includes an open stub (240), and the first controllable capacitance circuit is electrically connected to the first L-shaped microstrip transmission line at the open stub of the first L-shaped microstrip transmission line; and The second L-shaped microstrip transmission line includes an open stub (242), and the second controllable capacitance circuit is electrically connected to the second L-shaped microstrip transmission line at the open stub of the second L-shaped microstrip transmission line.

3. The circuit according to claim 1, characterized in that The at least one controllable capacitance circuit (260) is controlled in response to a digital capacitance control signal received at a control interface (470) of the at least one controllable capacitance circuit.

4. The circuit according to claim 1, characterized in that The at least one controllable capacitance circuit comprises: a first digitally controllable capacitance circuit (260, 560), the first digitally controllable capacitance circuit (260, 560) being electrically connected to the first L-shaped microstrip transmission line and comprising a first control interface, wherein the capacitance of the first digitally controllable capacitance circuit is controllable in response to a first digital capacitance control signal received at the first control interface (570); and A second digitally controllable capacitor circuit (262, 562), the second digitally controllable capacitor circuit (262, 562) is electrically connected to the second L-shaped microstrip transmission line and includes a second control interface, wherein the capacitance of the second digitally controllable capacitor circuit is controllable in response to a second digital capacitor control signal received at the second control interface (570).

5. The circuit according to claim 1, characterized in that From a plan view perspective, a portion of the first L-shaped microstrip transmission line (230) intersects a portion of the slotline structure (236), and wherein from a plan view perspective, a portion of the second L-shaped microstrip transmission line (232) intersects a portion of the slotline structure.

6. The circuit according to claim 5, characterized in that: The first L-shaped microstrip transmission line includes an open stub (240), and the first L-shaped microstrip transmission line intersects a portion of the slotline structure proximate to the open stub of the first L-shaped microstrip transmission line; and The second L-shaped microstrip transmission line includes an open stub (242), and the second L-shaped microstrip transmission line intersects a portion of the slotline structure proximate to the open stub of the second L-shaped microstrip transmission line.

7. The circuit according to claim 5, characterized in that The intersection of the first L-shaped microstrip transmission line (230) and the slotline structure (236) is separated by a dielectric layer (788), and wherein the intersection of the second L-shaped microstrip transmission line and the slotline structure is separated by the dielectric layer.

8. The circuit according to claim 7, characterized in that Also included is a printed circuit board (PCB), wherein the slotline formation (236) is formed as a gap in a conductive layer of the PCB.

9. A method for providing impedance compensation for a radio frequency (RF) front end, characterized in that: The method comprises: Receiving an RF signal (1002) at one of a first L-shaped microstrip transmission line (230) and a second L-shaped microstrip transmission line (232), the first L-shaped microstrip transmission line comprising a first linear portion and a second linear portion, the second linear portion extending substantially perpendicularly from the first linear portion at an elbow between the first linear portion and the second linear portion, the second L-shaped microstrip transmission line comprising a third linear portion and a fourth linear portion, the fourth linear portion extending substantially perpendicularly from the third linear portion at an elbow between the third linear portion and the fourth linear portion, wherein a slotline structure (236) including an elongated linear portion (254) extends between the first L-shaped microstrip transmission line and the second L-shaped microstrip transmission line and extends perpendicularly to a portion of the first L-shaped microstrip transmission line and a portion of the second L-shaped microstrip transmission line to electromagnetically couple the first L-shaped microstrip transmission line to the second L-shaped microstrip transmission line; and adjusting a capacitance at an open stub (240, 242) of at least one of the first L-shaped microstrip transmission line and the second L-shaped microstrip transmission line to provide impedance compensation (1004), Wherein, adjusting the capacitance at the open stub of at least one of the first L-shaped microstrip transmission line and the second L-shaped microstrip transmission line involves adjusting the capacitance at a first controllable capacitance circuit electrically connected to the open stub of the first L-shaped microstrip transmission line in response to receiving a first capacitance control signal, and adjusting the capacitance at a second controllable capacitance circuit electrically connected to the open stub of the second L-shaped microstrip transmission line in response to receiving a second capacitance control signal.

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